Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6057413

1

T20

96

T22

393

T45

9

full_word

2615104

1

T20

35

T22

168

T23

40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8672227	1			T20	131		T22	561		T23	40
auto[TlIntgErrCmd]	96	1			T45	1		T72	9		T71	9
auto[TlIntgErrData]	99	1			T45	4		T72	8		T71	4
auto[TlIntgErrBoth]	95	1			T45	5		T72	3		T71	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042632

1

T20

18

T22

62

T23

40

auto[1]

7629885

1

T20

113

T22

499

T45

6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	441081	1			T20	8		T22	30		T68	116
auto[TlIntgErrNone]	partial	auto[1]	5616075	1			T20	88		T22	363		T68	1711
auto[TlIntgErrNone]	full_word	auto[0]	601411	1			T20	10		T22	32		T23	40
auto[TlIntgErrNone]	full_word	auto[1]	2013660	1			T20	25		T22	136		T68	194
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T72	4		T71	5		T74	2
auto[TlIntgErrCmd]	partial	auto[1]	37	1			T45	1		T72	5		T71	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T114	1		T116	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T71	1		T116	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T45	3		T72	4		T71	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T45	1		T72	2		T71	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T72	1		T79	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T72	1		T114	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T72	3		T71	5		T74	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T45	4		T71	2		T86	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T45	1		T119	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T86	1		T116	1		T122	1