Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 186083 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1925916 1 T31 137 T32 33 T33 17



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 526315 1 T31 19 T32 6 T33 2
values[0x0] 734154 1 T31 58 T32 18 T33 9
values[0x1] 851530 1 T31 60 T32 18 T33 9



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 82859 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2029140 1 T31 137 T32 38 T33 19



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 7909 1 T31 2 T36 1 T37 4
valid_sources[0x01] 7368 1 T34 1 T37 5 T45 3
valid_sources[0x02] 8815 1 T34 1 T39 2 T72 4
valid_sources[0x03] 7647 1 T34 2 T37 1 T49 1
valid_sources[0x04] 8906 1 T34 2 T36 1 T39 1
valid_sources[0x05] 8323 1 T36 1 T86 3 T64 1
valid_sources[0x06] 8247 1 T32 1 T34 1 T36 1
valid_sources[0x07] 9103 1 T31 1 T78 1 T47 3
valid_sources[0x08] 8431 1 T32 1 T78 6 T47 1
valid_sources[0x09] 7623 1 T31 1 T36 1 T37 1
valid_sources[0x0a] 7658 1 T71 3 T78 1 T47 1
valid_sources[0x0b] 7730 1 T36 1 T78 4 T47 2
valid_sources[0x0c] 7844 1 T34 1 T36 1 T39 1
valid_sources[0x0d] 9646 1 T31 1 T34 2 T63 2
valid_sources[0x0e] 8006 1 T36 2 T37 1 T39 1
valid_sources[0x0f] 7985 1 T31 1 T32 1 T37 1
valid_sources[0x10] 8438 1 T32 2 T39 1 T49 1
valid_sources[0x11] 7810 1 T78 2 T46 4 T47 1
valid_sources[0x12] 8144 1 T31 1 T36 2 T37 4
valid_sources[0x13] 7415 1 T37 3 T46 1 T47 1
valid_sources[0x14] 8565 1 T31 1 T39 1 T46 1
valid_sources[0x15] 8519 1 T31 2 T36 2 T78 2
valid_sources[0x16] 8780 1 T34 1 T36 1 T39 2
valid_sources[0x17] 7693 1 T34 1 T39 1 T81 1
valid_sources[0x18] 8838 1 T31 1 T37 1 T78 3
valid_sources[0x19] 9354 1 T31 1 T34 1 T36 3
valid_sources[0x1a] 7537 1 T46 1 T49 1 T81 2
valid_sources[0x1b] 7432 1 T31 1 T36 1 T86 6
valid_sources[0x1c] 8459 1 T39 2 T64 6 T66 1
valid_sources[0x1d] 8734 1 T72 1 T78 4 T86 1
valid_sources[0x1e] 8678 1 T31 2 T39 2 T86 1
valid_sources[0x1f] 7558 1 T32 1 T34 1 T37 4
valid_sources[0x20] 7484 1 T49 3 T65 1 T97 6
valid_sources[0x21] 7437 1 T31 1 T34 2 T36 1
valid_sources[0x22] 8337 1 T31 1 T32 1 T34 1
valid_sources[0x23] 8037 1 T31 1 T36 1 T37 1
valid_sources[0x24] 7449 1 T37 3 T39 1 T78 1
valid_sources[0x25] 9773 1 T39 1 T97 6 T60 1
valid_sources[0x26] 8710 1 T31 1 T34 1 T37 1
valid_sources[0x27] 7704 1 T37 3 T78 1 T46 2
valid_sources[0x28] 7984 1 T32 1 T36 1 T39 1
valid_sources[0x29] 8161 1 T34 1 T36 3 T37 1
valid_sources[0x2a] 8543 1 T31 1 T37 2 T39 1
valid_sources[0x2b] 8273 1 T34 1 T47 2 T86 2
valid_sources[0x2c] 8153 1 T31 2 T34 1 T45 10
valid_sources[0x2d] 7722 1 T34 2 T36 1 T37 1
valid_sources[0x2e] 8485 1 T31 1 T32 1 T81 1
valid_sources[0x2f] 7403 1 T72 1 T46 3 T86 1
valid_sources[0x30] 8457 1 T34 1 T37 2 T72 6
valid_sources[0x31] 7480 1 T31 4 T32 1 T46 6
valid_sources[0x32] 8578 1 T34 1 T36 2 T78 6
valid_sources[0x33] 8051 1 T32 1 T36 1 T78 6
valid_sources[0x34] 8054 1 T36 1 T48 10 T49 3
valid_sources[0x35] 8834 1 T36 1 T37 1 T78 1
valid_sources[0x36] 7898 1 T31 1 T34 1 T36 1
valid_sources[0x37] 9867 1 T45 2 T78 2 T47 1
valid_sources[0x38] 7998 1 T36 1 T37 4 T49 5
valid_sources[0x39] 8210 1 T37 3 T45 5 T86 1
valid_sources[0x3a] 9103 1 T34 1 T36 1 T37 3
valid_sources[0x3b] 8834 1 T31 1 T36 5 T45 16
valid_sources[0x3c] 10052 1 T31 1 T32 1 T34 1
valid_sources[0x3d] 8375 1 T31 2 T32 1 T78 1
valid_sources[0x3e] 8462 1 T37 5 T39 1 T62 1
valid_sources[0x3f] 8164 1 T34 1 T36 2 T37 1
valid_sources[0x40] 7485 1 T31 1 T39 1 T81 1
valid_sources[0x41] 8740 1 T31 1 T37 2 T39 1
valid_sources[0x42] 8034 1 T31 1 T32 1 T34 1
valid_sources[0x43] 8000 1 T32 1 T34 1 T37 2
valid_sources[0x44] 8424 1 T31 2 T34 1 T49 5
valid_sources[0x45] 7493 1 T31 4 T72 2 T49 4
valid_sources[0x46] 7999 1 T34 1 T36 2 T37 3
valid_sources[0x47] 8996 1 T32 1 T34 1 T72 4
valid_sources[0x48] 8071 1 T31 1 T49 2 T47 2
valid_sources[0x49] 8821 1 T45 4 T72 2 T47 1
valid_sources[0x4a] 8060 1 T63 3 T46 2 T49 1
valid_sources[0x4b] 8258 1 T36 2 T37 1 T62 1
valid_sources[0x4c] 7944 1 T31 2 T36 2 T78 3
valid_sources[0x4d] 8076 1 T48 10 T47 1 T87 1
valid_sources[0x4e] 10056 1 T32 1 T37 1 T86 2
valid_sources[0x4f] 8738 1 T39 1 T72 2 T47 1
valid_sources[0x50] 7559 1 T31 1 T34 1 T37 1
valid_sources[0x51] 8771 1 T31 2 T36 1 T39 1
valid_sources[0x52] 8285 1 T31 1 T37 2 T39 1
valid_sources[0x53] 8562 1 T36 2 T62 1 T46 2
valid_sources[0x54] 8853 1 T31 2 T32 1 T34 1
valid_sources[0x55] 8685 1 T31 1 T34 1 T36 1
valid_sources[0x56] 8014 1 T34 1 T36 4 T72 5
valid_sources[0x57] 8544 1 T36 1 T37 1 T78 2
valid_sources[0x58] 8849 1 T32 1 T39 1 T49 1
valid_sources[0x59] 7758 1 T34 1 T37 1 T39 1
valid_sources[0x5a] 9303 1 T32 2 T34 1 T36 5
valid_sources[0x5b] 9597 1 T31 1 T37 5 T63 2
valid_sources[0x5c] 9235 1 T36 3 T37 5 T46 3
valid_sources[0x5d] 8567 1 T31 1 T37 7 T78 1
valid_sources[0x5e] 7453 1 T36 1 T39 1 T72 1
valid_sources[0x5f] 8463 1 T34 1 T39 1 T72 3
valid_sources[0x60] 8152 1 T31 1 T34 2 T36 2
valid_sources[0x61] 7891 1 T78 1 T81 1 T86 1
valid_sources[0x62] 8690 1 T34 1 T37 2 T48 26
valid_sources[0x63] 8089 1 T37 2 T78 1 T46 3
valid_sources[0x64] 8194 1 T31 1 T39 1 T46 1
valid_sources[0x65] 7976 1 T34 2 T37 3 T62 1
valid_sources[0x66] 8508 1 T31 1 T72 6 T78 1
valid_sources[0x67] 8896 1 T31 2 T34 1 T37 3
valid_sources[0x68] 8531 1 T36 1 T37 3 T45 10
valid_sources[0x69] 8183 1 T32 1 T46 1 T86 3
valid_sources[0x6a] 8564 1 T31 2 T37 1 T78 2
valid_sources[0x6b] 7249 1 T72 3 T86 3 T97 1
valid_sources[0x6c] 8079 1 T31 1 T39 1 T72 2
valid_sources[0x6d] 8248 1 T36 3 T37 4 T47 1
valid_sources[0x6e] 8160 1 T34 1 T78 1 T86 1
valid_sources[0x6f] 6747 1 T31 1 T36 1 T37 5
valid_sources[0x70] 8272 1 T31 2 T36 1 T37 1
valid_sources[0x71] 8463 1 T46 1 T86 2 T64 4
valid_sources[0x72] 8901 1 T31 1 T34 1 T37 2
valid_sources[0x73] 8003 1 T31 2 T72 1 T47 1
valid_sources[0x74] 7687 1 T33 10 T72 2 T97 3
valid_sources[0x75] 8394 1 T45 12 T86 2 T97 1
valid_sources[0x76] 8983 1 T34 1 T37 1 T47 1
valid_sources[0x77] 8205 1 T34 1 T36 1 T37 2
valid_sources[0x78] 9016 1 T36 3 T49 2 T64 2
valid_sources[0x79] 8701 1 T34 2 T49 6 T47 1
valid_sources[0x7a] 7459 1 T31 2 T34 1 T36 1
valid_sources[0x7b] 8532 1 T31 1 T47 2 T86 1
valid_sources[0x7c] 8003 1 T34 1 T37 1 T64 2
valid_sources[0x7d] 8466 1 T34 2 T37 4 T48 42
valid_sources[0x7e] 7603 1 T31 1 T36 2 T39 1
valid_sources[0x7f] 7579 1 T34 1 T36 1 T37 1
valid_sources[0x80] 7616 1 T32 1 T37 2 T72 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 486558 1 T31 19 T33 1 T34 32
values[0x0] all_enables biggest_size 719205 1 T31 58 T32 17 T33 8
values[0x1] all_enables biggest_size 720153 1 T31 60 T32 16 T33 8


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 426188 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1897383 1 T34 189 T36 21 T39 295



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 521361 1 T34 43 T36 4 T39 78
values[0x0] 745843 1 T34 80 T36 9 T39 100
values[0x1] 1056367 1 T34 85 T36 20 T39 150



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 162087 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2161484 1 T34 200 T36 28 T39 317



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 8846 1 T34 1 T39 1 T57 2
valid_sources[0x01] 8190 1 T39 2 T45 1 T64 1
valid_sources[0x02] 9288 1 T39 2 T59 1 T60 1
valid_sources[0x03] 9697 1 T46 2 T49 1 T60 1
valid_sources[0x04] 8575 1 T39 2 T46 2 T49 1
valid_sources[0x05] 8864 1 T39 1 T59 1 T70 1
valid_sources[0x06] 8748 1 T39 1 T45 1 T60 3
valid_sources[0x07] 9592 1 T36 1 T39 1 T59 1
valid_sources[0x08] 8513 1 T49 2 T60 6 T4 131
valid_sources[0x09] 8518 1 T64 1 T60 3 T85 2
valid_sources[0x0a] 9127 1 T34 2 T39 2 T49 1
valid_sources[0x0b] 8202 1 T59 1 T60 1 T70 1
valid_sources[0x0c] 10027 1 T39 7 T45 1 T59 1
valid_sources[0x0d] 9226 1 T39 6 T64 1 T60 1
valid_sources[0x0e] 8801 1 T46 1 T60 3 T117 1
valid_sources[0x0f] 8123 1 T39 1 T45 1 T49 1
valid_sources[0x10] 9587 1 T39 1 T49 1 T60 2
valid_sources[0x11] 8449 1 T39 2 T68 1 T70 2
valid_sources[0x12] 8780 1 T39 3 T45 4 T49 1
valid_sources[0x13] 8808 1 T36 2 T59 1 T60 2
valid_sources[0x14] 10362 1 T39 5 T60 2 T70 1
valid_sources[0x15] 9285 1 T34 3 T49 1 T60 4
valid_sources[0x16] 8445 1 T39 2 T46 1 T57 1
valid_sources[0x17] 8948 1 T39 1 T75 1 T68 1
valid_sources[0x18] 9868 1 T34 8 T39 1 T64 1
valid_sources[0x19] 10282 1 T59 1 T4 124 T6 62
valid_sources[0x1a] 8540 1 T49 1 T59 2 T61 2
valid_sources[0x1b] 8544 1 T39 1 T46 2 T49 1
valid_sources[0x1c] 8890 1 T36 1 T60 4 T4 130
valid_sources[0x1d] 9439 1 T39 3 T85 2 T4 129
valid_sources[0x1e] 9500 1 T46 1 T59 1 T60 1
valid_sources[0x1f] 8264 1 T39 1 T88 2 T70 1
valid_sources[0x20] 8195 1 T39 2 T49 1 T82 2
valid_sources[0x21] 8940 1 T39 2 T49 1 T84 1
valid_sources[0x22] 9016 1 T34 4 T46 1 T64 1
valid_sources[0x23] 10092 1 T64 1 T76 1 T70 1
valid_sources[0x24] 8771 1 T34 8 T39 4 T45 1
valid_sources[0x25] 10042 1 T39 4 T45 4 T64 1
valid_sources[0x26] 8711 1 T49 2 T60 2 T68 3
valid_sources[0x27] 10086 1 T49 1 T64 1 T68 2
valid_sources[0x28] 8970 1 T39 3 T70 5 T4 146
valid_sources[0x29] 9113 1 T45 1 T60 4 T67 82
valid_sources[0x2a] 9226 1 T34 2 T39 1 T64 1
valid_sources[0x2b] 11362 1 T34 1 T39 1 T45 1
valid_sources[0x2c] 9085 1 T49 2 T60 1 T68 1
valid_sources[0x2d] 8659 1 T36 1 T39 1 T47 10
valid_sources[0x2e] 9808 1 T49 1 T59 1 T60 2
valid_sources[0x2f] 8127 1 T39 1 T48 1 T46 1
valid_sources[0x30] 8727 1 T39 1 T45 1 T49 1
valid_sources[0x31] 8995 1 T39 1 T64 1 T76 1
valid_sources[0x32] 8866 1 T39 1 T49 1 T60 1
valid_sources[0x33] 8703 1 T39 1 T49 1 T47 1
valid_sources[0x34] 9682 1 T49 1 T60 2 T76 1
valid_sources[0x35] 9755 1 T39 2 T49 1 T68 1
valid_sources[0x36] 8491 1 T45 3 T75 2 T85 1
valid_sources[0x37] 8482 1 T39 1 T64 1 T65 1
valid_sources[0x38] 8289 1 T36 6 T39 2 T49 1
valid_sources[0x39] 9245 1 T70 2 T4 150 T6 65
valid_sources[0x3a] 9440 1 T39 1 T59 1 T60 6
valid_sources[0x3b] 9102 1 T39 2 T49 1 T64 2
valid_sources[0x3c] 8793 1 T39 1 T60 2 T70 1
valid_sources[0x3d] 9536 1 T39 5 T45 1 T59 1
valid_sources[0x3e] 8429 1 T39 1 T64 1 T60 3
valid_sources[0x3f] 8962 1 T39 1 T49 1 T60 1
valid_sources[0x40] 9233 1 T39 3 T46 1 T85 1
valid_sources[0x41] 9352 1 T49 1 T64 1 T60 1
valid_sources[0x42] 8833 1 T39 3 T60 9 T70 2
valid_sources[0x43] 9277 1 T39 1 T46 1 T49 1
valid_sources[0x44] 8679 1 T34 4 T39 1 T60 4
valid_sources[0x45] 8409 1 T59 1 T60 1 T70 2
valid_sources[0x46] 9020 1 T34 3 T39 1 T68 1
valid_sources[0x47] 11034 1 T39 1 T49 1 T64 1
valid_sources[0x48] 9388 1 T49 1 T60 2 T76 1
valid_sources[0x49] 9040 1 T39 1 T57 1 T60 1
valid_sources[0x4a] 8605 1 T39 1 T49 1 T60 3
valid_sources[0x4b] 8920 1 T34 7 T39 1 T59 1
valid_sources[0x4c] 8494 1 T39 2 T66 5 T4 150
valid_sources[0x4d] 9511 1 T65 2 T70 1 T4 131
valid_sources[0x4e] 8542 1 T39 2 T49 3 T60 1
valid_sources[0x4f] 8930 1 T39 1 T59 2 T60 1
valid_sources[0x50] 9794 1 T39 1 T49 2 T88 1
valid_sources[0x51] 9083 1 T39 2 T60 1 T70 1
valid_sources[0x52] 8992 1 T60 2 T70 1 T4 160
valid_sources[0x53] 8629 1 T59 2 T70 1 T118 1
valid_sources[0x54] 9126 1 T60 2 T70 1 T4 89
valid_sources[0x55] 8520 1 T64 1 T60 2 T61 1
valid_sources[0x56] 8905 1 T34 6 T39 3 T59 1
valid_sources[0x57] 8312 1 T39 1 T60 1 T85 2
valid_sources[0x58] 8659 1 T34 24 T57 1 T60 1
valid_sources[0x59] 10253 1 T39 3 T64 1 T60 3
valid_sources[0x5a] 8218 1 T57 1 T59 1 T60 2
valid_sources[0x5b] 8154 1 T34 3 T39 1 T59 1
valid_sources[0x5c] 8779 1 T34 10 T39 1 T59 1
valid_sources[0x5d] 9745 1 T49 1 T64 2 T60 1
valid_sources[0x5e] 8441 1 T39 1 T60 2 T84 2
valid_sources[0x5f] 9161 1 T39 2 T85 3 T4 122
valid_sources[0x60] 9739 1 T39 1 T59 3 T60 4
valid_sources[0x61] 8842 1 T39 3 T57 1 T60 4
valid_sources[0x62] 8790 1 T39 2 T70 1 T85 1
valid_sources[0x63] 8778 1 T39 1 T49 1 T65 1
valid_sources[0x64] 9367 1 T39 4 T60 1 T76 1
valid_sources[0x65] 7981 1 T34 7 T39 1 T46 2
valid_sources[0x66] 9284 1 T39 1 T64 1 T68 1
valid_sources[0x67] 8609 1 T60 6 T76 1 T85 3
valid_sources[0x68] 8942 1 T39 2 T49 2 T59 2
valid_sources[0x69] 8560 1 T47 2 T70 4 T4 100
valid_sources[0x6a] 9515 1 T39 2 T45 1 T47 2
valid_sources[0x6b] 9077 1 T39 1 T59 2 T76 1
valid_sources[0x6c] 8557 1 T36 1 T39 1 T60 4
valid_sources[0x6d] 9058 1 T39 7 T64 1 T68 1
valid_sources[0x6e] 9120 1 T39 3 T59 1 T60 2
valid_sources[0x6f] 11091 1 T39 1 T60 1 T70 1
valid_sources[0x70] 9609 1 T39 1 T60 2 T68 1
valid_sources[0x71] 8029 1 T39 1 T59 1 T60 2
valid_sources[0x72] 8615 1 T77 3 T68 1 T70 1
valid_sources[0x73] 9434 1 T39 2 T64 1 T60 3
valid_sources[0x74] 8658 1 T49 1 T64 2 T59 2
valid_sources[0x75] 8476 1 T34 4 T39 3 T49 1
valid_sources[0x76] 8351 1 T59 1 T75 4 T70 1
valid_sources[0x77] 8310 1 T36 1 T39 1 T45 1
valid_sources[0x78] 8684 1 T34 8 T48 1 T59 1
valid_sources[0x79] 9366 1 T36 3 T39 5 T60 1
valid_sources[0x7a] 8555 1 T65 1 T70 1 T118 1
valid_sources[0x7b] 9626 1 T60 2 T70 1 T118 1
valid_sources[0x7c] 9839 1 T34 4 T58 9 T60 2
valid_sources[0x7d] 8883 1 T36 1 T59 1 T75 1
valid_sources[0x7e] 9012 1 T39 1 T76 1 T4 140
valid_sources[0x7f] 9572 1 T59 1 T60 3 T70 1
valid_sources[0x80] 8557 1 T34 10 T39 1 T49 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 478506 1 T34 43 T36 4 T39 78
values[0x0] all_enables biggest_size 709631 1 T34 76 T36 7 T39 98
values[0x1] all_enables biggest_size 709246 1 T34 70 T36 10 T39 119

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