Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5286955

1

T34

304

T36

176

T39

600

full_word

2275795

1

T34

212

T36

27

T39

339

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7562450	1			T34	516		T36	203		T39	939
auto[TlIntgErrCmd]	101	1			T48	4		T57	8		T61	8
auto[TlIntgErrData]	99	1			T48	3		T57	5		T61	9
auto[TlIntgErrBoth]	100	1			T48	3		T57	7		T61	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

907786

1

T34

60

T36

9

T39

107

auto[1]

6654964

1

T34

456

T36

194

T39

832

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	382970	1			T34	15		T36	5		T39	25
auto[TlIntgErrNone]	partial	auto[1]	4903707	1			T34	289		T36	171		T39	575
auto[TlIntgErrNone]	full_word	auto[0]	524678	1			T34	45		T36	4		T39	82
auto[TlIntgErrNone]	full_word	auto[1]	1751095	1			T34	167		T36	23		T39	257
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T48	1		T57	4		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T48	2		T57	4		T61	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T113	2		T111	1		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T48	1		T83	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T57	1		T61	3		T66	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T48	3		T57	3		T61	6
auto[TlIntgErrData]	full_word	auto[0]	5	1			T57	1		T110	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T84	1		T113	1		T111	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T48	1		T57	2		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T48	2		T57	4		T61	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T57	1		T82	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T66	1		T84	1		T112	2