SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_kmac_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 0 | 7 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_kmac_done | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_kmac_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
kmac_first | 606 | 1 | T35 | 1 | T37 | 1 | T38 | 1 | ||||
same_cycle | 8 | 1 | T65 | 1 | T67 | 1 | T88 | 1 | ||||
rom_first | 1411 | 1 | T30 | 1 | T31 | 1 | T32 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
stall_repeat | 86304802 | 1 | T30 | 25036 | T31 | 5601 | T32 | 70330 | ||||
stall_long | 9034741 | 1 | T30 | 3115 | T32 | 7284 | T33 | 7384 | ||||
stall_1 | 847741 | 1 | T30 | 996 | T31 | 2746 | T32 | 191 | ||||
zero_delay_5 | 4345274 | 1 | T30 | 1 | T31 | 85 | T37 | 8856 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |