Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 198948 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2038958 1 T23 122 T24 74 T25 336



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 559727 1 T23 7 T24 71 T25 52
values[0x0] 776662 1 T23 62 T24 17 T25 168
values[0x1] 901517 1 T23 53 T24 19 T25 183



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 88562 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2149344 1 T23 122 T24 80 T25 361



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 8426 1 T23 5 T25 1 T29 2
valid_sources[0x01] 8626 1 T25 2 T29 1 T48 7
valid_sources[0x02] 7533 1 T24 1 T29 3 T48 1
valid_sources[0x03] 7740 1 T25 4 T29 5 T70 1
valid_sources[0x04] 9261 1 T24 1 T25 1 T29 1
valid_sources[0x05] 9908 1 T24 1 T25 2 T47 2
valid_sources[0x06] 7758 1 T25 6 T29 1 T48 4
valid_sources[0x07] 9407 1 T23 4 T24 1 T29 1
valid_sources[0x08] 9245 1 T25 3 T48 3 T64 2
valid_sources[0x09] 7773 1 T25 4 T48 2 T64 1
valid_sources[0x0a] 8435 1 T25 1 T29 2 T30 9
valid_sources[0x0b] 8307 1 T24 2 T25 3 T48 2
valid_sources[0x0c] 8716 1 T25 1 T29 2 T47 8
valid_sources[0x0d] 9015 1 T70 2 T64 1 T65 2
valid_sources[0x0e] 8795 1 T25 2 T29 2 T48 1
valid_sources[0x0f] 8497 1 T24 1 T29 1 T69 10
valid_sources[0x10] 8530 1 T23 4 T25 3 T29 1
valid_sources[0x11] 8386 1 T25 1 T28 1 T29 1
valid_sources[0x12] 8166 1 T29 1 T48 2 T64 1
valid_sources[0x13] 8365 1 T28 1 T29 1 T65 1
valid_sources[0x14] 9737 1 T25 8 T29 1 T48 1
valid_sources[0x15] 8435 1 T25 5 T29 4 T32 1
valid_sources[0x16] 9939 1 T25 2 T26 9 T30 10
valid_sources[0x17] 8392 1 T28 1 T29 1 T64 2
valid_sources[0x18] 7355 1 T25 2 T29 1 T30 10
valid_sources[0x19] 8819 1 T24 1 T29 1 T48 1
valid_sources[0x1a] 9187 1 T25 4 T29 5 T48 3
valid_sources[0x1b] 9477 1 T25 1 T30 12 T48 1
valid_sources[0x1c] 8758 1 T24 1 T27 2 T29 3
valid_sources[0x1d] 9012 1 T30 24 T48 1 T86 1
valid_sources[0x1e] 8434 1 T24 1 T29 1 T47 2
valid_sources[0x1f] 8870 1 T24 1 T29 2 T48 4
valid_sources[0x20] 10313 1 T29 2 T47 1 T48 2
valid_sources[0x21] 8623 1 T25 7 T29 2 T47 3
valid_sources[0x22] 10082 1 T25 2 T69 31 T48 1
valid_sources[0x23] 9345 1 T25 1 T29 3 T48 1
valid_sources[0x24] 8679 1 T25 3 T26 10 T32 1
valid_sources[0x25] 8715 1 T24 5 T25 4 T29 1
valid_sources[0x26] 8846 1 T23 6 T29 1 T48 6
valid_sources[0x27] 9101 1 T25 4 T29 2 T30 5
valid_sources[0x28] 8770 1 T25 2 T29 1 T48 3
valid_sources[0x29] 7786 1 T25 2 T29 2 T64 2
valid_sources[0x2a] 8543 1 T24 2 T29 1 T72 2
valid_sources[0x2b] 8920 1 T24 2 T25 2 T28 1
valid_sources[0x2c] 8334 1 T25 1 T29 2 T48 4
valid_sources[0x2d] 8693 1 T25 1 T29 2 T64 1
valid_sources[0x2e] 8441 1 T25 1 T29 2 T30 4
valid_sources[0x2f] 8448 1 T25 1 T29 1 T65 2
valid_sources[0x30] 8422 1 T30 2 T48 2 T64 1
valid_sources[0x31] 8329 1 T24 1 T25 2 T28 1
valid_sources[0x32] 6889 1 T29 1 T47 2 T48 2
valid_sources[0x33] 9044 1 T25 3 T48 3 T65 1
valid_sources[0x34] 8196 1 T29 2 T30 5 T48 6
valid_sources[0x35] 8507 1 T25 2 T29 1 T48 1
valid_sources[0x36] 9890 1 T25 2 T29 3 T70 1
valid_sources[0x37] 9038 1 T25 2 T29 3 T64 1
valid_sources[0x38] 8187 1 T25 4 T48 2 T65 1
valid_sources[0x39] 10059 1 T24 2 T25 1 T29 2
valid_sources[0x3a] 9256 1 T25 1 T28 1 T29 3
valid_sources[0x3b] 9764 1 T23 13 T24 2 T25 1
valid_sources[0x3c] 8934 1 T70 1 T64 2 T86 1
valid_sources[0x3d] 8717 1 T25 2 T29 5 T30 10
valid_sources[0x3e] 9521 1 T47 2 T64 2 T65 1
valid_sources[0x3f] 10373 1 T23 24 T25 2 T29 3
valid_sources[0x40] 8156 1 T24 2 T25 1 T48 3
valid_sources[0x41] 9477 1 T24 2 T25 3 T30 42
valid_sources[0x42] 8763 1 T29 2 T30 9 T48 2
valid_sources[0x43] 7655 1 T29 3 T48 1 T86 2
valid_sources[0x44] 9299 1 T25 1 T29 2 T30 2
valid_sources[0x45] 7697 1 T25 4 T29 1 T47 3
valid_sources[0x46] 9003 1 T24 1 T29 1 T64 1
valid_sources[0x47] 8640 1 T23 1 T25 1 T28 1
valid_sources[0x48] 8816 1 T23 5 T24 1 T25 1
valid_sources[0x49] 8993 1 T25 1 T29 2 T64 2
valid_sources[0x4a] 9240 1 T25 1 T29 2 T48 3
valid_sources[0x4b] 8865 1 T47 7 T48 1 T64 1
valid_sources[0x4c] 8308 1 T25 1 T64 3 T86 2
valid_sources[0x4d] 8151 1 T25 3 T47 5 T70 1
valid_sources[0x4e] 8503 1 T29 2 T86 1 T65 1
valid_sources[0x4f] 8299 1 T29 1 T48 2 T64 1
valid_sources[0x50] 8127 1 T24 2 T25 2 T29 3
valid_sources[0x51] 8740 1 T25 2 T28 1 T47 1
valid_sources[0x52] 8597 1 T29 3 T70 1 T48 1
valid_sources[0x53] 9528 1 T25 5 T47 1 T48 4
valid_sources[0x54] 10379 1 T24 1 T29 3 T47 3
valid_sources[0x55] 7793 1 T25 1 T29 1 T70 1
valid_sources[0x56] 8899 1 T25 1 T28 1 T29 2
valid_sources[0x57] 8432 1 T24 1 T25 1 T29 2
valid_sources[0x58] 9603 1 T25 2 T29 1 T86 1
valid_sources[0x59] 7890 1 T24 1 T25 5 T48 2
valid_sources[0x5a] 8796 1 T25 2 T70 1 T48 2
valid_sources[0x5b] 7554 1 T29 2 T48 3 T86 2
valid_sources[0x5c] 8584 1 T29 4 T48 1 T64 1
valid_sources[0x5d] 8204 1 T25 6 T29 1 T70 3
valid_sources[0x5e] 8271 1 T25 2 T30 8 T48 1
valid_sources[0x5f] 9228 1 T25 3 T48 1 T86 1
valid_sources[0x60] 7669 1 T24 1 T25 1 T29 1
valid_sources[0x61] 9338 1 T24 1 T25 4 T29 1
valid_sources[0x62] 8209 1 T25 4 T29 1 T47 3
valid_sources[0x63] 9625 1 T29 2 T48 2 T64 4
valid_sources[0x64] 8100 1 T28 1 T29 4 T47 15
valid_sources[0x65] 9667 1 T29 2 T30 16 T48 3
valid_sources[0x66] 7768 1 T29 1 T48 1 T64 1
valid_sources[0x67] 8024 1 T47 2 T48 4 T65 1
valid_sources[0x68] 8645 1 T24 2 T25 1 T48 1
valid_sources[0x69] 9873 1 T24 1 T47 3 T69 10
valid_sources[0x6a] 9075 1 T29 2 T48 1 T64 2
valid_sources[0x6b] 8548 1 T27 4 T29 4 T47 2
valid_sources[0x6c] 9960 1 T24 1 T25 3 T28 1
valid_sources[0x6d] 8269 1 T29 3 T47 4 T48 2
valid_sources[0x6e] 8268 1 T24 2 T47 1 T69 75
valid_sources[0x6f] 7846 1 T25 4 T28 1 T30 10
valid_sources[0x70] 8410 1 T25 2 T29 2 T48 1
valid_sources[0x71] 8768 1 T25 2 T28 1 T48 1
valid_sources[0x72] 7932 1 T23 7 T24 1 T28 1
valid_sources[0x73] 10281 1 T25 1 T47 2 T64 1
valid_sources[0x74] 8073 1 T24 1 T25 3 T29 2
valid_sources[0x75] 8807 1 T24 2 T25 1 T48 5
valid_sources[0x76] 8441 1 T25 1 T29 2 T48 1
valid_sources[0x77] 9818 1 T24 2 T25 3 T73 10
valid_sources[0x78] 8639 1 T24 1 T25 2 T28 2
valid_sources[0x79] 9353 1 T24 1 T25 2 T29 3
valid_sources[0x7a] 9007 1 T25 1 T29 2 T48 1
valid_sources[0x7b] 8117 1 T25 4 T28 1 T29 1
valid_sources[0x7c] 8195 1 T30 6 T48 2 T64 1
valid_sources[0x7d] 8623 1 T25 4 T29 1 T47 2
valid_sources[0x7e] 9177 1 T25 4 T29 2 T70 1
valid_sources[0x7f] 7931 1 T28 1 T29 1 T48 1
valid_sources[0x80] 9052 1 T47 2 T48 2 T64 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 516328 1 T23 7 T24 41 T25 4
values[0x0] all_enables biggest_size 760939 1 T23 62 T24 17 T25 155
values[0x1] all_enables biggest_size 761691 1 T23 53 T24 16 T25 177


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 458808 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2021337 1 T25 40 T29 320 T30 40



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 559059 1 T25 40 T29 83 T30 40
values[0x0] 794829 1 T29 132 T32 6 T48 92
values[0x1] 1126257 1 T29 213 T32 15 T48 161



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 173747 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2306398 1 T25 40 T29 389 T30 40



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 9325 1 T29 3 T65 2 T75 2
valid_sources[0x01] 9871 1 T75 3 T85 5 T115 4
valid_sources[0x02] 9340 1 T64 2 T65 4 T75 2
valid_sources[0x03] 11262 1 T29 4 T64 1 T65 1
valid_sources[0x04] 10255 1 T48 1 T75 2 T77 1
valid_sources[0x05] 8734 1 T29 1 T48 1 T66 1
valid_sources[0x06] 9305 1 T32 1 T47 1 T64 1
valid_sources[0x07] 9466 1 T29 3 T64 1 T67 1
valid_sources[0x08] 9165 1 T29 2 T32 1 T75 1
valid_sources[0x09] 9436 1 T29 2 T75 1 T77 2
valid_sources[0x0a] 9412 1 T29 2 T64 1 T66 1
valid_sources[0x0b] 9337 1 T25 1 T29 1 T48 1
valid_sources[0x0c] 8554 1 T29 2 T64 2 T75 2
valid_sources[0x0d] 9758 1 T29 2 T48 2 T65 2
valid_sources[0x0e] 9507 1 T29 3 T64 1 T77 2
valid_sources[0x0f] 9053 1 T29 2 T75 2 T77 5
valid_sources[0x10] 9711 1 T29 1 T69 40 T48 3
valid_sources[0x11] 9683 1 T29 5 T48 1 T66 1
valid_sources[0x12] 9323 1 T29 2 T64 1 T65 1
valid_sources[0x13] 9734 1 T25 1 T47 1 T64 1
valid_sources[0x14] 9262 1 T48 1 T75 1 T127 4
valid_sources[0x15] 8983 1 T25 1 T29 2 T66 1
valid_sources[0x16] 9616 1 T29 1 T48 14 T64 3
valid_sources[0x17] 8594 1 T29 1 T48 2 T64 2
valid_sources[0x18] 9032 1 T29 5 T32 1 T65 1
valid_sources[0x19] 9235 1 T29 3 T48 3 T64 2
valid_sources[0x1a] 9225 1 T29 1 T48 4 T64 2
valid_sources[0x1b] 10362 1 T75 3 T77 1 T127 1
valid_sources[0x1c] 9415 1 T29 3 T64 2 T75 5
valid_sources[0x1d] 10623 1 T29 2 T30 10 T64 2
valid_sources[0x1e] 9178 1 T29 4 T64 1 T65 1
valid_sources[0x1f] 11216 1 T29 5 T75 3 T127 6
valid_sources[0x20] 9439 1 T29 1 T75 2 T77 2
valid_sources[0x21] 9403 1 T29 1 T66 1 T68 1
valid_sources[0x22] 9990 1 T29 1 T48 4 T77 2
valid_sources[0x23] 9481 1 T29 3 T48 2 T64 3
valid_sources[0x24] 9461 1 T29 1 T64 1 T65 1
valid_sources[0x25] 11065 1 T29 2 T48 2 T49 1
valid_sources[0x26] 9321 1 T29 3 T64 1 T75 2
valid_sources[0x27] 9428 1 T29 5 T48 2 T64 1
valid_sources[0x28] 9796 1 T29 1 T64 2 T75 4
valid_sources[0x29] 9172 1 T29 4 T66 1 T75 3
valid_sources[0x2a] 9080 1 T29 2 T32 1 T64 1
valid_sources[0x2b] 9301 1 T29 3 T66 1 T75 1
valid_sources[0x2c] 8930 1 T75 1 T77 2 T127 2
valid_sources[0x2d] 10251 1 T29 4 T32 1 T75 3
valid_sources[0x2e] 11222 1 T29 1 T64 1 T66 1
valid_sources[0x2f] 9759 1 T25 2 T64 1 T75 2
valid_sources[0x30] 9304 1 T25 2 T29 2 T30 6
valid_sources[0x31] 11018 1 T29 1 T47 1 T75 3
valid_sources[0x32] 8637 1 T29 3 T48 7 T64 1
valid_sources[0x33] 9276 1 T29 5 T47 1 T75 3
valid_sources[0x34] 9586 1 T25 1 T29 1 T48 1
valid_sources[0x35] 9326 1 T29 3 T65 1 T75 2
valid_sources[0x36] 9869 1 T29 2 T48 1 T66 1
valid_sources[0x37] 9417 1 T29 2 T64 2 T65 2
valid_sources[0x38] 9908 1 T29 2 T48 2 T64 1
valid_sources[0x39] 9525 1 T29 1 T64 2 T75 2
valid_sources[0x3a] 8822 1 T29 3 T64 1 T65 2
valid_sources[0x3b] 10015 1 T75 4 T77 3 T127 1
valid_sources[0x3c] 11271 1 T29 1 T48 6 T75 1
valid_sources[0x3d] 9080 1 T29 1 T48 2 T75 3
valid_sources[0x3e] 9646 1 T29 2 T47 1 T75 1
valid_sources[0x3f] 9158 1 T25 1 T48 11 T64 1
valid_sources[0x40] 9502 1 T29 1 T47 1 T48 3
valid_sources[0x41] 9668 1 T29 1 T66 1 T67 1
valid_sources[0x42] 11325 1 T29 2 T32 1 T75 1
valid_sources[0x43] 9455 1 T29 1 T32 1 T75 3
valid_sources[0x44] 11232 1 T29 1 T75 4 T85 1
valid_sources[0x45] 10754 1 T29 1 T48 4 T75 4
valid_sources[0x46] 9410 1 T25 2 T29 4 T64 2
valid_sources[0x47] 9795 1 T75 3 T85 1 T115 3
valid_sources[0x48] 9120 1 T29 4 T32 1 T47 1
valid_sources[0x49] 9528 1 T29 1 T48 7 T66 1
valid_sources[0x4a] 10060 1 T29 1 T48 6 T75 3
valid_sources[0x4b] 8375 1 T29 3 T48 1 T65 3
valid_sources[0x4c] 8612 1 T29 2 T67 1 T75 1
valid_sources[0x4d] 11078 1 T29 1 T48 1 T64 1
valid_sources[0x4e] 8351 1 T29 1 T32 1 T75 1
valid_sources[0x4f] 9117 1 T48 6 T64 1 T65 2
valid_sources[0x50] 9391 1 T64 1 T75 2 T77 2
valid_sources[0x51] 9659 1 T29 2 T48 2 T75 1
valid_sources[0x52] 9331 1 T29 2 T64 2 T75 4
valid_sources[0x53] 9623 1 T29 1 T64 1 T50 1
valid_sources[0x54] 13487 1 T29 1 T64 1 T75 1
valid_sources[0x55] 9559 1 T48 1 T64 2 T75 3
valid_sources[0x56] 9911 1 T29 1 T75 2 T129 1
valid_sources[0x57] 10049 1 T29 1 T48 1 T64 1
valid_sources[0x58] 9943 1 T29 4 T48 4 T65 3
valid_sources[0x59] 9593 1 T29 1 T64 2 T75 2
valid_sources[0x5a] 8975 1 T29 3 T47 1 T77 3
valid_sources[0x5b] 10404 1 T29 2 T64 1 T75 1
valid_sources[0x5c] 9741 1 T25 1 T29 2 T75 1
valid_sources[0x5d] 8558 1 T29 3 T32 1 T75 1
valid_sources[0x5e] 9947 1 T29 1 T75 1 T77 3
valid_sources[0x5f] 10734 1 T29 1 T64 2 T65 1
valid_sources[0x60] 9472 1 T29 2 T129 2 T127 1
valid_sources[0x61] 10182 1 T25 2 T29 2 T64 1
valid_sources[0x62] 9129 1 T29 2 T47 1 T48 1
valid_sources[0x63] 8516 1 T25 1 T29 4 T64 1
valid_sources[0x64] 8667 1 T29 3 T32 1 T48 4
valid_sources[0x65] 9995 1 T25 1 T29 1 T47 1
valid_sources[0x66] 9620 1 T29 1 T124 8 T127 5
valid_sources[0x67] 10644 1 T29 1 T75 2 T129 1
valid_sources[0x68] 11180 1 T29 2 T48 1 T64 3
valid_sources[0x69] 9813 1 T25 2 T29 1 T32 1
valid_sources[0x6a] 10107 1 T29 1 T48 1 T75 2
valid_sources[0x6b] 12541 1 T25 1 T29 1 T48 2
valid_sources[0x6c] 8986 1 T29 1 T65 1 T75 3
valid_sources[0x6d] 9825 1 T64 1 T75 2 T77 4
valid_sources[0x6e] 9190 1 T29 1 T48 3 T75 4
valid_sources[0x6f] 8392 1 T29 2 T48 14 T75 5
valid_sources[0x70] 8664 1 T29 3 T48 6 T64 1
valid_sources[0x71] 9449 1 T29 1 T48 1 T64 2
valid_sources[0x72] 9418 1 T29 1 T48 12 T64 1
valid_sources[0x73] 10269 1 T25 1 T65 1 T75 2
valid_sources[0x74] 9404 1 T25 1 T29 1 T74 230
valid_sources[0x75] 9119 1 T29 1 T66 1 T75 2
valid_sources[0x76] 9696 1 T50 1 T75 1 T85 2
valid_sources[0x77] 9218 1 T29 1 T48 5 T64 1
valid_sources[0x78] 10277 1 T29 4 T64 1 T85 1
valid_sources[0x79] 9381 1 T25 1 T29 3 T75 3
valid_sources[0x7a] 10161 1 T65 2 T75 1 T77 4
valid_sources[0x7b] 9282 1 T25 1 T29 1 T64 1
valid_sources[0x7c] 9519 1 T48 3 T64 1 T65 2
valid_sources[0x7d] 9892 1 T29 1 T64 2 T66 1
valid_sources[0x7e] 10391 1 T29 1 T30 3 T65 5
valid_sources[0x7f] 8604 1 T25 1 T29 1 T64 2
valid_sources[0x80] 9029 1 T29 1 T48 8 T65 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 509225 1 T25 40 T29 83 T30 40
values[0x0] all_enables biggest_size 756160 1 T29 119 T32 5 T48 90
values[0x1] all_enables biggest_size 755952 1 T29 118 T32 8 T48 100

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%