Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5607604

1

T29

1135

T32

66

T48

1312

full_word

2420940

1

T25

40

T29

396

T30

40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8028244	1			T25	40		T29	1531		T30	40
auto[TlIntgErrCmd]	111	1			T50	5		T67	7		T68	6
auto[TlIntgErrData]	103	1			T50	4		T67	8		T76	6
auto[TlIntgErrBoth]	86	1			T50	1		T67	5		T68	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967358

1

T25

40

T29

127

T30

40

auto[1]

7061186

1

T29

1404

T32

85

T48

1466

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	409286	1			T29	38		T32	2		T48	144
auto[TlIntgErrNone]	partial	auto[1]	5198046	1			T29	1097		T32	64		T48	1168
auto[TlIntgErrNone]	full_word	auto[0]	557924	1			T25	40		T29	89		T30	40
auto[TlIntgErrNone]	full_word	auto[1]	1862988	1			T29	307		T32	21		T48	298
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T50	2		T68	2		T76	8
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T50	3		T67	5		T68	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T67	1		T120	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T67	1		T121	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T67	6		T76	3		T78	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T50	4		T67	1		T76	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T67	1		T124	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T124	1		T120	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T67	2		T68	3		T78	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T50	1		T67	3		T68	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T76	1		T78	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T78	2		T120	2		T125	1