Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 167283 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1700580 1 T30 178 T31 122 T32 35



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 466894 1 T30 15 T31 9 T32 5
values[0x0] 648991 1 T30 79 T31 56 T32 21
values[0x1] 751978 1 T30 84 T31 57 T32 14



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 74673 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1793190 1 T30 178 T31 122 T32 36



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 8180 1 T34 2 T59 8 T58 3
valid_sources[0x01] 8140 1 T34 2 T38 1 T39 3
valid_sources[0x02] 7830 1 T34 6 T39 1 T46 6
valid_sources[0x03] 7394 1 T65 10 T57 1 T71 4
valid_sources[0x04] 7103 1 T30 2 T34 2 T61 1
valid_sources[0x05] 7450 1 T39 3 T45 1 T48 2
valid_sources[0x06] 8045 1 T34 5 T45 1 T56 1
valid_sources[0x07] 7908 1 T34 3 T39 1 T46 2
valid_sources[0x08] 7684 1 T34 2 T37 3 T39 2
valid_sources[0x09] 7461 1 T56 1 T57 2 T58 2
valid_sources[0x0a] 7623 1 T36 1 T37 19 T38 11
valid_sources[0x0b] 7700 1 T30 1 T46 2 T56 1
valid_sources[0x0c] 5874 1 T38 15 T39 2 T45 1
valid_sources[0x0d] 7993 1 T34 2 T36 1 T39 3
valid_sources[0x0e] 7721 1 T34 2 T38 3 T39 3
valid_sources[0x0f] 7101 1 T39 1 T77 1 T58 3
valid_sources[0x10] 6133 1 T39 1 T59 1 T70 5
valid_sources[0x11] 7697 1 T34 3 T36 4 T39 3
valid_sources[0x12] 6853 1 T30 1 T38 10 T45 3
valid_sources[0x13] 6485 1 T45 1 T46 2 T75 1
valid_sources[0x14] 7654 1 T30 1 T39 1 T46 4
valid_sources[0x15] 7487 1 T34 1 T45 1 T48 2
valid_sources[0x16] 6670 1 T30 1 T32 10 T39 1
valid_sources[0x17] 7603 1 T30 2 T36 2 T37 1
valid_sources[0x18] 8633 1 T30 3 T34 1 T39 1
valid_sources[0x19] 6576 1 T30 2 T45 3 T46 4
valid_sources[0x1a] 6527 1 T34 1 T39 1 T45 1
valid_sources[0x1b] 6856 1 T46 1 T48 6 T56 1
valid_sources[0x1c] 7792 1 T38 11 T39 1 T56 2
valid_sources[0x1d] 7078 1 T30 2 T56 1 T77 1
valid_sources[0x1e] 6887 1 T35 2 T36 6 T37 4
valid_sources[0x1f] 6419 1 T34 1 T39 1 T45 2
valid_sources[0x20] 6408 1 T36 2 T39 1 T45 3
valid_sources[0x21] 7117 1 T45 2 T56 1 T57 3
valid_sources[0x22] 8002 1 T38 8 T39 1 T45 3
valid_sources[0x23] 7299 1 T30 2 T31 1 T35 1
valid_sources[0x24] 6073 1 T45 1 T58 1 T71 2
valid_sources[0x25] 7005 1 T34 2 T37 5 T75 1
valid_sources[0x26] 7155 1 T46 1 T58 3 T71 2
valid_sources[0x27] 6572 1 T34 1 T39 1 T56 2
valid_sources[0x28] 6804 1 T37 14 T39 2 T75 1
valid_sources[0x29] 8403 1 T30 4 T36 2 T39 2
valid_sources[0x2a] 7317 1 T45 1 T57 1 T58 1
valid_sources[0x2b] 6902 1 T34 1 T39 1 T46 6
valid_sources[0x2c] 6833 1 T34 6 T38 11 T39 1
valid_sources[0x2d] 7296 1 T30 1 T57 2 T58 1
valid_sources[0x2e] 6851 1 T38 1 T46 2 T65 22
valid_sources[0x2f] 6970 1 T30 1 T39 1 T46 1
valid_sources[0x30] 7797 1 T31 5 T34 2 T39 1
valid_sources[0x31] 7944 1 T31 10 T34 6 T39 2
valid_sources[0x32] 8120 1 T30 1 T45 2 T77 1
valid_sources[0x33] 8533 1 T36 3 T45 1 T46 3
valid_sources[0x34] 7961 1 T30 3 T34 2 T37 17
valid_sources[0x35] 6843 1 T46 3 T56 2 T57 1
valid_sources[0x36] 7222 1 T36 2 T39 1 T46 2
valid_sources[0x37] 7637 1 T36 2 T37 6 T39 2
valid_sources[0x38] 7550 1 T30 1 T39 4 T56 1
valid_sources[0x39] 8337 1 T36 2 T37 20 T39 2
valid_sources[0x3a] 6519 1 T37 10 T45 1 T57 1
valid_sources[0x3b] 7422 1 T30 4 T31 10 T39 1
valid_sources[0x3c] 6633 1 T34 1 T46 12 T56 1
valid_sources[0x3d] 8076 1 T30 1 T34 2 T39 3
valid_sources[0x3e] 7112 1 T31 17 T37 4 T39 2
valid_sources[0x3f] 6916 1 T30 3 T34 2 T35 1
valid_sources[0x40] 6504 1 T30 1 T46 6 T56 2
valid_sources[0x41] 7619 1 T37 7 T39 2 T46 1
valid_sources[0x42] 7737 1 T30 1 T39 1 T57 3
valid_sources[0x43] 7173 1 T39 2 T61 1 T56 1
valid_sources[0x44] 7566 1 T30 1 T39 1 T75 1
valid_sources[0x45] 6703 1 T30 1 T46 4 T56 1
valid_sources[0x46] 8478 1 T30 1 T39 1 T45 1
valid_sources[0x47] 7214 1 T34 2 T39 1 T46 2
valid_sources[0x48] 7674 1 T34 2 T45 3 T57 1
valid_sources[0x49] 6569 1 T30 2 T31 1 T35 3
valid_sources[0x4a] 7985 1 T39 2 T46 1 T47 4
valid_sources[0x4b] 6904 1 T30 2 T39 1 T58 4
valid_sources[0x4c] 8336 1 T31 4 T34 1 T39 1
valid_sources[0x4d] 7611 1 T37 10 T39 1 T46 2
valid_sources[0x4e] 5966 1 T37 5 T45 1 T77 1
valid_sources[0x4f] 8267 1 T30 4 T31 7 T46 7
valid_sources[0x50] 7288 1 T45 1 T46 5 T58 2
valid_sources[0x51] 7325 1 T37 4 T39 1 T46 1
valid_sources[0x52] 7137 1 T36 1 T39 3 T75 1
valid_sources[0x53] 6729 1 T39 1 T45 1 T48 8
valid_sources[0x54] 6396 1 T36 2 T45 2 T56 2
valid_sources[0x55] 8669 1 T39 1 T45 1 T46 4
valid_sources[0x56] 6499 1 T36 1 T45 2 T46 4
valid_sources[0x57] 6558 1 T35 1 T39 2 T45 1
valid_sources[0x58] 7475 1 T34 1 T37 3 T45 1
valid_sources[0x59] 6834 1 T37 27 T39 1 T45 1
valid_sources[0x5a] 8716 1 T34 2 T45 2 T56 4
valid_sources[0x5b] 7635 1 T34 7 T39 1 T46 2
valid_sources[0x5c] 7260 1 T30 4 T39 1 T61 1
valid_sources[0x5d] 8608 1 T30 1 T36 1 T45 1
valid_sources[0x5e] 6672 1 T45 2 T46 6 T58 1
valid_sources[0x5f] 7030 1 T37 8 T38 2 T46 1
valid_sources[0x60] 8146 1 T30 1 T36 4 T39 1
valid_sources[0x61] 6208 1 T30 6 T36 2 T45 3
valid_sources[0x62] 6072 1 T36 1 T39 1 T46 1
valid_sources[0x63] 7210 1 T30 1 T37 5 T39 1
valid_sources[0x64] 6816 1 T36 1 T38 3 T39 2
valid_sources[0x65] 6813 1 T37 2 T39 2 T48 4
valid_sources[0x66] 7316 1 T58 2 T71 2 T63 10
valid_sources[0x67] 7960 1 T61 2 T45 1 T46 1
valid_sources[0x68] 7390 1 T36 2 T46 1 T48 1
valid_sources[0x69] 6661 1 T38 4 T39 1 T45 1
valid_sources[0x6a] 8180 1 T37 33 T39 1 T46 1
valid_sources[0x6b] 6436 1 T30 2 T39 3 T46 2
valid_sources[0x6c] 7632 1 T39 1 T45 2 T46 2
valid_sources[0x6d] 7451 1 T37 7 T46 1 T75 1
valid_sources[0x6e] 7084 1 T31 6 T34 2 T45 1
valid_sources[0x6f] 7561 1 T39 1 T45 1 T46 1
valid_sources[0x70] 7254 1 T30 2 T36 1 T39 2
valid_sources[0x71] 7043 1 T37 2 T56 1 T57 1
valid_sources[0x72] 8205 1 T30 1 T38 7 T39 1
valid_sources[0x73] 8115 1 T30 2 T36 3 T39 1
valid_sources[0x74] 7557 1 T30 1 T36 1 T61 1
valid_sources[0x75] 7145 1 T36 5 T37 10 T39 2
valid_sources[0x76] 6766 1 T30 1 T36 1 T39 1
valid_sources[0x77] 7631 1 T30 3 T39 1 T61 1
valid_sources[0x78] 7785 1 T34 6 T36 2 T39 1
valid_sources[0x79] 6865 1 T37 5 T39 2 T45 2
valid_sources[0x7a] 7073 1 T34 2 T36 1 T37 13
valid_sources[0x7b] 7105 1 T30 2 T39 1 T46 5
valid_sources[0x7c] 6092 1 T39 3 T58 3 T70 31
valid_sources[0x7d] 6808 1 T34 1 T35 1 T39 1
valid_sources[0x7e] 7254 1 T39 1 T45 1 T46 6
valid_sources[0x7f] 7842 1 T31 7 T39 2 T57 3
valid_sources[0x80] 7087 1 T39 2 T46 4 T77 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 430189 1 T30 15 T31 9 T32 2
values[0x0] all_enables biggest_size 635694 1 T30 79 T31 56 T32 20
values[0x1] all_enables biggest_size 634697 1 T30 84 T31 57 T32 13


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 386068 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1672806 1 T34 284 T36 304 T37 40



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 464955 1 T34 75 T36 80 T37 40
values[0x0] 657399 1 T34 115 T36 117 T38 1
values[0x1] 936520 1 T34 163 T36 130 T38 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 147218 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1911656 1 T34 327 T36 322 T37 40



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 9463 1 T34 2 T58 1 T60 1
valid_sources[0x01] 9293 1 T36 1 T46 1 T47 2
valid_sources[0x02] 6264 1 T60 12 T71 1 T67 2
valid_sources[0x03] 7971 1 T34 1 T36 1 T47 1
valid_sources[0x04] 7955 1 T34 1 T36 1 T56 1
valid_sources[0x05] 7630 1 T34 1 T36 2 T47 1
valid_sources[0x06] 8693 1 T34 2 T36 4 T60 3
valid_sources[0x07] 8954 1 T34 2 T36 1 T57 2
valid_sources[0x08] 6701 1 T34 2 T60 3 T66 1
valid_sources[0x09] 7900 1 T36 3 T48 1 T57 1
valid_sources[0x0a] 7100 1 T34 2 T36 1 T37 1
valid_sources[0x0b] 8156 1 T34 2 T56 1 T60 8
valid_sources[0x0c] 7347 1 T34 5 T60 2 T66 1
valid_sources[0x0d] 8028 1 T36 1 T48 2 T56 2
valid_sources[0x0e] 7468 1 T36 1 T46 1 T56 1
valid_sources[0x0f] 7305 1 T34 2 T57 1 T60 3
valid_sources[0x10] 10076 1 T34 4 T37 3 T48 1
valid_sources[0x11] 9087 1 T34 1 T57 1 T60 2
valid_sources[0x12] 8192 1 T36 2 T67 1 T64 1
valid_sources[0x13] 8890 1 T34 2 T48 1 T56 2
valid_sources[0x14] 6767 1 T34 2 T36 1 T56 1
valid_sources[0x15] 8464 1 T34 2 T36 1 T57 2
valid_sources[0x16] 8003 1 T34 1 T36 3 T57 2
valid_sources[0x17] 9630 1 T60 2 T66 2 T116 3
valid_sources[0x18] 8147 1 T34 2 T56 1 T57 2
valid_sources[0x19] 7311 1 T34 3 T36 1 T57 3
valid_sources[0x1a] 6598 1 T57 3 T60 10 T67 2
valid_sources[0x1b] 8796 1 T34 1 T36 1 T67 1
valid_sources[0x1c] 8518 1 T36 1 T57 2 T67 1
valid_sources[0x1d] 9078 1 T34 5 T37 2 T48 3
valid_sources[0x1e] 9512 1 T34 1 T36 3 T60 10
valid_sources[0x1f] 7563 1 T36 2 T47 1 T48 1
valid_sources[0x20] 7543 1 T48 1 T56 2 T57 1
valid_sources[0x21] 9392 1 T36 1 T56 1 T58 1
valid_sources[0x22] 8117 1 T34 4 T36 1 T56 2
valid_sources[0x23] 8640 1 T34 2 T36 1 T48 1
valid_sources[0x24] 7415 1 T34 3 T36 1 T46 1
valid_sources[0x25] 7606 1 T34 1 T57 2 T60 3
valid_sources[0x26] 9151 1 T34 1 T36 1 T65 1
valid_sources[0x27] 7299 1 T34 2 T65 2 T57 2
valid_sources[0x28] 6911 1 T34 2 T36 1 T64 2
valid_sources[0x29] 7468 1 T34 2 T36 1 T56 1
valid_sources[0x2a] 8110 1 T34 2 T37 1 T56 2
valid_sources[0x2b] 8728 1 T34 1 T36 2 T47 1
valid_sources[0x2c] 6902 1 T34 2 T36 1 T60 1
valid_sources[0x2d] 7772 1 T34 3 T37 3 T56 1
valid_sources[0x2e] 9276 1 T36 1 T56 1 T57 2
valid_sources[0x2f] 8457 1 T34 1 T36 3 T56 1
valid_sources[0x30] 8669 1 T56 3 T57 1 T60 2
valid_sources[0x31] 8188 1 T34 1 T36 2 T48 1
valid_sources[0x32] 7709 1 T36 1 T57 1 T66 2
valid_sources[0x33] 8126 1 T34 1 T36 1 T56 1
valid_sources[0x34] 10446 1 T36 3 T48 1 T57 2
valid_sources[0x35] 7639 1 T36 2 T37 3 T57 1
valid_sources[0x36] 8014 1 T34 2 T36 2 T46 1
valid_sources[0x37] 7843 1 T34 1 T36 1 T57 2
valid_sources[0x38] 7428 1 T34 2 T36 3 T57 1
valid_sources[0x39] 7388 1 T34 3 T48 1 T56 2
valid_sources[0x3a] 7268 1 T34 2 T36 1 T57 1
valid_sources[0x3b] 8412 1 T34 2 T36 1 T37 1
valid_sources[0x3c] 9377 1 T34 1 T36 2 T56 1
valid_sources[0x3d] 8627 1 T36 1 T56 1 T64 1
valid_sources[0x3e] 7951 1 T34 1 T36 1 T57 1
valid_sources[0x3f] 9473 1 T36 2 T47 1 T57 1
valid_sources[0x40] 9124 1 T34 2 T37 1 T57 1
valid_sources[0x41] 7318 1 T34 1 T36 1 T48 1
valid_sources[0x42] 7623 1 T34 1 T36 1 T65 1
valid_sources[0x43] 9058 1 T34 5 T36 4 T57 1
valid_sources[0x44] 8146 1 T34 3 T36 1 T46 1
valid_sources[0x45] 7939 1 T34 2 T36 4 T46 1
valid_sources[0x46] 6730 1 T66 1 T67 1 T116 1
valid_sources[0x47] 7648 1 T34 3 T46 2 T48 2
valid_sources[0x48] 8034 1 T34 2 T36 1 T56 1
valid_sources[0x49] 8220 1 T34 2 T36 1 T57 1
valid_sources[0x4a] 7117 1 T34 1 T36 2 T48 1
valid_sources[0x4b] 7206 1 T48 1 T56 2 T57 1
valid_sources[0x4c] 10708 1 T36 2 T38 1 T48 1
valid_sources[0x4d] 8290 1 T36 2 T47 2 T57 3
valid_sources[0x4e] 6856 1 T34 2 T48 1 T57 3
valid_sources[0x4f] 7036 1 T36 1 T46 1 T47 1
valid_sources[0x50] 8971 1 T34 3 T36 3 T48 2
valid_sources[0x51] 7118 1 T34 3 T46 1 T47 2
valid_sources[0x52] 8059 1 T34 1 T48 3 T60 2
valid_sources[0x53] 7795 1 T34 3 T47 1 T48 1
valid_sources[0x54] 7741 1 T36 1 T37 1 T46 1
valid_sources[0x55] 7431 1 T34 1 T36 4 T56 1
valid_sources[0x56] 7635 1 T34 1 T36 6 T60 1
valid_sources[0x57] 7240 1 T34 2 T36 1 T66 1
valid_sources[0x58] 7164 1 T34 1 T57 5 T58 1
valid_sources[0x59] 8963 1 T34 1 T36 1 T48 1
valid_sources[0x5a] 8371 1 T34 4 T36 1 T57 1
valid_sources[0x5b] 7656 1 T36 1 T48 2 T56 4
valid_sources[0x5c] 8077 1 T34 1 T36 1 T48 1
valid_sources[0x5d] 8442 1 T36 2 T57 3 T69 3
valid_sources[0x5e] 9002 1 T34 1 T36 1 T47 2
valid_sources[0x5f] 8133 1 T34 1 T36 1 T46 1
valid_sources[0x60] 7295 1 T36 3 T46 1 T48 1
valid_sources[0x61] 7491 1 T34 3 T36 3 T56 3
valid_sources[0x62] 9206 1 T34 2 T56 3 T60 1
valid_sources[0x63] 7120 1 T57 2 T117 2 T64 1
valid_sources[0x64] 8754 1 T34 1 T48 1 T56 2
valid_sources[0x65] 8718 1 T34 1 T36 1 T48 1
valid_sources[0x66] 9682 1 T34 2 T36 1 T47 1
valid_sources[0x67] 7536 1 T34 1 T36 2 T57 3
valid_sources[0x68] 7895 1 T34 1 T36 2 T48 1
valid_sources[0x69] 8591 1 T34 2 T56 1 T59 1
valid_sources[0x6a] 7558 1 T36 1 T47 1 T48 1
valid_sources[0x6b] 7871 1 T34 2 T36 2 T37 1
valid_sources[0x6c] 7271 1 T34 2 T46 3 T56 1
valid_sources[0x6d] 9662 1 T34 3 T66 2 T67 2
valid_sources[0x6e] 8020 1 T34 1 T60 1 T66 4
valid_sources[0x6f] 7134 1 T36 2 T56 1 T60 1
valid_sources[0x70] 8176 1 T34 1 T60 2 T71 1
valid_sources[0x71] 9283 1 T34 3 T67 4 T64 1
valid_sources[0x72] 8233 1 T36 2 T56 3 T60 4
valid_sources[0x73] 9022 1 T34 1 T36 3 T60 7
valid_sources[0x74] 7598 1 T36 2 T48 1 T57 1
valid_sources[0x75] 8484 1 T34 2 T36 1 T46 1
valid_sources[0x76] 6954 1 T34 1 T36 2 T48 2
valid_sources[0x77] 7157 1 T34 3 T36 1 T60 3
valid_sources[0x78] 7506 1 T34 3 T36 1 T56 1
valid_sources[0x79] 8337 1 T34 1 T36 2 T46 2
valid_sources[0x7a] 7201 1 T36 2 T57 3 T60 8
valid_sources[0x7b] 8181 1 T34 1 T36 1 T56 1
valid_sources[0x7c] 8969 1 T36 4 T56 4 T57 3
valid_sources[0x7d] 9323 1 T34 2 T48 2 T57 1
valid_sources[0x7e] 6966 1 T34 1 T36 2 T48 1
valid_sources[0x7f] 7208 1 T34 1 T36 1 T37 1
valid_sources[0x80] 6486 1 T34 1 T36 1 T48 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 422016 1 T34 75 T36 80 T37 40
values[0x0] all_enables biggest_size 624959 1 T34 107 T36 117 T47 20
values[0x1] all_enables biggest_size 625831 1 T34 102 T36 107 T47 24

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%