Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4699060

1

T34

612

T36

402

T38

10

full_word

2007518

1

T34

321

T36

342

T37

40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6706288	1			T34	933		T36	744		T37	40
auto[TlIntgErrCmd]	107	1			T38	2		T58	9		T63	7
auto[TlIntgErrData]	92	1			T38	4		T58	5		T63	7
auto[TlIntgErrBoth]	91	1			T38	4		T58	6		T63	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

804092

1

T34

95

T36

134

T37

40

auto[1]

5902486

1

T34

838

T36

610

T38

5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	341482	1			T34	17		T36	47		T47	1
auto[TlIntgErrNone]	partial	auto[1]	4357312	1			T34	595		T36	355		T47	86
auto[TlIntgErrNone]	full_word	auto[0]	462495	1			T34	78		T36	87		T37	40
auto[TlIntgErrNone]	full_word	auto[1]	1544999	1			T34	243		T36	255		T47	44
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T38	1		T58	3		T63	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T38	1		T58	4		T63	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T58	1		T105	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T58	1		T68	2		T106	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T38	3		T58	3		T63	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T38	1		T58	2		T63	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T107	1		T108	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T63	2		T106	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T38	1		T58	1		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T38	3		T58	4		T63	5
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T58	1		T63	1		T68	1