Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl_fsm
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.67 100.00 96.36 100.00 96.97 75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm 93.67 100.00 96.36 100.00 96.97 75.00



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.67 100.00 96.36 100.00 96.97 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.92 100.00 96.30 90.00 100.00 98.31 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_compare 97.56 100.00 95.35 90.00 100.00 100.00 100.00
u_counter 100.00 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_fsm
Line No.TotalCoveredPercent
TOTAL5858100.00
ALWAYS13833100.00
ALWAYS1411919100.00
ALWAYS20933100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN22011100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24711100.00
CONT_ASSIGN25111100.00
ALWAYS26155100.00
ALWAYS27033100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN27911100.00
ALWAYS28833100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN30711100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN31211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 3 3
141 1 1
142 1 1
144 1 1
148 1 1
149 1 1
MISSING_ELSE
154 1 1
155 1 1
156 1 1
157 1 1
163 2 2
MISSING_ELSE
167 2 2
MISSING_ELSE
171 2 2
MISSING_ELSE
194 1 1
197 1 1
MISSING_ELSE
203 1 1
204 1 1
MISSING_ELSE
209 3 3
216 1 1
217 1 1
220 1 1
223 1 1
224 1 1
231 1 1
232 1 1
233 1 1
239 1 1
241 1 1
242 1 1
243 1 1
247 1 1
251 1 1
261 1 1
262 1 1
263 1 1
MISSING_ELSE
265 1 1
266 1 1
MISSING_ELSE
270 1 1
271 1 1
273 1 1
277 1 1
278 1 1
279 1 1
288 1 1
289 1 1
291 1 1
304 1 1
307 1 1
309 1 1
310 1 1
312 1 1


Cond Coverage for Module : rom_ctrl_fsm
TotalCoveredPercent
Conditions555396.36
Logical555396.36
Non-Logical00
Event00

 LINE       148
 EXPRESSION (counter_lnt && kmac_rom_rdy_i && kmac_rom_vld_o)
             -----1-----    -------2------    -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       156
 EXPRESSION (kmac_err_i ? Invalid : KmacAhead)
             -----1----
-1-StatusTests
0CoveredT4,T16,T17
1CoveredT18,T19,T20

 LINE       157
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----
-1-StatusTests
0CoveredT21,T22,T23
1Not Covered

 LINE       163
 EXPRESSION (kmac_err_i ? Invalid : Checking)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T24

 LINE       194
 EXPRESSION 
 Number  Term
      1  (checker_done && ((!(state_q inside {Checking, Done})))) || 
      2  (counter_done && (state_q == ReadingLow)) || 
      3  (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead})))))
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT25,T26,T27
100CoveredT28,T16,T25

 LINE       194
 SUB-EXPRESSION (checker_done && ((!(state_q inside {Checking, Done}))))
                 ------1-----    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT28,T16,T25

 LINE       194
 SUB-EXPRESSION (counter_done && (state_q == ReadingLow))
                 ------1-----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T26,T27

 LINE       194
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 SUB-EXPRESSION (kmac_done_i && ((!(state_q inside {ReadingHigh, RomAhead}))))
                 -----1-----    ----------------------2----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 EXPRESSION (((state_q == ReadingHigh) || (state_q == KmacAhead)) & ((~counter_done)))
             --------------------------1-------------------------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION ((state_q == ReadingHigh) || (state_q == KmacAhead))
                 ------------1-----------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T16,T17
10CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (state_q == ReadingHigh)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (state_q == KmacAhead)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T16,T17

 LINE       265
 EXPRESSION (counter_read_req && (state_q == ReadingLow) && ((!counter_lnt)))
             --------1-------    -----------2-----------    --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       265
 SUB-EXPRESSION (state_q == ReadingLow)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       277
 EXPRESSION (kmac_rom_rdy_i | (state_q inside {ReadingHigh, KmacAhead}))
             -------1------   --------------------2--------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       291
 EXPRESSION ((state_q != Checking) && (state_d == Checking))
             ----------1----------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       291
 SUB-EXPRESSION (state_q != Checking)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       291
 SUB-EXPRESSION (state_d == Checking)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       312
 EXPRESSION (fsm_alert | checker_alert | unexpected_counter_change)
             ----1----   ------2------   ------------3------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT28,T16,T21
010CoveredT29,T28,T16
100CoveredT2,T6,T29

FSM Coverage for Module : rom_ctrl_fsm
Summary for FSM :: state_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 13 13 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Checking 157 Covered T30
Done 171 Covered T30
Invalid 156 Covered T30
KmacAhead 156 Covered T30
ReadingHigh 149 Covered T30
ReadingLow 145 Covered T30
RomAhead 155 Covered T30


transitionsLine No.CoveredTests
Checking->Done 171 Covered T30
Checking->Invalid 197 Covered T30
Done->Invalid 197 Covered T30
KmacAhead->Checking 167 Covered T30
KmacAhead->Invalid 197 Covered T30
ReadingHigh->Checking 157 Covered T30
ReadingHigh->Invalid 156 Covered T30
ReadingHigh->KmacAhead 156 Covered T30
ReadingHigh->RomAhead 155 Covered T30
ReadingLow->Invalid 197 Covered T30
ReadingLow->ReadingHigh 149 Covered T30
RomAhead->Checking 163 Covered T30
RomAhead->Invalid 163 Covered T30



Branch Coverage for Module : rom_ctrl_fsm
Line No.TotalCoveredPercent
Branches 33 32 96.97
IF 138 2 2 100.00
CASE 144 17 16 94.12
IF 194 2 2 100.00
IF 203 2 2 100.00
IF 209 2 2 100.00
IF 262 2 2 100.00
IF 265 2 2 100.00
IF 270 2 2 100.00
IF 288 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 144 case (state_q) -2-: 148 if (((counter_lnt && kmac_rom_rdy_i) && kmac_rom_vld_o)) -3-: 154 case ({kmac_done_i, counter_done}) -4-: 156 (kmac_err_i) ? -5-: 157 (kmac_err_i) ? -6-: 163 if (kmac_done_i) -7-: 163 (kmac_err_i) ? -8-: 167 if (counter_done) -9-: 171 if (checker_done)

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
ReadingLow 1 - - - - - - - Covered T1,T2,T3
ReadingLow 0 - - - - - - - Covered T1,T2,T3
ReadingHigh - 2'b01 - - - - - - Covered T1,T2,T3
ReadingHigh - 2'b10 1 - - - - - Covered T18,T19,T20
ReadingHigh - 2'b10 0 - - - - - Covered T4,T16,T17
ReadingHigh - 2'b11 - 1 - - - - Not Covered
ReadingHigh - 2'b11 - 0 - - - - Covered T21,T22,T23
ReadingHigh - default - - - - - - Covered T1,T2,T3
RomAhead - - - - 1 1 - - Covered T2,T6,T24
RomAhead - - - - 1 0 - - Covered T1,T2,T3
RomAhead - - - - 0 - - - Covered T1,T2,T3
KmacAhead - - - - - - 1 - Covered T4,T16,T17
KmacAhead - - - - - - 0 - Covered T4,T16,T17
Checking - - - - - - - 1 Covered T1,T2,T3
Checking - - - - - - - 0 Covered T1,T2,T3
Done - - - - - - - - Covered T1,T2,T3
default - - - - - - - - Covered T2,T6,T29


LineNo. Expression -1-: 194 if ((((checker_done && (!(state_q inside {Checking, Done}))) || (counter_done && (state_q == ReadingLow))) || (kmac_done_i && (!(state_q inside {ReadingHigh, RomAhead})))))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if (alert_o)

Branches:
-1-StatusTests
1 Covered T2,T6,T29
0 Covered T1,T2,T3


LineNo. Expression -1-: 209 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 262 if (kmac_rom_rdy_i)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 265 if (((counter_read_req && (state_q == ReadingLow)) && (!counter_lnt)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 270 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 288 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : rom_ctrl_fsm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 3 75.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 3 75.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
LastImpliesValid_A 246636731 18419 0 0
RelAddrWide_A 246636731 11873 0 0
SecCmCFILinear_A 246636731 0 0 1324
u_state_regs_A 246636731 246455221 0 0


LastImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 246636731 18419 0 0
T1 94875 3 0 0
T2 272337 55 0 0
T3 132302 13 0 0
T4 28717 3 0 0
T5 676561 51 0 0
T6 386493 71 0 0
T7 75509 4 0 0
T8 231054 60 0 0
T9 844340 91 0 0
T10 43003 3 0 0

RelAddrWide_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 246636731 11873 0 0
T1 94875 8 0 0
T2 272337 16 0 0
T3 132302 16 0 0
T4 28717 24 0 0
T5 676561 40 0 0
T6 386493 16 0 0
T7 75509 8 0 0
T8 231054 40 0 0
T9 844340 32 0 0
T10 43003 16 0 0

SecCmCFILinear_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 246636731 0 0 1324

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 246636731 246455221 0 0
T1 94875 94788 0 0
T2 272337 272218 0 0
T3 132302 132130 0 0
T4 28717 28406 0 0
T5 676561 676108 0 0
T6 386493 386363 0 0
T7 75509 75457 0 0
T8 231054 231033 0 0
T9 844340 843898 0 0
T10 43003 42814 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%