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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.43 97.04 92.50 97.88 100.00 98.37 98.04 98.14


Total test records in report: 438
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T51 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.166955341 Feb 18 12:41:54 PM PST 24 Feb 18 12:54:19 PM PST 24 76440516624 ps
T296 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.502943240 Feb 18 12:41:50 PM PST 24 Feb 18 12:45:20 PM PST 24 28227727960 ps
T297 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2716441076 Feb 18 12:41:25 PM PST 24 Feb 18 12:41:41 PM PST 24 1943102728 ps
T298 /workspace/coverage/default/1.rom_ctrl_alert_test.501210545 Feb 18 12:41:16 PM PST 24 Feb 18 12:41:31 PM PST 24 1225281089 ps
T299 /workspace/coverage/default/45.rom_ctrl_smoke.1893779183 Feb 18 12:42:55 PM PST 24 Feb 18 12:43:25 PM PST 24 6359578169 ps
T300 /workspace/coverage/default/14.rom_ctrl_alert_test.600403644 Feb 18 12:41:48 PM PST 24 Feb 18 12:42:04 PM PST 24 1597324252 ps
T301 /workspace/coverage/default/44.rom_ctrl_smoke.1087872589 Feb 18 12:42:51 PM PST 24 Feb 18 12:43:10 PM PST 24 2086815967 ps
T302 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.920742136 Feb 18 12:41:29 PM PST 24 Feb 18 12:41:36 PM PST 24 96095294 ps
T303 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.60235187 Feb 18 12:42:44 PM PST 24 Feb 18 12:46:08 PM PST 24 3113334453 ps
T304 /workspace/coverage/default/17.rom_ctrl_smoke.2020093534 Feb 18 12:41:48 PM PST 24 Feb 18 12:42:22 PM PST 24 24714976986 ps
T305 /workspace/coverage/default/20.rom_ctrl_stress_all.166323638 Feb 18 12:41:55 PM PST 24 Feb 18 12:42:30 PM PST 24 14122254987 ps
T306 /workspace/coverage/default/33.rom_ctrl_stress_all.3842388863 Feb 18 12:42:33 PM PST 24 Feb 18 12:43:18 PM PST 24 19331799765 ps
T307 /workspace/coverage/default/34.rom_ctrl_smoke.2078361876 Feb 18 12:42:35 PM PST 24 Feb 18 12:43:20 PM PST 24 17557554714 ps
T308 /workspace/coverage/default/48.rom_ctrl_stress_all.3966837246 Feb 18 12:43:10 PM PST 24 Feb 18 12:43:59 PM PST 24 19534462670 ps
T309 /workspace/coverage/default/11.rom_ctrl_stress_all.3411539494 Feb 18 12:41:39 PM PST 24 Feb 18 12:42:09 PM PST 24 3239378655 ps
T310 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.117101006 Feb 18 12:42:55 PM PST 24 Feb 18 12:43:06 PM PST 24 619999850 ps
T311 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.281468896 Feb 18 12:41:24 PM PST 24 Feb 18 12:41:35 PM PST 24 909590952 ps
T312 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.847336063 Feb 18 12:41:55 PM PST 24 Feb 18 12:42:15 PM PST 24 5242665072 ps
T313 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.857206362 Feb 18 12:42:51 PM PST 24 Feb 18 12:44:31 PM PST 24 1572077647 ps
T314 /workspace/coverage/default/47.rom_ctrl_stress_all.683323375 Feb 18 12:43:04 PM PST 24 Feb 18 12:43:55 PM PST 24 10354368077 ps
T315 /workspace/coverage/default/1.rom_ctrl_stress_all.609121588 Feb 18 12:41:18 PM PST 24 Feb 18 12:41:53 PM PST 24 2637880157 ps
T316 /workspace/coverage/default/33.rom_ctrl_smoke.2123055695 Feb 18 12:42:32 PM PST 24 Feb 18 12:42:45 PM PST 24 1655546736 ps
T317 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.841067324 Feb 18 12:41:19 PM PST 24 Feb 18 12:41:34 PM PST 24 17433212421 ps
T318 /workspace/coverage/default/27.rom_ctrl_alert_test.3667229586 Feb 18 12:42:10 PM PST 24 Feb 18 12:42:23 PM PST 24 3263135777 ps
T319 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3509521996 Feb 18 12:41:49 PM PST 24 Feb 18 12:42:03 PM PST 24 2108743530 ps
T320 /workspace/coverage/default/48.rom_ctrl_smoke.355780123 Feb 18 12:43:14 PM PST 24 Feb 18 12:43:32 PM PST 24 780209790 ps
T321 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3396550976 Feb 18 12:42:38 PM PST 24 Feb 18 12:42:56 PM PST 24 3947035616 ps
T322 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1906256800 Feb 18 12:41:54 PM PST 24 Feb 18 12:45:49 PM PST 24 25254456724 ps
T323 /workspace/coverage/default/0.rom_ctrl_stress_all.1772880196 Feb 18 12:41:13 PM PST 24 Feb 18 12:41:40 PM PST 24 387303693 ps
T324 /workspace/coverage/default/2.rom_ctrl_alert_test.2068900310 Feb 18 12:41:16 PM PST 24 Feb 18 12:41:31 PM PST 24 4576308052 ps
T325 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4123184620 Feb 18 12:42:25 PM PST 24 Feb 18 12:42:36 PM PST 24 1659755578 ps
T326 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1769815519 Feb 18 12:42:54 PM PST 24 Feb 18 12:43:02 PM PST 24 1846730816 ps
T41 /workspace/coverage/default/1.rom_ctrl_sec_cm.1425840382 Feb 18 12:41:19 PM PST 24 Feb 18 12:43:08 PM PST 24 2326556787 ps
T327 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.735427644 Feb 18 12:43:09 PM PST 24 Feb 18 12:43:20 PM PST 24 1104147200 ps
T328 /workspace/coverage/default/31.rom_ctrl_stress_all.1485972042 Feb 18 12:42:25 PM PST 24 Feb 18 12:42:37 PM PST 24 1736344787 ps
T329 /workspace/coverage/default/45.rom_ctrl_stress_all.604654999 Feb 18 12:42:54 PM PST 24 Feb 18 12:44:15 PM PST 24 30220445579 ps
T330 /workspace/coverage/default/19.rom_ctrl_stress_all.3094501573 Feb 18 12:41:54 PM PST 24 Feb 18 12:44:13 PM PST 24 61158979127 ps
T331 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.291210442 Feb 18 12:42:45 PM PST 24 Feb 18 12:43:00 PM PST 24 1441705115 ps
T332 /workspace/coverage/default/14.rom_ctrl_smoke.1066311705 Feb 18 12:41:42 PM PST 24 Feb 18 12:42:13 PM PST 24 12596158152 ps
T333 /workspace/coverage/default/13.rom_ctrl_smoke.966717544 Feb 18 12:41:41 PM PST 24 Feb 18 12:42:13 PM PST 24 10882613093 ps
T334 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1489709670 Feb 18 12:41:55 PM PST 24 Feb 18 12:42:10 PM PST 24 2720812298 ps
T335 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2518846457 Feb 18 12:41:30 PM PST 24 Feb 18 12:41:55 PM PST 24 2522966830 ps
T336 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2425470984 Feb 18 12:42:10 PM PST 24 Feb 18 12:42:25 PM PST 24 1394767720 ps
T62 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.64627424 Feb 18 12:35:29 PM PST 24 Feb 18 12:35:35 PM PST 24 377964396 ps
T63 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1995331268 Feb 18 12:35:13 PM PST 24 Feb 18 12:35:33 PM PST 24 8597705556 ps
T64 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3617939116 Feb 18 12:35:34 PM PST 24 Feb 18 12:37:03 PM PST 24 40163413557 ps
T71 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.521779993 Feb 18 12:35:03 PM PST 24 Feb 18 12:35:10 PM PST 24 347527310 ps
T72 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2146454029 Feb 18 12:35:12 PM PST 24 Feb 18 12:36:42 PM PST 24 52017969889 ps
T337 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2858684531 Feb 18 12:35:19 PM PST 24 Feb 18 12:35:37 PM PST 24 1985519482 ps
T73 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.117165037 Feb 18 12:35:31 PM PST 24 Feb 18 12:35:45 PM PST 24 2653916230 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1501923736 Feb 18 12:35:17 PM PST 24 Feb 18 12:35:32 PM PST 24 6119260304 ps
T338 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.868860880 Feb 18 12:35:10 PM PST 24 Feb 18 12:35:20 PM PST 24 923530334 ps
T339 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.395727759 Feb 18 12:35:13 PM PST 24 Feb 18 12:35:23 PM PST 24 3281681744 ps
T340 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2514964594 Feb 18 12:35:16 PM PST 24 Feb 18 12:35:31 PM PST 24 1306106754 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.495219416 Feb 18 12:35:15 PM PST 24 Feb 18 12:36:15 PM PST 24 14417519130 ps
T75 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4253685990 Feb 18 12:35:29 PM PST 24 Feb 18 12:35:43 PM PST 24 4469837813 ps
T58 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1411651812 Feb 18 12:34:54 PM PST 24 Feb 18 12:35:36 PM PST 24 220679940 ps
T59 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3824947303 Feb 18 12:35:15 PM PST 24 Feb 18 12:36:28 PM PST 24 229013682 ps
T341 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.207767194 Feb 18 12:35:28 PM PST 24 Feb 18 12:35:46 PM PST 24 7764631938 ps
T103 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1582844643 Feb 18 12:34:59 PM PST 24 Feb 18 12:35:13 PM PST 24 13876474061 ps
T99 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1815772766 Feb 18 12:35:14 PM PST 24 Feb 18 12:35:25 PM PST 24 1534928581 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.270276450 Feb 18 12:35:22 PM PST 24 Feb 18 12:35:33 PM PST 24 2074313286 ps
T77 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3347933075 Feb 18 12:35:22 PM PST 24 Feb 18 12:36:27 PM PST 24 6067972718 ps
T342 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2631540307 Feb 18 12:34:56 PM PST 24 Feb 18 12:35:17 PM PST 24 10421186656 ps
T78 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.758289091 Feb 18 12:35:26 PM PST 24 Feb 18 12:35:55 PM PST 24 550071410 ps
T60 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2749102818 Feb 18 12:35:19 PM PST 24 Feb 18 12:36:38 PM PST 24 15977888676 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3627006395 Feb 18 12:35:12 PM PST 24 Feb 18 12:35:54 PM PST 24 445313790 ps
T343 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2442851965 Feb 18 12:35:06 PM PST 24 Feb 18 12:35:21 PM PST 24 4868834746 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2754937647 Feb 18 12:34:57 PM PST 24 Feb 18 12:35:42 PM PST 24 1530822855 ps
T344 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1188468802 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:15 PM PST 24 14642705179 ps
T345 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2914688472 Feb 18 12:34:59 PM PST 24 Feb 18 12:35:12 PM PST 24 730680818 ps
T100 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2310030292 Feb 18 12:35:21 PM PST 24 Feb 18 12:35:42 PM PST 24 2695574347 ps
T346 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1638294000 Feb 18 12:35:06 PM PST 24 Feb 18 12:35:23 PM PST 24 5411874061 ps
T105 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2025310187 Feb 18 12:35:07 PM PST 24 Feb 18 12:36:26 PM PST 24 21969615131 ps
T101 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.942575672 Feb 18 12:35:13 PM PST 24 Feb 18 12:35:31 PM PST 24 3766849033 ps
T347 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3862582779 Feb 18 12:34:59 PM PST 24 Feb 18 12:35:19 PM PST 24 1930872628 ps
T348 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2252379701 Feb 18 12:35:21 PM PST 24 Feb 18 12:35:41 PM PST 24 6180392231 ps
T349 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.160724799 Feb 18 12:35:04 PM PST 24 Feb 18 12:35:21 PM PST 24 1972559397 ps
T350 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2811952593 Feb 18 12:35:29 PM PST 24 Feb 18 12:35:46 PM PST 24 6671166364 ps
T351 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1916322489 Feb 18 12:35:14 PM PST 24 Feb 18 12:35:28 PM PST 24 423894724 ps
T83 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.771953719 Feb 18 12:35:21 PM PST 24 Feb 18 12:35:36 PM PST 24 11510657655 ps
T352 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2979081076 Feb 18 12:35:15 PM PST 24 Feb 18 12:35:33 PM PST 24 1759746955 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.110119640 Feb 18 12:35:05 PM PST 24 Feb 18 12:36:20 PM PST 24 1563033177 ps
T353 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1339330573 Feb 18 12:35:23 PM PST 24 Feb 18 12:35:43 PM PST 24 5679068731 ps
T354 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4234777186 Feb 18 12:35:28 PM PST 24 Feb 18 12:35:49 PM PST 24 11988198753 ps
T355 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3879038971 Feb 18 12:35:31 PM PST 24 Feb 18 12:35:47 PM PST 24 2820806463 ps
T84 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4272421512 Feb 18 12:35:20 PM PST 24 Feb 18 12:35:36 PM PST 24 1600268643 ps
T356 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1392785745 Feb 18 12:35:20 PM PST 24 Feb 18 12:35:29 PM PST 24 225750601 ps
T357 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3848046557 Feb 18 12:35:31 PM PST 24 Feb 18 12:35:44 PM PST 24 605338561 ps
T358 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2150398646 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:07 PM PST 24 87573736 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.830747065 Feb 18 12:34:59 PM PST 24 Feb 18 12:35:23 PM PST 24 367102386 ps
T113 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2793794774 Feb 18 12:35:28 PM PST 24 Feb 18 12:36:42 PM PST 24 288615087 ps
T359 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.577183352 Feb 18 12:35:27 PM PST 24 Feb 18 12:35:44 PM PST 24 1800285820 ps
T360 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.147122954 Feb 18 12:35:12 PM PST 24 Feb 18 12:35:26 PM PST 24 2408838273 ps
T361 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.91799446 Feb 18 12:35:20 PM PST 24 Feb 18 12:36:31 PM PST 24 24742425756 ps
T362 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2910651545 Feb 18 12:35:26 PM PST 24 Feb 18 12:35:44 PM PST 24 2097530679 ps
T363 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1793381001 Feb 18 12:35:25 PM PST 24 Feb 18 12:35:43 PM PST 24 2140939452 ps
T364 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.882951003 Feb 18 12:35:11 PM PST 24 Feb 18 12:35:23 PM PST 24 1807048667 ps
T86 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.417220029 Feb 18 12:35:27 PM PST 24 Feb 18 12:36:31 PM PST 24 32787057398 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3610279528 Feb 18 12:35:07 PM PST 24 Feb 18 12:35:17 PM PST 24 816011078 ps
T366 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3898813797 Feb 18 12:35:26 PM PST 24 Feb 18 12:35:34 PM PST 24 346416002 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1131466124 Feb 18 12:35:15 PM PST 24 Feb 18 12:35:55 PM PST 24 200524719 ps
T107 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3740600992 Feb 18 12:35:14 PM PST 24 Feb 18 12:36:25 PM PST 24 788999485 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3766008672 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:14 PM PST 24 179339660 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2921603694 Feb 18 12:34:57 PM PST 24 Feb 18 12:35:12 PM PST 24 1109700841 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.377619045 Feb 18 12:35:14 PM PST 24 Feb 18 12:35:29 PM PST 24 2171023187 ps
T87 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.962866975 Feb 18 12:35:15 PM PST 24 Feb 18 12:35:44 PM PST 24 2217052192 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1101369972 Feb 18 12:35:31 PM PST 24 Feb 18 12:36:02 PM PST 24 3392154801 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.590115276 Feb 18 12:35:18 PM PST 24 Feb 18 12:35:31 PM PST 24 7927040238 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4077587472 Feb 18 12:34:56 PM PST 24 Feb 18 12:36:30 PM PST 24 10811825149 ps
T373 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1624468805 Feb 18 12:35:12 PM PST 24 Feb 18 12:35:26 PM PST 24 237041952 ps
T89 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3917118949 Feb 18 12:35:16 PM PST 24 Feb 18 12:36:26 PM PST 24 130873150164 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1025967559 Feb 18 12:35:21 PM PST 24 Feb 18 12:35:41 PM PST 24 2092769394 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3468848956 Feb 18 12:35:01 PM PST 24 Feb 18 12:35:22 PM PST 24 8523783669 ps
T375 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3634295957 Feb 18 12:35:24 PM PST 24 Feb 18 12:36:13 PM PST 24 1807709432 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2166243822 Feb 18 12:35:22 PM PST 24 Feb 18 12:36:43 PM PST 24 10247893233 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.322910110 Feb 18 12:35:23 PM PST 24 Feb 18 12:35:35 PM PST 24 403442864 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3295102043 Feb 18 12:35:01 PM PST 24 Feb 18 12:36:11 PM PST 24 22748823527 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1091296089 Feb 18 12:35:05 PM PST 24 Feb 18 12:35:17 PM PST 24 2865786930 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2164536198 Feb 18 12:35:22 PM PST 24 Feb 18 12:35:38 PM PST 24 1413122629 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4014574928 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:22 PM PST 24 4769863678 ps
T381 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.502355942 Feb 18 12:35:24 PM PST 24 Feb 18 12:35:40 PM PST 24 6367465589 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4093032023 Feb 18 12:35:21 PM PST 24 Feb 18 12:35:33 PM PST 24 135784357 ps
T383 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1464792112 Feb 18 12:35:18 PM PST 24 Feb 18 12:35:29 PM PST 24 237967405 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3531266183 Feb 18 12:35:06 PM PST 24 Feb 18 12:35:26 PM PST 24 1845698886 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.184531680 Feb 18 12:34:57 PM PST 24 Feb 18 12:35:08 PM PST 24 111290635 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1713542014 Feb 18 12:35:02 PM PST 24 Feb 18 12:35:13 PM PST 24 438763592 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3623275672 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:19 PM PST 24 690495816 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2910765817 Feb 18 12:35:01 PM PST 24 Feb 18 12:35:20 PM PST 24 3659842961 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2259478370 Feb 18 12:35:14 PM PST 24 Feb 18 12:35:20 PM PST 24 1377634722 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1246205181 Feb 18 12:34:56 PM PST 24 Feb 18 12:35:09 PM PST 24 1436371482 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.752019745 Feb 18 12:35:02 PM PST 24 Feb 18 12:35:17 PM PST 24 1073520743 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4031231012 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:17 PM PST 24 417140966 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.883399728 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:15 PM PST 24 3618846479 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3422448550 Feb 18 12:34:59 PM PST 24 Feb 18 12:35:11 PM PST 24 672776313 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4128046291 Feb 18 12:35:18 PM PST 24 Feb 18 12:35:32 PM PST 24 272702230 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2762856819 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:26 PM PST 24 1990734217 ps
T396 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.211156452 Feb 18 12:35:31 PM PST 24 Feb 18 12:35:48 PM PST 24 7077991540 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3665332402 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:15 PM PST 24 1313492645 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2496612495 Feb 18 12:35:11 PM PST 24 Feb 18 12:35:31 PM PST 24 2173739461 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4218599558 Feb 18 12:35:06 PM PST 24 Feb 18 12:35:44 PM PST 24 35088202649 ps
T399 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.690695237 Feb 18 12:35:22 PM PST 24 Feb 18 12:35:41 PM PST 24 13227223790 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2785038516 Feb 18 12:35:33 PM PST 24 Feb 18 12:35:43 PM PST 24 833053605 ps
T401 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2650362422 Feb 18 12:35:16 PM PST 24 Feb 18 12:36:02 PM PST 24 5628536568 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.306620100 Feb 18 12:35:23 PM PST 24 Feb 18 12:35:40 PM PST 24 6114383001 ps
T402 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1977962586 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:14 PM PST 24 88852792 ps
T403 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.318339651 Feb 18 12:35:15 PM PST 24 Feb 18 12:35:34 PM PST 24 1949320509 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.398022805 Feb 18 12:35:01 PM PST 24 Feb 18 12:35:11 PM PST 24 209677883 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2045159598 Feb 18 12:35:06 PM PST 24 Feb 18 12:35:21 PM PST 24 1574855749 ps
T406 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3876023549 Feb 18 12:35:17 PM PST 24 Feb 18 12:35:27 PM PST 24 151308297 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.906309565 Feb 18 12:35:10 PM PST 24 Feb 18 12:35:54 PM PST 24 32283963764 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3019074683 Feb 18 12:35:05 PM PST 24 Feb 18 12:35:19 PM PST 24 1268312274 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1284147244 Feb 18 12:35:27 PM PST 24 Feb 18 12:36:40 PM PST 24 754890338 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.70956262 Feb 18 12:35:08 PM PST 24 Feb 18 12:35:20 PM PST 24 817034000 ps
T408 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.465127684 Feb 18 12:35:06 PM PST 24 Feb 18 12:35:23 PM PST 24 15982654201 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3527711813 Feb 18 12:35:16 PM PST 24 Feb 18 12:36:06 PM PST 24 19347271664 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4244638895 Feb 18 12:35:20 PM PST 24 Feb 18 12:35:40 PM PST 24 6049342197 ps
T411 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3023101233 Feb 18 12:35:13 PM PST 24 Feb 18 12:35:37 PM PST 24 8637751182 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3968554971 Feb 18 12:34:59 PM PST 24 Feb 18 12:35:17 PM PST 24 1122171850 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3363548628 Feb 18 12:35:13 PM PST 24 Feb 18 12:36:26 PM PST 24 8249277560 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1661821126 Feb 18 12:35:17 PM PST 24 Feb 18 12:36:40 PM PST 24 2013215320 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3197387028 Feb 18 12:35:22 PM PST 24 Feb 18 12:36:04 PM PST 24 1451437809 ps
T414 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.745870560 Feb 18 12:35:35 PM PST 24 Feb 18 12:36:16 PM PST 24 377562035 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2248513568 Feb 18 12:35:11 PM PST 24 Feb 18 12:35:27 PM PST 24 1324914192 ps
T416 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3728514414 Feb 18 12:35:13 PM PST 24 Feb 18 12:35:31 PM PST 24 1225016602 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1106090173 Feb 18 12:35:02 PM PST 24 Feb 18 12:36:34 PM PST 24 20729947562 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.366456998 Feb 18 12:35:10 PM PST 24 Feb 18 12:35:23 PM PST 24 764171323 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.630309920 Feb 18 12:35:13 PM PST 24 Feb 18 12:35:25 PM PST 24 2796908573 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.264665501 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:16 PM PST 24 12814555091 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4159291094 Feb 18 12:35:18 PM PST 24 Feb 18 12:35:26 PM PST 24 90425626 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1651835869 Feb 18 12:34:54 PM PST 24 Feb 18 12:35:09 PM PST 24 6796152008 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1603964604 Feb 18 12:35:18 PM PST 24 Feb 18 12:36:15 PM PST 24 24282507040 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2956742614 Feb 18 12:35:26 PM PST 24 Feb 18 12:35:44 PM PST 24 2118507402 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3047698755 Feb 18 12:35:11 PM PST 24 Feb 18 12:35:25 PM PST 24 1910562770 ps
T425 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1216170603 Feb 18 12:35:14 PM PST 24 Feb 18 12:36:00 PM PST 24 5408139162 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1346224851 Feb 18 12:35:32 PM PST 24 Feb 18 12:35:48 PM PST 24 19053058930 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2799231888 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:09 PM PST 24 793105135 ps
T428 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2600600807 Feb 18 12:35:32 PM PST 24 Feb 18 12:35:47 PM PST 24 1932506352 ps
T429 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.822378222 Feb 18 12:35:18 PM PST 24 Feb 18 12:35:39 PM PST 24 3355833639 ps
T430 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.17882201 Feb 18 12:35:16 PM PST 24 Feb 18 12:35:35 PM PST 24 9268854550 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2995398801 Feb 18 12:34:57 PM PST 24 Feb 18 12:35:14 PM PST 24 1784833022 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2157097564 Feb 18 12:35:21 PM PST 24 Feb 18 12:35:38 PM PST 24 2096743647 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3763723569 Feb 18 12:34:58 PM PST 24 Feb 18 12:35:14 PM PST 24 1677179137 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2080153332 Feb 18 12:34:58 PM PST 24 Feb 18 12:36:17 PM PST 24 1316688922 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.953148184 Feb 18 12:34:54 PM PST 24 Feb 18 12:35:14 PM PST 24 8194502150 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4147336478 Feb 18 12:35:13 PM PST 24 Feb 18 12:35:26 PM PST 24 2153993251 ps
T437 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2442139893 Feb 18 12:35:17 PM PST 24 Feb 18 12:36:05 PM PST 24 1856871212 ps
T438 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.785604319 Feb 18 12:35:25 PM PST 24 Feb 18 12:35:45 PM PST 24 367264301 ps

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3127038887
Short name T10
Test name
Test status
Simulation time 3646165724 ps
CPU time 105.25 seconds
Started Feb 18 12:41:14 PM PST 24
Finished Feb 18 12:43:03 PM PST 24
Peak memory 224808 kb
Host smart-66eb111c-b70d-454d-9330-f1dde19a37fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127038887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3127038887
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.509119375
Short name T14
Test name
Test status
Simulation time 120941821991 ps
CPU time 1129.9 seconds
Started Feb 18 12:41:47 PM PST 24
Finished Feb 18 01:00:38 PM PST 24
Peak memory 233324 kb
Host smart-18726721-b35f-47e5-b304-eeca12eaca81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509119375 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.509119375
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1346134359
Short name T5
Test name
Test status
Simulation time 36580396361 ps
CPU time 34.39 seconds
Started Feb 18 12:41:22 PM PST 24
Finished Feb 18 12:41:57 PM PST 24
Peak memory 212896 kb
Host smart-978a7928-f3da-47d5-bbe5-2cb11f74f74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346134359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1346134359
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3824947303
Short name T59
Test name
Test status
Simulation time 229013682 ps
CPU time 70.57 seconds
Started Feb 18 12:35:15 PM PST 24
Finished Feb 18 12:36:28 PM PST 24
Peak memory 210628 kb
Host smart-74c5d590-2137-478f-846b-3ffdb9c8a2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824947303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3824947303
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3801654212
Short name T25
Test name
Test status
Simulation time 9702919503 ps
CPU time 58.62 seconds
Started Feb 18 12:42:44 PM PST 24
Finished Feb 18 12:43:43 PM PST 24
Peak memory 212368 kb
Host smart-fb00e636-3add-4293-baef-e4b47f8f2791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801654212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3801654212
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2727114650
Short name T200
Test name
Test status
Simulation time 3763462882 ps
CPU time 119.78 seconds
Started Feb 18 12:41:30 PM PST 24
Finished Feb 18 12:43:31 PM PST 24
Peak memory 220504 kb
Host smart-f25fb6e7-77fd-4863-98f0-37d9559fdc3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727114650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2727114650
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4087883668
Short name T16
Test name
Test status
Simulation time 459899280793 ps
CPU time 1441.38 seconds
Started Feb 18 12:42:03 PM PST 24
Finished Feb 18 01:06:09 PM PST 24
Peak memory 235840 kb
Host smart-b5a8beaf-5ccb-480d-830f-596209d83a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087883668 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4087883668
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2469966981
Short name T33
Test name
Test status
Simulation time 23061838844 ps
CPU time 62.88 seconds
Started Feb 18 12:41:19 PM PST 24
Finished Feb 18 12:42:23 PM PST 24
Peak memory 232660 kb
Host smart-babbd85f-07bf-4b4e-a583-c4d043c0940b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469966981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2469966981
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2146454029
Short name T72
Test name
Test status
Simulation time 52017969889 ps
CPU time 87.22 seconds
Started Feb 18 12:35:12 PM PST 24
Finished Feb 18 12:36:42 PM PST 24
Peak memory 210720 kb
Host smart-dae09087-91ce-48ed-8524-cd52fed7578a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146454029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2146454029
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2754937647
Short name T110
Test name
Test status
Simulation time 1530822855 ps
CPU time 40.32 seconds
Started Feb 18 12:34:57 PM PST 24
Finished Feb 18 12:35:42 PM PST 24
Peak memory 212216 kb
Host smart-f8364aeb-3d83-4f82-be4a-8260e9fa6e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754937647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2754937647
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1551361922
Short name T61
Test name
Test status
Simulation time 5689350518 ps
CPU time 17.58 seconds
Started Feb 18 12:42:20 PM PST 24
Finished Feb 18 12:42:39 PM PST 24
Peak memory 211176 kb
Host smart-75b1f573-b399-4e1f-bf9c-c601f93017e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551361922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1551361922
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2723599147
Short name T37
Test name
Test status
Simulation time 801201629 ps
CPU time 6.95 seconds
Started Feb 18 12:41:35 PM PST 24
Finished Feb 18 12:41:44 PM PST 24
Peak memory 211120 kb
Host smart-19fa9611-97f4-45bb-9e6b-ed16cbbde724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723599147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2723599147
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.758289091
Short name T78
Test name
Test status
Simulation time 550071410 ps
CPU time 27.35 seconds
Started Feb 18 12:35:26 PM PST 24
Finished Feb 18 12:35:55 PM PST 24
Peak memory 210484 kb
Host smart-78f5ca57-2ced-43ba-8fea-c926e9234bde
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758289091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.758289091
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3800572859
Short name T129
Test name
Test status
Simulation time 3919829334 ps
CPU time 30.76 seconds
Started Feb 18 12:41:37 PM PST 24
Finished Feb 18 12:42:10 PM PST 24
Peak memory 211884 kb
Host smart-0e1f9d4a-2eb4-4fee-9444-91bccd0348b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800572859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3800572859
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3455370720
Short name T208
Test name
Test status
Simulation time 1843067373 ps
CPU time 9.55 seconds
Started Feb 18 12:41:44 PM PST 24
Finished Feb 18 12:41:54 PM PST 24
Peak memory 211660 kb
Host smart-0ee14706-f770-4b50-8945-1cf6f5396c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455370720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3455370720
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3580605556
Short name T96
Test name
Test status
Simulation time 413720952 ps
CPU time 5.56 seconds
Started Feb 18 12:42:34 PM PST 24
Finished Feb 18 12:42:41 PM PST 24
Peak memory 210980 kb
Host smart-43073539-b30a-4b5c-955d-24d81c996259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580605556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3580605556
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1284147244
Short name T111
Test name
Test status
Simulation time 754890338 ps
CPU time 71.46 seconds
Started Feb 18 12:35:27 PM PST 24
Finished Feb 18 12:36:40 PM PST 24
Peak memory 210656 kb
Host smart-ab527a8a-d81a-45eb-9c63-58fdac84fb4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284147244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1284147244
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2166243822
Short name T115
Test name
Test status
Simulation time 10247893233 ps
CPU time 77.43 seconds
Started Feb 18 12:35:22 PM PST 24
Finished Feb 18 12:36:43 PM PST 24
Peak memory 211660 kb
Host smart-fc86317c-58ac-411b-b428-23cbefd75c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166243822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2166243822
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3007635864
Short name T44
Test name
Test status
Simulation time 70046441919 ps
CPU time 308.95 seconds
Started Feb 18 12:41:37 PM PST 24
Finished Feb 18 12:46:48 PM PST 24
Peak memory 236800 kb
Host smart-61a63b09-a0e3-44a7-a3e6-65aa863c8b33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007635864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3007635864
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2631540307
Short name T342
Test name
Test status
Simulation time 10421186656 ps
CPU time 16.44 seconds
Started Feb 18 12:34:56 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 210708 kb
Host smart-6d11043b-c946-4799-ab65-13d95e43477e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631540307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2631540307
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2921603694
Short name T368
Test name
Test status
Simulation time 1109700841 ps
CPU time 10.87 seconds
Started Feb 18 12:34:57 PM PST 24
Finished Feb 18 12:35:12 PM PST 24
Peak memory 210592 kb
Host smart-9e10c444-0fcc-478c-a6bf-41d25b9e3c58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921603694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2921603694
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3763723569
Short name T433
Test name
Test status
Simulation time 1677179137 ps
CPU time 11.87 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:14 PM PST 24
Peak memory 210556 kb
Host smart-ca984f6d-c684-4edd-96cd-ea0706a5182a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763723569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3763723569
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.184531680
Short name T384
Test name
Test status
Simulation time 111290635 ps
CPU time 6.46 seconds
Started Feb 18 12:34:57 PM PST 24
Finished Feb 18 12:35:08 PM PST 24
Peak memory 215312 kb
Host smart-0cecc583-01ae-4166-83d3-8a4eaeef4346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184531680 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.184531680
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2995398801
Short name T431
Test name
Test status
Simulation time 1784833022 ps
CPU time 13.12 seconds
Started Feb 18 12:34:57 PM PST 24
Finished Feb 18 12:35:14 PM PST 24
Peak memory 210568 kb
Host smart-d7d2b477-1c60-4d3e-b9e9-d8d7112cf79c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995398801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2995398801
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.883399728
Short name T392
Test name
Test status
Simulation time 3618846479 ps
CPU time 13.59 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:15 PM PST 24
Peak memory 210584 kb
Host smart-58974295-19fc-45aa-a8d4-163b33638c58
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883399728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.883399728
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1188468802
Short name T344
Test name
Test status
Simulation time 14642705179 ps
CPU time 12.48 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:15 PM PST 24
Peak memory 210584 kb
Host smart-3c48148f-ba08-4e30-9bae-dd551fe5d0f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188468802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1188468802
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1106090173
Short name T95
Test name
Test status
Simulation time 20729947562 ps
CPU time 88.8 seconds
Started Feb 18 12:35:02 PM PST 24
Finished Feb 18 12:36:34 PM PST 24
Peak memory 210628 kb
Host smart-006d80d7-8c6d-4b14-84aa-0aee36d7ba1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106090173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1106090173
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2150398646
Short name T358
Test name
Test status
Simulation time 87573736 ps
CPU time 4.4 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:07 PM PST 24
Peak memory 210620 kb
Host smart-eaf26631-f3ad-4db0-bf3e-288928f3af19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150398646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2150398646
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1651835869
Short name T421
Test name
Test status
Simulation time 6796152008 ps
CPU time 10.61 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 215180 kb
Host smart-9f306176-f8a4-4321-b08e-0fe5bf2f1753
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651835869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1651835869
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1582844643
Short name T103
Test name
Test status
Simulation time 13876474061 ps
CPU time 9.66 seconds
Started Feb 18 12:34:59 PM PST 24
Finished Feb 18 12:35:13 PM PST 24
Peak memory 210724 kb
Host smart-4c6a1449-510a-4e1d-9d56-1b0699d89037
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582844643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1582844643
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3422448550
Short name T393
Test name
Test status
Simulation time 672776313 ps
CPU time 7.35 seconds
Started Feb 18 12:34:59 PM PST 24
Finished Feb 18 12:35:11 PM PST 24
Peak memory 210632 kb
Host smart-c75f3d4f-7704-4980-ba7d-b9dc781f3076
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422448550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3422448550
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3531266183
Short name T91
Test name
Test status
Simulation time 1845698886 ps
CPU time 17.82 seconds
Started Feb 18 12:35:06 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 210636 kb
Host smart-9dc036b7-7283-4904-990e-0a22be8e3fb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531266183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3531266183
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2799231888
Short name T427
Test name
Test status
Simulation time 793105135 ps
CPU time 7.04 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 215008 kb
Host smart-4b43eb1e-e022-48f0-8dc5-aa80b8cf19b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799231888 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2799231888
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3468848956
Short name T90
Test name
Test status
Simulation time 8523783669 ps
CPU time 16.25 seconds
Started Feb 18 12:35:01 PM PST 24
Finished Feb 18 12:35:22 PM PST 24
Peak memory 210620 kb
Host smart-6172e8a7-4646-4876-a238-c7cef6809817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468848956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3468848956
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.953148184
Short name T435
Test name
Test status
Simulation time 8194502150 ps
CPU time 15.97 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:35:14 PM PST 24
Peak memory 210612 kb
Host smart-a87a8c3e-8f13-4398-a4e3-99dca066bd31
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953148184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.953148184
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.465127684
Short name T408
Test name
Test status
Simulation time 15982654201 ps
CPU time 15.15 seconds
Started Feb 18 12:35:06 PM PST 24
Finished Feb 18 12:35:23 PM PST 24
Peak memory 210620 kb
Host smart-4a490f5d-7b70-46f0-bd34-4ac832668368
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465127684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
465127684
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4077587472
Short name T372
Test name
Test status
Simulation time 10811825149 ps
CPU time 90.57 seconds
Started Feb 18 12:34:56 PM PST 24
Finished Feb 18 12:36:30 PM PST 24
Peak memory 210664 kb
Host smart-30c7d358-a90f-4817-92fa-39719240ca35
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077587472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4077587472
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3623275672
Short name T386
Test name
Test status
Simulation time 690495816 ps
CPU time 8.42 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:19 PM PST 24
Peak memory 210532 kb
Host smart-5052f89b-2197-4dcf-ab1f-ac917632a5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623275672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3623275672
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.264665501
Short name T419
Test name
Test status
Simulation time 12814555091 ps
CPU time 14.03 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:35:16 PM PST 24
Peak memory 214296 kb
Host smart-cf9ff97c-a92b-425f-84b1-8314f25dc5d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264665501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.264665501
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1411651812
Short name T58
Test name
Test status
Simulation time 220679940 ps
CPU time 37.66 seconds
Started Feb 18 12:34:54 PM PST 24
Finished Feb 18 12:35:36 PM PST 24
Peak memory 212284 kb
Host smart-a7e1a1bb-3b8f-4bb0-a0af-af61c610b9db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411651812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1411651812
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.377619045
Short name T369
Test name
Test status
Simulation time 2171023187 ps
CPU time 12.86 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:35:29 PM PST 24
Peak memory 215484 kb
Host smart-f35f5811-93c6-4c15-a737-d0b552b6ff3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377619045 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.377619045
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.17882201
Short name T430
Test name
Test status
Simulation time 9268854550 ps
CPU time 15.85 seconds
Started Feb 18 12:35:16 PM PST 24
Finished Feb 18 12:35:35 PM PST 24
Peak memory 210632 kb
Host smart-fb03192f-17ec-493a-bd8c-40b9b68d4390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17882201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.17882201
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3347933075
Short name T77
Test name
Test status
Simulation time 6067972718 ps
CPU time 61.68 seconds
Started Feb 18 12:35:22 PM PST 24
Finished Feb 18 12:36:27 PM PST 24
Peak memory 210632 kb
Host smart-37ac4630-55a3-4ad7-899f-375558a3fa86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347933075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3347933075
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1815772766
Short name T99
Test name
Test status
Simulation time 1534928581 ps
CPU time 8.8 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:35:25 PM PST 24
Peak memory 210660 kb
Host smart-c1842732-51c6-401f-beff-534bb2d83e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815772766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1815772766
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.366456998
Short name T417
Test name
Test status
Simulation time 764171323 ps
CPU time 11.6 seconds
Started Feb 18 12:35:10 PM PST 24
Finished Feb 18 12:35:23 PM PST 24
Peak memory 214568 kb
Host smart-ab0a4a38-9896-46b0-aa6c-e2d7551dd9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366456998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.366456998
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3627006395
Short name T109
Test name
Test status
Simulation time 445313790 ps
CPU time 38.57 seconds
Started Feb 18 12:35:12 PM PST 24
Finished Feb 18 12:35:54 PM PST 24
Peak memory 210644 kb
Host smart-4fe38348-81c2-4b77-8617-751f3b2829e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627006395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3627006395
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2252379701
Short name T348
Test name
Test status
Simulation time 6180392231 ps
CPU time 16.58 seconds
Started Feb 18 12:35:21 PM PST 24
Finished Feb 18 12:35:41 PM PST 24
Peak memory 215708 kb
Host smart-006a9a1a-6e27-4e85-810d-31a0e18ee4c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252379701 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2252379701
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2514964594
Short name T340
Test name
Test status
Simulation time 1306106754 ps
CPU time 11.6 seconds
Started Feb 18 12:35:16 PM PST 24
Finished Feb 18 12:35:31 PM PST 24
Peak memory 210620 kb
Host smart-5a334641-de18-4a47-8581-050656f3b7b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514964594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2514964594
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2496612495
Short name T398
Test name
Test status
Simulation time 2173739461 ps
CPU time 17.02 seconds
Started Feb 18 12:35:11 PM PST 24
Finished Feb 18 12:35:31 PM PST 24
Peak memory 210692 kb
Host smart-1d735bed-e1a4-4845-803c-e67a35634ea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496612495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2496612495
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3728514414
Short name T416
Test name
Test status
Simulation time 1225016602 ps
CPU time 15.43 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:35:31 PM PST 24
Peak memory 214752 kb
Host smart-28b1645b-5c3e-48b3-9668-cc10a3282250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728514414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3728514414
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.395727759
Short name T339
Test name
Test status
Simulation time 3281681744 ps
CPU time 7.76 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:35:23 PM PST 24
Peak memory 215180 kb
Host smart-b5c2d5ac-7ee8-404d-b60b-eb0e02f21655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395727759 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.395727759
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2164536198
Short name T379
Test name
Test status
Simulation time 1413122629 ps
CPU time 12.25 seconds
Started Feb 18 12:35:22 PM PST 24
Finished Feb 18 12:35:38 PM PST 24
Peak memory 210580 kb
Host smart-82d773bf-5ab1-43b0-9f8a-0ad0a4620440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164536198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2164536198
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3917118949
Short name T89
Test name
Test status
Simulation time 130873150164 ps
CPU time 66.5 seconds
Started Feb 18 12:35:16 PM PST 24
Finished Feb 18 12:36:26 PM PST 24
Peak memory 210660 kb
Host smart-f8be4804-4329-4ec3-83ef-8bb648e37b48
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917118949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3917118949
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.942575672
Short name T101
Test name
Test status
Simulation time 3766849033 ps
CPU time 15.43 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:35:31 PM PST 24
Peak memory 210556 kb
Host smart-f5c20327-6e59-4e38-a136-e53589562362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942575672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.942575672
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.822378222
Short name T429
Test name
Test status
Simulation time 3355833639 ps
CPU time 17.88 seconds
Started Feb 18 12:35:18 PM PST 24
Finished Feb 18 12:35:39 PM PST 24
Peak memory 216192 kb
Host smart-d89f0efe-6b69-42f5-9c37-cc5890c56616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822378222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.822378222
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2442139893
Short name T437
Test name
Test status
Simulation time 1856871212 ps
CPU time 45.48 seconds
Started Feb 18 12:35:17 PM PST 24
Finished Feb 18 12:36:05 PM PST 24
Peak memory 212176 kb
Host smart-d6a7b2a9-5514-43a5-ad6e-4afb8649fea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442139893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2442139893
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3023101233
Short name T411
Test name
Test status
Simulation time 8637751182 ps
CPU time 21.3 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:35:37 PM PST 24
Peak memory 215500 kb
Host smart-814989f2-870b-4c6e-a096-c1bca0e027af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023101233 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3023101233
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4272421512
Short name T84
Test name
Test status
Simulation time 1600268643 ps
CPU time 13.38 seconds
Started Feb 18 12:35:20 PM PST 24
Finished Feb 18 12:35:36 PM PST 24
Peak memory 210568 kb
Host smart-2924b42c-7b4b-410b-b119-42a377ffb406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272421512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4272421512
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1603964604
Short name T422
Test name
Test status
Simulation time 24282507040 ps
CPU time 54.29 seconds
Started Feb 18 12:35:18 PM PST 24
Finished Feb 18 12:36:15 PM PST 24
Peak memory 210624 kb
Host smart-e5275b4d-eaeb-4853-92af-17a85ec75e05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603964604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1603964604
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.630309920
Short name T418
Test name
Test status
Simulation time 2796908573 ps
CPU time 8.91 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:35:25 PM PST 24
Peak memory 210640 kb
Host smart-b6ab1840-c980-4b40-a823-6e82f9ed1d74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630309920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.630309920
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.690695237
Short name T399
Test name
Test status
Simulation time 13227223790 ps
CPU time 15.94 seconds
Started Feb 18 12:35:22 PM PST 24
Finished Feb 18 12:35:41 PM PST 24
Peak memory 216296 kb
Host smart-7a5a934d-1477-448e-82a5-c47eff6e4ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690695237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.690695237
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3197387028
Short name T114
Test name
Test status
Simulation time 1451437809 ps
CPU time 38.39 seconds
Started Feb 18 12:35:22 PM PST 24
Finished Feb 18 12:36:04 PM PST 24
Peak memory 211312 kb
Host smart-e82a8186-eb52-46dd-86ac-5c91248ca46a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197387028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3197387028
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.322910110
Short name T376
Test name
Test status
Simulation time 403442864 ps
CPU time 8.61 seconds
Started Feb 18 12:35:23 PM PST 24
Finished Feb 18 12:35:35 PM PST 24
Peak memory 215512 kb
Host smart-18f5ea3d-cc57-495b-8f1c-085e2e662efb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322910110 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.322910110
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1346224851
Short name T426
Test name
Test status
Simulation time 19053058930 ps
CPU time 12.55 seconds
Started Feb 18 12:35:32 PM PST 24
Finished Feb 18 12:35:48 PM PST 24
Peak memory 210644 kb
Host smart-e8f1887c-a15e-431f-a0ae-3929fe1613bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346224851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1346224851
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3527711813
Short name T409
Test name
Test status
Simulation time 19347271664 ps
CPU time 46.15 seconds
Started Feb 18 12:35:16 PM PST 24
Finished Feb 18 12:36:06 PM PST 24
Peak memory 210620 kb
Host smart-5ba623d4-4058-4f41-9dcf-f0c01a91b024
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527711813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3527711813
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4253685990
Short name T75
Test name
Test status
Simulation time 4469837813 ps
CPU time 11.94 seconds
Started Feb 18 12:35:29 PM PST 24
Finished Feb 18 12:35:43 PM PST 24
Peak memory 210728 kb
Host smart-a1de2dd0-a9b8-49c6-bf2f-0dca51ebf041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253685990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4253685990
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4234777186
Short name T354
Test name
Test status
Simulation time 11988198753 ps
CPU time 17.43 seconds
Started Feb 18 12:35:28 PM PST 24
Finished Feb 18 12:35:49 PM PST 24
Peak memory 218892 kb
Host smart-fcea4c71-a50c-4709-9901-fc1e08203f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234777186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4234777186
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2749102818
Short name T60
Test name
Test status
Simulation time 15977888676 ps
CPU time 76.14 seconds
Started Feb 18 12:35:19 PM PST 24
Finished Feb 18 12:36:38 PM PST 24
Peak memory 211712 kb
Host smart-6bc2216c-dd81-4d37-8779-0b69f686a8d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749102818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2749102818
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3879038971
Short name T355
Test name
Test status
Simulation time 2820806463 ps
CPU time 13.77 seconds
Started Feb 18 12:35:31 PM PST 24
Finished Feb 18 12:35:47 PM PST 24
Peak memory 216008 kb
Host smart-620bdf02-326f-452d-992b-bdeb973fda28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879038971 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3879038971
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1025967559
Short name T374
Test name
Test status
Simulation time 2092769394 ps
CPU time 16.07 seconds
Started Feb 18 12:35:21 PM PST 24
Finished Feb 18 12:35:41 PM PST 24
Peak memory 210564 kb
Host smart-1281b7a1-a30c-4681-83ae-b9b8c46e24f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025967559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1025967559
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.785604319
Short name T438
Test name
Test status
Simulation time 367264301 ps
CPU time 18.75 seconds
Started Feb 18 12:35:25 PM PST 24
Finished Feb 18 12:35:45 PM PST 24
Peak memory 210548 kb
Host smart-da37857c-e260-4dc4-bc53-ab2d4c8ddf75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785604319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.785604319
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.64627424
Short name T62
Test name
Test status
Simulation time 377964396 ps
CPU time 4.26 seconds
Started Feb 18 12:35:29 PM PST 24
Finished Feb 18 12:35:35 PM PST 24
Peak memory 210616 kb
Host smart-bf6c6ef4-ef25-4210-b490-36f21d64b2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64627424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ct
rl_same_csr_outstanding.64627424
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1339330573
Short name T353
Test name
Test status
Simulation time 5679068731 ps
CPU time 16.94 seconds
Started Feb 18 12:35:23 PM PST 24
Finished Feb 18 12:35:43 PM PST 24
Peak memory 215380 kb
Host smart-9772d1d4-8468-46c3-8164-d7b79c0ac8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339330573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1339330573
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2793794774
Short name T113
Test name
Test status
Simulation time 288615087 ps
CPU time 70.5 seconds
Started Feb 18 12:35:28 PM PST 24
Finished Feb 18 12:36:42 PM PST 24
Peak memory 212276 kb
Host smart-0d473c9f-64ea-4451-8800-63fa426d6a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793794774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2793794774
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2785038516
Short name T400
Test name
Test status
Simulation time 833053605 ps
CPU time 7.28 seconds
Started Feb 18 12:35:33 PM PST 24
Finished Feb 18 12:35:43 PM PST 24
Peak memory 218936 kb
Host smart-b855539b-5741-4063-8fc4-821c77dad3c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785038516 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2785038516
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.771953719
Short name T83
Test name
Test status
Simulation time 11510657655 ps
CPU time 11.35 seconds
Started Feb 18 12:35:21 PM PST 24
Finished Feb 18 12:35:36 PM PST 24
Peak memory 210736 kb
Host smart-ca937ce6-0a3d-4d7e-80b1-640a3b28cb32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771953719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.771953719
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3617939116
Short name T64
Test name
Test status
Simulation time 40163413557 ps
CPU time 86.73 seconds
Started Feb 18 12:35:34 PM PST 24
Finished Feb 18 12:37:03 PM PST 24
Peak memory 210700 kb
Host smart-f602466b-2682-4763-b6db-68a9f70d2481
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617939116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3617939116
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2811952593
Short name T350
Test name
Test status
Simulation time 6671166364 ps
CPU time 14.64 seconds
Started Feb 18 12:35:29 PM PST 24
Finished Feb 18 12:35:46 PM PST 24
Peak memory 210724 kb
Host smart-61fe1e2c-7522-4e67-92c4-d004926d29d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811952593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2811952593
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4093032023
Short name T382
Test name
Test status
Simulation time 135784357 ps
CPU time 9 seconds
Started Feb 18 12:35:21 PM PST 24
Finished Feb 18 12:35:33 PM PST 24
Peak memory 214780 kb
Host smart-aa4d7b95-4bea-4599-a36f-038ee67ba74d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093032023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4093032023
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4244638895
Short name T410
Test name
Test status
Simulation time 6049342197 ps
CPU time 16.11 seconds
Started Feb 18 12:35:20 PM PST 24
Finished Feb 18 12:35:40 PM PST 24
Peak memory 216080 kb
Host smart-0f716eca-8b2f-46a9-8470-6373a6113b07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244638895 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4244638895
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.117165037
Short name T73
Test name
Test status
Simulation time 2653916230 ps
CPU time 12.3 seconds
Started Feb 18 12:35:31 PM PST 24
Finished Feb 18 12:35:45 PM PST 24
Peak memory 210620 kb
Host smart-6ab13e30-8a02-4c1f-9e35-cd75c90dcc46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117165037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.117165037
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.417220029
Short name T86
Test name
Test status
Simulation time 32787057398 ps
CPU time 62.88 seconds
Started Feb 18 12:35:27 PM PST 24
Finished Feb 18 12:36:31 PM PST 24
Peak memory 210620 kb
Host smart-18bd8f52-2959-4bdc-97db-f94e7b1efff3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417220029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.417220029
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.211156452
Short name T396
Test name
Test status
Simulation time 7077991540 ps
CPU time 14.63 seconds
Started Feb 18 12:35:31 PM PST 24
Finished Feb 18 12:35:48 PM PST 24
Peak memory 210460 kb
Host smart-f481c79b-c44b-4c46-86e1-26404a2f4bdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211156452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.211156452
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4128046291
Short name T394
Test name
Test status
Simulation time 272702230 ps
CPU time 10.88 seconds
Started Feb 18 12:35:18 PM PST 24
Finished Feb 18 12:35:32 PM PST 24
Peak memory 214792 kb
Host smart-63ae5f92-1911-47d6-afe2-3bb85028b1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128046291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4128046291
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3634295957
Short name T375
Test name
Test status
Simulation time 1807709432 ps
CPU time 46.89 seconds
Started Feb 18 12:35:24 PM PST 24
Finished Feb 18 12:36:13 PM PST 24
Peak memory 210716 kb
Host smart-99f51da6-ff64-449b-9e05-145a5ca4215f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634295957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3634295957
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2157097564
Short name T432
Test name
Test status
Simulation time 2096743647 ps
CPU time 13.29 seconds
Started Feb 18 12:35:21 PM PST 24
Finished Feb 18 12:35:38 PM PST 24
Peak memory 216048 kb
Host smart-7c4f93f2-95fd-45e9-807b-a6413f93ae1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157097564 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2157097564
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.502355942
Short name T381
Test name
Test status
Simulation time 6367465589 ps
CPU time 13.41 seconds
Started Feb 18 12:35:24 PM PST 24
Finished Feb 18 12:35:40 PM PST 24
Peak memory 210656 kb
Host smart-7a3fd443-562d-4c82-aba5-2210c09fe599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502355942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.502355942
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.91799446
Short name T361
Test name
Test status
Simulation time 24742425756 ps
CPU time 67.32 seconds
Started Feb 18 12:35:20 PM PST 24
Finished Feb 18 12:36:31 PM PST 24
Peak memory 210624 kb
Host smart-c490dbf1-a010-450c-942d-1ba576cef5bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91799446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pas
sthru_mem_tl_intg_err.91799446
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1793381001
Short name T363
Test name
Test status
Simulation time 2140939452 ps
CPU time 16.58 seconds
Started Feb 18 12:35:25 PM PST 24
Finished Feb 18 12:35:43 PM PST 24
Peak memory 210624 kb
Host smart-4c1a991f-739d-4fd1-a625-f15dbb5fcd7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793381001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1793381001
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.577183352
Short name T359
Test name
Test status
Simulation time 1800285820 ps
CPU time 16.26 seconds
Started Feb 18 12:35:27 PM PST 24
Finished Feb 18 12:35:44 PM PST 24
Peak memory 214124 kb
Host smart-6f57f9d7-448a-444f-9372-a0231945e9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577183352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.577183352
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2600600807
Short name T428
Test name
Test status
Simulation time 1932506352 ps
CPU time 8.58 seconds
Started Feb 18 12:35:32 PM PST 24
Finished Feb 18 12:35:47 PM PST 24
Peak memory 214832 kb
Host smart-ce357c46-f187-47b4-9b45-d2bdc2d6575c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600600807 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2600600807
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.306620100
Short name T88
Test name
Test status
Simulation time 6114383001 ps
CPU time 13.4 seconds
Started Feb 18 12:35:23 PM PST 24
Finished Feb 18 12:35:40 PM PST 24
Peak memory 210720 kb
Host smart-76bfdcd9-78c0-459f-a0c6-6dee18b7f8bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306620100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.306620100
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1101369972
Short name T370
Test name
Test status
Simulation time 3392154801 ps
CPU time 29.23 seconds
Started Feb 18 12:35:31 PM PST 24
Finished Feb 18 12:36:02 PM PST 24
Peak memory 210536 kb
Host smart-af1afb50-a055-4cea-88bb-892fb6cbd258
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101369972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1101369972
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2310030292
Short name T100
Test name
Test status
Simulation time 2695574347 ps
CPU time 16.86 seconds
Started Feb 18 12:35:21 PM PST 24
Finished Feb 18 12:35:42 PM PST 24
Peak memory 210724 kb
Host smart-37bc8239-7d60-4605-8293-e95dfbb19cf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310030292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2310030292
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3848046557
Short name T357
Test name
Test status
Simulation time 605338561 ps
CPU time 10.67 seconds
Started Feb 18 12:35:31 PM PST 24
Finished Feb 18 12:35:44 PM PST 24
Peak memory 214588 kb
Host smart-d816c9e1-9750-4f81-a39a-b71816b07ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848046557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3848046557
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.745870560
Short name T414
Test name
Test status
Simulation time 377562035 ps
CPU time 38.16 seconds
Started Feb 18 12:35:35 PM PST 24
Finished Feb 18 12:36:16 PM PST 24
Peak memory 210696 kb
Host smart-1c5a8677-75c3-4e42-82ca-4dcd8030703e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745870560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.745870560
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.398022805
Short name T404
Test name
Test status
Simulation time 209677883 ps
CPU time 5.67 seconds
Started Feb 18 12:35:01 PM PST 24
Finished Feb 18 12:35:11 PM PST 24
Peak memory 210564 kb
Host smart-8d4103a9-d64f-44cf-8d9f-8358f265a92c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398022805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.398022805
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4014574928
Short name T380
Test name
Test status
Simulation time 4769863678 ps
CPU time 11.78 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:22 PM PST 24
Peak memory 210600 kb
Host smart-7146bbe5-b8e4-4cf3-a495-345eb007865e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014574928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4014574928
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3968554971
Short name T412
Test name
Test status
Simulation time 1122171850 ps
CPU time 12.65 seconds
Started Feb 18 12:34:59 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 210664 kb
Host smart-b5bf3760-97f0-41b7-a860-f0e395e40a6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968554971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3968554971
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1246205181
Short name T389
Test name
Test status
Simulation time 1436371482 ps
CPU time 9.18 seconds
Started Feb 18 12:34:56 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 215408 kb
Host smart-088b58f0-a11a-47af-b118-eb732d2408c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246205181 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1246205181
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2914688472
Short name T345
Test name
Test status
Simulation time 730680818 ps
CPU time 8.32 seconds
Started Feb 18 12:34:59 PM PST 24
Finished Feb 18 12:35:12 PM PST 24
Peak memory 210568 kb
Host smart-1e635284-5822-473e-ab75-733882f6d96a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914688472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2914688472
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2910765817
Short name T387
Test name
Test status
Simulation time 3659842961 ps
CPU time 14.4 seconds
Started Feb 18 12:35:01 PM PST 24
Finished Feb 18 12:35:20 PM PST 24
Peak memory 210652 kb
Host smart-47ad54c3-a72f-4c57-95ef-1acad30e410d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910765817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2910765817
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.70956262
Short name T407
Test name
Test status
Simulation time 817034000 ps
CPU time 9.27 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:20 PM PST 24
Peak memory 210488 kb
Host smart-4e664675-ab3f-4069-b187-1f2ef40c1bbf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70956262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.70956262
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.830747065
Short name T85
Test name
Test status
Simulation time 367102386 ps
CPU time 19.1 seconds
Started Feb 18 12:34:59 PM PST 24
Finished Feb 18 12:35:23 PM PST 24
Peak memory 210672 kb
Host smart-5aa8967d-0f83-4a3b-92e3-4da391084f2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830747065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.830747065
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3862582779
Short name T347
Test name
Test status
Simulation time 1930872628 ps
CPU time 14.53 seconds
Started Feb 18 12:34:59 PM PST 24
Finished Feb 18 12:35:19 PM PST 24
Peak memory 210624 kb
Host smart-eb4436c5-2592-4eee-8c1e-7af9765018c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862582779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3862582779
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1638294000
Short name T346
Test name
Test status
Simulation time 5411874061 ps
CPU time 15.65 seconds
Started Feb 18 12:35:06 PM PST 24
Finished Feb 18 12:35:23 PM PST 24
Peak memory 215364 kb
Host smart-7a6d970c-caae-48d6-8502-a941aedefca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638294000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1638294000
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2080153332
Short name T434
Test name
Test status
Simulation time 1316688922 ps
CPU time 75.53 seconds
Started Feb 18 12:34:58 PM PST 24
Finished Feb 18 12:36:17 PM PST 24
Peak memory 210656 kb
Host smart-9e80fc29-46dd-4aee-9733-8e0f9728acd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080153332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2080153332
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3766008672
Short name T367
Test name
Test status
Simulation time 179339660 ps
CPU time 4.43 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:14 PM PST 24
Peak memory 210560 kb
Host smart-d62de04b-70a2-4b0d-a3f1-857b2f294742
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766008672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3766008672
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3610279528
Short name T365
Test name
Test status
Simulation time 816011078 ps
CPU time 7.56 seconds
Started Feb 18 12:35:07 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 210596 kb
Host smart-24930a6a-790e-443f-a6d7-c0235ed388a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610279528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3610279528
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2442851965
Short name T343
Test name
Test status
Simulation time 4868834746 ps
CPU time 13.66 seconds
Started Feb 18 12:35:06 PM PST 24
Finished Feb 18 12:35:21 PM PST 24
Peak memory 210668 kb
Host smart-4d460776-5ae0-4678-a970-cef0bc8a6554
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442851965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2442851965
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2956742614
Short name T423
Test name
Test status
Simulation time 2118507402 ps
CPU time 16.94 seconds
Started Feb 18 12:35:26 PM PST 24
Finished Feb 18 12:35:44 PM PST 24
Peak memory 215400 kb
Host smart-add44378-67e5-4325-867d-9d62a452d764
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956742614 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2956742614
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.160724799
Short name T349
Test name
Test status
Simulation time 1972559397 ps
CPU time 14.74 seconds
Started Feb 18 12:35:04 PM PST 24
Finished Feb 18 12:35:21 PM PST 24
Peak memory 210600 kb
Host smart-2017212c-b8af-41b2-9739-54e08f2a7c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160724799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.160724799
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2910651545
Short name T362
Test name
Test status
Simulation time 2097530679 ps
CPU time 16.27 seconds
Started Feb 18 12:35:26 PM PST 24
Finished Feb 18 12:35:44 PM PST 24
Peak memory 210428 kb
Host smart-17a29a1f-6760-432a-b051-581068aceedd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910651545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2910651545
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2858684531
Short name T337
Test name
Test status
Simulation time 1985519482 ps
CPU time 15.65 seconds
Started Feb 18 12:35:19 PM PST 24
Finished Feb 18 12:35:37 PM PST 24
Peak memory 210512 kb
Host smart-3cddadea-c1fa-4444-b306-c052c92d8fca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858684531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2858684531
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3295102043
Short name T377
Test name
Test status
Simulation time 22748823527 ps
CPU time 65.7 seconds
Started Feb 18 12:35:01 PM PST 24
Finished Feb 18 12:36:11 PM PST 24
Peak memory 210604 kb
Host smart-8272018d-6e73-4db5-a6ae-e1841767a851
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295102043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3295102043
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1501923736
Short name T98
Test name
Test status
Simulation time 6119260304 ps
CPU time 12.61 seconds
Started Feb 18 12:35:17 PM PST 24
Finished Feb 18 12:35:32 PM PST 24
Peak memory 210708 kb
Host smart-401996bf-99a1-4015-9cce-7c8d94da1720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501923736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1501923736
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2045159598
Short name T405
Test name
Test status
Simulation time 1574855749 ps
CPU time 13.2 seconds
Started Feb 18 12:35:06 PM PST 24
Finished Feb 18 12:35:21 PM PST 24
Peak memory 215060 kb
Host smart-25c110eb-29e0-48f4-a733-7ce0d889d7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045159598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2045159598
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1661821126
Short name T108
Test name
Test status
Simulation time 2013215320 ps
CPU time 79.51 seconds
Started Feb 18 12:35:17 PM PST 24
Finished Feb 18 12:36:40 PM PST 24
Peak memory 210648 kb
Host smart-70a43c50-563b-4ca7-a85c-5bcf8d1d4ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661821126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1661821126
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3019074683
Short name T94
Test name
Test status
Simulation time 1268312274 ps
CPU time 12.2 seconds
Started Feb 18 12:35:05 PM PST 24
Finished Feb 18 12:35:19 PM PST 24
Peak memory 210636 kb
Host smart-0281daf9-339c-4227-a8ef-19fa062f8e52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019074683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3019074683
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.752019745
Short name T390
Test name
Test status
Simulation time 1073520743 ps
CPU time 11.05 seconds
Started Feb 18 12:35:02 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 210632 kb
Host smart-b0f93f88-fe26-456b-8cf5-59a1d314486b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752019745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.752019745
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4159291094
Short name T420
Test name
Test status
Simulation time 90425626 ps
CPU time 5.68 seconds
Started Feb 18 12:35:18 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 210584 kb
Host smart-527161a5-d01f-482b-b0d9-fc6ee424bdd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159291094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4159291094
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2762856819
Short name T395
Test name
Test status
Simulation time 1990734217 ps
CPU time 16.47 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 214912 kb
Host smart-ba62d991-ff3d-4d28-9960-5d9fa59f5d5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762856819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2762856819
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1713542014
Short name T385
Test name
Test status
Simulation time 438763592 ps
CPU time 6.99 seconds
Started Feb 18 12:35:02 PM PST 24
Finished Feb 18 12:35:13 PM PST 24
Peak memory 210560 kb
Host smart-12e708f9-9cd0-424b-afe1-3f8328438baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713542014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1713542014
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.590115276
Short name T371
Test name
Test status
Simulation time 7927040238 ps
CPU time 10.43 seconds
Started Feb 18 12:35:18 PM PST 24
Finished Feb 18 12:35:31 PM PST 24
Peak memory 210644 kb
Host smart-30accaf6-e953-4d8a-a820-f9bf0eb1c1c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590115276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.590115276
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1091296089
Short name T378
Test name
Test status
Simulation time 2865786930 ps
CPU time 10.43 seconds
Started Feb 18 12:35:05 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 210568 kb
Host smart-32862800-d5cb-4493-90e8-9bc482cf77c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091296089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1091296089
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4218599558
Short name T92
Test name
Test status
Simulation time 35088202649 ps
CPU time 37.06 seconds
Started Feb 18 12:35:06 PM PST 24
Finished Feb 18 12:35:44 PM PST 24
Peak memory 210668 kb
Host smart-e57e216a-75d8-44d0-95ff-3add60b3f32d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218599558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4218599558
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3665332402
Short name T397
Test name
Test status
Simulation time 1313492645 ps
CPU time 5.99 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:15 PM PST 24
Peak memory 210592 kb
Host smart-2a1860ca-6720-4f41-86df-bdb094f4ba42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665332402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3665332402
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4031231012
Short name T391
Test name
Test status
Simulation time 417140966 ps
CPU time 7.03 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 214840 kb
Host smart-9274624e-d7ad-4d8d-91f2-0689b2019c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031231012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4031231012
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2025310187
Short name T105
Test name
Test status
Simulation time 21969615131 ps
CPU time 77.31 seconds
Started Feb 18 12:35:07 PM PST 24
Finished Feb 18 12:36:26 PM PST 24
Peak memory 211756 kb
Host smart-0377411f-7777-43a3-af12-6d6ac7e95892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025310187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2025310187
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3876023549
Short name T406
Test name
Test status
Simulation time 151308297 ps
CPU time 7.15 seconds
Started Feb 18 12:35:17 PM PST 24
Finished Feb 18 12:35:27 PM PST 24
Peak memory 214628 kb
Host smart-d8a5b708-a494-49da-bb2a-e4ce5205fba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876023549 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3876023549
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1977962586
Short name T402
Test name
Test status
Simulation time 88852792 ps
CPU time 4.16 seconds
Started Feb 18 12:35:08 PM PST 24
Finished Feb 18 12:35:14 PM PST 24
Peak memory 210564 kb
Host smart-590358c5-684c-4d9a-8422-0ea3aa1c6458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977962586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1977962586
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.521779993
Short name T71
Test name
Test status
Simulation time 347527310 ps
CPU time 4.42 seconds
Started Feb 18 12:35:03 PM PST 24
Finished Feb 18 12:35:10 PM PST 24
Peak memory 210580 kb
Host smart-d8b16fbc-e6ef-4fe3-944f-a614d178b620
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521779993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.521779993
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1464792112
Short name T383
Test name
Test status
Simulation time 237967405 ps
CPU time 8.61 seconds
Started Feb 18 12:35:18 PM PST 24
Finished Feb 18 12:35:29 PM PST 24
Peak memory 214912 kb
Host smart-4d595ed0-ca28-4f61-b450-c8fa04a22324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464792112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1464792112
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.110119640
Short name T106
Test name
Test status
Simulation time 1563033177 ps
CPU time 73.99 seconds
Started Feb 18 12:35:05 PM PST 24
Finished Feb 18 12:36:20 PM PST 24
Peak memory 212204 kb
Host smart-7d8b0e9d-19a3-4dc3-bd1b-ceb2922c77cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110119640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.110119640
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.207767194
Short name T341
Test name
Test status
Simulation time 7764631938 ps
CPU time 16.3 seconds
Started Feb 18 12:35:28 PM PST 24
Finished Feb 18 12:35:46 PM PST 24
Peak memory 216352 kb
Host smart-3345399d-51df-4049-9bc2-e6ad68166bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207767194 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.207767194
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.318339651
Short name T403
Test name
Test status
Simulation time 1949320509 ps
CPU time 15.15 seconds
Started Feb 18 12:35:15 PM PST 24
Finished Feb 18 12:35:34 PM PST 24
Peak memory 210576 kb
Host smart-d06b4f6a-837a-4e14-8e66-2dd71f23224c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318339651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.318339651
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.906309565
Short name T93
Test name
Test status
Simulation time 32283963764 ps
CPU time 42.82 seconds
Started Feb 18 12:35:10 PM PST 24
Finished Feb 18 12:35:54 PM PST 24
Peak memory 210652 kb
Host smart-f3dabaef-8a8a-47dd-870c-85fd4bb4ffcb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906309565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.906309565
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2259478370
Short name T388
Test name
Test status
Simulation time 1377634722 ps
CPU time 4.13 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:35:20 PM PST 24
Peak memory 210624 kb
Host smart-8338b2ee-42ad-498c-b47c-03e0d1edb11b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259478370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2259478370
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.868860880
Short name T338
Test name
Test status
Simulation time 923530334 ps
CPU time 9.03 seconds
Started Feb 18 12:35:10 PM PST 24
Finished Feb 18 12:35:20 PM PST 24
Peak memory 214912 kb
Host smart-4282218c-258f-48fc-b388-640c48b240ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868860880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.868860880
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3740600992
Short name T107
Test name
Test status
Simulation time 788999485 ps
CPU time 68.83 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:36:25 PM PST 24
Peak memory 211492 kb
Host smart-3a06e0b9-ff45-4b12-8ed0-7b4eb4ba5fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740600992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3740600992
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1624468805
Short name T373
Test name
Test status
Simulation time 237041952 ps
CPU time 10.77 seconds
Started Feb 18 12:35:12 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 215256 kb
Host smart-1e773769-2209-4465-9422-d64bb84f31e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624468805 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1624468805
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4147336478
Short name T436
Test name
Test status
Simulation time 2153993251 ps
CPU time 10.85 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 210592 kb
Host smart-3439c78c-474e-4683-8e7f-ce7695d79c5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147336478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4147336478
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.495219416
Short name T74
Test name
Test status
Simulation time 14417519130 ps
CPU time 57.74 seconds
Started Feb 18 12:35:15 PM PST 24
Finished Feb 18 12:36:15 PM PST 24
Peak memory 210628 kb
Host smart-8f75e3b5-95e8-4c8d-8137-cedeb3ae5868
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495219416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.495219416
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1995331268
Short name T63
Test name
Test status
Simulation time 8597705556 ps
CPU time 16.71 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:35:33 PM PST 24
Peak memory 210536 kb
Host smart-dcbad67b-f46c-4087-b47c-4deb397af1e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995331268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1995331268
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3898813797
Short name T366
Test name
Test status
Simulation time 346416002 ps
CPU time 6.42 seconds
Started Feb 18 12:35:26 PM PST 24
Finished Feb 18 12:35:34 PM PST 24
Peak memory 214508 kb
Host smart-39f62672-83bb-4cf3-a36b-28591d94fb09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898813797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3898813797
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1216170603
Short name T425
Test name
Test status
Simulation time 5408139162 ps
CPU time 44.23 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:36:00 PM PST 24
Peak memory 211576 kb
Host smart-ed11e1d0-4372-4879-bd00-3f5c539525fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216170603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1216170603
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3047698755
Short name T424
Test name
Test status
Simulation time 1910562770 ps
CPU time 10.82 seconds
Started Feb 18 12:35:11 PM PST 24
Finished Feb 18 12:35:25 PM PST 24
Peak memory 213548 kb
Host smart-2e5be50f-4ed3-4759-91dc-dbf4051ee24e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047698755 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3047698755
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.147122954
Short name T360
Test name
Test status
Simulation time 2408838273 ps
CPU time 11.35 seconds
Started Feb 18 12:35:12 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 210648 kb
Host smart-23c52e53-2d65-4293-be8b-bbcd8204db3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147122954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.147122954
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3363548628
Short name T413
Test name
Test status
Simulation time 8249277560 ps
CPU time 69.9 seconds
Started Feb 18 12:35:13 PM PST 24
Finished Feb 18 12:36:26 PM PST 24
Peak memory 210656 kb
Host smart-f44c365e-fecc-4790-8c2a-bb7e1589ed86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363548628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3363548628
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2979081076
Short name T352
Test name
Test status
Simulation time 1759746955 ps
CPU time 16.44 seconds
Started Feb 18 12:35:15 PM PST 24
Finished Feb 18 12:35:33 PM PST 24
Peak memory 210592 kb
Host smart-7c727d7c-8aff-4d33-b4c9-d21d1b96158d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979081076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2979081076
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1392785745
Short name T356
Test name
Test status
Simulation time 225750601 ps
CPU time 6.21 seconds
Started Feb 18 12:35:20 PM PST 24
Finished Feb 18 12:35:29 PM PST 24
Peak memory 214660 kb
Host smart-d9f12efe-b7fb-4832-9796-9a1c8ab1e999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392785745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1392785745
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2650362422
Short name T401
Test name
Test status
Simulation time 5628536568 ps
CPU time 42.71 seconds
Started Feb 18 12:35:16 PM PST 24
Finished Feb 18 12:36:02 PM PST 24
Peak memory 211532 kb
Host smart-09c17105-345b-4b68-8cad-0df23e19a4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650362422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2650362422
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2248513568
Short name T415
Test name
Test status
Simulation time 1324914192 ps
CPU time 14.35 seconds
Started Feb 18 12:35:11 PM PST 24
Finished Feb 18 12:35:27 PM PST 24
Peak memory 216316 kb
Host smart-67f301f3-3d15-49fb-b6bd-1b4b1be962bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248513568 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2248513568
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.270276450
Short name T76
Test name
Test status
Simulation time 2074313286 ps
CPU time 7.47 seconds
Started Feb 18 12:35:22 PM PST 24
Finished Feb 18 12:35:33 PM PST 24
Peak memory 210508 kb
Host smart-b1d7265d-2402-4818-8593-0f74b34077d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270276450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.270276450
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.962866975
Short name T87
Test name
Test status
Simulation time 2217052192 ps
CPU time 27.32 seconds
Started Feb 18 12:35:15 PM PST 24
Finished Feb 18 12:35:44 PM PST 24
Peak memory 210632 kb
Host smart-2c9c2987-50e4-4db6-8f3e-8acb7670a691
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962866975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.962866975
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.882951003
Short name T364
Test name
Test status
Simulation time 1807048667 ps
CPU time 10.32 seconds
Started Feb 18 12:35:11 PM PST 24
Finished Feb 18 12:35:23 PM PST 24
Peak memory 210640 kb
Host smart-eedf85af-e21a-41cb-9ff2-f4a8ba669d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882951003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.882951003
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1916322489
Short name T351
Test name
Test status
Simulation time 423894724 ps
CPU time 11.32 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:35:28 PM PST 24
Peak memory 214960 kb
Host smart-722bbf12-6d78-4829-951e-fa7a7baf35df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916322489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1916322489
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1131466124
Short name T112
Test name
Test status
Simulation time 200524719 ps
CPU time 38.12 seconds
Started Feb 18 12:35:15 PM PST 24
Finished Feb 18 12:35:55 PM PST 24
Peak memory 211204 kb
Host smart-1c369ed1-5a8d-41ba-82ac-174bd0a24d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131466124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1131466124
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.513546965
Short name T218
Test name
Test status
Simulation time 326912914 ps
CPU time 5.82 seconds
Started Feb 18 12:41:15 PM PST 24
Finished Feb 18 12:41:24 PM PST 24
Peak memory 211044 kb
Host smart-6e2646aa-b237-45bd-81c3-828dc8118293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513546965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.513546965
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2596965325
Short name T163
Test name
Test status
Simulation time 7873703653 ps
CPU time 31.76 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:41:49 PM PST 24
Peak memory 211148 kb
Host smart-91f4c9b0-2914-4bf4-b988-ccc3033ddbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596965325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2596965325
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2217624179
Short name T292
Test name
Test status
Simulation time 4132229994 ps
CPU time 16.39 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:41:34 PM PST 24
Peak memory 211164 kb
Host smart-d7af18dd-030d-4635-9a7d-daf006a89f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217624179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2217624179
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.894169790
Short name T225
Test name
Test status
Simulation time 6191096063 ps
CPU time 44.54 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:42:01 PM PST 24
Peak memory 213888 kb
Host smart-22f549ff-2bce-467a-9fa3-ac72b6b2f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894169790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.894169790
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1772880196
Short name T323
Test name
Test status
Simulation time 387303693 ps
CPU time 22.26 seconds
Started Feb 18 12:41:13 PM PST 24
Finished Feb 18 12:41:40 PM PST 24
Peak memory 215320 kb
Host smart-070edf78-b10b-44b3-a9cd-21c92c5198c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772880196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1772880196
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.501210545
Short name T298
Test name
Test status
Simulation time 1225281089 ps
CPU time 11.82 seconds
Started Feb 18 12:41:16 PM PST 24
Finished Feb 18 12:41:31 PM PST 24
Peak memory 210992 kb
Host smart-f94a7b78-1db7-409d-8ca1-ff56a49776a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501210545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.501210545
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1393856512
Short name T29
Test name
Test status
Simulation time 2583755725 ps
CPU time 148.3 seconds
Started Feb 18 12:41:19 PM PST 24
Finished Feb 18 12:43:48 PM PST 24
Peak memory 237700 kb
Host smart-5faf9b85-0b82-4a8f-844e-abd2de400790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393856512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1393856512
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2842011339
Short name T221
Test name
Test status
Simulation time 4344868327 ps
CPU time 22.93 seconds
Started Feb 18 12:41:16 PM PST 24
Finished Feb 18 12:41:42 PM PST 24
Peak memory 211836 kb
Host smart-a07ac260-bde7-4db9-9a3e-c85683fc4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842011339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2842011339
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2874788828
Short name T276
Test name
Test status
Simulation time 424716069 ps
CPU time 8.07 seconds
Started Feb 18 12:41:16 PM PST 24
Finished Feb 18 12:41:27 PM PST 24
Peak memory 210944 kb
Host smart-9126e203-3090-47bd-b3d1-3eb9a173693d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2874788828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2874788828
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1425840382
Short name T41
Test name
Test status
Simulation time 2326556787 ps
CPU time 107.96 seconds
Started Feb 18 12:41:19 PM PST 24
Finished Feb 18 12:43:08 PM PST 24
Peak memory 236592 kb
Host smart-417433f9-dc40-4580-a8ca-580cc09421cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425840382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1425840382
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3584985404
Short name T82
Test name
Test status
Simulation time 182079308 ps
CPU time 10.36 seconds
Started Feb 18 12:41:17 PM PST 24
Finished Feb 18 12:41:30 PM PST 24
Peak memory 212824 kb
Host smart-c677172e-7c55-41f1-aa85-ae4f4433efed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584985404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3584985404
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.609121588
Short name T315
Test name
Test status
Simulation time 2637880157 ps
CPU time 33.82 seconds
Started Feb 18 12:41:18 PM PST 24
Finished Feb 18 12:41:53 PM PST 24
Peak memory 215392 kb
Host smart-120d0cf8-4ae6-4f27-a5b5-8c8b74c7a91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609121588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.609121588
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2005718587
Short name T148
Test name
Test status
Simulation time 1909243312 ps
CPU time 16.15 seconds
Started Feb 18 12:41:37 PM PST 24
Finished Feb 18 12:41:55 PM PST 24
Peak memory 210996 kb
Host smart-426315da-f1ba-4dae-b3ea-08774e613088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005718587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2005718587
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3592178997
Short name T9
Test name
Test status
Simulation time 15194329503 ps
CPU time 21.89 seconds
Started Feb 18 12:41:37 PM PST 24
Finished Feb 18 12:42:01 PM PST 24
Peak memory 213664 kb
Host smart-5f26f3bc-77b0-4573-ab17-055f42a2663f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592178997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3592178997
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1801965150
Short name T295
Test name
Test status
Simulation time 4840966009 ps
CPU time 50.28 seconds
Started Feb 18 12:41:37 PM PST 24
Finished Feb 18 12:42:29 PM PST 24
Peak memory 213116 kb
Host smart-824e1f00-1889-40ad-8ef5-1a37784834a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801965150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1801965150
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3185624263
Short name T209
Test name
Test status
Simulation time 6453990945 ps
CPU time 14.84 seconds
Started Feb 18 12:41:36 PM PST 24
Finished Feb 18 12:41:53 PM PST 24
Peak memory 211100 kb
Host smart-73ac4ece-44db-44a8-9122-f9c2e679e254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185624263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3185624263
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1290948376
Short name T182
Test name
Test status
Simulation time 2223611617 ps
CPU time 16.62 seconds
Started Feb 18 12:41:38 PM PST 24
Finished Feb 18 12:41:56 PM PST 24
Peak memory 211396 kb
Host smart-8e168363-b17d-42d4-897c-47763a8b35a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290948376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1290948376
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1214353280
Short name T189
Test name
Test status
Simulation time 341167045 ps
CPU time 7.93 seconds
Started Feb 18 12:41:40 PM PST 24
Finished Feb 18 12:41:48 PM PST 24
Peak memory 211004 kb
Host smart-ae967b6c-4f69-4c91-ad29-5ad6ce70b39c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214353280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1214353280
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1238881726
Short name T118
Test name
Test status
Simulation time 28262370154 ps
CPU time 30.34 seconds
Started Feb 18 12:41:39 PM PST 24
Finished Feb 18 12:42:10 PM PST 24
Peak memory 214340 kb
Host smart-95374e91-e9c0-48fe-a2f2-c02aae76b8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238881726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1238881726
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3411539494
Short name T309
Test name
Test status
Simulation time 3239378655 ps
CPU time 28.4 seconds
Started Feb 18 12:41:39 PM PST 24
Finished Feb 18 12:42:09 PM PST 24
Peak memory 213168 kb
Host smart-97e4fc91-0803-4327-bf66-79770f12f367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411539494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3411539494
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1913325260
Short name T205
Test name
Test status
Simulation time 10632942648 ps
CPU time 13.88 seconds
Started Feb 18 12:41:46 PM PST 24
Finished Feb 18 12:42:01 PM PST 24
Peak memory 211224 kb
Host smart-2976f0c5-31ae-4727-ac3b-12e5b247aa1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913325260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1913325260
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1937707183
Short name T171
Test name
Test status
Simulation time 2464241165 ps
CPU time 24.18 seconds
Started Feb 18 12:41:45 PM PST 24
Finished Feb 18 12:42:10 PM PST 24
Peak memory 211084 kb
Host smart-42d0d5aa-9ebb-4702-8f50-fb69177fa730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937707183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1937707183
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3282053932
Short name T178
Test name
Test status
Simulation time 1793800314 ps
CPU time 15.86 seconds
Started Feb 18 12:41:43 PM PST 24
Finished Feb 18 12:42:00 PM PST 24
Peak memory 211028 kb
Host smart-54e63334-4069-4635-8bcc-1604b32f7ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282053932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3282053932
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1589683101
Short name T288
Test name
Test status
Simulation time 2817359115 ps
CPU time 32.1 seconds
Started Feb 18 12:41:41 PM PST 24
Finished Feb 18 12:42:13 PM PST 24
Peak memory 213476 kb
Host smart-3fb1e163-4548-46b4-aad0-f3dd12e57958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589683101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1589683101
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4150801263
Short name T270
Test name
Test status
Simulation time 7933328960 ps
CPU time 45.84 seconds
Started Feb 18 12:41:36 PM PST 24
Finished Feb 18 12:42:24 PM PST 24
Peak memory 216596 kb
Host smart-62044e19-d7a7-420c-9b42-9da4fba060be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150801263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4150801263
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.905201070
Short name T242
Test name
Test status
Simulation time 6675823857 ps
CPU time 14.03 seconds
Started Feb 18 12:41:42 PM PST 24
Finished Feb 18 12:41:57 PM PST 24
Peak memory 211188 kb
Host smart-ff09471d-d057-41af-97a4-3ff3f0c05e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905201070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.905201070
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2603103147
Short name T128
Test name
Test status
Simulation time 1439797223 ps
CPU time 13.79 seconds
Started Feb 18 12:41:47 PM PST 24
Finished Feb 18 12:42:01 PM PST 24
Peak memory 211064 kb
Host smart-9192129d-3e65-4adb-9563-451799965c2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603103147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2603103147
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.966717544
Short name T333
Test name
Test status
Simulation time 10882613093 ps
CPU time 31.18 seconds
Started Feb 18 12:41:41 PM PST 24
Finished Feb 18 12:42:13 PM PST 24
Peak memory 213420 kb
Host smart-e9409f7c-a2fc-4ebe-8f70-dfeb0dff6e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966717544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.966717544
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3800029043
Short name T207
Test name
Test status
Simulation time 10078482798 ps
CPU time 46.7 seconds
Started Feb 18 12:41:43 PM PST 24
Finished Feb 18 12:42:31 PM PST 24
Peak memory 213852 kb
Host smart-359a263d-5c18-466a-8401-c1ce3c5d1402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800029043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3800029043
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.446597087
Short name T45
Test name
Test status
Simulation time 141777203703 ps
CPU time 2673.39 seconds
Started Feb 18 12:41:40 PM PST 24
Finished Feb 18 01:26:15 PM PST 24
Peak memory 251780 kb
Host smart-2591194e-f3d0-4339-8f29-7ceea11c1615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446597087 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.446597087
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.600403644
Short name T300
Test name
Test status
Simulation time 1597324252 ps
CPU time 14.12 seconds
Started Feb 18 12:41:48 PM PST 24
Finished Feb 18 12:42:04 PM PST 24
Peak memory 211104 kb
Host smart-2a4dff0f-5eb1-409b-a588-c397b654a8dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600403644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.600403644
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3271275058
Short name T191
Test name
Test status
Simulation time 16726078937 ps
CPU time 33.31 seconds
Started Feb 18 12:41:42 PM PST 24
Finished Feb 18 12:42:17 PM PST 24
Peak memory 211984 kb
Host smart-2c873247-cee2-46d2-8739-bc249ff182cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271275058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3271275058
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2657614405
Short name T214
Test name
Test status
Simulation time 5085292315 ps
CPU time 12.29 seconds
Started Feb 18 12:41:41 PM PST 24
Finished Feb 18 12:41:54 PM PST 24
Peak memory 211260 kb
Host smart-697e16b9-a4d4-48f7-a721-7a25425bc953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657614405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2657614405
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1066311705
Short name T332
Test name
Test status
Simulation time 12596158152 ps
CPU time 30.03 seconds
Started Feb 18 12:41:42 PM PST 24
Finished Feb 18 12:42:13 PM PST 24
Peak memory 214328 kb
Host smart-0aa24a23-43c4-4874-bca6-b5e74b2e960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066311705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1066311705
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3660715180
Short name T156
Test name
Test status
Simulation time 7802741419 ps
CPU time 30.26 seconds
Started Feb 18 12:41:42 PM PST 24
Finished Feb 18 12:42:13 PM PST 24
Peak memory 213652 kb
Host smart-2a87c29d-47b0-4007-a366-fe7230f127b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660715180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3660715180
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.837746214
Short name T206
Test name
Test status
Simulation time 2049265486 ps
CPU time 17.81 seconds
Started Feb 18 12:41:49 PM PST 24
Finished Feb 18 12:42:09 PM PST 24
Peak memory 211076 kb
Host smart-4a5a76c2-01c7-44fc-812e-c86358ab962e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837746214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.837746214
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2745134303
Short name T279
Test name
Test status
Simulation time 313168509824 ps
CPU time 424.52 seconds
Started Feb 18 12:41:52 PM PST 24
Finished Feb 18 12:48:59 PM PST 24
Peak memory 240372 kb
Host smart-cccad63e-98ae-4b2d-bd60-74b26cf48e61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745134303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2745134303
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3675008480
Short name T223
Test name
Test status
Simulation time 181367508 ps
CPU time 9.71 seconds
Started Feb 18 12:41:48 PM PST 24
Finished Feb 18 12:41:59 PM PST 24
Peak memory 211492 kb
Host smart-a4d84966-1d88-4ff4-88fe-fc54ac166f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675008480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3675008480
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.405592399
Short name T238
Test name
Test status
Simulation time 1501874761 ps
CPU time 7.02 seconds
Started Feb 18 12:41:53 PM PST 24
Finished Feb 18 12:42:02 PM PST 24
Peak memory 211076 kb
Host smart-a476202a-1180-4088-8fa3-9ec033d049a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405592399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.405592399
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.672705281
Short name T201
Test name
Test status
Simulation time 3751011944 ps
CPU time 11.96 seconds
Started Feb 18 12:41:50 PM PST 24
Finished Feb 18 12:42:03 PM PST 24
Peak memory 212944 kb
Host smart-4e3a86b1-89ae-47d7-9e33-0a0e2bcd1414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672705281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.672705281
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1311867661
Short name T216
Test name
Test status
Simulation time 5922704715 ps
CPU time 27.42 seconds
Started Feb 18 12:41:52 PM PST 24
Finished Feb 18 12:42:22 PM PST 24
Peak memory 217592 kb
Host smart-7d7d6b68-14aa-4395-8d03-0fad1319ce05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311867661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1311867661
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3568872540
Short name T174
Test name
Test status
Simulation time 1590679922 ps
CPU time 12.29 seconds
Started Feb 18 12:41:53 PM PST 24
Finished Feb 18 12:42:07 PM PST 24
Peak memory 211064 kb
Host smart-6708d394-9e5c-4eb5-9193-5ed597a1e428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568872540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3568872540
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.502943240
Short name T296
Test name
Test status
Simulation time 28227727960 ps
CPU time 208.59 seconds
Started Feb 18 12:41:50 PM PST 24
Finished Feb 18 12:45:20 PM PST 24
Peak memory 233732 kb
Host smart-03ccfe99-bae0-4978-b88c-67c22675455a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502943240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.502943240
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1291565938
Short name T184
Test name
Test status
Simulation time 6567355662 ps
CPU time 20.53 seconds
Started Feb 18 12:41:48 PM PST 24
Finished Feb 18 12:42:09 PM PST 24
Peak memory 212384 kb
Host smart-2a654cc4-bedb-41f8-9d93-ab80dbb03b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291565938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1291565938
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3509521996
Short name T319
Test name
Test status
Simulation time 2108743530 ps
CPU time 11.88 seconds
Started Feb 18 12:41:49 PM PST 24
Finished Feb 18 12:42:03 PM PST 24
Peak memory 211136 kb
Host smart-4567fab7-bff6-4b37-bbf0-b21818d51fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509521996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3509521996
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1159044398
Short name T42
Test name
Test status
Simulation time 4316475158 ps
CPU time 25.97 seconds
Started Feb 18 12:41:49 PM PST 24
Finished Feb 18 12:42:17 PM PST 24
Peak memory 212668 kb
Host smart-f6dab9fb-3127-45c9-8910-7221547778ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159044398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1159044398
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2495291388
Short name T55
Test name
Test status
Simulation time 3946140135 ps
CPU time 43.05 seconds
Started Feb 18 12:41:49 PM PST 24
Finished Feb 18 12:42:34 PM PST 24
Peak memory 213016 kb
Host smart-70e7a63c-9978-496f-afc4-da128eca7ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495291388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2495291388
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1663350227
Short name T219
Test name
Test status
Simulation time 1152418813 ps
CPU time 11.54 seconds
Started Feb 18 12:41:49 PM PST 24
Finished Feb 18 12:42:02 PM PST 24
Peak memory 210992 kb
Host smart-bb6f8d49-3fdd-43cb-828f-c05936c513c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663350227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1663350227
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1106059466
Short name T203
Test name
Test status
Simulation time 38676937357 ps
CPU time 197.43 seconds
Started Feb 18 12:41:47 PM PST 24
Finished Feb 18 12:45:05 PM PST 24
Peak memory 237776 kb
Host smart-fc6e93fb-6b62-4d0b-ba6b-b3edbf05eb34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106059466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1106059466
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2331700611
Short name T249
Test name
Test status
Simulation time 175986310 ps
CPU time 9.52 seconds
Started Feb 18 12:41:50 PM PST 24
Finished Feb 18 12:42:01 PM PST 24
Peak memory 211996 kb
Host smart-47312106-57e1-4f55-bd85-a7c126d1dcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331700611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2331700611
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3665212904
Short name T151
Test name
Test status
Simulation time 13244687463 ps
CPU time 13.17 seconds
Started Feb 18 12:41:48 PM PST 24
Finished Feb 18 12:42:02 PM PST 24
Peak memory 211000 kb
Host smart-6cebd092-b068-45e1-8886-c3517eb0a877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665212904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3665212904
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2020093534
Short name T304
Test name
Test status
Simulation time 24714976986 ps
CPU time 31.78 seconds
Started Feb 18 12:41:48 PM PST 24
Finished Feb 18 12:42:22 PM PST 24
Peak memory 214324 kb
Host smart-928182a9-bfab-4ca7-ae64-0b48df9b5873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020093534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2020093534
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2427874062
Short name T120
Test name
Test status
Simulation time 672683461 ps
CPU time 7.62 seconds
Started Feb 18 12:41:46 PM PST 24
Finished Feb 18 12:41:55 PM PST 24
Peak memory 211056 kb
Host smart-b43cf1e8-7997-4a11-a29f-4a04a5c41c18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427874062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2427874062
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3217603496
Short name T152
Test name
Test status
Simulation time 4598002542 ps
CPU time 11.42 seconds
Started Feb 18 12:41:55 PM PST 24
Finished Feb 18 12:42:08 PM PST 24
Peak memory 211168 kb
Host smart-879b9a82-1264-4564-b980-43106b9130fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217603496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3217603496
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3168514848
Short name T228
Test name
Test status
Simulation time 5626555785 ps
CPU time 98.78 seconds
Started Feb 18 12:41:55 PM PST 24
Finished Feb 18 12:43:35 PM PST 24
Peak memory 228508 kb
Host smart-78470f33-ec8d-4ed7-9507-0015957536a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168514848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3168514848
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.847336063
Short name T312
Test name
Test status
Simulation time 5242665072 ps
CPU time 18.55 seconds
Started Feb 18 12:41:55 PM PST 24
Finished Feb 18 12:42:15 PM PST 24
Peak memory 211960 kb
Host smart-e68c05a6-19dd-4d75-ae0d-27bbcf7f3def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847336063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.847336063
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3731612138
Short name T160
Test name
Test status
Simulation time 1705366301 ps
CPU time 15.66 seconds
Started Feb 18 12:41:53 PM PST 24
Finished Feb 18 12:42:11 PM PST 24
Peak memory 211080 kb
Host smart-40a24b86-15e0-4242-a3d0-2dc875898fd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731612138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3731612138
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.13138375
Short name T177
Test name
Test status
Simulation time 1085159178 ps
CPU time 10.72 seconds
Started Feb 18 12:42:01 PM PST 24
Finished Feb 18 12:42:17 PM PST 24
Peak memory 213556 kb
Host smart-17ce20bb-f982-409c-9029-4b0bab0600ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13138375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.13138375
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3707992241
Short name T202
Test name
Test status
Simulation time 1974862866 ps
CPU time 20.28 seconds
Started Feb 18 12:41:54 PM PST 24
Finished Feb 18 12:42:16 PM PST 24
Peak memory 210936 kb
Host smart-88f6d28b-1b3e-44de-8fa8-3a39892d5484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707992241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3707992241
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.166955341
Short name T51
Test name
Test status
Simulation time 76440516624 ps
CPU time 743.15 seconds
Started Feb 18 12:41:54 PM PST 24
Finished Feb 18 12:54:19 PM PST 24
Peak memory 231108 kb
Host smart-8e08e70e-b0bb-465b-98ea-6ac6e70b02a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166955341 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.166955341
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.994560060
Short name T217
Test name
Test status
Simulation time 711599455 ps
CPU time 9 seconds
Started Feb 18 12:41:56 PM PST 24
Finished Feb 18 12:42:06 PM PST 24
Peak memory 211096 kb
Host smart-b3cc1e45-e99e-4f44-96e9-1d830faf340e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994560060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.994560060
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4060447594
Short name T253
Test name
Test status
Simulation time 10500722947 ps
CPU time 127.41 seconds
Started Feb 18 12:41:55 PM PST 24
Finished Feb 18 12:44:04 PM PST 24
Peak memory 236748 kb
Host smart-62180a03-16cb-4587-bb41-9b66b05b2671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060447594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4060447594
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.470872247
Short name T145
Test name
Test status
Simulation time 257877295 ps
CPU time 10.84 seconds
Started Feb 18 12:41:53 PM PST 24
Finished Feb 18 12:42:06 PM PST 24
Peak memory 211092 kb
Host smart-b19029d8-06e2-4bde-a5d7-aec109c6af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470872247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.470872247
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1489709670
Short name T334
Test name
Test status
Simulation time 2720812298 ps
CPU time 13.72 seconds
Started Feb 18 12:41:55 PM PST 24
Finished Feb 18 12:42:10 PM PST 24
Peak memory 211156 kb
Host smart-d88f6878-4a83-4e48-9e5e-8d7c97244f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489709670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1489709670
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.48985251
Short name T224
Test name
Test status
Simulation time 4120663655 ps
CPU time 41.3 seconds
Started Feb 18 12:41:53 PM PST 24
Finished Feb 18 12:42:36 PM PST 24
Peak memory 212720 kb
Host smart-0158da1e-6c37-40cb-a8cd-eb6da3e8f278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48985251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.48985251
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3094501573
Short name T330
Test name
Test status
Simulation time 61158979127 ps
CPU time 137.37 seconds
Started Feb 18 12:41:54 PM PST 24
Finished Feb 18 12:44:13 PM PST 24
Peak memory 219340 kb
Host smart-e9c635d7-2202-4395-a2c9-d0f0e06b8626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094501573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3094501573
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2068900310
Short name T324
Test name
Test status
Simulation time 4576308052 ps
CPU time 11.79 seconds
Started Feb 18 12:41:16 PM PST 24
Finished Feb 18 12:41:31 PM PST 24
Peak memory 211212 kb
Host smart-2b46f36e-135a-476d-a306-64dd11ab42ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068900310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2068900310
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.896750420
Short name T247
Test name
Test status
Simulation time 380130890211 ps
CPU time 358.59 seconds
Started Feb 18 12:41:19 PM PST 24
Finished Feb 18 12:47:19 PM PST 24
Peak memory 237716 kb
Host smart-7761dff8-13e9-48a4-a454-d7076d43843a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896750420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.896750420
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1151741506
Short name T246
Test name
Test status
Simulation time 5181450615 ps
CPU time 24.3 seconds
Started Feb 18 12:41:19 PM PST 24
Finished Feb 18 12:41:45 PM PST 24
Peak memory 211904 kb
Host smart-5c254ac1-5de4-43e4-9106-5a0c5eae0c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151741506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1151741506
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.841067324
Short name T317
Test name
Test status
Simulation time 17433212421 ps
CPU time 14.18 seconds
Started Feb 18 12:41:19 PM PST 24
Finished Feb 18 12:41:34 PM PST 24
Peak memory 211136 kb
Host smart-080d8b42-0b15-4998-94bb-313474c16aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841067324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.841067324
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1757599346
Short name T40
Test name
Test status
Simulation time 16655555092 ps
CPU time 109.47 seconds
Started Feb 18 12:41:16 PM PST 24
Finished Feb 18 12:43:08 PM PST 24
Peak memory 232972 kb
Host smart-3a495e2e-185d-47d1-b802-f2c50feb71dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757599346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1757599346
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2958711120
Short name T17
Test name
Test status
Simulation time 1584852916 ps
CPU time 26.64 seconds
Started Feb 18 12:41:18 PM PST 24
Finished Feb 18 12:41:46 PM PST 24
Peak memory 212904 kb
Host smart-e5ac3f4d-5693-40df-83f2-afe2594ed259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958711120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2958711120
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2413706004
Short name T139
Test name
Test status
Simulation time 97708843 ps
CPU time 4.49 seconds
Started Feb 18 12:42:00 PM PST 24
Finished Feb 18 12:42:08 PM PST 24
Peak memory 211052 kb
Host smart-27dccc99-1e66-499d-818e-b297b4ed8071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413706004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2413706004
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1906256800
Short name T322
Test name
Test status
Simulation time 25254456724 ps
CPU time 232.49 seconds
Started Feb 18 12:41:54 PM PST 24
Finished Feb 18 12:45:49 PM PST 24
Peak memory 224584 kb
Host smart-a7d6b6bb-7adf-4bb0-817b-cbb7f1bee7df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906256800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1906256800
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1345982321
Short name T56
Test name
Test status
Simulation time 4098881773 ps
CPU time 21.27 seconds
Started Feb 18 12:42:03 PM PST 24
Finished Feb 18 12:42:29 PM PST 24
Peak memory 212208 kb
Host smart-024c7dcd-074f-4073-a766-139641c724bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345982321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1345982321
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.791606228
Short name T11
Test name
Test status
Simulation time 1748876448 ps
CPU time 15.23 seconds
Started Feb 18 12:41:56 PM PST 24
Finished Feb 18 12:42:12 PM PST 24
Peak memory 210984 kb
Host smart-febc8e30-eede-4f75-aff6-ce36839418a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791606228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.791606228
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4166116686
Short name T195
Test name
Test status
Simulation time 8455003140 ps
CPU time 40.02 seconds
Started Feb 18 12:41:55 PM PST 24
Finished Feb 18 12:42:37 PM PST 24
Peak memory 213676 kb
Host smart-2205ade6-b6a0-48c5-bd1c-8365a0c46dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166116686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4166116686
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.166323638
Short name T305
Test name
Test status
Simulation time 14122254987 ps
CPU time 33.83 seconds
Started Feb 18 12:41:55 PM PST 24
Finished Feb 18 12:42:30 PM PST 24
Peak memory 215156 kb
Host smart-825612ba-32fc-4441-bacc-0696449019fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166323638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.166323638
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3617203645
Short name T183
Test name
Test status
Simulation time 5719733055 ps
CPU time 13.3 seconds
Started Feb 18 12:42:00 PM PST 24
Finished Feb 18 12:42:15 PM PST 24
Peak memory 211124 kb
Host smart-e3e32d36-26f9-4255-aec7-919306679a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617203645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3617203645
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3931634534
Short name T277
Test name
Test status
Simulation time 173797254486 ps
CPU time 491.32 seconds
Started Feb 18 12:42:00 PM PST 24
Finished Feb 18 12:50:12 PM PST 24
Peak memory 233632 kb
Host smart-f14541bc-e54d-4d99-a3dc-b5b8c52a763c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931634534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3931634534
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1127574184
Short name T135
Test name
Test status
Simulation time 12942835955 ps
CPU time 27.45 seconds
Started Feb 18 12:42:02 PM PST 24
Finished Feb 18 12:42:35 PM PST 24
Peak memory 211792 kb
Host smart-16b27c66-c984-424f-952e-5575808b5bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127574184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1127574184
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.447732699
Short name T230
Test name
Test status
Simulation time 1658263138 ps
CPU time 15.59 seconds
Started Feb 18 12:42:01 PM PST 24
Finished Feb 18 12:42:22 PM PST 24
Peak memory 211068 kb
Host smart-81f277e4-7fe6-43e9-a667-0463c0a1af2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=447732699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.447732699
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3916286934
Short name T173
Test name
Test status
Simulation time 3698335306 ps
CPU time 35.89 seconds
Started Feb 18 12:42:01 PM PST 24
Finished Feb 18 12:42:42 PM PST 24
Peak memory 213312 kb
Host smart-858584a5-3a9a-4edd-9c4f-539026c05896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916286934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3916286934
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3014990188
Short name T142
Test name
Test status
Simulation time 5348572496 ps
CPU time 37.61 seconds
Started Feb 18 12:42:01 PM PST 24
Finished Feb 18 12:42:42 PM PST 24
Peak memory 214148 kb
Host smart-e7d38355-c4b5-4428-98c7-8d81d031a0a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014990188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3014990188
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.510734820
Short name T259
Test name
Test status
Simulation time 89314625 ps
CPU time 4.46 seconds
Started Feb 18 12:42:07 PM PST 24
Finished Feb 18 12:42:13 PM PST 24
Peak memory 211060 kb
Host smart-3e9f53d0-4323-4a69-9e4e-0f9716722e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510734820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.510734820
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2610807607
Short name T275
Test name
Test status
Simulation time 3236595698 ps
CPU time 27.25 seconds
Started Feb 18 12:42:08 PM PST 24
Finished Feb 18 12:42:37 PM PST 24
Peak memory 211764 kb
Host smart-9eda71e6-6ae2-44d8-905a-fa1e714669e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610807607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2610807607
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2178805923
Short name T126
Test name
Test status
Simulation time 364798016 ps
CPU time 5.39 seconds
Started Feb 18 12:42:01 PM PST 24
Finished Feb 18 12:42:12 PM PST 24
Peak memory 211064 kb
Host smart-0f616929-a38b-491c-9c76-3c5a11a94927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178805923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2178805923
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.996368504
Short name T119
Test name
Test status
Simulation time 8227581283 ps
CPU time 21.29 seconds
Started Feb 18 12:42:04 PM PST 24
Finished Feb 18 12:42:29 PM PST 24
Peak memory 212540 kb
Host smart-664ef91d-c5b6-49a6-9095-80586eadfa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996368504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.996368504
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3526399979
Short name T164
Test name
Test status
Simulation time 12382539403 ps
CPU time 61.69 seconds
Started Feb 18 12:42:02 PM PST 24
Finished Feb 18 12:43:08 PM PST 24
Peak memory 219328 kb
Host smart-91bb2f42-403b-4bb9-a297-89029c2ec46d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526399979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3526399979
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3588775653
Short name T285
Test name
Test status
Simulation time 2106921763 ps
CPU time 8.22 seconds
Started Feb 18 12:42:09 PM PST 24
Finished Feb 18 12:42:19 PM PST 24
Peak memory 211092 kb
Host smart-0bbc28a6-88cd-4366-9d83-86f69e49ea97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588775653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3588775653
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3213411450
Short name T194
Test name
Test status
Simulation time 4217227419 ps
CPU time 32.97 seconds
Started Feb 18 12:42:08 PM PST 24
Finished Feb 18 12:42:43 PM PST 24
Peak memory 211080 kb
Host smart-53f49615-f605-4475-83e0-343a362b89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213411450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3213411450
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.319694605
Short name T147
Test name
Test status
Simulation time 1855083782 ps
CPU time 15.09 seconds
Started Feb 18 12:42:09 PM PST 24
Finished Feb 18 12:42:25 PM PST 24
Peak memory 211000 kb
Host smart-45a83e10-49ad-4a37-8f97-b2a0bde9500f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319694605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.319694605
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3056646676
Short name T81
Test name
Test status
Simulation time 2291979866 ps
CPU time 18.26 seconds
Started Feb 18 12:42:08 PM PST 24
Finished Feb 18 12:42:28 PM PST 24
Peak memory 212712 kb
Host smart-ee601f06-c9ac-471b-8b05-8ef1736f2ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056646676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3056646676
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2208657199
Short name T232
Test name
Test status
Simulation time 4683235651 ps
CPU time 33.79 seconds
Started Feb 18 12:42:09 PM PST 24
Finished Feb 18 12:42:45 PM PST 24
Peak memory 213736 kb
Host smart-782bc7c4-584f-410d-ad5c-4096e59e9c36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208657199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2208657199
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3126849110
Short name T146
Test name
Test status
Simulation time 2005752491 ps
CPU time 15.55 seconds
Started Feb 18 12:42:12 PM PST 24
Finished Feb 18 12:42:31 PM PST 24
Peak memory 211052 kb
Host smart-da410152-325d-4ae5-85d7-bbbc1ed1ee8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126849110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3126849110
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4154704225
Short name T176
Test name
Test status
Simulation time 14988422380 ps
CPU time 100.44 seconds
Started Feb 18 12:42:08 PM PST 24
Finished Feb 18 12:43:50 PM PST 24
Peak memory 233568 kb
Host smart-da705f10-d1bd-4a8a-9e1a-02c02c3ad800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154704225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4154704225
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3123411063
Short name T141
Test name
Test status
Simulation time 3092779185 ps
CPU time 28.17 seconds
Started Feb 18 12:42:05 PM PST 24
Finished Feb 18 12:42:36 PM PST 24
Peak memory 211684 kb
Host smart-9a31ded7-362c-42a3-9957-bf93e51c7447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123411063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3123411063
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2425470984
Short name T336
Test name
Test status
Simulation time 1394767720 ps
CPU time 13.08 seconds
Started Feb 18 12:42:10 PM PST 24
Finished Feb 18 12:42:25 PM PST 24
Peak memory 211004 kb
Host smart-7d2e11cd-2dbe-44e4-9c6e-c5400f119e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425470984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2425470984
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1363075200
Short name T197
Test name
Test status
Simulation time 11611230147 ps
CPU time 26.96 seconds
Started Feb 18 12:42:07 PM PST 24
Finished Feb 18 12:42:36 PM PST 24
Peak memory 213576 kb
Host smart-84aa48db-7d2e-4457-a544-06aeed21b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363075200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1363075200
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2706305685
Short name T137
Test name
Test status
Simulation time 768427274 ps
CPU time 39.52 seconds
Started Feb 18 12:42:07 PM PST 24
Finished Feb 18 12:42:48 PM PST 24
Peak memory 215272 kb
Host smart-8c77a6cb-d2b8-42d8-90fe-18dfdf50588e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706305685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2706305685
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1104819998
Short name T289
Test name
Test status
Simulation time 6081208606 ps
CPU time 15.69 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 12:42:34 PM PST 24
Peak memory 211140 kb
Host smart-2ae8245b-4a82-4aac-b6c3-f468ce10aff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104819998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1104819998
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1060257767
Short name T27
Test name
Test status
Simulation time 4273774911 ps
CPU time 35.03 seconds
Started Feb 18 12:42:11 PM PST 24
Finished Feb 18 12:42:47 PM PST 24
Peak memory 211704 kb
Host smart-aa771858-9289-454a-bb18-6d3ad4ad37d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060257767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1060257767
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1513907444
Short name T283
Test name
Test status
Simulation time 379262593 ps
CPU time 8.02 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 12:42:26 PM PST 24
Peak memory 210972 kb
Host smart-d0496599-a50b-4e76-af67-9375701a2cde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513907444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1513907444
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2381426020
Short name T3
Test name
Test status
Simulation time 9594585338 ps
CPU time 23.14 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 12:42:41 PM PST 24
Peak memory 213820 kb
Host smart-c456364e-0143-476e-8178-b6e0683a0e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381426020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2381426020
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2611480427
Short name T117
Test name
Test status
Simulation time 8001323281 ps
CPU time 23.36 seconds
Started Feb 18 12:42:10 PM PST 24
Finished Feb 18 12:42:34 PM PST 24
Peak memory 213864 kb
Host smart-bda3b99f-0fb7-416d-89e8-f6f0b401c51f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611480427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2611480427
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1510954547
Short name T212
Test name
Test status
Simulation time 414867568 ps
CPU time 4.19 seconds
Started Feb 18 12:42:14 PM PST 24
Finished Feb 18 12:42:23 PM PST 24
Peak memory 211016 kb
Host smart-257dcccd-a61f-4c7f-8b73-ec3495a3b237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510954547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1510954547
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3188494722
Short name T231
Test name
Test status
Simulation time 7913495643 ps
CPU time 33.22 seconds
Started Feb 18 12:42:14 PM PST 24
Finished Feb 18 12:42:52 PM PST 24
Peak memory 212236 kb
Host smart-9bb09f2a-2c1d-46be-ac5b-dcb9884e3d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188494722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3188494722
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.246003577
Short name T211
Test name
Test status
Simulation time 1898628129 ps
CPU time 10.83 seconds
Started Feb 18 12:42:12 PM PST 24
Finished Feb 18 12:42:28 PM PST 24
Peak memory 211032 kb
Host smart-e94bbc42-c074-485f-9081-a96ea3fd8bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246003577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.246003577
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2807053792
Short name T168
Test name
Test status
Simulation time 183831785 ps
CPU time 10.69 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 12:42:29 PM PST 24
Peak memory 212848 kb
Host smart-63f3a6f1-575a-4b8a-84d3-0afd125aaa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807053792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2807053792
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4194815336
Short name T241
Test name
Test status
Simulation time 38203756646 ps
CPU time 40.04 seconds
Started Feb 18 12:42:14 PM PST 24
Finished Feb 18 12:42:59 PM PST 24
Peak memory 217356 kb
Host smart-fe10fb4d-1940-45e8-a1be-a1c2431f5c71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194815336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4194815336
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3667229586
Short name T318
Test name
Test status
Simulation time 3263135777 ps
CPU time 11.38 seconds
Started Feb 18 12:42:10 PM PST 24
Finished Feb 18 12:42:23 PM PST 24
Peak memory 211164 kb
Host smart-644129e7-7ef3-4673-abc6-27f1ff36f109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667229586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3667229586
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3203886259
Short name T239
Test name
Test status
Simulation time 132131181904 ps
CPU time 350.13 seconds
Started Feb 18 12:42:12 PM PST 24
Finished Feb 18 12:48:05 PM PST 24
Peak memory 232640 kb
Host smart-7f1fde1d-d747-46c9-aba2-61cdc62e337d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203886259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3203886259
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.922080280
Short name T234
Test name
Test status
Simulation time 4165174458 ps
CPU time 33.94 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 12:42:51 PM PST 24
Peak memory 211732 kb
Host smart-53f5c7d0-9cc7-4e7d-a45e-3a3091200352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922080280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.922080280
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2613623209
Short name T264
Test name
Test status
Simulation time 778563492 ps
CPU time 10.57 seconds
Started Feb 18 12:42:14 PM PST 24
Finished Feb 18 12:42:29 PM PST 24
Peak memory 211008 kb
Host smart-85cf24f4-a62c-461d-9969-4a83423d20f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613623209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2613623209
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.541441013
Short name T39
Test name
Test status
Simulation time 15398141522 ps
CPU time 34.06 seconds
Started Feb 18 12:42:14 PM PST 24
Finished Feb 18 12:42:53 PM PST 24
Peak memory 214168 kb
Host smart-0b3f7096-450a-449e-88df-24b45a431a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541441013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.541441013
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1200634926
Short name T166
Test name
Test status
Simulation time 34124057615 ps
CPU time 45 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 12:43:03 PM PST 24
Peak memory 219340 kb
Host smart-e612efc2-1593-441b-aa19-2194fd4c14c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200634926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1200634926
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2951374607
Short name T46
Test name
Test status
Simulation time 121153795098 ps
CPU time 4682.13 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 02:00:21 PM PST 24
Peak memory 235692 kb
Host smart-2c04c6f0-194c-44af-8961-c508c9945130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951374607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2951374607
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2468109420
Short name T159
Test name
Test status
Simulation time 14254294454 ps
CPU time 16.72 seconds
Started Feb 18 12:42:20 PM PST 24
Finished Feb 18 12:42:37 PM PST 24
Peak memory 211188 kb
Host smart-eed00704-89f0-4488-baab-61c4ee702cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468109420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2468109420
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1522349605
Short name T235
Test name
Test status
Simulation time 1410284064 ps
CPU time 81.65 seconds
Started Feb 18 12:42:19 PM PST 24
Finished Feb 18 12:43:42 PM PST 24
Peak memory 236420 kb
Host smart-254b4762-6445-4055-a5ca-5df2ff8890c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522349605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1522349605
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.150710355
Short name T21
Test name
Test status
Simulation time 171969919 ps
CPU time 9.65 seconds
Started Feb 18 12:42:21 PM PST 24
Finished Feb 18 12:42:33 PM PST 24
Peak memory 211660 kb
Host smart-6295830a-2404-48d0-846f-cf5434422293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150710355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.150710355
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1708068823
Short name T254
Test name
Test status
Simulation time 747834079 ps
CPU time 7.79 seconds
Started Feb 18 12:42:22 PM PST 24
Finished Feb 18 12:42:32 PM PST 24
Peak memory 211004 kb
Host smart-ae0bc2aa-6c83-4079-8cdb-d2dc205bec58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708068823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1708068823
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2688288512
Short name T227
Test name
Test status
Simulation time 5057100002 ps
CPU time 24.76 seconds
Started Feb 18 12:42:13 PM PST 24
Finished Feb 18 12:42:42 PM PST 24
Peak memory 213796 kb
Host smart-9f29bb20-3d74-4ce4-9c38-6bd2bdb16947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688288512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2688288512
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1392832727
Short name T262
Test name
Test status
Simulation time 332876260 ps
CPU time 4.47 seconds
Started Feb 18 12:42:26 PM PST 24
Finished Feb 18 12:42:33 PM PST 24
Peak memory 211032 kb
Host smart-0190728a-6c9c-414e-93e3-dc73c33f2a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392832727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1392832727
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4123184620
Short name T325
Test name
Test status
Simulation time 1659755578 ps
CPU time 9.46 seconds
Started Feb 18 12:42:25 PM PST 24
Finished Feb 18 12:42:36 PM PST 24
Peak memory 211504 kb
Host smart-2a00e3bc-0cb9-4780-9f72-d56e6bcd38c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123184620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4123184620
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2752223681
Short name T257
Test name
Test status
Simulation time 2158388079 ps
CPU time 17.8 seconds
Started Feb 18 12:42:22 PM PST 24
Finished Feb 18 12:42:42 PM PST 24
Peak memory 211152 kb
Host smart-9c7f0558-8854-4518-aeb2-56cd69ef5b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752223681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2752223681
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3282015117
Short name T181
Test name
Test status
Simulation time 4271862360 ps
CPU time 34.96 seconds
Started Feb 18 12:42:27 PM PST 24
Finished Feb 18 12:43:04 PM PST 24
Peak memory 213316 kb
Host smart-ca6e06b5-f0c3-443c-a117-a247fd4b2c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282015117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3282015117
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2148885650
Short name T236
Test name
Test status
Simulation time 1359363427 ps
CPU time 51.13 seconds
Started Feb 18 12:42:23 PM PST 24
Finished Feb 18 12:43:16 PM PST 24
Peak memory 219256 kb
Host smart-d27f161c-60f2-4d3a-b33f-40a3273ee254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148885650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2148885650
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2386869702
Short name T245
Test name
Test status
Simulation time 4960352740 ps
CPU time 10.25 seconds
Started Feb 18 12:41:15 PM PST 24
Finished Feb 18 12:41:28 PM PST 24
Peak memory 211236 kb
Host smart-ef9340b0-8cb1-447c-92db-50c6b02a3ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386869702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2386869702
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2301878298
Short name T143
Test name
Test status
Simulation time 2968631959 ps
CPU time 27.4 seconds
Started Feb 18 12:41:18 PM PST 24
Finished Feb 18 12:41:47 PM PST 24
Peak memory 211196 kb
Host smart-f1b4ab2f-5751-4e44-b8ae-e5aedb00badc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301878298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2301878298
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3223966814
Short name T155
Test name
Test status
Simulation time 7213756458 ps
CPU time 14.11 seconds
Started Feb 18 12:41:20 PM PST 24
Finished Feb 18 12:41:35 PM PST 24
Peak memory 211184 kb
Host smart-7a0a6cb8-dd6f-4ff6-810c-07911c96576b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223966814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3223966814
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3173075609
Short name T18
Test name
Test status
Simulation time 1241791181 ps
CPU time 104.11 seconds
Started Feb 18 12:41:20 PM PST 24
Finished Feb 18 12:43:05 PM PST 24
Peak memory 238388 kb
Host smart-2f7b232e-889a-4743-bab8-786568ee24c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173075609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3173075609
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2717731524
Short name T213
Test name
Test status
Simulation time 678687591 ps
CPU time 14.74 seconds
Started Feb 18 12:41:16 PM PST 24
Finished Feb 18 12:41:34 PM PST 24
Peak memory 213300 kb
Host smart-931ebdce-0746-4452-8b2d-000827ca3146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717731524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2717731524
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1388275101
Short name T149
Test name
Test status
Simulation time 5418764772 ps
CPU time 16.14 seconds
Started Feb 18 12:41:18 PM PST 24
Finished Feb 18 12:41:36 PM PST 24
Peak memory 212084 kb
Host smart-f291ad4b-f27a-445e-9aa2-ff05f546bfbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388275101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1388275101
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2688247466
Short name T50
Test name
Test status
Simulation time 96440037624 ps
CPU time 2130.82 seconds
Started Feb 18 12:41:16 PM PST 24
Finished Feb 18 01:16:50 PM PST 24
Peak memory 246324 kb
Host smart-c8edb18a-4f39-42af-85b5-b40fd7142f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688247466 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2688247466
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.155789524
Short name T165
Test name
Test status
Simulation time 664914605 ps
CPU time 8.69 seconds
Started Feb 18 12:42:29 PM PST 24
Finished Feb 18 12:42:39 PM PST 24
Peak memory 211044 kb
Host smart-84c87146-5915-4577-84ad-27a92a2bdcf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155789524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.155789524
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1341717324
Short name T269
Test name
Test status
Simulation time 4088841942 ps
CPU time 33.52 seconds
Started Feb 18 12:42:30 PM PST 24
Finished Feb 18 12:43:05 PM PST 24
Peak memory 211628 kb
Host smart-2d6d2708-b0ed-4ce2-87c5-932d2b8b1fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341717324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1341717324
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.18546734
Short name T124
Test name
Test status
Simulation time 395187394 ps
CPU time 5.74 seconds
Started Feb 18 12:42:25 PM PST 24
Finished Feb 18 12:42:32 PM PST 24
Peak memory 211056 kb
Host smart-0cfc5500-679d-40c4-b18e-5b6578326c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18546734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.18546734
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.18362642
Short name T169
Test name
Test status
Simulation time 188239297 ps
CPU time 10.51 seconds
Started Feb 18 12:42:26 PM PST 24
Finished Feb 18 12:42:38 PM PST 24
Peak memory 213176 kb
Host smart-886b45da-7f14-45a4-ac57-cc55ee56e256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18362642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.18362642
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.801732312
Short name T57
Test name
Test status
Simulation time 127224642524 ps
CPU time 68.95 seconds
Started Feb 18 12:42:25 PM PST 24
Finished Feb 18 12:43:35 PM PST 24
Peak memory 219352 kb
Host smart-d26a1267-a3cb-4408-ae90-362b604d541c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801732312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.801732312
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.131281902
Short name T260
Test name
Test status
Simulation time 179211235 ps
CPU time 4.44 seconds
Started Feb 18 12:42:28 PM PST 24
Finished Feb 18 12:42:34 PM PST 24
Peak memory 211116 kb
Host smart-e7ed5af3-5a6b-4173-82e6-33f42630ca79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131281902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.131281902
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2512973487
Short name T172
Test name
Test status
Simulation time 3822967512 ps
CPU time 30.57 seconds
Started Feb 18 12:42:26 PM PST 24
Finished Feb 18 12:42:58 PM PST 24
Peak memory 211136 kb
Host smart-f2602050-cce9-412e-9c7b-48bf26c3a9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512973487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2512973487
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4238017730
Short name T97
Test name
Test status
Simulation time 440310399 ps
CPU time 8.65 seconds
Started Feb 18 12:42:25 PM PST 24
Finished Feb 18 12:42:36 PM PST 24
Peak memory 211068 kb
Host smart-4ce32c8e-5140-45e3-95f3-f32211c2694e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238017730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4238017730
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1466766410
Short name T229
Test name
Test status
Simulation time 3796148912 ps
CPU time 24.43 seconds
Started Feb 18 12:42:29 PM PST 24
Finished Feb 18 12:42:54 PM PST 24
Peak memory 213360 kb
Host smart-1597e3e9-aed7-4e09-86fb-212d3043b260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466766410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1466766410
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1485972042
Short name T328
Test name
Test status
Simulation time 1736344787 ps
CPU time 10.35 seconds
Started Feb 18 12:42:25 PM PST 24
Finished Feb 18 12:42:37 PM PST 24
Peak memory 211056 kb
Host smart-6ffdedee-3d01-4dd6-b032-14e26eed0213
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485972042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1485972042
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3001573626
Short name T261
Test name
Test status
Simulation time 4439630605 ps
CPU time 10.49 seconds
Started Feb 18 12:42:33 PM PST 24
Finished Feb 18 12:42:46 PM PST 24
Peak memory 211128 kb
Host smart-d8dc5a2d-c9f2-4c6f-be5d-e673cbf5f01e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001573626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3001573626
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.228493290
Short name T31
Test name
Test status
Simulation time 24780124736 ps
CPU time 254.83 seconds
Started Feb 18 12:42:33 PM PST 24
Finished Feb 18 12:46:50 PM PST 24
Peak memory 236776 kb
Host smart-1e205cc0-1d86-44b5-8ea8-845b34a832e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228493290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.228493290
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2971373231
Short name T222
Test name
Test status
Simulation time 362285893 ps
CPU time 9.46 seconds
Started Feb 18 12:42:34 PM PST 24
Finished Feb 18 12:42:45 PM PST 24
Peak memory 211456 kb
Host smart-d62c3dd5-5be3-4b32-8e25-de3d57a22baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971373231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2971373231
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1591677109
Short name T136
Test name
Test status
Simulation time 4013542539 ps
CPU time 11.83 seconds
Started Feb 18 12:42:32 PM PST 24
Finished Feb 18 12:42:47 PM PST 24
Peak memory 211116 kb
Host smart-0f8aefa4-5f31-4ba4-a569-b7c1f981efef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591677109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1591677109
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1020605713
Short name T161
Test name
Test status
Simulation time 11172213977 ps
CPU time 31.05 seconds
Started Feb 18 12:42:26 PM PST 24
Finished Feb 18 12:42:59 PM PST 24
Peak memory 213872 kb
Host smart-c98e1673-6b11-462a-9e1e-ffb47ea6e4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020605713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1020605713
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.491839163
Short name T255
Test name
Test status
Simulation time 2720614342 ps
CPU time 19.49 seconds
Started Feb 18 12:42:32 PM PST 24
Finished Feb 18 12:42:54 PM PST 24
Peak memory 214108 kb
Host smart-3ed0aa80-a9e9-4a36-ab40-fc907c89a69a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491839163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.491839163
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3366632705
Short name T220
Test name
Test status
Simulation time 39365757040 ps
CPU time 16.03 seconds
Started Feb 18 12:42:38 PM PST 24
Finished Feb 18 12:42:55 PM PST 24
Peak memory 210564 kb
Host smart-e4e304cd-c050-40fa-b9a3-0983bf335549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366632705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3366632705
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4291761337
Short name T22
Test name
Test status
Simulation time 26922409779 ps
CPU time 25.43 seconds
Started Feb 18 12:42:32 PM PST 24
Finished Feb 18 12:43:00 PM PST 24
Peak memory 211868 kb
Host smart-b131dc37-3cbb-4224-b00b-abec200e5b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291761337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4291761337
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.282486086
Short name T190
Test name
Test status
Simulation time 99080818 ps
CPU time 5.61 seconds
Started Feb 18 12:42:32 PM PST 24
Finished Feb 18 12:42:41 PM PST 24
Peak memory 211108 kb
Host smart-8f498942-b078-48e5-807f-3c15e2940bf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282486086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.282486086
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2123055695
Short name T316
Test name
Test status
Simulation time 1655546736 ps
CPU time 10.27 seconds
Started Feb 18 12:42:32 PM PST 24
Finished Feb 18 12:42:45 PM PST 24
Peak memory 213056 kb
Host smart-a36bd91a-8ad0-4612-85ef-1ebcd1c2c6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123055695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2123055695
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3842388863
Short name T306
Test name
Test status
Simulation time 19331799765 ps
CPU time 42.11 seconds
Started Feb 18 12:42:33 PM PST 24
Finished Feb 18 12:43:18 PM PST 24
Peak memory 216304 kb
Host smart-7eac4c5a-e440-4ea0-ad3b-f584cec40532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842388863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3842388863
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2970682197
Short name T47
Test name
Test status
Simulation time 301801171879 ps
CPU time 6664.14 seconds
Started Feb 18 12:42:38 PM PST 24
Finished Feb 18 02:33:44 PM PST 24
Peak memory 241664 kb
Host smart-5b974064-4e75-4156-9dc2-73f37ab76bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970682197 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2970682197
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2886664181
Short name T70
Test name
Test status
Simulation time 3780766000 ps
CPU time 15.53 seconds
Started Feb 18 12:42:33 PM PST 24
Finished Feb 18 12:42:51 PM PST 24
Peak memory 211292 kb
Host smart-8aa7ec0a-236a-4125-a645-18764ac6a1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886664181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2886664181
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1624245482
Short name T43
Test name
Test status
Simulation time 6518269770 ps
CPU time 185.27 seconds
Started Feb 18 12:42:33 PM PST 24
Finished Feb 18 12:45:41 PM PST 24
Peak memory 224812 kb
Host smart-69b15c6d-c18d-4b28-b48d-cd8f7b88fe00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624245482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1624245482
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2285906666
Short name T175
Test name
Test status
Simulation time 5346270985 ps
CPU time 16.9 seconds
Started Feb 18 12:42:31 PM PST 24
Finished Feb 18 12:42:51 PM PST 24
Peak memory 212028 kb
Host smart-90000c6b-de13-468c-be06-7aa5f1dc1d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285906666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2285906666
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2078361876
Short name T307
Test name
Test status
Simulation time 17557554714 ps
CPU time 43.8 seconds
Started Feb 18 12:42:35 PM PST 24
Finished Feb 18 12:43:20 PM PST 24
Peak memory 215180 kb
Host smart-5e37ad29-5dd1-49b8-a5c5-4de472047937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078361876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2078361876
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2866517511
Short name T226
Test name
Test status
Simulation time 9974644293 ps
CPU time 36.55 seconds
Started Feb 18 12:42:33 PM PST 24
Finished Feb 18 12:43:12 PM PST 24
Peak memory 214180 kb
Host smart-4d01f26f-6179-404a-8049-49637095941d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866517511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2866517511
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3424140067
Short name T284
Test name
Test status
Simulation time 620782501 ps
CPU time 8.49 seconds
Started Feb 18 12:42:36 PM PST 24
Finished Feb 18 12:42:46 PM PST 24
Peak memory 211032 kb
Host smart-6f1fd321-59f2-4d33-968e-810ecfd62a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424140067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3424140067
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3172303281
Short name T26
Test name
Test status
Simulation time 898109854 ps
CPU time 15.51 seconds
Started Feb 18 12:42:45 PM PST 24
Finished Feb 18 12:43:01 PM PST 24
Peak memory 211512 kb
Host smart-9a4d9b8e-5e5c-4e78-9b57-1134e2e1c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172303281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3172303281
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3396550976
Short name T321
Test name
Test status
Simulation time 3947035616 ps
CPU time 17.58 seconds
Started Feb 18 12:42:38 PM PST 24
Finished Feb 18 12:42:56 PM PST 24
Peak memory 210756 kb
Host smart-28714c03-54a5-4b2b-8c75-4357b7fe4e68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396550976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3396550976
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3557943887
Short name T53
Test name
Test status
Simulation time 999818123 ps
CPU time 13.4 seconds
Started Feb 18 12:42:33 PM PST 24
Finished Feb 18 12:42:49 PM PST 24
Peak memory 211184 kb
Host smart-a31f26ff-2950-419a-b7e7-03f760d9d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557943887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3557943887
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3382973238
Short name T204
Test name
Test status
Simulation time 1594582250 ps
CPU time 23.81 seconds
Started Feb 18 12:42:32 PM PST 24
Finished Feb 18 12:42:59 PM PST 24
Peak memory 215008 kb
Host smart-174b8d51-bc51-49f1-8035-58f0ae61dc63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382973238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3382973238
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3014580404
Short name T294
Test name
Test status
Simulation time 3009467590 ps
CPU time 13.4 seconds
Started Feb 18 12:42:45 PM PST 24
Finished Feb 18 12:42:59 PM PST 24
Peak memory 211240 kb
Host smart-12c19f2f-f8dd-45f4-be98-fca2c98492f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014580404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3014580404
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2380463165
Short name T35
Test name
Test status
Simulation time 27695087396 ps
CPU time 157.63 seconds
Started Feb 18 12:42:37 PM PST 24
Finished Feb 18 12:45:16 PM PST 24
Peak memory 231824 kb
Host smart-877c2c5c-a277-4667-a105-9264390a097c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380463165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2380463165
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2303761203
Short name T250
Test name
Test status
Simulation time 31497267817 ps
CPU time 22.78 seconds
Started Feb 18 12:42:39 PM PST 24
Finished Feb 18 12:43:03 PM PST 24
Peak memory 211896 kb
Host smart-816a84e3-f045-4325-a7ca-fb3a5151a668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303761203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2303761203
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.291210442
Short name T331
Test name
Test status
Simulation time 1441705115 ps
CPU time 13.57 seconds
Started Feb 18 12:42:45 PM PST 24
Finished Feb 18 12:43:00 PM PST 24
Peak memory 211080 kb
Host smart-07729801-b073-465c-80e5-185bcbaefbf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291210442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.291210442
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2233465493
Short name T256
Test name
Test status
Simulation time 796755626 ps
CPU time 15.33 seconds
Started Feb 18 12:42:39 PM PST 24
Finished Feb 18 12:42:55 PM PST 24
Peak memory 211616 kb
Host smart-7df49d13-11b4-4ace-9f63-23fcfe2aef27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233465493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2233465493
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.598981873
Short name T196
Test name
Test status
Simulation time 1898964817 ps
CPU time 29.7 seconds
Started Feb 18 12:42:38 PM PST 24
Finished Feb 18 12:43:09 PM PST 24
Peak memory 215328 kb
Host smart-a2b6844e-128f-4373-9c85-e65dc376fccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598981873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.598981873
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.741664674
Short name T167
Test name
Test status
Simulation time 2139760969 ps
CPU time 16.86 seconds
Started Feb 18 12:42:38 PM PST 24
Finished Feb 18 12:42:56 PM PST 24
Peak memory 211068 kb
Host smart-e2dde113-4262-4be6-b20d-c3d0faa455e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741664674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.741664674
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3214592267
Short name T281
Test name
Test status
Simulation time 118742472331 ps
CPU time 315.27 seconds
Started Feb 18 12:42:37 PM PST 24
Finished Feb 18 12:47:53 PM PST 24
Peak memory 233672 kb
Host smart-2c0219ec-6298-443a-9600-b837c301e0a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214592267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3214592267
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1868917647
Short name T274
Test name
Test status
Simulation time 6066317611 ps
CPU time 19.79 seconds
Started Feb 18 12:42:45 PM PST 24
Finished Feb 18 12:43:06 PM PST 24
Peak memory 211536 kb
Host smart-dde06bd8-509d-4ddc-a54a-d62496ae8743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868917647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1868917647
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1797305847
Short name T130
Test name
Test status
Simulation time 3358026859 ps
CPU time 15.68 seconds
Started Feb 18 12:42:37 PM PST 24
Finished Feb 18 12:42:54 PM PST 24
Peak memory 211152 kb
Host smart-203124e0-ba3b-4f78-aff8-44d097cea549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797305847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1797305847
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.517421822
Short name T122
Test name
Test status
Simulation time 16530930477 ps
CPU time 33.77 seconds
Started Feb 18 12:42:38 PM PST 24
Finished Feb 18 12:43:13 PM PST 24
Peak memory 214208 kb
Host smart-e2ebcbe9-e48f-4214-a276-68efd8f5dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517421822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.517421822
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1603305814
Short name T293
Test name
Test status
Simulation time 2513060169 ps
CPU time 22.3 seconds
Started Feb 18 12:42:37 PM PST 24
Finished Feb 18 12:43:00 PM PST 24
Peak memory 214652 kb
Host smart-46e15d4d-8091-497c-9185-c4e53adbe15c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603305814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1603305814
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3682996400
Short name T6
Test name
Test status
Simulation time 7942831837 ps
CPU time 15.83 seconds
Started Feb 18 12:42:44 PM PST 24
Finished Feb 18 12:43:01 PM PST 24
Peak memory 211144 kb
Host smart-8aa08cf0-8b76-4d87-bc2c-d4619f1cf994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682996400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3682996400
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.60235187
Short name T303
Test name
Test status
Simulation time 3113334453 ps
CPU time 203.18 seconds
Started Feb 18 12:42:44 PM PST 24
Finished Feb 18 12:46:08 PM PST 24
Peak memory 237780 kb
Host smart-142ead79-0372-491a-a51e-28667c7c6985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60235187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_co
rrupt_sig_fatal_chk.60235187
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1668204336
Short name T290
Test name
Test status
Simulation time 6502362627 ps
CPU time 20.81 seconds
Started Feb 18 12:42:43 PM PST 24
Finished Feb 18 12:43:04 PM PST 24
Peak memory 212104 kb
Host smart-57b5651b-b563-4e4d-9bfd-c5f234b9ede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668204336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1668204336
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1921308852
Short name T4
Test name
Test status
Simulation time 180015771 ps
CPU time 6.67 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:42:58 PM PST 24
Peak memory 210944 kb
Host smart-aaff5678-bb0f-422b-8761-ed103598166f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921308852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1921308852
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.193779834
Short name T273
Test name
Test status
Simulation time 10314737575 ps
CPU time 32.88 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:43:24 PM PST 24
Peak memory 213336 kb
Host smart-0be4f7ab-d140-463a-a934-c8fcfba54b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193779834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.193779834
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.378876709
Short name T158
Test name
Test status
Simulation time 2732920078 ps
CPU time 36.24 seconds
Started Feb 18 12:42:45 PM PST 24
Finished Feb 18 12:43:22 PM PST 24
Peak memory 215736 kb
Host smart-0d5765bb-2d0e-4cf4-93ab-eb063bc8f28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378876709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.378876709
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2382430845
Short name T244
Test name
Test status
Simulation time 1034888849 ps
CPU time 10.88 seconds
Started Feb 18 12:42:44 PM PST 24
Finished Feb 18 12:42:56 PM PST 24
Peak memory 211036 kb
Host smart-d78c2ce8-757e-46ca-8bd5-507a0b0b56e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382430845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2382430845
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3404333243
Short name T267
Test name
Test status
Simulation time 168680613 ps
CPU time 9.5 seconds
Started Feb 18 12:42:43 PM PST 24
Finished Feb 18 12:42:53 PM PST 24
Peak memory 211516 kb
Host smart-f46435af-d89f-489f-89f4-e1f55eb3b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404333243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3404333243
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1531998240
Short name T104
Test name
Test status
Simulation time 1237600169 ps
CPU time 12.86 seconds
Started Feb 18 12:42:44 PM PST 24
Finished Feb 18 12:42:57 PM PST 24
Peak memory 211056 kb
Host smart-23362c98-5b86-4b5c-8cdb-22925b67a813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531998240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1531998240
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1807382611
Short name T8
Test name
Test status
Simulation time 11382576263 ps
CPU time 29.71 seconds
Started Feb 18 12:42:46 PM PST 24
Finished Feb 18 12:43:17 PM PST 24
Peak memory 213684 kb
Host smart-f3604e0a-9aec-4e79-be16-00f36b87770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807382611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1807382611
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2959696225
Short name T282
Test name
Test status
Simulation time 4731630249 ps
CPU time 11.12 seconds
Started Feb 18 12:41:24 PM PST 24
Finished Feb 18 12:41:36 PM PST 24
Peak memory 211100 kb
Host smart-0419c211-e3f3-4269-870a-0db6ad4cad59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959696225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2959696225
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2860000814
Short name T271
Test name
Test status
Simulation time 347264733 ps
CPU time 9.41 seconds
Started Feb 18 12:41:24 PM PST 24
Finished Feb 18 12:41:35 PM PST 24
Peak memory 211596 kb
Host smart-160f23dc-a308-4d16-aecd-a663e3c9c431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860000814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2860000814
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.281468896
Short name T311
Test name
Test status
Simulation time 909590952 ps
CPU time 10.52 seconds
Started Feb 18 12:41:24 PM PST 24
Finished Feb 18 12:41:35 PM PST 24
Peak memory 210976 kb
Host smart-587c98e9-8d58-4174-b688-eef35b3a0b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281468896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.281468896
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.887985188
Short name T36
Test name
Test status
Simulation time 1092523409 ps
CPU time 101.09 seconds
Started Feb 18 12:41:19 PM PST 24
Finished Feb 18 12:43:01 PM PST 24
Peak memory 235376 kb
Host smart-bd408452-6a1e-4035-bbd8-687d4706cd6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887985188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.887985188
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.222134472
Short name T138
Test name
Test status
Simulation time 1102218424 ps
CPU time 13.4 seconds
Started Feb 18 12:41:21 PM PST 24
Finished Feb 18 12:41:35 PM PST 24
Peak memory 212136 kb
Host smart-908ea9fe-a1d8-4818-b97e-6da4f348bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222134472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.222134472
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.390454305
Short name T102
Test name
Test status
Simulation time 15179738080 ps
CPU time 45.19 seconds
Started Feb 18 12:41:21 PM PST 24
Finished Feb 18 12:42:07 PM PST 24
Peak memory 219320 kb
Host smart-8ac24001-5118-4166-9158-f7f411f4bc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390454305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.390454305
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.247329948
Short name T153
Test name
Test status
Simulation time 892272651 ps
CPU time 9.72 seconds
Started Feb 18 12:42:50 PM PST 24
Finished Feb 18 12:43:03 PM PST 24
Peak memory 211036 kb
Host smart-48b7c038-3c66-4ccb-8c63-7e214d7e91bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247329948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.247329948
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.518145550
Short name T248
Test name
Test status
Simulation time 3605712433 ps
CPU time 119.49 seconds
Started Feb 18 12:42:46 PM PST 24
Finished Feb 18 12:44:48 PM PST 24
Peak memory 228012 kb
Host smart-23cb0b71-0678-42ef-89ce-d0a285f331ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518145550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.518145550
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2360864705
Short name T20
Test name
Test status
Simulation time 665041220 ps
CPU time 9.47 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:43:00 PM PST 24
Peak memory 211344 kb
Host smart-6e4f1564-ec09-49b9-aea2-ffad9a9bf28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360864705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2360864705
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.410754710
Short name T12
Test name
Test status
Simulation time 2034688265 ps
CPU time 17.49 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:43:08 PM PST 24
Peak memory 210920 kb
Host smart-6906cc71-b34d-4104-a794-1af2686c2c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410754710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.410754710
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1208465603
Short name T263
Test name
Test status
Simulation time 6842249103 ps
CPU time 20.29 seconds
Started Feb 18 12:42:44 PM PST 24
Finished Feb 18 12:43:05 PM PST 24
Peak memory 219400 kb
Host smart-1298fbb4-9b73-4153-a7a5-651666673ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208465603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1208465603
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4151835789
Short name T7
Test name
Test status
Simulation time 8625292769 ps
CPU time 77.3 seconds
Started Feb 18 12:42:44 PM PST 24
Finished Feb 18 12:44:01 PM PST 24
Peak memory 216596 kb
Host smart-ad0a62c4-fe43-40d5-adc7-1c5e11c7fea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151835789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4151835789
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.475566932
Short name T49
Test name
Test status
Simulation time 90139349361 ps
CPU time 3599.97 seconds
Started Feb 18 12:42:42 PM PST 24
Finished Feb 18 01:42:44 PM PST 24
Peak memory 252244 kb
Host smart-12b4fad7-d676-4951-be1c-49e6597f171a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475566932 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.475566932
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2987322202
Short name T187
Test name
Test status
Simulation time 5717463938 ps
CPU time 8.21 seconds
Started Feb 18 12:42:51 PM PST 24
Finished Feb 18 12:43:02 PM PST 24
Peak memory 211200 kb
Host smart-f5604767-bf70-43db-99f8-e8825ec196d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987322202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2987322202
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.857206362
Short name T313
Test name
Test status
Simulation time 1572077647 ps
CPU time 97.59 seconds
Started Feb 18 12:42:51 PM PST 24
Finished Feb 18 12:44:31 PM PST 24
Peak memory 228196 kb
Host smart-729222a4-fd04-47e8-9973-909fd5db9763
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857206362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.857206362
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3155730071
Short name T125
Test name
Test status
Simulation time 22120251124 ps
CPU time 27.87 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:43:19 PM PST 24
Peak memory 211828 kb
Host smart-40a27a79-676c-444b-9117-5e35c61a613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155730071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3155730071
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.932781585
Short name T199
Test name
Test status
Simulation time 215397139 ps
CPU time 6.86 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:42:57 PM PST 24
Peak memory 211028 kb
Host smart-6ba554d5-b46d-4c4d-9c94-8234633ebeca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932781585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.932781585
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.692694206
Short name T52
Test name
Test status
Simulation time 2001073033 ps
CPU time 25.77 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:43:16 PM PST 24
Peak memory 213412 kb
Host smart-f755fe4a-e69f-4fba-a7f2-9f2c01893416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692694206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.692694206
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.84094465
Short name T140
Test name
Test status
Simulation time 4392051402 ps
CPU time 17.68 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:43:08 PM PST 24
Peak memory 214684 kb
Host smart-3c619c15-fe3b-4c14-a660-34cccf52446a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84094465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.rom_ctrl_stress_all.84094465
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2523241834
Short name T185
Test name
Test status
Simulation time 28015566220 ps
CPU time 15.04 seconds
Started Feb 18 12:42:51 PM PST 24
Finished Feb 18 12:43:09 PM PST 24
Peak memory 210808 kb
Host smart-62c25e5e-a36e-441a-9811-c7724a01e554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523241834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2523241834
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1858969193
Short name T215
Test name
Test status
Simulation time 2106771631 ps
CPU time 23.21 seconds
Started Feb 18 12:42:48 PM PST 24
Finished Feb 18 12:43:13 PM PST 24
Peak memory 211432 kb
Host smart-be0d3951-1ece-48ac-b02a-72b4ffdb0e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858969193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1858969193
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3756230676
Short name T291
Test name
Test status
Simulation time 1081192508 ps
CPU time 11.75 seconds
Started Feb 18 12:42:53 PM PST 24
Finished Feb 18 12:43:06 PM PST 24
Peak memory 211112 kb
Host smart-3fb9aaf7-6d75-481e-86fa-e34158c0a0fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756230676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3756230676
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1841575559
Short name T133
Test name
Test status
Simulation time 714971189 ps
CPU time 9.92 seconds
Started Feb 18 12:42:53 PM PST 24
Finished Feb 18 12:43:04 PM PST 24
Peak memory 213208 kb
Host smart-0a649201-2fc7-428c-982a-cb94b2e74fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841575559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1841575559
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.108854403
Short name T127
Test name
Test status
Simulation time 652595174 ps
CPU time 35.93 seconds
Started Feb 18 12:42:53 PM PST 24
Finished Feb 18 12:43:30 PM PST 24
Peak memory 214888 kb
Host smart-5e6eb578-7c7b-4bd7-8fd4-bad8a2344af5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108854403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.108854403
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3337876110
Short name T150
Test name
Test status
Simulation time 637063281 ps
CPU time 4.22 seconds
Started Feb 18 12:42:58 PM PST 24
Finished Feb 18 12:43:03 PM PST 24
Peak memory 211088 kb
Host smart-8541c165-a6db-406b-9bc2-6a76caae4ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337876110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3337876110
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.588877205
Short name T28
Test name
Test status
Simulation time 4753048723 ps
CPU time 23.3 seconds
Started Feb 18 12:42:47 PM PST 24
Finished Feb 18 12:43:13 PM PST 24
Peak memory 211132 kb
Host smart-0c8059e7-2119-41c2-ab6e-9b8afc932e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588877205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.588877205
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1804533879
Short name T186
Test name
Test status
Simulation time 676246149 ps
CPU time 9.76 seconds
Started Feb 18 12:42:50 PM PST 24
Finished Feb 18 12:43:03 PM PST 24
Peak memory 210980 kb
Host smart-49a4f5f2-0a19-4b1a-b07f-2980479b9f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1804533879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1804533879
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.702084818
Short name T80
Test name
Test status
Simulation time 4883324776 ps
CPU time 27.28 seconds
Started Feb 18 12:42:53 PM PST 24
Finished Feb 18 12:43:21 PM PST 24
Peak memory 213236 kb
Host smart-6f185c68-b70d-4792-8d15-37cc61fa5b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702084818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.702084818
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3054310028
Short name T240
Test name
Test status
Simulation time 7786062081 ps
CPU time 39.91 seconds
Started Feb 18 12:42:54 PM PST 24
Finished Feb 18 12:43:35 PM PST 24
Peak memory 215588 kb
Host smart-66644863-4548-46b6-a5e9-8aa95f024662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054310028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3054310028
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2178269398
Short name T193
Test name
Test status
Simulation time 919605552 ps
CPU time 4.19 seconds
Started Feb 18 12:42:54 PM PST 24
Finished Feb 18 12:42:59 PM PST 24
Peak memory 211048 kb
Host smart-b44da57a-aff6-4320-ac7f-4ccf1244e1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178269398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2178269398
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2896078120
Short name T180
Test name
Test status
Simulation time 691840752 ps
CPU time 9.53 seconds
Started Feb 18 12:42:55 PM PST 24
Finished Feb 18 12:43:05 PM PST 24
Peak memory 211608 kb
Host smart-39e8aa19-6c2d-45c5-8a19-a08d4299afd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896078120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2896078120
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1769815519
Short name T326
Test name
Test status
Simulation time 1846730816 ps
CPU time 7.68 seconds
Started Feb 18 12:42:54 PM PST 24
Finished Feb 18 12:43:02 PM PST 24
Peak memory 210980 kb
Host smart-939a9070-7205-4742-978e-ee9bd0c3a4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769815519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1769815519
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1087872589
Short name T301
Test name
Test status
Simulation time 2086815967 ps
CPU time 16.85 seconds
Started Feb 18 12:42:51 PM PST 24
Finished Feb 18 12:43:10 PM PST 24
Peak memory 213644 kb
Host smart-91b23cab-07da-4b9b-81ba-34fe9b4c64de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087872589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1087872589
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.422841133
Short name T13
Test name
Test status
Simulation time 25271864209 ps
CPU time 53.98 seconds
Started Feb 18 12:42:55 PM PST 24
Finished Feb 18 12:43:50 PM PST 24
Peak memory 217152 kb
Host smart-866d60b8-2c58-414c-9810-8b6230993957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422841133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.422841133
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1854946617
Short name T38
Test name
Test status
Simulation time 4606200012 ps
CPU time 12.01 seconds
Started Feb 18 12:43:05 PM PST 24
Finished Feb 18 12:43:18 PM PST 24
Peak memory 211192 kb
Host smart-a24b43f0-ef73-48f0-a38b-8a5718e49d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854946617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1854946617
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.117101006
Short name T310
Test name
Test status
Simulation time 619999850 ps
CPU time 9.63 seconds
Started Feb 18 12:42:55 PM PST 24
Finished Feb 18 12:43:06 PM PST 24
Peak memory 211692 kb
Host smart-1ff4762d-148e-438a-93f5-ec6270ced245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117101006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.117101006
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1521768357
Short name T265
Test name
Test status
Simulation time 5832413226 ps
CPU time 13.64 seconds
Started Feb 18 12:42:55 PM PST 24
Finished Feb 18 12:43:09 PM PST 24
Peak memory 211204 kb
Host smart-2afe4da8-7f0d-4453-ac73-7b6b2a30082c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521768357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1521768357
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1893779183
Short name T299
Test name
Test status
Simulation time 6359578169 ps
CPU time 29.07 seconds
Started Feb 18 12:42:55 PM PST 24
Finished Feb 18 12:43:25 PM PST 24
Peak memory 214432 kb
Host smart-44e2dfbf-9c39-4ca2-a3c1-4017f009ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893779183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1893779183
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.604654999
Short name T329
Test name
Test status
Simulation time 30220445579 ps
CPU time 80.33 seconds
Started Feb 18 12:42:54 PM PST 24
Finished Feb 18 12:44:15 PM PST 24
Peak memory 219404 kb
Host smart-7e2a79b0-49c7-4325-b260-655ad2044a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604654999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.604654999
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1420079120
Short name T69
Test name
Test status
Simulation time 89230371 ps
CPU time 4.3 seconds
Started Feb 18 12:43:03 PM PST 24
Finished Feb 18 12:43:08 PM PST 24
Peak memory 211024 kb
Host smart-bc95361b-99fe-4c81-a180-835b3ae8d804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420079120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1420079120
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.482844784
Short name T30
Test name
Test status
Simulation time 31508468788 ps
CPU time 324.21 seconds
Started Feb 18 12:43:06 PM PST 24
Finished Feb 18 12:48:31 PM PST 24
Peak memory 233780 kb
Host smart-73990fd2-a9ba-4365-ba58-e0528d67e66a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482844784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.482844784
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2455828584
Short name T162
Test name
Test status
Simulation time 822251200 ps
CPU time 15.06 seconds
Started Feb 18 12:43:02 PM PST 24
Finished Feb 18 12:43:19 PM PST 24
Peak memory 211748 kb
Host smart-0030db19-ad6f-478c-838d-a49612a9ec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455828584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2455828584
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.856682902
Short name T237
Test name
Test status
Simulation time 96025921 ps
CPU time 5.27 seconds
Started Feb 18 12:43:04 PM PST 24
Finished Feb 18 12:43:10 PM PST 24
Peak memory 211028 kb
Host smart-107d001f-4e17-4a94-b2f8-eb24cdf96926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856682902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.856682902
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4188594445
Short name T192
Test name
Test status
Simulation time 2303433174 ps
CPU time 31 seconds
Started Feb 18 12:43:05 PM PST 24
Finished Feb 18 12:43:37 PM PST 24
Peak memory 213312 kb
Host smart-770f65c3-f45b-4b4b-9fbf-5ff3aa8299e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188594445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4188594445
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.75314250
Short name T272
Test name
Test status
Simulation time 1607549439 ps
CPU time 6.06 seconds
Started Feb 18 12:43:05 PM PST 24
Finished Feb 18 12:43:12 PM PST 24
Peak memory 211040 kb
Host smart-04b5f28c-75cb-4b87-97b5-aafba5cbbd75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75314250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.75314250
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4294364627
Short name T15
Test name
Test status
Simulation time 62411383737 ps
CPU time 675.06 seconds
Started Feb 18 12:43:04 PM PST 24
Finished Feb 18 12:54:20 PM PST 24
Peak memory 235856 kb
Host smart-5a3d1499-d666-4575-8f41-164e638d1e79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294364627 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4294364627
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3679554462
Short name T210
Test name
Test status
Simulation time 5356604608 ps
CPU time 15.09 seconds
Started Feb 18 12:43:12 PM PST 24
Finished Feb 18 12:43:29 PM PST 24
Peak memory 211164 kb
Host smart-e0a76ea9-848d-4f49-9bf0-8680a4b232fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679554462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3679554462
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.340395363
Short name T258
Test name
Test status
Simulation time 1469670555 ps
CPU time 82.41 seconds
Started Feb 18 12:43:03 PM PST 24
Finished Feb 18 12:44:27 PM PST 24
Peak memory 236668 kb
Host smart-2f92bb6b-7525-42e0-a46e-ae0ec33d4a5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340395363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.340395363
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4257130976
Short name T123
Test name
Test status
Simulation time 2452913389 ps
CPU time 24.52 seconds
Started Feb 18 12:43:09 PM PST 24
Finished Feb 18 12:43:35 PM PST 24
Peak memory 211620 kb
Host smart-afdf3a11-ebd3-4109-882e-c2e630e281dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257130976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4257130976
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3544615972
Short name T54
Test name
Test status
Simulation time 2931405632 ps
CPU time 13.93 seconds
Started Feb 18 12:43:03 PM PST 24
Finished Feb 18 12:43:18 PM PST 24
Peak memory 211132 kb
Host smart-891bb16f-a995-435c-9735-56b4af01233a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544615972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3544615972
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1196142809
Short name T2
Test name
Test status
Simulation time 1376864106 ps
CPU time 15.01 seconds
Started Feb 18 12:43:03 PM PST 24
Finished Feb 18 12:43:19 PM PST 24
Peak memory 212684 kb
Host smart-8701f02f-3bc7-4628-8787-fd98e8d8cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196142809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1196142809
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.683323375
Short name T314
Test name
Test status
Simulation time 10354368077 ps
CPU time 50.42 seconds
Started Feb 18 12:43:04 PM PST 24
Finished Feb 18 12:43:55 PM PST 24
Peak memory 219296 kb
Host smart-213d4c50-af53-4e8f-a5ba-2179f2fb1cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683323375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.683323375
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.392736117
Short name T268
Test name
Test status
Simulation time 3847907721 ps
CPU time 15.72 seconds
Started Feb 18 12:43:10 PM PST 24
Finished Feb 18 12:43:27 PM PST 24
Peak memory 211120 kb
Host smart-194e1eac-bbfa-444a-8b2f-e81f76246895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392736117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.392736117
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2818952671
Short name T34
Test name
Test status
Simulation time 9342375433 ps
CPU time 139.53 seconds
Started Feb 18 12:43:09 PM PST 24
Finished Feb 18 12:45:30 PM PST 24
Peak memory 212428 kb
Host smart-c6bfe88c-393b-47b0-97a2-cdcb6af5e0b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818952671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2818952671
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.735427644
Short name T327
Test name
Test status
Simulation time 1104147200 ps
CPU time 9.33 seconds
Started Feb 18 12:43:09 PM PST 24
Finished Feb 18 12:43:20 PM PST 24
Peak memory 211680 kb
Host smart-c6aa9d63-a5a9-4047-8a3a-b33c545aa9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735427644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.735427644
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3780886127
Short name T23
Test name
Test status
Simulation time 3722728299 ps
CPU time 16.74 seconds
Started Feb 18 12:43:11 PM PST 24
Finished Feb 18 12:43:28 PM PST 24
Peak memory 211292 kb
Host smart-a3c3d559-7005-487d-baea-c33aa66b4aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780886127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3780886127
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.355780123
Short name T320
Test name
Test status
Simulation time 780209790 ps
CPU time 16.14 seconds
Started Feb 18 12:43:14 PM PST 24
Finished Feb 18 12:43:32 PM PST 24
Peak memory 213416 kb
Host smart-1d7d996e-dd6e-4dc1-be28-c2124fc64169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355780123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.355780123
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3966837246
Short name T308
Test name
Test status
Simulation time 19534462670 ps
CPU time 47.85 seconds
Started Feb 18 12:43:10 PM PST 24
Finished Feb 18 12:43:59 PM PST 24
Peak memory 219280 kb
Host smart-fcafb1d2-34b9-48a4-8d51-b680e9389eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966837246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3966837246
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.948368057
Short name T67
Test name
Test status
Simulation time 85706637 ps
CPU time 4.34 seconds
Started Feb 18 12:43:10 PM PST 24
Finished Feb 18 12:43:16 PM PST 24
Peak memory 211084 kb
Host smart-f271c7d8-82d1-47c3-b451-a9c48e4c69d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948368057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.948368057
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.435694915
Short name T198
Test name
Test status
Simulation time 233109473447 ps
CPU time 432.64 seconds
Started Feb 18 12:43:11 PM PST 24
Finished Feb 18 12:50:24 PM PST 24
Peak memory 224508 kb
Host smart-a9a8e7c6-a315-4f44-aa5e-60f5bbb317f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435694915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.435694915
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1317499925
Short name T121
Test name
Test status
Simulation time 1076521388 ps
CPU time 11.09 seconds
Started Feb 18 12:43:09 PM PST 24
Finished Feb 18 12:43:22 PM PST 24
Peak memory 211500 kb
Host smart-8cdde650-6982-46e6-8e3c-9eddbe341531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317499925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1317499925
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3311481902
Short name T170
Test name
Test status
Simulation time 7855655948 ps
CPU time 14.16 seconds
Started Feb 18 12:43:11 PM PST 24
Finished Feb 18 12:43:27 PM PST 24
Peak memory 211184 kb
Host smart-0dd534ac-3e5e-4560-bee6-436ce12f2a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311481902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3311481902
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3870414007
Short name T266
Test name
Test status
Simulation time 3672782582 ps
CPU time 32.18 seconds
Started Feb 18 12:43:08 PM PST 24
Finished Feb 18 12:43:43 PM PST 24
Peak memory 213292 kb
Host smart-ae56a2cc-e01a-4d90-81cd-9582018774c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870414007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3870414007
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.749076729
Short name T179
Test name
Test status
Simulation time 4149143392 ps
CPU time 40.8 seconds
Started Feb 18 12:43:09 PM PST 24
Finished Feb 18 12:43:52 PM PST 24
Peak memory 214956 kb
Host smart-590b5e31-c331-4ee4-a7e9-c43c77317bf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749076729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.749076729
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3436879478
Short name T65
Test name
Test status
Simulation time 3930098764 ps
CPU time 10.37 seconds
Started Feb 18 12:41:25 PM PST 24
Finished Feb 18 12:41:36 PM PST 24
Peak memory 211164 kb
Host smart-46c76164-7334-48da-9548-4abd0dde2a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436879478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3436879478
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1992700007
Short name T278
Test name
Test status
Simulation time 4208486680 ps
CPU time 33.19 seconds
Started Feb 18 12:41:31 PM PST 24
Finished Feb 18 12:42:05 PM PST 24
Peak memory 211576 kb
Host smart-560d75e0-e0d1-456a-b712-11869058c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992700007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1992700007
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2716441076
Short name T297
Test name
Test status
Simulation time 1943102728 ps
CPU time 16.02 seconds
Started Feb 18 12:41:25 PM PST 24
Finished Feb 18 12:41:41 PM PST 24
Peak memory 211036 kb
Host smart-d2e9aece-4ccd-4913-9fc7-8375e118a5c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716441076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2716441076
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1846345600
Short name T251
Test name
Test status
Simulation time 2030884795 ps
CPU time 13.58 seconds
Started Feb 18 12:41:20 PM PST 24
Finished Feb 18 12:41:34 PM PST 24
Peak memory 212444 kb
Host smart-dc6d8a68-dbd9-4459-af95-a930d02ac2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846345600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1846345600
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3974878011
Short name T188
Test name
Test status
Simulation time 8999100412 ps
CPU time 26.14 seconds
Started Feb 18 12:41:24 PM PST 24
Finished Feb 18 12:41:51 PM PST 24
Peak memory 219292 kb
Host smart-972f8c6b-d1bc-4ebb-9d9d-97873fdc062c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974878011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3974878011
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3682811090
Short name T66
Test name
Test status
Simulation time 7803580696 ps
CPU time 14.5 seconds
Started Feb 18 12:41:20 PM PST 24
Finished Feb 18 12:41:36 PM PST 24
Peak memory 211096 kb
Host smart-550d0794-30fd-4628-ada1-1519e2724d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682811090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3682811090
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2682355049
Short name T233
Test name
Test status
Simulation time 11283034493 ps
CPU time 25.46 seconds
Started Feb 18 12:41:25 PM PST 24
Finished Feb 18 12:41:51 PM PST 24
Peak memory 211148 kb
Host smart-092f2ed8-222b-4f2c-bd8a-af88aafb2e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682355049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2682355049
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4121911646
Short name T287
Test name
Test status
Simulation time 5527292979 ps
CPU time 14.77 seconds
Started Feb 18 12:41:24 PM PST 24
Finished Feb 18 12:41:40 PM PST 24
Peak memory 211124 kb
Host smart-ebf695e8-a840-40d1-bba7-7437292a766a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121911646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4121911646
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.910493860
Short name T79
Test name
Test status
Simulation time 667250919 ps
CPU time 10.09 seconds
Started Feb 18 12:41:24 PM PST 24
Finished Feb 18 12:41:35 PM PST 24
Peak memory 213076 kb
Host smart-f593f9fa-a1f1-48cf-adcd-28eb0afc6d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910493860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.910493860
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4014494962
Short name T116
Test name
Test status
Simulation time 1253581574 ps
CPU time 19.42 seconds
Started Feb 18 12:41:31 PM PST 24
Finished Feb 18 12:41:51 PM PST 24
Peak memory 214820 kb
Host smart-b34fae8c-df41-44a8-91d8-35e6088ffd16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014494962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4014494962
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3772018607
Short name T154
Test name
Test status
Simulation time 175431726 ps
CPU time 4.3 seconds
Started Feb 18 12:41:27 PM PST 24
Finished Feb 18 12:41:32 PM PST 24
Peak memory 211000 kb
Host smart-69b29829-fc79-4262-9990-ccd9f87426b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772018607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3772018607
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.355608909
Short name T157
Test name
Test status
Simulation time 2892172123 ps
CPU time 83.16 seconds
Started Feb 18 12:41:28 PM PST 24
Finished Feb 18 12:42:52 PM PST 24
Peak memory 227688 kb
Host smart-8196f93b-7e9f-4089-88aa-10b5306c8301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355608909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.355608909
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2778956503
Short name T252
Test name
Test status
Simulation time 3287142236 ps
CPU time 28.79 seconds
Started Feb 18 12:41:28 PM PST 24
Finished Feb 18 12:41:57 PM PST 24
Peak memory 212284 kb
Host smart-f862a5cd-168e-48f3-81d4-1d7faab169bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778956503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2778956503
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.661265615
Short name T132
Test name
Test status
Simulation time 723431898 ps
CPU time 9.78 seconds
Started Feb 18 12:41:27 PM PST 24
Finished Feb 18 12:41:38 PM PST 24
Peak memory 211084 kb
Host smart-04be09fd-746a-4b65-b0c7-0c1b7db3c343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661265615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.661265615
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3554682894
Short name T1
Test name
Test status
Simulation time 3808170039 ps
CPU time 33.78 seconds
Started Feb 18 12:41:30 PM PST 24
Finished Feb 18 12:42:05 PM PST 24
Peak memory 213480 kb
Host smart-07fb46c1-fd3a-4f48-bd81-fa31bebd270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554682894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3554682894
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3203260365
Short name T24
Test name
Test status
Simulation time 759769855 ps
CPU time 6.56 seconds
Started Feb 18 12:41:27 PM PST 24
Finished Feb 18 12:41:35 PM PST 24
Peak memory 211012 kb
Host smart-08af0c7c-2417-4f15-b987-a8020557d93a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203260365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3203260365
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2574519621
Short name T286
Test name
Test status
Simulation time 377476089 ps
CPU time 4.28 seconds
Started Feb 18 12:41:31 PM PST 24
Finished Feb 18 12:41:36 PM PST 24
Peak memory 211080 kb
Host smart-632fb8c9-1dcb-48dd-aa91-08816acd2357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574519621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2574519621
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4027670636
Short name T32
Test name
Test status
Simulation time 1118096779 ps
CPU time 68.78 seconds
Started Feb 18 12:41:28 PM PST 24
Finished Feb 18 12:42:38 PM PST 24
Peak memory 228260 kb
Host smart-c41261ac-74c3-4690-9d42-8a05aa5b226c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027670636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4027670636
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2518846457
Short name T335
Test name
Test status
Simulation time 2522966830 ps
CPU time 24.38 seconds
Started Feb 18 12:41:30 PM PST 24
Finished Feb 18 12:41:55 PM PST 24
Peak memory 211560 kb
Host smart-49cb266a-2f55-46a7-aa64-4ef89fd7eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518846457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2518846457
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3201415527
Short name T19
Test name
Test status
Simulation time 1713274691 ps
CPU time 14.86 seconds
Started Feb 18 12:41:31 PM PST 24
Finished Feb 18 12:41:46 PM PST 24
Peak memory 210996 kb
Host smart-a24a14b8-3886-4a00-b875-dc1bd41ec8ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201415527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3201415527
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.343988697
Short name T144
Test name
Test status
Simulation time 2064029089 ps
CPU time 23.97 seconds
Started Feb 18 12:41:29 PM PST 24
Finished Feb 18 12:41:54 PM PST 24
Peak memory 212820 kb
Host smart-3f0474cd-e501-43ac-b092-f89380d6d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343988697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.343988697
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2162983580
Short name T134
Test name
Test status
Simulation time 3996005162 ps
CPU time 39.2 seconds
Started Feb 18 12:41:27 PM PST 24
Finished Feb 18 12:42:07 PM PST 24
Peak memory 213324 kb
Host smart-9d51c5cc-686a-4c47-87e3-d3c9e58263d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162983580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2162983580
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1579660035
Short name T48
Test name
Test status
Simulation time 279072000410 ps
CPU time 2686.63 seconds
Started Feb 18 12:41:30 PM PST 24
Finished Feb 18 01:26:19 PM PST 24
Peak memory 244944 kb
Host smart-33f6939e-0eba-4511-965d-f208a931eb1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579660035 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1579660035
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2371932408
Short name T68
Test name
Test status
Simulation time 1539785251 ps
CPU time 13.33 seconds
Started Feb 18 12:41:36 PM PST 24
Finished Feb 18 12:41:52 PM PST 24
Peak memory 211080 kb
Host smart-49f4a132-7157-49ad-a93a-89cbe44da74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371932408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2371932408
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3082612377
Short name T280
Test name
Test status
Simulation time 16561697077 ps
CPU time 34.05 seconds
Started Feb 18 12:41:36 PM PST 24
Finished Feb 18 12:42:12 PM PST 24
Peak memory 211984 kb
Host smart-1ca71a75-3d6e-4854-8707-64dd368f9f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082612377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3082612377
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.920742136
Short name T302
Test name
Test status
Simulation time 96095294 ps
CPU time 5.52 seconds
Started Feb 18 12:41:29 PM PST 24
Finished Feb 18 12:41:36 PM PST 24
Peak memory 211064 kb
Host smart-1ca13bac-82a2-4e33-8185-12476952c217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920742136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.920742136
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.573065900
Short name T131
Test name
Test status
Simulation time 3774337853 ps
CPU time 32.63 seconds
Started Feb 18 12:41:29 PM PST 24
Finished Feb 18 12:42:04 PM PST 24
Peak memory 213508 kb
Host smart-d24d356e-f453-47ee-b986-0b4d155b8409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573065900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.573065900
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1892099193
Short name T243
Test name
Test status
Simulation time 8682182415 ps
CPU time 17.1 seconds
Started Feb 18 12:41:30 PM PST 24
Finished Feb 18 12:41:48 PM PST 24
Peak memory 212192 kb
Host smart-4a462bf9-3fdb-4ee0-90ed-a9393a21d20d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892099193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1892099193
Directory /workspace/9.rom_ctrl_stress_all/latest
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