Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.36	98.96	91.67	97.69	100.00	97.78	98.05

Total modules in report: 44

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_fifo_sync_cnt	77.78	100.00	33.33			100.00
prim_fifo_sync_cnt	66.67		33.33			100.00
prim_fifo_sync_cnt ( parameter Depth=2,Width=2,Secure=0 )	100.00	100.00
prim_fifo_sync_cnt ( parameter Depth=2,Width=2,Secure=1 )	100.00	100.00
rom_ctrl_scrambled_rom	87.50	75.00					100.00
prim_generic_rom	88.89	66.67				100.00	100.00
prim_count	90.00			90.00
prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )	90.00			90.00
prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )	90.00			90.00
tlul_adapter_sram	92.00	96.92	82.20			88.89	100.00
rom_ctrl_fsm	93.67	100.00	96.36		100.00	96.97	75.00
prim_fifo_sync	94.29	100.00	77.15			100.00	100.00
prim_fifo_sync	100.00						100.00
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	80.77		80.77
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	100.00	100.00				100.00
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	95.10	100.00	85.29			100.00
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	65.38		65.38
tlul_rsp_intg_gen	94.44	88.89					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	66.67	66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=0 )	100.00	100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
rom_ctrl	94.98	100.00	98.28	97.33		100.00	79.31
rom_ctrl_mux	95.24	100.00	85.71			100.00
tlul_adapter_reg	98.91	100.00	95.65			100.00	100.00
rom_ctrl_compare	99.07	100.00	95.35		100.00	100.00	100.00
rom_ctrl_regs_csr_assert_fpv	100.00						100.00
tlul_data_integ_dec	100.00	100.00
prim_sparse_fsm_flop	100.00	100.00					100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
rom_ctrl_counter	100.00	100.00	100.00			100.00	100.00
prim_alert_sender	100.00			100.00
rom_ctrl_regs_reg_top	100.00	100.00	100.00			100.00	100.00
prim_mubi4_sender	100.00	100.00					100.00
tlul_assert	100.00	100.00				100.00	100.00
prim_onehot_check	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_subreg	100.00	100.00				100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL=0,Mubi=0 )	100.00		100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
rom_ctrl_rom_reg_top	100.00	100.00				100.00
prim_subreg_arb	100.00	100.00
prim_rom_adv	100.00	100.00				100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_sram_byte	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_subst_perm	100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_secded_inv_64_57_dec	100.00			100.00
prim_prince	100.00			100.00
prim_generic_flop	100.00	100.00				100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_flop
tb
prim_rom
prim_sec_anchor_buf