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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.45 97.04 92.65 97.88 100.00 98.37 98.04 98.14


Total test records in report: 448
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T300 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4217367307 Feb 21 12:55:59 PM PST 24 Feb 21 12:56:13 PM PST 24 1475840785 ps
T301 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3139765370 Feb 21 12:55:55 PM PST 24 Feb 21 12:56:01 PM PST 24 100737649 ps
T302 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2216080859 Feb 21 12:55:53 PM PST 24 Feb 21 12:55:59 PM PST 24 194222566 ps
T303 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.409640111 Feb 21 12:56:03 PM PST 24 Feb 21 12:58:30 PM PST 24 86615894313 ps
T304 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2874098221 Feb 21 12:56:01 PM PST 24 Feb 21 12:56:17 PM PST 24 7525769404 ps
T305 /workspace/coverage/default/41.rom_ctrl_smoke.2039309339 Feb 21 12:56:16 PM PST 24 Feb 21 12:56:43 PM PST 24 4458206380 ps
T306 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1874339978 Feb 21 12:55:43 PM PST 24 Feb 21 12:55:55 PM PST 24 3809645553 ps
T307 /workspace/coverage/default/38.rom_ctrl_smoke.3416008576 Feb 21 12:56:02 PM PST 24 Feb 21 12:56:36 PM PST 24 13701517725 ps
T308 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3727856500 Feb 21 12:56:01 PM PST 24 Feb 21 12:59:14 PM PST 24 64921057769 ps
T309 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3537777086 Feb 21 12:55:33 PM PST 24 Feb 21 12:58:42 PM PST 24 122334638749 ps
T310 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.923945732 Feb 21 12:55:32 PM PST 24 Feb 21 12:55:42 PM PST 24 177261552 ps
T311 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3099948100 Feb 21 12:55:51 PM PST 24 Feb 21 12:56:04 PM PST 24 5314840709 ps
T312 /workspace/coverage/default/21.rom_ctrl_stress_all.664206824 Feb 21 12:55:53 PM PST 24 Feb 21 12:56:56 PM PST 24 46826311844 ps
T313 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.622125479 Feb 21 12:56:10 PM PST 24 Feb 21 12:56:44 PM PST 24 32804506494 ps
T39 /workspace/coverage/default/1.rom_ctrl_sec_cm.3951820735 Feb 21 12:55:17 PM PST 24 Feb 21 12:57:07 PM PST 24 2837928493 ps
T314 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1103644161 Feb 21 12:55:32 PM PST 24 Feb 21 12:56:00 PM PST 24 12122458970 ps
T315 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1947566242 Feb 21 12:55:53 PM PST 24 Feb 21 12:59:55 PM PST 24 21104894700 ps
T316 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3734996167 Feb 21 12:56:20 PM PST 24 Feb 21 12:56:29 PM PST 24 380421412 ps
T317 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.592118262 Feb 21 12:56:21 PM PST 24 Feb 21 12:56:36 PM PST 24 20111872823 ps
T318 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1021215477 Feb 21 12:56:11 PM PST 24 Feb 21 12:56:23 PM PST 24 3052816087 ps
T319 /workspace/coverage/default/7.rom_ctrl_smoke.2556011146 Feb 21 12:55:36 PM PST 24 Feb 21 12:55:47 PM PST 24 758972582 ps
T320 /workspace/coverage/default/45.rom_ctrl_alert_test.3606273611 Feb 21 12:56:12 PM PST 24 Feb 21 12:56:24 PM PST 24 1200346042 ps
T40 /workspace/coverage/default/2.rom_ctrl_sec_cm.2862061842 Feb 21 12:55:15 PM PST 24 Feb 21 12:56:12 PM PST 24 2889716722 ps
T321 /workspace/coverage/default/10.rom_ctrl_smoke.1548463390 Feb 21 12:55:37 PM PST 24 Feb 21 12:56:04 PM PST 24 2419960899 ps
T322 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3657604776 Feb 21 12:55:16 PM PST 24 Feb 21 12:55:47 PM PST 24 4635675429 ps
T323 /workspace/coverage/default/2.rom_ctrl_stress_all.4118033646 Feb 21 12:55:22 PM PST 24 Feb 21 12:55:57 PM PST 24 11125567968 ps
T324 /workspace/coverage/default/45.rom_ctrl_smoke.185068480 Feb 21 12:56:12 PM PST 24 Feb 21 12:56:23 PM PST 24 188083251 ps
T325 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.741608636 Feb 21 12:55:50 PM PST 24 Feb 21 01:00:07 PM PST 24 63330707713 ps
T326 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2741505984 Feb 21 12:56:19 PM PST 24 Feb 21 12:56:40 PM PST 24 7188223887 ps
T327 /workspace/coverage/default/17.rom_ctrl_stress_all.3630190504 Feb 21 12:55:43 PM PST 24 Feb 21 12:56:37 PM PST 24 9816269873 ps
T328 /workspace/coverage/default/29.rom_ctrl_smoke.2706551820 Feb 21 12:55:49 PM PST 24 Feb 21 12:56:23 PM PST 24 6865352549 ps
T329 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3727114657 Feb 21 12:55:15 PM PST 24 Feb 21 12:57:41 PM PST 24 30380490293 ps
T330 /workspace/coverage/default/5.rom_ctrl_alert_test.3959894207 Feb 21 12:55:33 PM PST 24 Feb 21 12:55:37 PM PST 24 85855720 ps
T331 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3599155175 Feb 21 12:56:04 PM PST 24 Feb 21 12:56:21 PM PST 24 10198498604 ps
T332 /workspace/coverage/default/19.rom_ctrl_smoke.1855087303 Feb 21 12:56:13 PM PST 24 Feb 21 12:56:40 PM PST 24 5838853116 ps
T333 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3275792540 Feb 21 12:55:54 PM PST 24 Feb 21 12:56:27 PM PST 24 8064370152 ps
T334 /workspace/coverage/default/36.rom_ctrl_alert_test.1465741368 Feb 21 12:56:20 PM PST 24 Feb 21 12:56:31 PM PST 24 534287515 ps
T335 /workspace/coverage/default/8.rom_ctrl_smoke.1001787098 Feb 21 12:55:36 PM PST 24 Feb 21 12:56:01 PM PST 24 2529589411 ps
T336 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3662045050 Feb 21 12:55:55 PM PST 24 Feb 21 12:56:05 PM PST 24 170576565 ps
T337 /workspace/coverage/default/6.rom_ctrl_alert_test.2419408572 Feb 21 12:55:32 PM PST 24 Feb 21 12:55:40 PM PST 24 573733678 ps
T338 /workspace/coverage/default/11.rom_ctrl_smoke.2792425662 Feb 21 12:55:43 PM PST 24 Feb 21 12:56:12 PM PST 24 2765397823 ps
T339 /workspace/coverage/default/24.rom_ctrl_stress_all.2895778283 Feb 21 12:55:54 PM PST 24 Feb 21 12:56:07 PM PST 24 3152287832 ps
T340 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1329587736 Feb 21 12:56:08 PM PST 24 Feb 21 12:56:23 PM PST 24 1415686478 ps
T341 /workspace/coverage/default/48.rom_ctrl_alert_test.1752540671 Feb 21 12:56:19 PM PST 24 Feb 21 12:56:30 PM PST 24 3110731376 ps
T342 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.37326975 Feb 21 12:55:39 PM PST 24 Feb 21 12:55:56 PM PST 24 3523066794 ps
T343 /workspace/coverage/default/18.rom_ctrl_alert_test.2691928695 Feb 21 12:55:40 PM PST 24 Feb 21 12:55:47 PM PST 24 1307195196 ps
T344 /workspace/coverage/default/35.rom_ctrl_smoke.3887776190 Feb 21 12:56:06 PM PST 24 Feb 21 12:56:28 PM PST 24 1937468558 ps
T345 /workspace/coverage/default/46.rom_ctrl_stress_all.2174924785 Feb 21 12:56:10 PM PST 24 Feb 21 12:57:12 PM PST 24 11021898059 ps
T346 /workspace/coverage/default/18.rom_ctrl_stress_all.1552823056 Feb 21 12:55:46 PM PST 24 Feb 21 12:56:01 PM PST 24 7717899407 ps
T347 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.243340282 Feb 21 12:56:08 PM PST 24 Feb 21 12:58:33 PM PST 24 2431572486 ps
T348 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.595672000 Feb 21 12:55:14 PM PST 24 Feb 21 12:55:24 PM PST 24 168459172 ps
T349 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2764204694 Feb 21 12:56:07 PM PST 24 Feb 21 12:56:13 PM PST 24 93683404 ps
T350 /workspace/coverage/default/17.rom_ctrl_alert_test.2916117603 Feb 21 12:55:40 PM PST 24 Feb 21 12:55:48 PM PST 24 1026731877 ps
T59 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1535811049 Feb 21 02:51:34 PM PST 24 Feb 21 02:52:46 PM PST 24 319336935 ps
T62 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3181233503 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:46 PM PST 24 3011178561 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.321939927 Feb 21 02:50:58 PM PST 24 Feb 21 02:51:03 PM PST 24 85450847 ps
T351 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3270600589 Feb 21 02:51:05 PM PST 24 Feb 21 02:51:14 PM PST 24 1460118175 ps
T352 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3569463402 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:53 PM PST 24 1886099589 ps
T66 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.592513992 Feb 21 02:51:05 PM PST 24 Feb 21 02:52:21 PM PST 24 32566610617 ps
T353 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1491413684 Feb 21 02:51:17 PM PST 24 Feb 21 02:51:25 PM PST 24 378212615 ps
T354 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1595061070 Feb 21 02:51:16 PM PST 24 Feb 21 02:51:26 PM PST 24 1739148665 ps
T355 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3978457203 Feb 21 02:51:04 PM PST 24 Feb 21 02:51:15 PM PST 24 1721303167 ps
T119 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2565352968 Feb 21 02:51:01 PM PST 24 Feb 21 02:51:13 PM PST 24 1235970815 ps
T356 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.67210155 Feb 21 02:51:02 PM PST 24 Feb 21 02:51:19 PM PST 24 1970605126 ps
T357 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1329052972 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:39 PM PST 24 1041100459 ps
T120 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3266611145 Feb 21 02:51:07 PM PST 24 Feb 21 02:51:13 PM PST 24 88975285 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2518183285 Feb 21 02:51:12 PM PST 24 Feb 21 02:51:18 PM PST 24 96864841 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2505503414 Feb 21 02:51:23 PM PST 24 Feb 21 02:51:38 PM PST 24 3402397493 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.413909555 Feb 21 02:51:30 PM PST 24 Feb 21 02:51:47 PM PST 24 19353123948 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3939860299 Feb 21 02:51:06 PM PST 24 Feb 21 02:51:21 PM PST 24 1616457301 ps
T360 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3329671949 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:43 PM PST 24 164971600 ps
T121 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3590320409 Feb 21 02:51:14 PM PST 24 Feb 21 02:51:25 PM PST 24 3906707074 ps
T69 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4240864668 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:19 PM PST 24 433324855 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1336843914 Feb 21 02:51:03 PM PST 24 Feb 21 02:51:17 PM PST 24 12311673327 ps
T361 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3635689132 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:42 PM PST 24 366109315 ps
T60 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2399094041 Feb 21 02:51:22 PM PST 24 Feb 21 02:52:09 PM PST 24 7965719578 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1384242716 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:48 PM PST 24 2018808613 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1523126480 Feb 21 02:51:25 PM PST 24 Feb 21 02:51:31 PM PST 24 89929162 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.103907893 Feb 21 02:51:18 PM PST 24 Feb 21 02:52:28 PM PST 24 8855434640 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2813382227 Feb 21 02:50:56 PM PST 24 Feb 21 02:51:00 PM PST 24 89909109 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1374972826 Feb 21 02:51:03 PM PST 24 Feb 21 02:51:13 PM PST 24 3442505619 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1931936834 Feb 21 02:51:29 PM PST 24 Feb 21 02:51:45 PM PST 24 7346228840 ps
T71 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1704506301 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:27 PM PST 24 530832198 ps
T61 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.482832415 Feb 21 02:51:28 PM PST 24 Feb 21 02:52:47 PM PST 24 1694651865 ps
T72 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1195877151 Feb 21 02:51:04 PM PST 24 Feb 21 02:52:16 PM PST 24 15379222297 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.98000448 Feb 21 02:51:10 PM PST 24 Feb 21 02:51:17 PM PST 24 671454753 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1761844676 Feb 21 02:51:14 PM PST 24 Feb 21 02:51:31 PM PST 24 6677078729 ps
T369 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1503226013 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:42 PM PST 24 85800777 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4041077174 Feb 21 02:51:31 PM PST 24 Feb 21 02:51:45 PM PST 24 1554787631 ps
T74 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2833696957 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:41 PM PST 24 347339062 ps
T80 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2814846145 Feb 21 02:51:30 PM PST 24 Feb 21 02:52:00 PM PST 24 3655405207 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3992857556 Feb 21 02:51:25 PM PST 24 Feb 21 02:51:45 PM PST 24 717877596 ps
T127 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.946095005 Feb 21 02:51:59 PM PST 24 Feb 21 02:52:40 PM PST 24 2025074436 ps
T82 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1066598667 Feb 21 02:51:35 PM PST 24 Feb 21 02:51:54 PM PST 24 3978979504 ps
T370 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.667387078 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:49 PM PST 24 5234880243 ps
T83 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3438492765 Feb 21 02:51:32 PM PST 24 Feb 21 02:52:39 PM PST 24 8022584196 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3950962607 Feb 21 02:51:36 PM PST 24 Feb 21 02:52:04 PM PST 24 573115886 ps
T130 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1157951978 Feb 21 02:51:15 PM PST 24 Feb 21 02:52:02 PM PST 24 1882916270 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4039488214 Feb 21 02:51:10 PM PST 24 Feb 21 02:51:20 PM PST 24 694482431 ps
T133 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3993451440 Feb 21 02:51:35 PM PST 24 Feb 21 02:52:15 PM PST 24 855422655 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1845045638 Feb 21 02:51:02 PM PST 24 Feb 21 02:51:15 PM PST 24 776098507 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1964155159 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:26 PM PST 24 747442307 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1483673945 Feb 21 02:50:58 PM PST 24 Feb 21 02:51:14 PM PST 24 3696520556 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.599596637 Feb 21 02:50:53 PM PST 24 Feb 21 02:51:09 PM PST 24 3801648906 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.425245994 Feb 21 02:51:04 PM PST 24 Feb 21 02:51:10 PM PST 24 177786698 ps
T128 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2074008166 Feb 21 02:51:16 PM PST 24 Feb 21 02:52:36 PM PST 24 3595262357 ps
T377 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3541102531 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:26 PM PST 24 6504938846 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.409902599 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:27 PM PST 24 274131977 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.36648177 Feb 21 02:51:17 PM PST 24 Feb 21 02:51:23 PM PST 24 85731083 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4086171535 Feb 21 02:51:00 PM PST 24 Feb 21 02:51:09 PM PST 24 449214528 ps
T380 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1894968025 Feb 21 02:51:18 PM PST 24 Feb 21 02:51:23 PM PST 24 88917559 ps
T381 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2688800399 Feb 21 02:51:04 PM PST 24 Feb 21 02:51:21 PM PST 24 2151490656 ps
T134 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2070780242 Feb 21 02:51:29 PM PST 24 Feb 21 02:52:52 PM PST 24 2414657328 ps
T382 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4045264141 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:25 PM PST 24 130743182 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1519754080 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:27 PM PST 24 261166239 ps
T126 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.118285747 Feb 21 02:50:56 PM PST 24 Feb 21 02:51:54 PM PST 24 27498663097 ps
T384 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1077770857 Feb 21 02:51:29 PM PST 24 Feb 21 02:51:45 PM PST 24 6258289983 ps
T135 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.837594378 Feb 21 02:51:26 PM PST 24 Feb 21 02:52:09 PM PST 24 1717802669 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.222363016 Feb 21 02:51:31 PM PST 24 Feb 21 02:51:50 PM PST 24 372905796 ps
T386 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.745768137 Feb 21 02:51:08 PM PST 24 Feb 21 02:51:23 PM PST 24 1722526388 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1314996771 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:43 PM PST 24 742197821 ps
T129 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3676144111 Feb 21 02:51:07 PM PST 24 Feb 21 02:52:16 PM PST 24 236318452 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1410591257 Feb 21 02:51:10 PM PST 24 Feb 21 02:51:25 PM PST 24 9419151105 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3108854912 Feb 21 02:51:03 PM PST 24 Feb 21 02:51:15 PM PST 24 1261081975 ps
T390 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3255550394 Feb 21 02:51:33 PM PST 24 Feb 21 02:51:49 PM PST 24 1662674694 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2483040138 Feb 21 02:51:04 PM PST 24 Feb 21 02:51:13 PM PST 24 575492110 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1511067761 Feb 21 02:51:44 PM PST 24 Feb 21 02:51:52 PM PST 24 320548718 ps
T137 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3243396914 Feb 21 02:51:16 PM PST 24 Feb 21 02:52:28 PM PST 24 5117260300 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3846687990 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:20 PM PST 24 438603679 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3897596558 Feb 21 02:51:16 PM PST 24 Feb 21 02:51:23 PM PST 24 350142992 ps
T395 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3424997972 Feb 21 02:51:17 PM PST 24 Feb 21 02:52:03 PM PST 24 4083321674 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3461256840 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:53 PM PST 24 1439234817 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2546255029 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:31 PM PST 24 6863466187 ps
T86 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1532755736 Feb 21 02:51:12 PM PST 24 Feb 21 02:51:41 PM PST 24 1062250536 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3698447708 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:26 PM PST 24 1397920544 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1802865952 Feb 21 02:51:30 PM PST 24 Feb 21 02:51:47 PM PST 24 1987980413 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2711088774 Feb 21 02:50:55 PM PST 24 Feb 21 02:50:59 PM PST 24 171524003 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3786245086 Feb 21 02:51:18 PM PST 24 Feb 21 02:51:32 PM PST 24 2349738216 ps
T138 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4175329739 Feb 21 02:51:12 PM PST 24 Feb 21 02:52:28 PM PST 24 1071556270 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1143100659 Feb 21 02:51:29 PM PST 24 Feb 21 02:51:36 PM PST 24 452503767 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.921187377 Feb 21 02:51:30 PM PST 24 Feb 21 02:53:06 PM PST 24 50631582154 ps
T403 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.739812778 Feb 21 02:51:30 PM PST 24 Feb 21 02:51:45 PM PST 24 22120774207 ps
T404 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1805912896 Feb 21 02:51:39 PM PST 24 Feb 21 02:51:50 PM PST 24 1086845995 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1327219748 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:38 PM PST 24 3133626470 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.260705360 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:26 PM PST 24 6432657832 ps
T407 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.131368942 Feb 21 02:51:51 PM PST 24 Feb 21 02:52:09 PM PST 24 2808817040 ps
T408 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4093968567 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:26 PM PST 24 7404763510 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1241786858 Feb 21 02:51:36 PM PST 24 Feb 21 02:52:12 PM PST 24 296290605 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1507961731 Feb 21 02:51:09 PM PST 24 Feb 21 02:51:14 PM PST 24 89163506 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.444452686 Feb 21 02:51:31 PM PST 24 Feb 21 02:51:36 PM PST 24 1659121598 ps
T412 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1319564756 Feb 21 02:51:06 PM PST 24 Feb 21 02:51:16 PM PST 24 108097816 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.24398303 Feb 21 02:51:01 PM PST 24 Feb 21 02:51:51 PM PST 24 2220778412 ps
T414 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.945117412 Feb 21 02:51:13 PM PST 24 Feb 21 02:52:48 PM PST 24 11753428756 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3669582196 Feb 21 02:51:31 PM PST 24 Feb 21 02:52:34 PM PST 24 5999434512 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.245628670 Feb 21 02:51:14 PM PST 24 Feb 21 02:51:29 PM PST 24 6012331382 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1723120948 Feb 21 02:51:31 PM PST 24 Feb 21 02:51:42 PM PST 24 4642535329 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1500775314 Feb 21 02:51:02 PM PST 24 Feb 21 02:51:12 PM PST 24 2984733355 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.240192039 Feb 21 02:51:01 PM PST 24 Feb 21 02:51:10 PM PST 24 669516184 ps
T418 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2273205102 Feb 21 02:51:42 PM PST 24 Feb 21 02:51:54 PM PST 24 2685249863 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3441079016 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:46 PM PST 24 6489778094 ps
T93 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2239566350 Feb 21 02:50:56 PM PST 24 Feb 21 02:52:30 PM PST 24 92562104320 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2523484516 Feb 21 02:51:39 PM PST 24 Feb 21 02:52:08 PM PST 24 1352601049 ps
T421 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1358256264 Feb 21 02:51:50 PM PST 24 Feb 21 02:52:27 PM PST 24 347985804 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3486076058 Feb 21 02:51:14 PM PST 24 Feb 21 02:51:50 PM PST 24 2971036094 ps
T422 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.247690423 Feb 21 02:51:17 PM PST 24 Feb 21 02:51:34 PM PST 24 5586212908 ps
T423 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2691893582 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:52 PM PST 24 3696229893 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.603133568 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:50 PM PST 24 9996361739 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2412577479 Feb 21 02:51:29 PM PST 24 Feb 21 02:51:34 PM PST 24 175470105 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.581343987 Feb 21 02:51:30 PM PST 24 Feb 21 02:52:19 PM PST 24 9158972606 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4290100842 Feb 21 02:51:09 PM PST 24 Feb 21 02:51:24 PM PST 24 1893887704 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.307837842 Feb 21 02:51:30 PM PST 24 Feb 21 02:51:49 PM PST 24 387142736 ps
T131 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2016713441 Feb 21 02:51:09 PM PST 24 Feb 21 02:51:55 PM PST 24 519087028 ps
T429 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3379756076 Feb 21 02:51:13 PM PST 24 Feb 21 02:51:31 PM PST 24 6262301847 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.910925641 Feb 21 02:51:07 PM PST 24 Feb 21 02:51:11 PM PST 24 88317028 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3667603282 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:27 PM PST 24 3536225346 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4001196510 Feb 21 02:51:01 PM PST 24 Feb 21 02:51:27 PM PST 24 1068897486 ps
T132 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2016313079 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:54 PM PST 24 1923503781 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3057617493 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:52 PM PST 24 7936188087 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1567246945 Feb 21 02:51:11 PM PST 24 Feb 21 02:51:22 PM PST 24 9317901954 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2351589414 Feb 21 02:51:12 PM PST 24 Feb 21 02:51:30 PM PST 24 10374331197 ps
T136 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3198740181 Feb 21 02:51:33 PM PST 24 Feb 21 02:52:50 PM PST 24 3054146172 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.111049534 Feb 21 02:51:12 PM PST 24 Feb 21 02:51:22 PM PST 24 1073371992 ps
T435 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2200173954 Feb 21 02:51:31 PM PST 24 Feb 21 02:51:44 PM PST 24 1485838881 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.263300971 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:46 PM PST 24 824563305 ps
T437 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4013897655 Feb 21 02:51:30 PM PST 24 Feb 21 02:52:34 PM PST 24 8120183125 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2871636878 Feb 21 02:51:17 PM PST 24 Feb 21 02:51:31 PM PST 24 3003814092 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.894191536 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:57 PM PST 24 2854740895 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1083604736 Feb 21 02:51:25 PM PST 24 Feb 21 02:51:32 PM PST 24 131664628 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3754147611 Feb 21 02:51:02 PM PST 24 Feb 21 02:51:16 PM PST 24 6673708033 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.426777926 Feb 21 02:51:05 PM PST 24 Feb 21 02:51:22 PM PST 24 23689013576 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3130174101 Feb 21 02:51:15 PM PST 24 Feb 21 02:51:24 PM PST 24 2904442999 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.213271772 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:35 PM PST 24 7836695685 ps
T443 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3728206844 Feb 21 02:51:04 PM PST 24 Feb 21 02:51:16 PM PST 24 898923757 ps
T444 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3947098606 Feb 21 02:51:31 PM PST 24 Feb 21 02:51:36 PM PST 24 378629241 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.32478730 Feb 21 02:51:12 PM PST 24 Feb 21 02:51:28 PM PST 24 3363498966 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2082853984 Feb 21 02:51:09 PM PST 24 Feb 21 02:51:15 PM PST 24 92908007 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1007573992 Feb 21 02:51:19 PM PST 24 Feb 21 02:51:31 PM PST 24 1369551411 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3104032733 Feb 21 02:51:18 PM PST 24 Feb 21 02:51:36 PM PST 24 1851881543 ps

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.756136045
Short name T9
Test name
Test status
Simulation time 52523068694 ps
CPU time 708.97 seconds
Started Feb 21 12:55:19 PM PST 24
Finished Feb 21 01:07:09 PM PST 24
Peak memory 227800 kb
Host smart-853b667b-ec5d-4a03-8625-2477976ef18c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756136045 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.756136045
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2937865815
Short name T6
Test name
Test status
Simulation time 43687121915 ps
CPU time 269.93 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 01:00:10 PM PST 24
Peak memory 234304 kb
Host smart-7f0036f9-5bb5-4cc7-b4d3-af4b0ae84f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937865815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2937865815
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1628160952
Short name T16
Test name
Test status
Simulation time 235740531357 ps
CPU time 4164.72 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 02:05:06 PM PST 24
Peak memory 253584 kb
Host smart-ba5f66d6-a020-4a9f-ad01-ed1010d53873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628160952 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1628160952
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2777080335
Short name T102
Test name
Test status
Simulation time 317640466469 ps
CPU time 425.97 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 01:02:44 PM PST 24
Peak memory 228740 kb
Host smart-06273775-075d-4ddc-ae5c-2b214c5888f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777080335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2777080335
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.482832415
Short name T61
Test name
Test status
Simulation time 1694651865 ps
CPU time 77.86 seconds
Started Feb 21 02:51:28 PM PST 24
Finished Feb 21 02:52:47 PM PST 24
Peak memory 211632 kb
Host smart-a0a28aef-979d-4970-bdaf-54bc80975d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482832415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.482832415
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3299703385
Short name T3
Test name
Test status
Simulation time 26856729081 ps
CPU time 69.51 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:57:29 PM PST 24
Peak memory 214628 kb
Host smart-048441b0-f12c-41b3-ab11-64aa735ed3b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299703385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3299703385
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2025373741
Short name T34
Test name
Test status
Simulation time 1749569076 ps
CPU time 108.15 seconds
Started Feb 21 12:55:20 PM PST 24
Finished Feb 21 12:57:09 PM PST 24
Peak memory 238312 kb
Host smart-8577a6a5-9fb4-4a67-b7a2-be0f42be7abf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025373741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2025373741
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.592513992
Short name T66
Test name
Test status
Simulation time 32566610617 ps
CPU time 76.07 seconds
Started Feb 21 02:51:05 PM PST 24
Finished Feb 21 02:52:21 PM PST 24
Peak memory 211152 kb
Host smart-5d2783d0-c3df-4e1b-908e-f35a01cde36f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592513992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.592513992
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3676144111
Short name T129
Test name
Test status
Simulation time 236318452 ps
CPU time 68.27 seconds
Started Feb 21 02:51:07 PM PST 24
Finished Feb 21 02:52:16 PM PST 24
Peak memory 212744 kb
Host smart-742a0927-6cfb-4e63-8281-c55cd569d89f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676144111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3676144111
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3863246159
Short name T7
Test name
Test status
Simulation time 216823469 ps
CPU time 5.99 seconds
Started Feb 21 12:55:48 PM PST 24
Finished Feb 21 12:55:54 PM PST 24
Peak memory 211124 kb
Host smart-b221af35-88a6-4043-852e-ca18ae0f73f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863246159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3863246159
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4128728251
Short name T146
Test name
Test status
Simulation time 5208811897 ps
CPU time 17.74 seconds
Started Feb 21 12:55:22 PM PST 24
Finished Feb 21 12:55:40 PM PST 24
Peak memory 211348 kb
Host smart-b221f390-d0c1-4545-979f-0791d50bdebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128728251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4128728251
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.11325748
Short name T228
Test name
Test status
Simulation time 168646876 ps
CPU time 9.28 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:55:47 PM PST 24
Peak memory 211712 kb
Host smart-9b0ef440-641b-4972-9514-12a64db11d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11325748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.11325748
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.946095005
Short name T127
Test name
Test status
Simulation time 2025074436 ps
CPU time 39.18 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:40 PM PST 24
Peak memory 211112 kb
Host smart-eb0fc74c-2685-4f8a-b8bf-ae0ed2a7d70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946095005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.946095005
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2074008166
Short name T128
Test name
Test status
Simulation time 3595262357 ps
CPU time 79.49 seconds
Started Feb 21 02:51:16 PM PST 24
Finished Feb 21 02:52:36 PM PST 24
Peak memory 212072 kb
Host smart-c77ee56a-32e6-4c8f-af11-80e61770c916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074008166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2074008166
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3438492765
Short name T83
Test name
Test status
Simulation time 8022584196 ps
CPU time 66.54 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:52:39 PM PST 24
Peak memory 211148 kb
Host smart-b616b3e3-079e-44a5-91f0-70db8ce68289
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438492765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3438492765
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2070780242
Short name T134
Test name
Test status
Simulation time 2414657328 ps
CPU time 82.39 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:52:52 PM PST 24
Peak memory 213128 kb
Host smart-c67657d8-d1d4-47c6-bf6d-bbd11c4acefa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070780242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2070780242
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1458342929
Short name T96
Test name
Test status
Simulation time 6526503475 ps
CPU time 13.87 seconds
Started Feb 21 12:56:06 PM PST 24
Finished Feb 21 12:56:20 PM PST 24
Peak memory 211316 kb
Host smart-1c019e80-50b1-459a-994c-65ea4cc250c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458342929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1458342929
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1964155159
Short name T84
Test name
Test status
Simulation time 747442307 ps
CPU time 6.92 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:26 PM PST 24
Peak memory 211080 kb
Host smart-e780873d-feea-472a-a9fd-b65022096ff0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964155159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1964155159
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1384242716
Short name T362
Test name
Test status
Simulation time 2018808613 ps
CPU time 15.23 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:48 PM PST 24
Peak memory 211084 kb
Host smart-e6415fb5-f78c-428a-92a8-ecd1faa68723
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384242716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1384242716
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4086171535
Short name T90
Test name
Test status
Simulation time 449214528 ps
CPU time 9.07 seconds
Started Feb 21 02:51:00 PM PST 24
Finished Feb 21 02:51:09 PM PST 24
Peak memory 211088 kb
Host smart-1a3a736e-ba30-4acf-871f-9263216e1e92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086171535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4086171535
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.599596637
Short name T375
Test name
Test status
Simulation time 3801648906 ps
CPU time 15.67 seconds
Started Feb 21 02:50:53 PM PST 24
Finished Feb 21 02:51:09 PM PST 24
Peak memory 215584 kb
Host smart-fa82189f-45f3-4a8a-9d38-f315f82f9dac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599596637 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.599596637
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.425245994
Short name T376
Test name
Test status
Simulation time 177786698 ps
CPU time 5.45 seconds
Started Feb 21 02:51:04 PM PST 24
Finished Feb 21 02:51:10 PM PST 24
Peak memory 211124 kb
Host smart-af2717e6-b9d8-4650-be09-629fd0865409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425245994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.425245994
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1007573992
Short name T447
Test name
Test status
Simulation time 1369551411 ps
CPU time 12.07 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 211008 kb
Host smart-d72faf03-b043-45a3-8859-db8e6c5d2cb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007573992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1007573992
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1374972826
Short name T366
Test name
Test status
Simulation time 3442505619 ps
CPU time 9.57 seconds
Started Feb 21 02:51:03 PM PST 24
Finished Feb 21 02:51:13 PM PST 24
Peak memory 211280 kb
Host smart-6c7c0b02-7bcb-4848-907b-f0d174634234
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374972826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1374972826
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.118285747
Short name T126
Test name
Test status
Simulation time 27498663097 ps
CPU time 57.72 seconds
Started Feb 21 02:50:56 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 211144 kb
Host smart-1deb3cca-dc95-4752-b22d-44a08fa237a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118285747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.118285747
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.409902599
Short name T378
Test name
Test status
Simulation time 274131977 ps
CPU time 8.16 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:27 PM PST 24
Peak memory 210812 kb
Host smart-5a757999-b65e-479b-ae10-4010b4a736f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409902599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.409902599
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.111049534
Short name T434
Test name
Test status
Simulation time 1073371992 ps
CPU time 8.53 seconds
Started Feb 21 02:51:12 PM PST 24
Finished Feb 21 02:51:22 PM PST 24
Peak memory 215316 kb
Host smart-28203170-7cf6-4635-b5ce-1339df2d2049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111049534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.111049534
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2016313079
Short name T132
Test name
Test status
Simulation time 1923503781 ps
CPU time 41.48 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 211272 kb
Host smart-f995c2a8-ccd2-47eb-83fc-fe0226feb9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016313079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2016313079
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.910925641
Short name T95
Test name
Test status
Simulation time 88317028 ps
CPU time 4.34 seconds
Started Feb 21 02:51:07 PM PST 24
Finished Feb 21 02:51:11 PM PST 24
Peak memory 211064 kb
Host smart-bc0728fa-e3b9-4b5b-8ff2-0ceef9a81b4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910925641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.910925641
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1483673945
Short name T374
Test name
Test status
Simulation time 3696520556 ps
CPU time 16.08 seconds
Started Feb 21 02:50:58 PM PST 24
Finished Feb 21 02:51:14 PM PST 24
Peak memory 211140 kb
Host smart-85a222cd-316e-43bc-90d3-64b72cc11076
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483673945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1483673945
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1761844676
Short name T368
Test name
Test status
Simulation time 6677078729 ps
CPU time 16.78 seconds
Started Feb 21 02:51:14 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 211060 kb
Host smart-750a9dc1-72a8-49b0-bb59-6cfd08dff982
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761844676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1761844676
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3698447708
Short name T398
Test name
Test status
Simulation time 1397920544 ps
CPU time 13.64 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:26 PM PST 24
Peak memory 219284 kb
Host smart-72201585-8cef-4d3b-aeec-3ce1abded4a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698447708 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3698447708
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2565352968
Short name T119
Test name
Test status
Simulation time 1235970815 ps
CPU time 11.62 seconds
Started Feb 21 02:51:01 PM PST 24
Finished Feb 21 02:51:13 PM PST 24
Peak memory 211088 kb
Host smart-6783473c-721d-4148-9ede-1d4acba6415f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565352968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2565352968
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2813382227
Short name T365
Test name
Test status
Simulation time 89909109 ps
CPU time 4.25 seconds
Started Feb 21 02:50:56 PM PST 24
Finished Feb 21 02:51:00 PM PST 24
Peak memory 210988 kb
Host smart-adac4681-ace9-4a51-b318-d57b0bce95e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813382227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2813382227
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3754147611
Short name T440
Test name
Test status
Simulation time 6673708033 ps
CPU time 13.41 seconds
Started Feb 21 02:51:02 PM PST 24
Finished Feb 21 02:51:16 PM PST 24
Peak memory 211072 kb
Host smart-4aa114de-92de-4bcf-a8a4-550552ebf0fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754147611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3754147611
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.103907893
Short name T364
Test name
Test status
Simulation time 8855434640 ps
CPU time 69.55 seconds
Started Feb 21 02:51:18 PM PST 24
Finished Feb 21 02:52:28 PM PST 24
Peak memory 211144 kb
Host smart-6b1487e1-7d2d-4a84-8860-9ceee072ea57
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103907893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.103907893
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.426777926
Short name T441
Test name
Test status
Simulation time 23689013576 ps
CPU time 16.87 seconds
Started Feb 21 02:51:05 PM PST 24
Finished Feb 21 02:51:22 PM PST 24
Peak memory 211132 kb
Host smart-b8fec3db-bac9-4b37-b71e-5c4395ceca14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426777926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.426777926
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1845045638
Short name T373
Test name
Test status
Simulation time 776098507 ps
CPU time 13.02 seconds
Started Feb 21 02:51:02 PM PST 24
Finished Feb 21 02:51:15 PM PST 24
Peak memory 214284 kb
Host smart-084083c6-200e-4341-ae28-611a16c71c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845045638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1845045638
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1410591257
Short name T388
Test name
Test status
Simulation time 9419151105 ps
CPU time 13.61 seconds
Started Feb 21 02:51:10 PM PST 24
Finished Feb 21 02:51:25 PM PST 24
Peak memory 215792 kb
Host smart-ce77b140-b600-4557-b349-c64cbcdc68af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410591257 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1410591257
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3590320409
Short name T121
Test name
Test status
Simulation time 3906707074 ps
CPU time 10.04 seconds
Started Feb 21 02:51:14 PM PST 24
Finished Feb 21 02:51:25 PM PST 24
Peak memory 211072 kb
Host smart-9b127128-0a44-41dd-a218-75e5860ad3aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590320409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3590320409
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1195877151
Short name T72
Test name
Test status
Simulation time 15379222297 ps
CPU time 71.7 seconds
Started Feb 21 02:51:04 PM PST 24
Finished Feb 21 02:52:16 PM PST 24
Peak memory 211144 kb
Host smart-b0081665-6e49-40c8-bf1c-d805a6694331
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195877151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1195877151
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4093968567
Short name T408
Test name
Test status
Simulation time 7404763510 ps
CPU time 7.09 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:26 PM PST 24
Peak memory 210924 kb
Host smart-53a29384-fc41-46a2-8712-b6e7d30b4457
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093968567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4093968567
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2351589414
Short name T433
Test name
Test status
Simulation time 10374331197 ps
CPU time 16.83 seconds
Started Feb 21 02:51:12 PM PST 24
Finished Feb 21 02:51:30 PM PST 24
Peak memory 215820 kb
Host smart-a2554640-dfb0-43be-8e56-8c89c288805f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351589414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2351589414
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3198740181
Short name T136
Test name
Test status
Simulation time 3054146172 ps
CPU time 76.26 seconds
Started Feb 21 02:51:33 PM PST 24
Finished Feb 21 02:52:50 PM PST 24
Peak memory 211144 kb
Host smart-c000c14a-9175-44ae-9b67-1240fd7aa306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198740181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3198740181
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4045264141
Short name T382
Test name
Test status
Simulation time 130743182 ps
CPU time 5.68 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:25 PM PST 24
Peak memory 214932 kb
Host smart-291564fc-888e-42d2-9c0f-b9d89fb44af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045264141 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4045264141
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2505503414
Short name T67
Test name
Test status
Simulation time 3402397493 ps
CPU time 14.22 seconds
Started Feb 21 02:51:23 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 211156 kb
Host smart-ba6e8efe-6c2b-4986-92e3-2a3550b01eb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505503414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2505503414
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4013897655
Short name T437
Test name
Test status
Simulation time 8120183125 ps
CPU time 64.03 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:52:34 PM PST 24
Peak memory 211096 kb
Host smart-a2f35a4b-a49f-4e8f-8d03-23873774b3b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013897655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4013897655
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.745768137
Short name T386
Test name
Test status
Simulation time 1722526388 ps
CPU time 14.54 seconds
Started Feb 21 02:51:08 PM PST 24
Finished Feb 21 02:51:23 PM PST 24
Peak memory 211280 kb
Host smart-ea4cd38d-a5fc-4b09-bf05-bdefb979560b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745768137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.745768137
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.36648177
Short name T379
Test name
Test status
Simulation time 85731083 ps
CPU time 6.37 seconds
Started Feb 21 02:51:17 PM PST 24
Finished Feb 21 02:51:23 PM PST 24
Peak memory 215240 kb
Host smart-b4ea5289-d292-486d-bfdb-c408a74c1211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36648177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.36648177
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.837594378
Short name T135
Test name
Test status
Simulation time 1717802669 ps
CPU time 41.71 seconds
Started Feb 21 02:51:26 PM PST 24
Finished Feb 21 02:52:09 PM PST 24
Peak memory 211064 kb
Host smart-d41cd166-b307-4c07-894b-62a603b678d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837594378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.837594378
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3541102531
Short name T377
Test name
Test status
Simulation time 6504938846 ps
CPU time 14.59 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:26 PM PST 24
Peak memory 216520 kb
Host smart-faf49d3d-a31d-46a0-928b-0bfe85a1f15a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541102531 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3541102531
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3947098606
Short name T444
Test name
Test status
Simulation time 378629241 ps
CPU time 4.16 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 211052 kb
Host smart-631f5d8a-53d8-4564-9f87-21a98db799d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947098606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3947098606
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.945117412
Short name T414
Test name
Test status
Simulation time 11753428756 ps
CPU time 94.24 seconds
Started Feb 21 02:51:13 PM PST 24
Finished Feb 21 02:52:48 PM PST 24
Peak memory 211128 kb
Host smart-f5ecbcc2-77c1-4eb3-8f04-f20a5999829c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945117412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.945117412
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1143100659
Short name T401
Test name
Test status
Simulation time 452503767 ps
CPU time 6.1 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 211036 kb
Host smart-30ee7a5f-dd4d-435e-8ccc-0ee8ec359a4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143100659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1143100659
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3255550394
Short name T390
Test name
Test status
Simulation time 1662674694 ps
CPU time 15.98 seconds
Started Feb 21 02:51:33 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 215132 kb
Host smart-1aa12073-25fc-477b-ad6d-00b5853966e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255550394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3255550394
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1314996771
Short name T387
Test name
Test status
Simulation time 742197821 ps
CPU time 8.09 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:43 PM PST 24
Peak memory 213176 kb
Host smart-e6dce7a8-c6f0-4b37-b2ca-00005d80cbde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314996771 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1314996771
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2871636878
Short name T438
Test name
Test status
Simulation time 3003814092 ps
CPU time 14.25 seconds
Started Feb 21 02:51:17 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 211124 kb
Host smart-a941f144-8632-461f-985e-dde61de75482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871636878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2871636878
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.222363016
Short name T385
Test name
Test status
Simulation time 372905796 ps
CPU time 18.96 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:50 PM PST 24
Peak memory 211080 kb
Host smart-ced5803b-751e-46e4-9530-254beace2201
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222363016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.222363016
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4041077174
Short name T73
Test name
Test status
Simulation time 1554787631 ps
CPU time 13.96 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:45 PM PST 24
Peak memory 211024 kb
Host smart-5776b07a-1e19-48ba-97e3-dedd26bcc7e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041077174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4041077174
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1491413684
Short name T353
Test name
Test status
Simulation time 378212615 ps
CPU time 7.29 seconds
Started Feb 21 02:51:17 PM PST 24
Finished Feb 21 02:51:25 PM PST 24
Peak memory 215336 kb
Host smart-3062e923-4824-431d-8cea-b25414ecd0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491413684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1491413684
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2399094041
Short name T60
Test name
Test status
Simulation time 7965719578 ps
CPU time 46.11 seconds
Started Feb 21 02:51:22 PM PST 24
Finished Feb 21 02:52:09 PM PST 24
Peak memory 211668 kb
Host smart-b89d2b09-68df-4946-80dc-5c2cfa3286be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399094041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2399094041
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3569463402
Short name T352
Test name
Test status
Simulation time 1886099589 ps
CPU time 15.83 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:53 PM PST 24
Peak memory 219264 kb
Host smart-837e366b-50aa-4c63-96f5-9b3da27746cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569463402 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3569463402
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1503226013
Short name T369
Test name
Test status
Simulation time 85800777 ps
CPU time 4.21 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 210652 kb
Host smart-14cd4bca-944a-4c4b-8f3a-2eaec6218e97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503226013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1503226013
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1532755736
Short name T86
Test name
Test status
Simulation time 1062250536 ps
CPU time 28.13 seconds
Started Feb 21 02:51:12 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 211076 kb
Host smart-900758ff-fd55-4e40-aa9c-d31b7f3b21aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532755736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1532755736
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3461256840
Short name T396
Test name
Test status
Simulation time 1439234817 ps
CPU time 12.5 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:53 PM PST 24
Peak memory 210964 kb
Host smart-c35820ad-2449-4659-aa7a-f3091ebeb28b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461256840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3461256840
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.667387078
Short name T370
Test name
Test status
Simulation time 5234880243 ps
CPU time 14.68 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 215528 kb
Host smart-4b6afc48-5249-4c3a-a984-b9ddb9646bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667387078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.667387078
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.581343987
Short name T426
Test name
Test status
Simulation time 9158972606 ps
CPU time 48.37 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:52:19 PM PST 24
Peak memory 211140 kb
Host smart-119f0776-3ff5-4ac1-8020-69a9a8461001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581343987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.581343987
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2200173954
Short name T435
Test name
Test status
Simulation time 1485838881 ps
CPU time 12.74 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:44 PM PST 24
Peak memory 214288 kb
Host smart-bac9998d-eeef-4eab-987c-cff8a834b253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200173954 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2200173954
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.603133568
Short name T424
Test name
Test status
Simulation time 9996361739 ps
CPU time 12.35 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:50 PM PST 24
Peak memory 211120 kb
Host smart-bed408c5-5b89-4aeb-893a-a64acb9cd7eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603133568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.603133568
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2523484516
Short name T420
Test name
Test status
Simulation time 1352601049 ps
CPU time 28.03 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:52:08 PM PST 24
Peak memory 211044 kb
Host smart-cfa90563-1f50-44d9-932b-d79e8eee8222
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523484516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2523484516
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1931936834
Short name T106
Test name
Test status
Simulation time 7346228840 ps
CPU time 15.1 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:51:45 PM PST 24
Peak memory 211104 kb
Host smart-6de29487-da57-4cf4-8897-e65e3b725a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931936834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1931936834
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.131368942
Short name T407
Test name
Test status
Simulation time 2808817040 ps
CPU time 17.57 seconds
Started Feb 21 02:51:51 PM PST 24
Finished Feb 21 02:52:09 PM PST 24
Peak memory 216500 kb
Host smart-72d2df54-128a-45ed-914b-1d1ab6675627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131368942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.131368942
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1241786858
Short name T409
Test name
Test status
Simulation time 296290605 ps
CPU time 36.15 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:52:12 PM PST 24
Peak memory 211260 kb
Host smart-88af53da-531a-4c88-9a46-a5c9701605d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241786858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1241786858
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3441079016
Short name T419
Test name
Test status
Simulation time 6489778094 ps
CPU time 14.42 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:46 PM PST 24
Peak memory 215696 kb
Host smart-178b0d53-242b-4e24-b247-19152afa7019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441079016 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3441079016
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3057617493
Short name T87
Test name
Test status
Simulation time 7936188087 ps
CPU time 16.05 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 211148 kb
Host smart-928e2b09-3038-4242-8c58-18a04ec10572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057617493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3057617493
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.307837842
Short name T428
Test name
Test status
Simulation time 387142736 ps
CPU time 19.04 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 211052 kb
Host smart-18eb73f5-78b8-41ff-a768-67ab8aeee5f4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307837842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.307837842
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2412577479
Short name T425
Test name
Test status
Simulation time 175470105 ps
CPU time 4.3 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:51:34 PM PST 24
Peak memory 211028 kb
Host smart-21e7ad40-bd95-4ba8-be77-33fd6fbcd53b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412577479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2412577479
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3329671949
Short name T360
Test name
Test status
Simulation time 164971600 ps
CPU time 7.92 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:43 PM PST 24
Peak memory 215620 kb
Host smart-4acd89d4-859c-4a3b-8ea1-57d62c482e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329671949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3329671949
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1535811049
Short name T59
Test name
Test status
Simulation time 319336935 ps
CPU time 71.84 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:52:46 PM PST 24
Peak memory 212704 kb
Host smart-9e714470-ed0f-4359-964f-2a3a7a211222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535811049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1535811049
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1329052972
Short name T357
Test name
Test status
Simulation time 1041100459 ps
CPU time 6.8 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 215156 kb
Host smart-c6c8d219-1559-4ecb-993b-41ad37050f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329052972 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1329052972
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.413909555
Short name T68
Test name
Test status
Simulation time 19353123948 ps
CPU time 15.51 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:51:47 PM PST 24
Peak memory 210992 kb
Host smart-d3d23802-8b5f-4669-b826-d9ca74e42e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413909555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.413909555
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2814846145
Short name T80
Test name
Test status
Simulation time 3655405207 ps
CPU time 30.05 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:52:00 PM PST 24
Peak memory 211112 kb
Host smart-4417e48f-7721-4cd5-9d16-d40949ca9ff6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814846145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2814846145
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.739812778
Short name T403
Test name
Test status
Simulation time 22120774207 ps
CPU time 13.65 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:51:45 PM PST 24
Peak memory 211092 kb
Host smart-4a6f3534-a923-457f-b44f-4a592dab1d77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739812778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.739812778
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.263300971
Short name T436
Test name
Test status
Simulation time 824563305 ps
CPU time 11.46 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:46 PM PST 24
Peak memory 214212 kb
Host smart-ecb5e84a-a50b-4b1c-9ca3-edf515c7d43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263300971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.263300971
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3993451440
Short name T133
Test name
Test status
Simulation time 855422655 ps
CPU time 39.12 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:52:15 PM PST 24
Peak memory 211076 kb
Host smart-3e031fb0-98ff-4751-9590-42a4d747add8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993451440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3993451440
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3635689132
Short name T361
Test name
Test status
Simulation time 366109315 ps
CPU time 4.41 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 212132 kb
Host smart-ac7a635a-14d0-45c6-bcd8-c9cab81768b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635689132 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3635689132
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3181233503
Short name T62
Test name
Test status
Simulation time 3011178561 ps
CPU time 8.88 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:46 PM PST 24
Peak memory 211024 kb
Host smart-d31fb6c4-563f-43a2-9a36-56b00d0018cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181233503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3181233503
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3669582196
Short name T92
Test name
Test status
Simulation time 5999434512 ps
CPU time 62.98 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:52:34 PM PST 24
Peak memory 211132 kb
Host smart-02cbe4ee-795c-40d4-aff0-29b40983dbca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669582196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3669582196
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2833696957
Short name T74
Test name
Test status
Simulation time 347339062 ps
CPU time 4.29 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 210948 kb
Host smart-994bf6b7-01c9-4256-90b2-a36b785f0bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833696957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2833696957
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1805912896
Short name T404
Test name
Test status
Simulation time 1086845995 ps
CPU time 9.85 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:50 PM PST 24
Peak memory 214428 kb
Host smart-cf580534-5258-4733-8541-5921fd5b4d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805912896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1805912896
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1358256264
Short name T421
Test name
Test status
Simulation time 347985804 ps
CPU time 36.38 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:52:27 PM PST 24
Peak memory 211680 kb
Host smart-9793286a-a389-4d5c-9e78-cb4cdc1c6b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358256264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1358256264
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2691893582
Short name T423
Test name
Test status
Simulation time 3696229893 ps
CPU time 14.22 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 213176 kb
Host smart-0a8d3da9-fe39-4a0f-8fad-53c83785bdc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691893582 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2691893582
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1077770857
Short name T384
Test name
Test status
Simulation time 6258289983 ps
CPU time 15.15 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:51:45 PM PST 24
Peak memory 211120 kb
Host smart-b1188ff9-b918-43a4-a7e8-5fde41586e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077770857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1077770857
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3950962607
Short name T371
Test name
Test status
Simulation time 573115886 ps
CPU time 27.79 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:52:04 PM PST 24
Peak memory 211264 kb
Host smart-b8572b60-3225-4c25-a281-06f3660dea79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950962607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3950962607
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.894191536
Short name T439
Test name
Test status
Simulation time 2854740895 ps
CPU time 16.07 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:57 PM PST 24
Peak memory 211108 kb
Host smart-e4ed3ffd-655e-4432-a734-1fd5bb5c2a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894191536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.894191536
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2273205102
Short name T418
Test name
Test status
Simulation time 2685249863 ps
CPU time 11.33 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 215352 kb
Host smart-16d89cbf-cf32-4680-98ff-0612eae31efd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273205102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2273205102
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1336843914
Short name T70
Test name
Test status
Simulation time 12311673327 ps
CPU time 14.41 seconds
Started Feb 21 02:51:03 PM PST 24
Finished Feb 21 02:51:17 PM PST 24
Peak memory 211136 kb
Host smart-09cacfd9-45cb-4643-9216-9439e2c8296e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336843914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1336843914
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1507961731
Short name T410
Test name
Test status
Simulation time 89163506 ps
CPU time 4.43 seconds
Started Feb 21 02:51:09 PM PST 24
Finished Feb 21 02:51:14 PM PST 24
Peak memory 211072 kb
Host smart-854d8777-7d7a-4553-9713-8995f916a6e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507961731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1507961731
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.245628670
Short name T85
Test name
Test status
Simulation time 6012331382 ps
CPU time 14.54 seconds
Started Feb 21 02:51:14 PM PST 24
Finished Feb 21 02:51:29 PM PST 24
Peak memory 211140 kb
Host smart-e65c4998-9cc0-4b5b-9c0f-8bf11341ba3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245628670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.245628670
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2518183285
Short name T358
Test name
Test status
Simulation time 96864841 ps
CPU time 4.93 seconds
Started Feb 21 02:51:12 PM PST 24
Finished Feb 21 02:51:18 PM PST 24
Peak memory 214252 kb
Host smart-f8691a7c-8c9e-42d4-b88c-5a3ac86bb3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518183285 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2518183285
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1567246945
Short name T432
Test name
Test status
Simulation time 9317901954 ps
CPU time 10.57 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:22 PM PST 24
Peak memory 211136 kb
Host smart-34d28cc9-ad29-470b-a419-7af343db5302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567246945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1567246945
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.240192039
Short name T417
Test name
Test status
Simulation time 669516184 ps
CPU time 7.7 seconds
Started Feb 21 02:51:01 PM PST 24
Finished Feb 21 02:51:10 PM PST 24
Peak memory 211008 kb
Host smart-64c0c36b-b114-4269-a9ce-d0292b4f7c3b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240192039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.240192039
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3270600589
Short name T351
Test name
Test status
Simulation time 1460118175 ps
CPU time 8.52 seconds
Started Feb 21 02:51:05 PM PST 24
Finished Feb 21 02:51:14 PM PST 24
Peak memory 211020 kb
Host smart-1d345286-f429-478a-8026-643d9a465780
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270600589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3270600589
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3992857556
Short name T81
Test name
Test status
Simulation time 717877596 ps
CPU time 18.65 seconds
Started Feb 21 02:51:25 PM PST 24
Finished Feb 21 02:51:45 PM PST 24
Peak memory 210992 kb
Host smart-3535ae0d-a130-4a1c-8e70-c94ed4fb4e39
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992857556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3992857556
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4039488214
Short name T372
Test name
Test status
Simulation time 694482431 ps
CPU time 8.79 seconds
Started Feb 21 02:51:10 PM PST 24
Finished Feb 21 02:51:20 PM PST 24
Peak memory 211064 kb
Host smart-ce47844b-fa97-4d0c-9eb9-b40c8b00906a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039488214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4039488214
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.67210155
Short name T356
Test name
Test status
Simulation time 1970605126 ps
CPU time 16.39 seconds
Started Feb 21 02:51:02 PM PST 24
Finished Feb 21 02:51:19 PM PST 24
Peak memory 215356 kb
Host smart-ae247c26-85bb-4867-a388-600a5eed236c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67210155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.67210155
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2016713441
Short name T131
Test name
Test status
Simulation time 519087028 ps
CPU time 44.49 seconds
Started Feb 21 02:51:09 PM PST 24
Finished Feb 21 02:51:55 PM PST 24
Peak memory 211616 kb
Host smart-ed104dfd-d033-4025-83b3-cec25ab2ab59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016713441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2016713441
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4290100842
Short name T427
Test name
Test status
Simulation time 1893887704 ps
CPU time 14.87 seconds
Started Feb 21 02:51:09 PM PST 24
Finished Feb 21 02:51:24 PM PST 24
Peak memory 211076 kb
Host smart-96fc8d5a-6c0c-4835-bdcb-a67be1411c0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290100842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4290100842
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3266611145
Short name T120
Test name
Test status
Simulation time 88975285 ps
CPU time 4.35 seconds
Started Feb 21 02:51:07 PM PST 24
Finished Feb 21 02:51:13 PM PST 24
Peak memory 211072 kb
Host smart-91a29bce-49d1-4a81-a8c5-b46144f2cd69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266611145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3266611145
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3786245086
Short name T91
Test name
Test status
Simulation time 2349738216 ps
CPU time 13.87 seconds
Started Feb 21 02:51:18 PM PST 24
Finished Feb 21 02:51:32 PM PST 24
Peak memory 211112 kb
Host smart-8145584a-adbe-44ce-b1b6-bed69a9fcd8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786245086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3786245086
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3108854912
Short name T389
Test name
Test status
Simulation time 1261081975 ps
CPU time 11.38 seconds
Started Feb 21 02:51:03 PM PST 24
Finished Feb 21 02:51:15 PM PST 24
Peak memory 214636 kb
Host smart-c664ced8-26d1-4a13-9e8d-01c80fc6265f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108854912 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3108854912
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2711088774
Short name T400
Test name
Test status
Simulation time 171524003 ps
CPU time 4.25 seconds
Started Feb 21 02:50:55 PM PST 24
Finished Feb 21 02:50:59 PM PST 24
Peak memory 211084 kb
Host smart-4c3be93e-d7ee-42b5-bf3a-2c0118373044
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711088774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2711088774
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3667603282
Short name T430
Test name
Test status
Simulation time 3536225346 ps
CPU time 14.94 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:27 PM PST 24
Peak memory 211088 kb
Host smart-7ef55dfa-9855-4bfb-a9ec-ed20fd1ed7ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667603282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3667603282
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.98000448
Short name T367
Test name
Test status
Simulation time 671454753 ps
CPU time 6.37 seconds
Started Feb 21 02:51:10 PM PST 24
Finished Feb 21 02:51:17 PM PST 24
Peak memory 211020 kb
Host smart-8c088d1e-52df-4444-83b9-c19c67c2b4fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98000448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.98000448
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2239566350
Short name T93
Test name
Test status
Simulation time 92562104320 ps
CPU time 94.07 seconds
Started Feb 21 02:50:56 PM PST 24
Finished Feb 21 02:52:30 PM PST 24
Peak memory 211124 kb
Host smart-00689e3c-e093-478d-892e-14190a63f80f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239566350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2239566350
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.321939927
Short name T63
Test name
Test status
Simulation time 85450847 ps
CPU time 4.44 seconds
Started Feb 21 02:50:58 PM PST 24
Finished Feb 21 02:51:03 PM PST 24
Peak memory 211048 kb
Host smart-0880d992-061c-4075-8f5a-12998ea0c1d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321939927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.321939927
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1319564756
Short name T412
Test name
Test status
Simulation time 108097816 ps
CPU time 8.69 seconds
Started Feb 21 02:51:06 PM PST 24
Finished Feb 21 02:51:16 PM PST 24
Peak memory 214296 kb
Host smart-b7021af9-abc1-4fe3-85db-eda0614b31e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319564756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1319564756
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1157951978
Short name T130
Test name
Test status
Simulation time 1882916270 ps
CPU time 46.67 seconds
Started Feb 21 02:51:15 PM PST 24
Finished Feb 21 02:52:02 PM PST 24
Peak memory 211660 kb
Host smart-f7f1c0fd-c32c-495c-b313-db4360037f72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157951978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1157951978
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.213271772
Short name T442
Test name
Test status
Simulation time 7836695685 ps
CPU time 15.8 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:35 PM PST 24
Peak memory 211120 kb
Host smart-f1271b7c-eefb-43ca-9b95-a2ada2607a20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213271772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.213271772
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1500775314
Short name T416
Test name
Test status
Simulation time 2984733355 ps
CPU time 9.72 seconds
Started Feb 21 02:51:02 PM PST 24
Finished Feb 21 02:51:12 PM PST 24
Peak memory 211340 kb
Host smart-4e34c99d-6630-4571-9fe5-32dfa7a9967b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500775314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1500775314
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3846687990
Short name T393
Test name
Test status
Simulation time 438603679 ps
CPU time 7.33 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:20 PM PST 24
Peak memory 211068 kb
Host smart-d7390a6b-7da9-43bf-8355-28b4bb5f67f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846687990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3846687990
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1802865952
Short name T399
Test name
Test status
Simulation time 1987980413 ps
CPU time 15.89 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:51:47 PM PST 24
Peak memory 214536 kb
Host smart-66955720-7b5e-402a-a9ec-45dc5142be28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802865952 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1802865952
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1523126480
Short name T363
Test name
Test status
Simulation time 89929162 ps
CPU time 4.31 seconds
Started Feb 21 02:51:25 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 211096 kb
Host smart-4f7fecb6-984c-4323-82f0-757420ce0180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523126480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1523126480
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3978457203
Short name T355
Test name
Test status
Simulation time 1721303167 ps
CPU time 9.75 seconds
Started Feb 21 02:51:04 PM PST 24
Finished Feb 21 02:51:15 PM PST 24
Peak memory 210996 kb
Host smart-a644525a-9986-497f-bf2c-d9fd370284f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978457203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3978457203
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3939860299
Short name T359
Test name
Test status
Simulation time 1616457301 ps
CPU time 14.37 seconds
Started Feb 21 02:51:06 PM PST 24
Finished Feb 21 02:51:21 PM PST 24
Peak memory 210980 kb
Host smart-1a2a9d8f-bd8a-47f4-a886-66b4926d80f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939860299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3939860299
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4001196510
Short name T431
Test name
Test status
Simulation time 1068897486 ps
CPU time 26.15 seconds
Started Feb 21 02:51:01 PM PST 24
Finished Feb 21 02:51:27 PM PST 24
Peak memory 211060 kb
Host smart-9fa7c61e-26aa-444f-a0be-b6c74cf4e5a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001196510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4001196510
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4240864668
Short name T69
Test name
Test status
Simulation time 433324855 ps
CPU time 6.91 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:19 PM PST 24
Peak memory 211072 kb
Host smart-ccd16994-d88a-4471-91c6-9fcb87be9a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240864668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4240864668
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2546255029
Short name T397
Test name
Test status
Simulation time 6863466187 ps
CPU time 19.46 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 216404 kb
Host smart-1319bae1-c15e-4e1c-af49-c1eebf6a5b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546255029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2546255029
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.24398303
Short name T413
Test name
Test status
Simulation time 2220778412 ps
CPU time 49.05 seconds
Started Feb 21 02:51:01 PM PST 24
Finished Feb 21 02:51:51 PM PST 24
Peak memory 211564 kb
Host smart-ef1fd07a-11bb-48f5-801b-4f1a0da51296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24398303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg
_err.24398303
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3379756076
Short name T429
Test name
Test status
Simulation time 6262301847 ps
CPU time 16.92 seconds
Started Feb 21 02:51:13 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 215472 kb
Host smart-dad9c110-65bc-4895-b861-86a604628e98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379756076 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3379756076
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1083604736
Short name T88
Test name
Test status
Simulation time 131664628 ps
CPU time 5.16 seconds
Started Feb 21 02:51:25 PM PST 24
Finished Feb 21 02:51:32 PM PST 24
Peak memory 211104 kb
Host smart-f9c98126-b35d-432c-8616-cb15c633fa1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083604736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1083604736
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3486076058
Short name T94
Test name
Test status
Simulation time 2971036094 ps
CPU time 36.08 seconds
Started Feb 21 02:51:14 PM PST 24
Finished Feb 21 02:51:50 PM PST 24
Peak memory 211144 kb
Host smart-f2afd9a1-1ef6-4330-bfe9-bd95bfdcc198
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486076058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3486076058
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2483040138
Short name T391
Test name
Test status
Simulation time 575492110 ps
CPU time 8.71 seconds
Started Feb 21 02:51:04 PM PST 24
Finished Feb 21 02:51:13 PM PST 24
Peak memory 211076 kb
Host smart-57830f4d-33af-4776-b07f-78d81a21b204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483040138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2483040138
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3104032733
Short name T448
Test name
Test status
Simulation time 1851881543 ps
CPU time 18.01 seconds
Started Feb 21 02:51:18 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 215196 kb
Host smart-e54072b5-4420-40b0-ab09-0b37bc7f5d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104032733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3104032733
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4175329739
Short name T138
Test name
Test status
Simulation time 1071556270 ps
CPU time 74.48 seconds
Started Feb 21 02:51:12 PM PST 24
Finished Feb 21 02:52:28 PM PST 24
Peak memory 211844 kb
Host smart-00eccdb4-18db-46aa-95dd-02a9aefb83d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175329739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4175329739
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1595061070
Short name T354
Test name
Test status
Simulation time 1739148665 ps
CPU time 9.96 seconds
Started Feb 21 02:51:16 PM PST 24
Finished Feb 21 02:51:26 PM PST 24
Peak memory 214264 kb
Host smart-c9811d58-e7d2-45b8-b495-384d735c4f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595061070 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1595061070
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3130174101
Short name T89
Test name
Test status
Simulation time 2904442999 ps
CPU time 8.88 seconds
Started Feb 21 02:51:15 PM PST 24
Finished Feb 21 02:51:24 PM PST 24
Peak memory 211152 kb
Host smart-ca0b32e9-fbe6-41e0-8d0c-1bc4bf5b9850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130174101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3130174101
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.921187377
Short name T402
Test name
Test status
Simulation time 50631582154 ps
CPU time 96.21 seconds
Started Feb 21 02:51:30 PM PST 24
Finished Feb 21 02:53:06 PM PST 24
Peak memory 211084 kb
Host smart-2e9408b6-28cd-41e7-9bdf-8489d75f1748
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921187377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.921187377
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2688800399
Short name T381
Test name
Test status
Simulation time 2151490656 ps
CPU time 16.68 seconds
Started Feb 21 02:51:04 PM PST 24
Finished Feb 21 02:51:21 PM PST 24
Peak memory 211144 kb
Host smart-60401aff-4826-43a6-8421-6dedc8deb463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688800399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2688800399
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1511067761
Short name T392
Test name
Test status
Simulation time 320548718 ps
CPU time 7.29 seconds
Started Feb 21 02:51:44 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 213320 kb
Host smart-3e761cf3-7a44-4b6b-aa1f-9a85cadaab20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511067761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1511067761
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.32478730
Short name T445
Test name
Test status
Simulation time 3363498966 ps
CPU time 14.72 seconds
Started Feb 21 02:51:12 PM PST 24
Finished Feb 21 02:51:28 PM PST 24
Peak memory 216300 kb
Host smart-78c05168-d05f-4b4f-84e4-96a15dec4a7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32478730 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.32478730
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.444452686
Short name T411
Test name
Test status
Simulation time 1659121598 ps
CPU time 4.37 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 211052 kb
Host smart-b7fc4dcb-a3f0-4bd9-914f-3c34e22765da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444452686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.444452686
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.247690423
Short name T422
Test name
Test status
Simulation time 5586212908 ps
CPU time 17.12 seconds
Started Feb 21 02:51:17 PM PST 24
Finished Feb 21 02:51:34 PM PST 24
Peak memory 211104 kb
Host smart-a15e86ad-f3e1-4b92-bdd6-dab00a5414a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247690423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.247690423
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3728206844
Short name T443
Test name
Test status
Simulation time 898923757 ps
CPU time 11.99 seconds
Started Feb 21 02:51:04 PM PST 24
Finished Feb 21 02:51:16 PM PST 24
Peak memory 215196 kb
Host smart-11dc3dd3-cf21-4d01-9ede-3bbb376c5a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728206844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3728206844
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2082853984
Short name T446
Test name
Test status
Simulation time 92908007 ps
CPU time 4.58 seconds
Started Feb 21 02:51:09 PM PST 24
Finished Feb 21 02:51:15 PM PST 24
Peak memory 211636 kb
Host smart-2ff6cbb0-b5ea-48dc-831c-0805810045e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082853984 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2082853984
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1723120948
Short name T415
Test name
Test status
Simulation time 4642535329 ps
CPU time 10.92 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 211120 kb
Host smart-9ac98bf9-250a-4aec-b79e-97b2c6948ff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723120948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1723120948
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1066598667
Short name T82
Test name
Test status
Simulation time 3978979504 ps
CPU time 18.67 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 211144 kb
Host smart-1d997aea-570b-4f3c-b7c2-55ef950f5696
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066598667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1066598667
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1894968025
Short name T380
Test name
Test status
Simulation time 88917559 ps
CPU time 4.53 seconds
Started Feb 21 02:51:18 PM PST 24
Finished Feb 21 02:51:23 PM PST 24
Peak memory 211052 kb
Host smart-34e36846-822c-43e2-8367-ee37953af6a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894968025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1894968025
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1519754080
Short name T383
Test name
Test status
Simulation time 261166239 ps
CPU time 7.62 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:27 PM PST 24
Peak memory 215420 kb
Host smart-495926cf-6f8d-43fc-832d-11f8132bd200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519754080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1519754080
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3243396914
Short name T137
Test name
Test status
Simulation time 5117260300 ps
CPU time 71.75 seconds
Started Feb 21 02:51:16 PM PST 24
Finished Feb 21 02:52:28 PM PST 24
Peak memory 211124 kb
Host smart-31a78789-6726-41de-9276-15b1ac516925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243396914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3243396914
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.260705360
Short name T406
Test name
Test status
Simulation time 6432657832 ps
CPU time 13.94 seconds
Started Feb 21 02:51:11 PM PST 24
Finished Feb 21 02:51:26 PM PST 24
Peak memory 213016 kb
Host smart-90fc5f6b-9fc7-460b-a5fd-8eda13a09f00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260705360 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.260705360
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1704506301
Short name T71
Test name
Test status
Simulation time 530832198 ps
CPU time 7.38 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:27 PM PST 24
Peak memory 211092 kb
Host smart-c3a7d5a7-1c3c-4ac1-aeed-67b39d8d7f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704506301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1704506301
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3897596558
Short name T394
Test name
Test status
Simulation time 350142992 ps
CPU time 6.14 seconds
Started Feb 21 02:51:16 PM PST 24
Finished Feb 21 02:51:23 PM PST 24
Peak memory 211040 kb
Host smart-cbc9731a-0fd3-47ab-a341-a0a43bfc486f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897596558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3897596558
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1327219748
Short name T405
Test name
Test status
Simulation time 3133626470 ps
CPU time 18.42 seconds
Started Feb 21 02:51:19 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 215376 kb
Host smart-4c89a7b6-795a-41ec-b09d-aa747cf9f2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327219748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1327219748
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3424997972
Short name T395
Test name
Test status
Simulation time 4083321674 ps
CPU time 45.46 seconds
Started Feb 21 02:51:17 PM PST 24
Finished Feb 21 02:52:03 PM PST 24
Peak memory 211604 kb
Host smart-a9bf7d59-68c0-4d86-8e57-4c2f993f06b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424997972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3424997972
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3533837715
Short name T179
Test name
Test status
Simulation time 9824115393 ps
CPU time 7.42 seconds
Started Feb 21 12:55:21 PM PST 24
Finished Feb 21 12:55:30 PM PST 24
Peak memory 211340 kb
Host smart-5e46fe22-6912-498c-b277-7c5312318776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533837715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3533837715
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2853859996
Short name T212
Test name
Test status
Simulation time 5000201676 ps
CPU time 56.44 seconds
Started Feb 21 12:55:15 PM PST 24
Finished Feb 21 12:56:12 PM PST 24
Peak memory 240036 kb
Host smart-649f3551-d600-4ff4-83ce-03a99c2868fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853859996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2853859996
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.171050765
Short name T187
Test name
Test status
Simulation time 1058303320 ps
CPU time 7.58 seconds
Started Feb 21 12:55:16 PM PST 24
Finished Feb 21 12:55:25 PM PST 24
Peak memory 211188 kb
Host smart-71a53e8e-502b-4a34-a615-a83eeb198904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171050765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.171050765
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.997964396
Short name T165
Test name
Test status
Simulation time 786763281 ps
CPU time 9.81 seconds
Started Feb 21 12:55:17 PM PST 24
Finished Feb 21 12:55:27 PM PST 24
Peak memory 213240 kb
Host smart-fcfcf587-0fa5-42a3-b4d4-739f3836d183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997964396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.997964396
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2567390013
Short name T109
Test name
Test status
Simulation time 3683115370 ps
CPU time 15.5 seconds
Started Feb 21 12:55:16 PM PST 24
Finished Feb 21 12:55:33 PM PST 24
Peak memory 211112 kb
Host smart-9ea66b22-74ba-4f90-a29b-b714cdd9e773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567390013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2567390013
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.673804678
Short name T195
Test name
Test status
Simulation time 1197232776 ps
CPU time 6.63 seconds
Started Feb 21 12:55:20 PM PST 24
Finished Feb 21 12:55:27 PM PST 24
Peak memory 211224 kb
Host smart-430f1f57-f112-460f-9fb1-5f1669d830b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673804678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.673804678
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3727114657
Short name T329
Test name
Test status
Simulation time 30380490293 ps
CPU time 145.58 seconds
Started Feb 21 12:55:15 PM PST 24
Finished Feb 21 12:57:41 PM PST 24
Peak memory 240164 kb
Host smart-b50125f4-ff54-4ab9-993d-f2a3040550b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727114657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3727114657
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.595672000
Short name T348
Test name
Test status
Simulation time 168459172 ps
CPU time 9.35 seconds
Started Feb 21 12:55:14 PM PST 24
Finished Feb 21 12:55:24 PM PST 24
Peak memory 211724 kb
Host smart-55fd8ea4-5f40-430a-bb0f-b80df98c426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595672000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.595672000
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2014213859
Short name T254
Test name
Test status
Simulation time 489365407 ps
CPU time 8.35 seconds
Started Feb 21 12:55:14 PM PST 24
Finished Feb 21 12:55:23 PM PST 24
Peak memory 211232 kb
Host smart-9c198ee2-5500-4373-a07e-a7b87523529a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014213859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2014213859
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3951820735
Short name T39
Test name
Test status
Simulation time 2837928493 ps
CPU time 108.29 seconds
Started Feb 21 12:55:17 PM PST 24
Finished Feb 21 12:57:07 PM PST 24
Peak memory 237084 kb
Host smart-ef559645-6fff-4ab1-8246-d532dc28eed0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951820735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3951820735
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3498741492
Short name T243
Test name
Test status
Simulation time 785841145 ps
CPU time 14.43 seconds
Started Feb 21 12:55:14 PM PST 24
Finished Feb 21 12:55:29 PM PST 24
Peak memory 213136 kb
Host smart-60b678cb-cea8-4c68-bbdf-a6b7abc50a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498741492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3498741492
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2454477635
Short name T124
Test name
Test status
Simulation time 320071606 ps
CPU time 14.25 seconds
Started Feb 21 12:55:22 PM PST 24
Finished Feb 21 12:55:36 PM PST 24
Peak memory 213084 kb
Host smart-f03a37a2-2eda-46f6-be3e-2d1cb8e56a47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454477635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2454477635
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4038328071
Short name T163
Test name
Test status
Simulation time 5451407783 ps
CPU time 13.55 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:55:53 PM PST 24
Peak memory 211368 kb
Host smart-e5f06da9-9002-40d7-a73d-5d74ff36581a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038328071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4038328071
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3448464060
Short name T172
Test name
Test status
Simulation time 14477770221 ps
CPU time 35 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:56:13 PM PST 24
Peak memory 211388 kb
Host smart-d7d7e566-b1af-489f-8c22-621d53de0856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448464060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3448464060
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2172149611
Short name T169
Test name
Test status
Simulation time 4807134998 ps
CPU time 12.23 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:55:50 PM PST 24
Peak memory 211384 kb
Host smart-fc627735-8126-4045-8cda-2b380d16b180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172149611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2172149611
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1548463390
Short name T321
Test name
Test status
Simulation time 2419960899 ps
CPU time 25.68 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:56:04 PM PST 24
Peak memory 213344 kb
Host smart-448f0fd3-0471-46ba-946e-f4d390c75afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548463390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1548463390
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2977487768
Short name T123
Test name
Test status
Simulation time 16863310835 ps
CPU time 29.75 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:56:08 PM PST 24
Peak memory 214984 kb
Host smart-f210f4ba-f22a-4a09-af71-3f8e4a535336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977487768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2977487768
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1746465596
Short name T207
Test name
Test status
Simulation time 2035820778 ps
CPU time 16.54 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:56:00 PM PST 24
Peak memory 211180 kb
Host smart-bc304f85-493e-4409-be43-d4710cbcec91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746465596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1746465596
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.842309695
Short name T199
Test name
Test status
Simulation time 14250185657 ps
CPU time 215.48 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:59:14 PM PST 24
Peak memory 219716 kb
Host smart-7b15ad3b-8eb2-4e2d-bb24-baecb0e80996
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842309695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.842309695
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1745155705
Short name T150
Test name
Test status
Simulation time 4377799640 ps
CPU time 34.09 seconds
Started Feb 21 12:55:41 PM PST 24
Finished Feb 21 12:56:16 PM PST 24
Peak memory 212204 kb
Host smart-5c629de1-ab26-4bd5-a7b2-10f46c8a9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745155705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1745155705
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3086292081
Short name T114
Test name
Test status
Simulation time 185099115 ps
CPU time 6.66 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:55:50 PM PST 24
Peak memory 210600 kb
Host smart-14db5f74-6add-4fa4-b9b5-069c778511d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086292081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3086292081
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2792425662
Short name T338
Test name
Test status
Simulation time 2765397823 ps
CPU time 28.88 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:56:12 PM PST 24
Peak memory 213248 kb
Host smart-9ec54b9d-5f8d-4617-b2ca-26dc0c4ac891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792425662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2792425662
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.511578121
Short name T25
Test name
Test status
Simulation time 984600791 ps
CPU time 12.75 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:55:51 PM PST 24
Peak memory 211124 kb
Host smart-0aef5c56-b460-4f13-b47b-df6dd04719db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511578121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.511578121
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.614542221
Short name T178
Test name
Test status
Simulation time 592089603 ps
CPU time 6.26 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:55:50 PM PST 24
Peak memory 211248 kb
Host smart-bcaca9d0-f0dd-4dc0-9bbf-39f87fd37b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614542221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.614542221
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3647263847
Short name T27
Test name
Test status
Simulation time 1199208542 ps
CPU time 17 seconds
Started Feb 21 12:55:46 PM PST 24
Finished Feb 21 12:56:03 PM PST 24
Peak memory 211604 kb
Host smart-1df4ae5c-fa3f-4e2c-97a6-05674b7b8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647263847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3647263847
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2928218184
Short name T144
Test name
Test status
Simulation time 1533699171 ps
CPU time 8.15 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:49 PM PST 24
Peak memory 211196 kb
Host smart-ca077a8f-2372-44fc-a284-556068e9b09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928218184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2928218184
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2680953209
Short name T75
Test name
Test status
Simulation time 519968399 ps
CPU time 10.45 seconds
Started Feb 21 12:55:41 PM PST 24
Finished Feb 21 12:55:52 PM PST 24
Peak memory 213304 kb
Host smart-41b66e1a-b061-4f6c-91bd-566226c1f16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680953209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2680953209
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1747915836
Short name T295
Test name
Test status
Simulation time 1422291176 ps
CPU time 19.59 seconds
Started Feb 21 12:55:41 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 218956 kb
Host smart-b9846bd5-fff1-4edf-977a-22f929b51103
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747915836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1747915836
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2672597867
Short name T289
Test name
Test status
Simulation time 2011833183 ps
CPU time 15.35 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:56 PM PST 24
Peak memory 211120 kb
Host smart-9e8a5d50-e6d3-4fd6-bd51-423919889830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672597867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2672597867
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.428593838
Short name T252
Test name
Test status
Simulation time 9765356734 ps
CPU time 124.7 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:57:46 PM PST 24
Peak memory 236732 kb
Host smart-0fadf163-95af-4f99-b01d-b6a48b3e3a19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428593838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.428593838
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3182385006
Short name T29
Test name
Test status
Simulation time 4913697464 ps
CPU time 23.78 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 212188 kb
Host smart-c99cf6bb-54cd-452a-8139-538a783c6946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182385006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3182385006
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2864759767
Short name T185
Test name
Test status
Simulation time 1466719616 ps
CPU time 14.11 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 12:55:53 PM PST 24
Peak memory 211220 kb
Host smart-d8326620-95aa-48e1-8937-8314d28113b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864759767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2864759767
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3287671289
Short name T4
Test name
Test status
Simulation time 435904981 ps
CPU time 13.32 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:54 PM PST 24
Peak memory 212096 kb
Host smart-131ade35-7ac0-44a5-bf40-5753afb6b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287671289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3287671289
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.849856931
Short name T76
Test name
Test status
Simulation time 10449195684 ps
CPU time 58.55 seconds
Started Feb 21 12:55:46 PM PST 24
Finished Feb 21 12:56:45 PM PST 24
Peak memory 217276 kb
Host smart-cb28be2b-91cf-4849-b078-29d11d5541d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849856931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.849856931
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.306858009
Short name T100
Test name
Test status
Simulation time 458267861 ps
CPU time 7.25 seconds
Started Feb 21 12:55:36 PM PST 24
Finished Feb 21 12:55:44 PM PST 24
Peak memory 211216 kb
Host smart-af0b9f3e-f821-451a-9ab1-3840f25a4b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306858009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.306858009
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3518725158
Short name T251
Test name
Test status
Simulation time 32743494786 ps
CPU time 233.88 seconds
Started Feb 21 12:55:42 PM PST 24
Finished Feb 21 12:59:37 PM PST 24
Peak memory 212856 kb
Host smart-5c3dd656-2a52-47c8-b11d-f04ef3ce5bc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518725158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3518725158
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2212297625
Short name T1
Test name
Test status
Simulation time 1191375946 ps
CPU time 12.25 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:55:56 PM PST 24
Peak memory 211220 kb
Host smart-7ab4985a-9b1a-4b56-b24c-13fa7c361e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212297625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2212297625
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2607265560
Short name T105
Test name
Test status
Simulation time 5886637972 ps
CPU time 28.78 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:56:10 PM PST 24
Peak memory 213924 kb
Host smart-95228924-940d-4309-a914-7001e0dcd687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607265560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2607265560
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4252786124
Short name T113
Test name
Test status
Simulation time 2464433492 ps
CPU time 29.11 seconds
Started Feb 21 12:55:44 PM PST 24
Finished Feb 21 12:56:13 PM PST 24
Peak memory 215512 kb
Host smart-af3502fd-c2af-4993-835b-1b4ec24e57fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252786124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4252786124
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1589457867
Short name T292
Test name
Test status
Simulation time 33048952006 ps
CPU time 3087.46 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 01:47:05 PM PST 24
Peak memory 229072 kb
Host smart-06f5675a-4b59-4ffa-bd02-26294ed7d6b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589457867 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1589457867
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3158555128
Short name T151
Test name
Test status
Simulation time 5242739012 ps
CPU time 8.81 seconds
Started Feb 21 12:55:41 PM PST 24
Finished Feb 21 12:55:51 PM PST 24
Peak memory 211340 kb
Host smart-092e73ae-1027-4224-a0a1-09e8ff149c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158555128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3158555128
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2202396626
Short name T299
Test name
Test status
Simulation time 24003335605 ps
CPU time 254.86 seconds
Started Feb 21 12:55:41 PM PST 24
Finished Feb 21 12:59:56 PM PST 24
Peak memory 232732 kb
Host smart-41ccd1ba-6172-48c0-af2c-f4d1f6c8a084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202396626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2202396626
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1223358691
Short name T176
Test name
Test status
Simulation time 3879253137 ps
CPU time 30.77 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:56:15 PM PST 24
Peak memory 211864 kb
Host smart-ed57b4e2-6991-4d9b-9571-ba7cfdda8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223358691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1223358691
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1874339978
Short name T306
Test name
Test status
Simulation time 3809645553 ps
CPU time 11.19 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:55:55 PM PST 24
Peak memory 211344 kb
Host smart-2758b34b-de09-4a0c-8967-f84301c7ae89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874339978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1874339978
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3730052110
Short name T297
Test name
Test status
Simulation time 2785863485 ps
CPU time 28.88 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 12:56:09 PM PST 24
Peak memory 212088 kb
Host smart-661142d1-3bc4-487f-a3bd-302b1c02588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730052110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3730052110
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.549447889
Short name T103
Test name
Test status
Simulation time 9486709188 ps
CPU time 87.29 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:57:04 PM PST 24
Peak memory 219500 kb
Host smart-d27c34b0-004e-4a31-b886-1f623702abd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549447889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.549447889
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3448763260
Short name T221
Test name
Test status
Simulation time 3195071316 ps
CPU time 9.12 seconds
Started Feb 21 12:55:42 PM PST 24
Finished Feb 21 12:55:52 PM PST 24
Peak memory 211316 kb
Host smart-570c12b3-4ed9-4108-8d1e-3e9669a9dd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448763260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3448763260
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2308884483
Short name T48
Test name
Test status
Simulation time 171445244489 ps
CPU time 435.78 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 01:02:54 PM PST 24
Peak memory 224808 kb
Host smart-c7070bbb-ec35-45ff-891c-88b3b386bee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308884483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2308884483
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.942404791
Short name T248
Test name
Test status
Simulation time 4107654516 ps
CPU time 21.37 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:56:03 PM PST 24
Peak memory 212804 kb
Host smart-340d7432-df80-46c0-82e1-2ecc8dd63792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942404791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.942404791
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1032924704
Short name T265
Test name
Test status
Simulation time 4125508962 ps
CPU time 16.79 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:56:00 PM PST 24
Peak memory 211312 kb
Host smart-3248907f-273b-493f-a074-b5a0d0991602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032924704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1032924704
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3988518340
Short name T166
Test name
Test status
Simulation time 3232038619 ps
CPU time 20.27 seconds
Started Feb 21 12:55:42 PM PST 24
Finished Feb 21 12:56:03 PM PST 24
Peak memory 213228 kb
Host smart-ac30ba5d-b817-48f2-a258-58ee5f85f7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988518340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3988518340
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1228332554
Short name T208
Test name
Test status
Simulation time 8486374614 ps
CPU time 21.1 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 212232 kb
Host smart-8943febf-512a-43d7-b21f-38f7a4dcecae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228332554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1228332554
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1149266890
Short name T14
Test name
Test status
Simulation time 19596268579 ps
CPU time 734.98 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 01:07:54 PM PST 24
Peak memory 233992 kb
Host smart-2facc4f7-d06c-43b7-b730-75904790ace3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149266890 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1149266890
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2916117603
Short name T350
Test name
Test status
Simulation time 1026731877 ps
CPU time 7.47 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:48 PM PST 24
Peak memory 211204 kb
Host smart-e09800d0-059e-4d29-bed0-b91a4c14d035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916117603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2916117603
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3958126031
Short name T30
Test name
Test status
Simulation time 8407768077 ps
CPU time 91.29 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:57:09 PM PST 24
Peak memory 227368 kb
Host smart-d69237d2-7211-4873-a5c7-76d25eaa4cd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958126031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3958126031
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.621702713
Short name T99
Test name
Test status
Simulation time 5572233904 ps
CPU time 25.33 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 212168 kb
Host smart-37d065ca-11c1-4cff-a756-f50687c57c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621702713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.621702713
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1151678131
Short name T10
Test name
Test status
Simulation time 1894276127 ps
CPU time 15.83 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 12:55:56 PM PST 24
Peak memory 211188 kb
Host smart-5e1f2b2d-b4f1-4555-84dc-276806082a3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151678131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1151678131
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3071270347
Short name T19
Test name
Test status
Simulation time 431130592 ps
CPU time 12.62 seconds
Started Feb 21 12:55:42 PM PST 24
Finished Feb 21 12:55:55 PM PST 24
Peak memory 213432 kb
Host smart-e1e76e84-717b-422a-9eec-ec5f466df49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071270347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3071270347
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3630190504
Short name T327
Test name
Test status
Simulation time 9816269873 ps
CPU time 53.9 seconds
Started Feb 21 12:55:43 PM PST 24
Finished Feb 21 12:56:37 PM PST 24
Peak memory 213732 kb
Host smart-001d5d36-51cd-4364-8208-30ad114f81c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630190504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3630190504
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2812789115
Short name T55
Test name
Test status
Simulation time 575341209146 ps
CPU time 5658.34 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 02:29:59 PM PST 24
Peak memory 255024 kb
Host smart-0402f8ac-c365-4afd-892f-06a6f83057d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812789115 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2812789115
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2691928695
Short name T343
Test name
Test status
Simulation time 1307195196 ps
CPU time 6 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:47 PM PST 24
Peak memory 211172 kb
Host smart-18efcee2-fc68-445b-b5fc-9d79bc1ff088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691928695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2691928695
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2094775858
Short name T32
Test name
Test status
Simulation time 56842060762 ps
CPU time 549.96 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 01:04:48 PM PST 24
Peak memory 234028 kb
Host smart-4626e1f9-91ba-4ceb-b1bd-4aec92d32aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094775858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2094775858
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.494630471
Short name T5
Test name
Test status
Simulation time 2932135972 ps
CPU time 27.29 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 211888 kb
Host smart-2be2cd65-690a-4623-924d-d4fafb799975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494630471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.494630471
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1096971585
Short name T26
Test name
Test status
Simulation time 3860727195 ps
CPU time 11.37 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:52 PM PST 24
Peak memory 211376 kb
Host smart-e8470ee9-27c3-442b-9dd2-cb6e89354f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096971585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1096971585
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4068135393
Short name T186
Test name
Test status
Simulation time 1855150007 ps
CPU time 20.79 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 213300 kb
Host smart-5223b2c3-0260-4d8f-b571-d38295d4734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068135393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4068135393
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1552823056
Short name T346
Test name
Test status
Simulation time 7717899407 ps
CPU time 14.46 seconds
Started Feb 21 12:55:46 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 219540 kb
Host smart-55a04f31-8cc3-4e37-a8e6-6052ceb080d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552823056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1552823056
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.543331996
Short name T259
Test name
Test status
Simulation time 10528698401 ps
CPU time 15.16 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:11 PM PST 24
Peak memory 211388 kb
Host smart-9ea9c069-d9d9-466c-9bbb-896c54aaaceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543331996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.543331996
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1211015014
Short name T145
Test name
Test status
Simulation time 19865677819 ps
CPU time 33.05 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:28 PM PST 24
Peak memory 212668 kb
Host smart-8d55511c-cd79-463f-b8fb-d85a48358ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211015014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1211015014
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2065488432
Short name T263
Test name
Test status
Simulation time 5907415293 ps
CPU time 14.07 seconds
Started Feb 21 12:55:56 PM PST 24
Finished Feb 21 12:56:10 PM PST 24
Peak memory 211300 kb
Host smart-96942d3b-7751-4ff8-811f-bfebac48d5e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065488432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2065488432
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1855087303
Short name T332
Test name
Test status
Simulation time 5838853116 ps
CPU time 26.16 seconds
Started Feb 21 12:56:13 PM PST 24
Finished Feb 21 12:56:40 PM PST 24
Peak memory 213672 kb
Host smart-c7451eff-dd50-49e6-b7e8-9f049718cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855087303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1855087303
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3391965796
Short name T116
Test name
Test status
Simulation time 1472779408 ps
CPU time 39.21 seconds
Started Feb 21 12:55:46 PM PST 24
Finished Feb 21 12:56:26 PM PST 24
Peak memory 219296 kb
Host smart-a3bc968c-a131-474f-96e6-17e4398996ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391965796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3391965796
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.710589118
Short name T216
Test name
Test status
Simulation time 84148662251 ps
CPU time 778.21 seconds
Started Feb 21 12:55:56 PM PST 24
Finished Feb 21 01:08:55 PM PST 24
Peak memory 235928 kb
Host smart-fbfe136e-6c32-494f-86fc-17d2ab661dcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710589118 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.710589118
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4186645590
Short name T12
Test name
Test status
Simulation time 722047060 ps
CPU time 8.87 seconds
Started Feb 21 12:55:18 PM PST 24
Finished Feb 21 12:55:28 PM PST 24
Peak memory 211240 kb
Host smart-528a3a06-1f8d-47f3-a2c2-fa4d15077308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186645590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4186645590
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2495443186
Short name T294
Test name
Test status
Simulation time 20669707650 ps
CPU time 28.24 seconds
Started Feb 21 12:55:16 PM PST 24
Finished Feb 21 12:55:45 PM PST 24
Peak memory 212284 kb
Host smart-235e8b15-b6c8-41c7-a97c-27987b5e97a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495443186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2495443186
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1037925108
Short name T235
Test name
Test status
Simulation time 2047582786 ps
CPU time 16.55 seconds
Started Feb 21 12:55:14 PM PST 24
Finished Feb 21 12:55:31 PM PST 24
Peak memory 211232 kb
Host smart-31b56cbb-3778-4d52-b04a-ef3a93f5b97c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037925108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1037925108
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2862061842
Short name T40
Test name
Test status
Simulation time 2889716722 ps
CPU time 55.55 seconds
Started Feb 21 12:55:15 PM PST 24
Finished Feb 21 12:56:12 PM PST 24
Peak memory 232492 kb
Host smart-f64b8e00-1634-45f9-8130-d64fc7660eba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862061842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2862061842
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.635453192
Short name T118
Test name
Test status
Simulation time 2363876163 ps
CPU time 24.42 seconds
Started Feb 21 12:55:16 PM PST 24
Finished Feb 21 12:55:42 PM PST 24
Peak memory 213536 kb
Host smart-168d4d37-9b16-4669-8cff-6cb0ad9cb49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635453192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.635453192
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4118033646
Short name T323
Test name
Test status
Simulation time 11125567968 ps
CPU time 34.01 seconds
Started Feb 21 12:55:22 PM PST 24
Finished Feb 21 12:55:57 PM PST 24
Peak memory 219520 kb
Host smart-5e94312b-4505-4103-a770-3ccaa4be2bc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118033646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4118033646
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4240241474
Short name T298
Test name
Test status
Simulation time 1856609494 ps
CPU time 7.33 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:02 PM PST 24
Peak memory 211156 kb
Host smart-5908f8d3-6806-4cf7-9dfb-3c4ef3790781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240241474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4240241474
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3510922318
Short name T242
Test name
Test status
Simulation time 355436869 ps
CPU time 9.34 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:10 PM PST 24
Peak memory 211132 kb
Host smart-0d0e4b14-56a8-4c60-a417-57734d58f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510922318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3510922318
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3033975819
Short name T122
Test name
Test status
Simulation time 2030472651 ps
CPU time 16.77 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:18 PM PST 24
Peak memory 211180 kb
Host smart-4762e25c-87f0-4bd9-870c-93fde2738527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033975819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3033975819
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1875319896
Short name T285
Test name
Test status
Simulation time 850358245 ps
CPU time 10.17 seconds
Started Feb 21 12:55:49 PM PST 24
Finished Feb 21 12:56:00 PM PST 24
Peak memory 213324 kb
Host smart-f4edd7ac-2820-4396-99ae-71b5beeee7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875319896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1875319896
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3435406748
Short name T253
Test name
Test status
Simulation time 14441769990 ps
CPU time 32.93 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:27 PM PST 24
Peak memory 214620 kb
Host smart-43f81c47-0fea-4dfd-9504-2790daa6caf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435406748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3435406748
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3769889699
Short name T274
Test name
Test status
Simulation time 866492342 ps
CPU time 7.29 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:56:00 PM PST 24
Peak memory 211204 kb
Host smart-65dcf360-1d8e-4070-8bb8-4970cc47a3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769889699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3769889699
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1947566242
Short name T315
Test name
Test status
Simulation time 21104894700 ps
CPU time 241.02 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:59:55 PM PST 24
Peak memory 229536 kb
Host smart-5fe422aa-25d8-4ef2-aa7a-427f6c77ef7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947566242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1947566242
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3275792540
Short name T333
Test name
Test status
Simulation time 8064370152 ps
CPU time 32.9 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:27 PM PST 24
Peak memory 212300 kb
Host smart-610d5ca6-77da-494c-a84b-c4eacfc7c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275792540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3275792540
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1560445848
Short name T183
Test name
Test status
Simulation time 422790137 ps
CPU time 5.12 seconds
Started Feb 21 12:56:00 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 211208 kb
Host smart-fc82d3a9-3252-47c3-9458-f52f120b11e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560445848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1560445848
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3711541241
Short name T224
Test name
Test status
Simulation time 3883232272 ps
CPU time 38.35 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:32 PM PST 24
Peak memory 213540 kb
Host smart-96646334-573d-46fd-8762-b417519b1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711541241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3711541241
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.664206824
Short name T312
Test name
Test status
Simulation time 46826311844 ps
CPU time 61.87 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:56:56 PM PST 24
Peak memory 216216 kb
Host smart-da7d6f3c-2059-49a3-a6d5-de884ca8094b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664206824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.664206824
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2422064784
Short name T214
Test name
Test status
Simulation time 1493630894 ps
CPU time 6.66 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:08 PM PST 24
Peak memory 211196 kb
Host smart-a550035c-d95e-4887-8e5c-e463a9640660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422064784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2422064784
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.741608636
Short name T325
Test name
Test status
Simulation time 63330707713 ps
CPU time 257.18 seconds
Started Feb 21 12:55:50 PM PST 24
Finished Feb 21 01:00:07 PM PST 24
Peak memory 235200 kb
Host smart-eed5894a-9a24-4b9a-8c84-a64d2128d706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741608636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.741608636
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1789452030
Short name T175
Test name
Test status
Simulation time 2075683813 ps
CPU time 9.26 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:11 PM PST 24
Peak memory 210768 kb
Host smart-43c9dcda-d1c7-4c6c-aa0f-a39dace1a06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789452030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1789452030
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.954907598
Short name T156
Test name
Test status
Simulation time 5380743943 ps
CPU time 13.35 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:09 PM PST 24
Peak memory 211560 kb
Host smart-04c4557d-5fd0-4f9c-8224-d80571bb54fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954907598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.954907598
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2677068247
Short name T110
Test name
Test status
Simulation time 747844741 ps
CPU time 9.6 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:04 PM PST 24
Peak memory 213576 kb
Host smart-c9a108f0-e3d1-4205-8f08-ffd1a745ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677068247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2677068247
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.285985504
Short name T239
Test name
Test status
Simulation time 460998819 ps
CPU time 10.97 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:07 PM PST 24
Peak memory 211436 kb
Host smart-1f60a444-d294-413e-a27d-671a7232ef7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285985504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.285985504
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1257600773
Short name T284
Test name
Test status
Simulation time 11859401779 ps
CPU time 12.5 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:07 PM PST 24
Peak memory 211380 kb
Host smart-563ba550-704b-4d48-8c0a-f741d89d897d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257600773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1257600773
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3412574934
Short name T218
Test name
Test status
Simulation time 755013628 ps
CPU time 9.39 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:03 PM PST 24
Peak memory 211628 kb
Host smart-90c15721-5219-4a47-a953-bb8d406823f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412574934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3412574934
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2216080859
Short name T302
Test name
Test status
Simulation time 194222566 ps
CPU time 5.58 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:55:59 PM PST 24
Peak memory 211148 kb
Host smart-dd418d82-378e-4890-96c5-c351d509e792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2216080859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2216080859
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.721723841
Short name T171
Test name
Test status
Simulation time 198582561 ps
CPU time 10.48 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:06 PM PST 24
Peak memory 213172 kb
Host smart-8d63d400-bc84-48f3-85fc-303db984564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721723841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.721723841
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1581142708
Short name T245
Test name
Test status
Simulation time 11536426627 ps
CPU time 39.45 seconds
Started Feb 21 12:56:00 PM PST 24
Finished Feb 21 12:56:40 PM PST 24
Peak memory 214340 kb
Host smart-f3ef3a0e-12c1-492b-b2a3-2d434ec09a92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581142708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1581142708
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1016166021
Short name T198
Test name
Test status
Simulation time 33522790999 ps
CPU time 1393.77 seconds
Started Feb 21 12:55:51 PM PST 24
Finished Feb 21 01:19:05 PM PST 24
Peak memory 235436 kb
Host smart-eae8528d-3499-412c-baa9-f3e54a5e774f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016166021 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1016166021
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3814142122
Short name T237
Test name
Test status
Simulation time 1149582233 ps
CPU time 8.16 seconds
Started Feb 21 12:55:56 PM PST 24
Finished Feb 21 12:56:04 PM PST 24
Peak memory 211308 kb
Host smart-b6b1bae4-c2c2-4a2a-af31-e7ad91effb8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814142122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3814142122
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1010564563
Short name T287
Test name
Test status
Simulation time 31391857068 ps
CPU time 191.45 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:59:05 PM PST 24
Peak memory 228800 kb
Host smart-ec38ae25-6b5d-4e88-a8c6-2ecba0388381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010564563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1010564563
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1754669826
Short name T112
Test name
Test status
Simulation time 2891634405 ps
CPU time 22.03 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:17 PM PST 24
Peak memory 211740 kb
Host smart-bd78ac45-e46a-477e-becb-053730c8c2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754669826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1754669826
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3139765370
Short name T301
Test name
Test status
Simulation time 100737649 ps
CPU time 5.69 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 211292 kb
Host smart-838c40fe-972c-4b9e-ad63-db1e71078047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139765370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3139765370
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2894143828
Short name T98
Test name
Test status
Simulation time 387727630 ps
CPU time 9.98 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:56:03 PM PST 24
Peak memory 213312 kb
Host smart-2a45b7ec-ff46-471d-9f24-5d3f95dc57f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894143828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2894143828
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2895778283
Short name T339
Test name
Test status
Simulation time 3152287832 ps
CPU time 12.74 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:07 PM PST 24
Peak memory 211212 kb
Host smart-d179852f-eb3e-43db-9903-f30f73f13631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895778283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2895778283
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3652568846
Short name T257
Test name
Test status
Simulation time 1804824964 ps
CPU time 9.88 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 211436 kb
Host smart-0a878432-fce0-4609-8353-5615035cc9f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652568846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3652568846
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3662045050
Short name T336
Test name
Test status
Simulation time 170576565 ps
CPU time 9.8 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:05 PM PST 24
Peak memory 211728 kb
Host smart-3c84c8fb-9a93-475b-9c32-592680045781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662045050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3662045050
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2992980962
Short name T22
Test name
Test status
Simulation time 9495120906 ps
CPU time 17.04 seconds
Started Feb 21 12:55:56 PM PST 24
Finished Feb 21 12:56:13 PM PST 24
Peak memory 211440 kb
Host smart-4eef11c4-7b53-4955-9b6d-94aa1449fe33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992980962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2992980962
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1741533210
Short name T288
Test name
Test status
Simulation time 3659940470 ps
CPU time 30.25 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 212992 kb
Host smart-05e86e2d-a8fb-433b-9ec0-780e2e41a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741533210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1741533210
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4279604150
Short name T258
Test name
Test status
Simulation time 31168079903 ps
CPU time 91.5 seconds
Started Feb 21 12:55:46 PM PST 24
Finished Feb 21 12:57:18 PM PST 24
Peak memory 219484 kb
Host smart-120118ea-fcea-41cd-91ad-8718efd18421
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279604150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4279604150
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1230699100
Short name T193
Test name
Test status
Simulation time 172409661 ps
CPU time 5.66 seconds
Started Feb 21 12:55:49 PM PST 24
Finished Feb 21 12:55:55 PM PST 24
Peak memory 211228 kb
Host smart-e5a74644-b55e-4c85-8aa7-20ef69457691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230699100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1230699100
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.409640111
Short name T303
Test name
Test status
Simulation time 86615894313 ps
CPU time 146.84 seconds
Started Feb 21 12:56:03 PM PST 24
Finished Feb 21 12:58:30 PM PST 24
Peak memory 212136 kb
Host smart-d3ad5241-2d47-4b3d-a152-569dc08a6bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409640111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.409640111
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4166788707
Short name T8
Test name
Test status
Simulation time 4187082286 ps
CPU time 21.51 seconds
Started Feb 21 12:55:49 PM PST 24
Finished Feb 21 12:56:12 PM PST 24
Peak memory 212880 kb
Host smart-358c08c2-9a2b-4d2d-b929-03a9a04f8d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166788707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4166788707
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1046114863
Short name T41
Test name
Test status
Simulation time 10168118367 ps
CPU time 17.26 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:13 PM PST 24
Peak memory 211376 kb
Host smart-5d609811-56fd-41da-b329-a164d19aa1d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046114863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1046114863
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2523496294
Short name T278
Test name
Test status
Simulation time 5622083109 ps
CPU time 25.08 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:36 PM PST 24
Peak memory 214004 kb
Host smart-466730e7-bf9e-47ba-84c7-0480f3fa657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523496294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2523496294
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3453358285
Short name T18
Test name
Test status
Simulation time 2472119995 ps
CPU time 14.75 seconds
Started Feb 21 12:55:48 PM PST 24
Finished Feb 21 12:56:03 PM PST 24
Peak memory 214620 kb
Host smart-a860f88c-c3ac-4a82-8487-60ab5dd40b9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453358285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3453358285
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2702829751
Short name T155
Test name
Test status
Simulation time 131902286 ps
CPU time 3.99 seconds
Started Feb 21 12:55:56 PM PST 24
Finished Feb 21 12:56:00 PM PST 24
Peak memory 211224 kb
Host smart-26bc632c-4909-4bcb-af69-7967b5838532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702829751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2702829751
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.622125479
Short name T313
Test name
Test status
Simulation time 32804506494 ps
CPU time 33.77 seconds
Started Feb 21 12:56:10 PM PST 24
Finished Feb 21 12:56:44 PM PST 24
Peak memory 213976 kb
Host smart-77c1c9bf-21ae-487f-9d8c-249649208d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622125479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.622125479
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2764204694
Short name T349
Test name
Test status
Simulation time 93683404 ps
CPU time 5.3 seconds
Started Feb 21 12:56:07 PM PST 24
Finished Feb 21 12:56:13 PM PST 24
Peak memory 211232 kb
Host smart-00510474-9d3f-4ec1-8458-3fa72b8625fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764204694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2764204694
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3475279161
Short name T223
Test name
Test status
Simulation time 5152605281 ps
CPU time 32.05 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:43 PM PST 24
Peak memory 214044 kb
Host smart-9922a6d5-3ad2-4f96-840b-f06793d65504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475279161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3475279161
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2434559961
Short name T204
Test name
Test status
Simulation time 283757356 ps
CPU time 11.67 seconds
Started Feb 21 12:56:02 PM PST 24
Finished Feb 21 12:56:14 PM PST 24
Peak memory 214472 kb
Host smart-1b4f267c-ca5b-4597-8f2f-8efb1729adcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434559961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2434559961
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3727856500
Short name T308
Test name
Test status
Simulation time 64921057769 ps
CPU time 193.17 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:59:14 PM PST 24
Peak memory 219676 kb
Host smart-92683b8e-ed38-4ef6-97ba-7e9eab5aa399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727856500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3727856500
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3384665482
Short name T43
Test name
Test status
Simulation time 28519865280 ps
CPU time 26.68 seconds
Started Feb 21 12:55:55 PM PST 24
Finished Feb 21 12:56:22 PM PST 24
Peak memory 212108 kb
Host smart-20637277-ba42-476d-b665-c10bdbc617ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384665482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3384665482
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.249861803
Short name T205
Test name
Test status
Simulation time 4656402174 ps
CPU time 15.28 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:10 PM PST 24
Peak memory 211372 kb
Host smart-1c8e6885-e7cf-4296-8da6-e7693ba6995f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249861803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.249861803
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.449604135
Short name T44
Test name
Test status
Simulation time 5594266576 ps
CPU time 17.44 seconds
Started Feb 21 12:55:50 PM PST 24
Finished Feb 21 12:56:07 PM PST 24
Peak memory 212496 kb
Host smart-46167f53-1ee0-4eb0-b27b-bdf2dbc1e4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449604135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.449604135
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1446286985
Short name T158
Test name
Test status
Simulation time 4108596152 ps
CPU time 36.43 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:38 PM PST 24
Peak memory 218992 kb
Host smart-3e9521bf-c776-4b9a-8079-c9912dea1e00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446286985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1446286985
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.655954840
Short name T53
Test name
Test status
Simulation time 183421795752 ps
CPU time 1916.39 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 01:28:08 PM PST 24
Peak memory 242076 kb
Host smart-6e4d5a31-9bd2-41ee-becd-e84704e62466
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655954840 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.655954840
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.104545820
Short name T190
Test name
Test status
Simulation time 6504667256 ps
CPU time 13.8 seconds
Started Feb 21 12:56:10 PM PST 24
Finished Feb 21 12:56:25 PM PST 24
Peak memory 211584 kb
Host smart-db199c79-b915-46c5-9149-67632fef40ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104545820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.104545820
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.98208002
Short name T230
Test name
Test status
Simulation time 8155957505 ps
CPU time 126.87 seconds
Started Feb 21 12:55:49 PM PST 24
Finished Feb 21 12:57:57 PM PST 24
Peak memory 220912 kb
Host smart-a712bab1-0015-4f41-afed-1f6d4d145d2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98208002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_co
rrupt_sig_fatal_chk.98208002
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.360598869
Short name T191
Test name
Test status
Simulation time 7142601440 ps
CPU time 23.64 seconds
Started Feb 21 12:56:04 PM PST 24
Finished Feb 21 12:56:28 PM PST 24
Peak memory 211960 kb
Host smart-2231ebc3-c525-480f-9980-2fbd298d2a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360598869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.360598869
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3004444673
Short name T250
Test name
Test status
Simulation time 100745388 ps
CPU time 5.7 seconds
Started Feb 21 12:55:49 PM PST 24
Finished Feb 21 12:55:55 PM PST 24
Peak memory 211220 kb
Host smart-2f290d31-6409-48b5-8569-c19c6967128c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004444673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3004444673
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2706551820
Short name T328
Test name
Test status
Simulation time 6865352549 ps
CPU time 33.35 seconds
Started Feb 21 12:55:49 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 214056 kb
Host smart-fb917210-4e6b-4e0d-982c-0c82d9972bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706551820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2706551820
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1601970932
Short name T77
Test name
Test status
Simulation time 1222020485 ps
CPU time 15.05 seconds
Started Feb 21 12:55:54 PM PST 24
Finished Feb 21 12:56:09 PM PST 24
Peak memory 211980 kb
Host smart-ad0fdd60-53d1-4fa6-b049-4660c6ebb384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601970932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1601970932
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.283569691
Short name T229
Test name
Test status
Simulation time 879217674 ps
CPU time 9.94 seconds
Started Feb 21 12:55:18 PM PST 24
Finished Feb 21 12:55:29 PM PST 24
Peak memory 211252 kb
Host smart-903b0d40-312e-4b7a-8737-4a49d708ff6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283569691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.283569691
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3657604776
Short name T322
Test name
Test status
Simulation time 4635675429 ps
CPU time 30.62 seconds
Started Feb 21 12:55:16 PM PST 24
Finished Feb 21 12:55:47 PM PST 24
Peak memory 212004 kb
Host smart-9425f588-a903-4631-be29-4d6aa0890451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657604776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3657604776
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2597298572
Short name T271
Test name
Test status
Simulation time 95569030 ps
CPU time 5.4 seconds
Started Feb 21 12:55:16 PM PST 24
Finished Feb 21 12:55:22 PM PST 24
Peak memory 211196 kb
Host smart-8ec5029e-3820-48ac-87d1-96d511248926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597298572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2597298572
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1234362323
Short name T35
Test name
Test status
Simulation time 197727895 ps
CPU time 99.36 seconds
Started Feb 21 12:55:15 PM PST 24
Finished Feb 21 12:56:55 PM PST 24
Peak memory 231660 kb
Host smart-1913b082-b6e5-44b3-8863-9c74c336191e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234362323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1234362323
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2451483067
Short name T277
Test name
Test status
Simulation time 8425299144 ps
CPU time 34.04 seconds
Started Feb 21 12:55:22 PM PST 24
Finished Feb 21 12:55:56 PM PST 24
Peak memory 213728 kb
Host smart-50650b16-6913-4acb-849e-c1eb4735b0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451483067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2451483067
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2288483260
Short name T177
Test name
Test status
Simulation time 1002035559 ps
CPU time 14.07 seconds
Started Feb 21 12:55:17 PM PST 24
Finished Feb 21 12:55:32 PM PST 24
Peak memory 214880 kb
Host smart-39ee491b-5d4f-4f94-8c78-fb9a17e35ba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288483260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2288483260
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.706296175
Short name T247
Test name
Test status
Simulation time 174961647 ps
CPU time 4.25 seconds
Started Feb 21 12:56:02 PM PST 24
Finished Feb 21 12:56:06 PM PST 24
Peak memory 211240 kb
Host smart-2cb5c804-150f-4077-be16-094938ea5406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706296175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.706296175
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.543016756
Short name T293
Test name
Test status
Simulation time 17793159626 ps
CPU time 33.04 seconds
Started Feb 21 12:55:58 PM PST 24
Finished Feb 21 12:56:31 PM PST 24
Peak memory 212124 kb
Host smart-8bdf219e-4f37-4aa2-85ac-1d98b97d881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543016756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.543016756
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3599155175
Short name T331
Test name
Test status
Simulation time 10198498604 ps
CPU time 16.85 seconds
Started Feb 21 12:56:04 PM PST 24
Finished Feb 21 12:56:21 PM PST 24
Peak memory 210920 kb
Host smart-3ac5847c-24df-4f6d-b693-12745c815f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599155175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3599155175
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3320796840
Short name T181
Test name
Test status
Simulation time 3001153013 ps
CPU time 16.47 seconds
Started Feb 21 12:56:04 PM PST 24
Finished Feb 21 12:56:21 PM PST 24
Peak memory 211976 kb
Host smart-c80f4c42-6a7c-4cfd-a057-0c688d9084a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320796840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3320796840
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2564582297
Short name T79
Test name
Test status
Simulation time 5968200375 ps
CPU time 39.47 seconds
Started Feb 21 12:55:53 PM PST 24
Finished Feb 21 12:56:33 PM PST 24
Peak memory 216424 kb
Host smart-ba916e19-87cc-47c1-b9ce-92721845107d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564582297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2564582297
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.745491482
Short name T54
Test name
Test status
Simulation time 58785111848 ps
CPU time 6633.29 seconds
Started Feb 21 12:56:03 PM PST 24
Finished Feb 21 02:46:37 PM PST 24
Peak memory 229704 kb
Host smart-05ecade2-e71a-4f60-b276-54ddda97e4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745491482 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.745491482
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1704293478
Short name T244
Test name
Test status
Simulation time 171894931 ps
CPU time 4.15 seconds
Started Feb 21 12:56:02 PM PST 24
Finished Feb 21 12:56:06 PM PST 24
Peak memory 211220 kb
Host smart-7dc636f4-dada-44c4-b77a-4ccb95f8159a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704293478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1704293478
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.257644705
Short name T200
Test name
Test status
Simulation time 27098119633 ps
CPU time 260.02 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 01:00:22 PM PST 24
Peak memory 228276 kb
Host smart-2598f0e7-9a94-4fdb-a9d0-a74241cc3480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257644705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.257644705
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2897682136
Short name T189
Test name
Test status
Simulation time 3977516458 ps
CPU time 15.76 seconds
Started Feb 21 12:56:00 PM PST 24
Finished Feb 21 12:56:16 PM PST 24
Peak memory 211728 kb
Host smart-d10e84af-63f6-45cd-a2af-7bfc5d7726b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897682136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2897682136
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.476352711
Short name T143
Test name
Test status
Simulation time 1960251712 ps
CPU time 16.24 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:27 PM PST 24
Peak memory 211236 kb
Host smart-f1b74b0c-c24f-47dd-af6c-002733daefb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476352711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.476352711
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2151061496
Short name T203
Test name
Test status
Simulation time 6432786164 ps
CPU time 35.62 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:47 PM PST 24
Peak memory 214132 kb
Host smart-b493b894-c061-413b-ab08-b213e61f6d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151061496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2151061496
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.761087008
Short name T213
Test name
Test status
Simulation time 1305194607 ps
CPU time 42.51 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:54 PM PST 24
Peak memory 219192 kb
Host smart-d4d24305-1d9b-4ea9-b359-72e10c865428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761087008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.761087008
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2227287618
Short name T196
Test name
Test status
Simulation time 89733233 ps
CPU time 4.33 seconds
Started Feb 21 12:56:10 PM PST 24
Finished Feb 21 12:56:15 PM PST 24
Peak memory 211432 kb
Host smart-867c7ace-d97c-4074-9115-0b2762a864ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227287618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2227287618
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.598348256
Short name T50
Test name
Test status
Simulation time 173303910297 ps
CPU time 384.96 seconds
Started Feb 21 12:56:03 PM PST 24
Finished Feb 21 01:02:28 PM PST 24
Peak memory 229580 kb
Host smart-e8d6d4d0-912c-4ae1-9946-d80356910906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598348256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.598348256
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1538884172
Short name T24
Test name
Test status
Simulation time 22658026564 ps
CPU time 26.74 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:36 PM PST 24
Peak memory 212120 kb
Host smart-3b6572a0-9222-45b8-bb5e-9103f8d5fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538884172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1538884172
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3099948100
Short name T311
Test name
Test status
Simulation time 5314840709 ps
CPU time 13.3 seconds
Started Feb 21 12:55:51 PM PST 24
Finished Feb 21 12:56:04 PM PST 24
Peak memory 211272 kb
Host smart-0e2cd13b-d63e-4175-a965-19577564f36b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099948100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3099948100
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3233635820
Short name T162
Test name
Test status
Simulation time 366197214 ps
CPU time 10.32 seconds
Started Feb 21 12:56:04 PM PST 24
Finished Feb 21 12:56:15 PM PST 24
Peak memory 213424 kb
Host smart-183a2541-7d6b-41eb-8c42-e5fcbac5dbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233635820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3233635820
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1118296379
Short name T219
Test name
Test status
Simulation time 1946117395 ps
CPU time 27.93 seconds
Started Feb 21 12:56:04 PM PST 24
Finished Feb 21 12:56:32 PM PST 24
Peak memory 213400 kb
Host smart-65961356-15fa-4b10-9113-db66502feb3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118296379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1118296379
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.235910723
Short name T64
Test name
Test status
Simulation time 8889884755 ps
CPU time 12.98 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:22 PM PST 24
Peak memory 211384 kb
Host smart-f77ba8ac-6c64-4ea9-96ee-9000b62c30e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235910723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.235910723
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.243340282
Short name T347
Test name
Test status
Simulation time 2431572486 ps
CPU time 143.51 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:58:33 PM PST 24
Peak memory 237048 kb
Host smart-843f9faf-ce27-485d-9448-465e30a8d41c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243340282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.243340282
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2741505984
Short name T326
Test name
Test status
Simulation time 7188223887 ps
CPU time 20.17 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:40 PM PST 24
Peak memory 212472 kb
Host smart-f75030d3-d970-44a9-aa74-0092813c3c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741505984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2741505984
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4217367307
Short name T300
Test name
Test status
Simulation time 1475840785 ps
CPU time 13.74 seconds
Started Feb 21 12:55:59 PM PST 24
Finished Feb 21 12:56:13 PM PST 24
Peak memory 211196 kb
Host smart-e82e99c1-f455-4a17-b064-fff643ad86a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217367307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4217367307
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.442584621
Short name T283
Test name
Test status
Simulation time 8924193089 ps
CPU time 25.02 seconds
Started Feb 21 12:56:10 PM PST 24
Finished Feb 21 12:56:35 PM PST 24
Peak memory 213652 kb
Host smart-5c48053f-78de-4dad-835b-7eaeae2cf1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442584621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.442584621
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3140175191
Short name T256
Test name
Test status
Simulation time 2136179044 ps
CPU time 24.54 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 12:56:39 PM PST 24
Peak memory 213276 kb
Host smart-94b55a83-cb29-48b4-aee3-8c7aeb4929e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140175191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3140175191
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1519325208
Short name T45
Test name
Test status
Simulation time 101270898883 ps
CPU time 2736.72 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 01:41:52 PM PST 24
Peak memory 235960 kb
Host smart-f6f1d87e-267d-4ede-bbef-32da316ab687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519325208 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1519325208
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2070873621
Short name T197
Test name
Test status
Simulation time 7653758881 ps
CPU time 15.86 seconds
Started Feb 21 12:56:05 PM PST 24
Finished Feb 21 12:56:22 PM PST 24
Peak memory 211380 kb
Host smart-f53a237f-0606-4397-8d4f-31b5dc08a344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070873621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2070873621
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3854087332
Short name T47
Test name
Test status
Simulation time 2050431788 ps
CPU time 14.77 seconds
Started Feb 21 12:56:10 PM PST 24
Finished Feb 21 12:56:25 PM PST 24
Peak memory 211880 kb
Host smart-2ea454a4-ffb9-4338-81c7-da62c8cde63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854087332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3854087332
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3734996167
Short name T316
Test name
Test status
Simulation time 380421412 ps
CPU time 5.71 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:56:29 PM PST 24
Peak memory 211120 kb
Host smart-7bdf5e31-7b59-4438-b6cd-002c5904fd40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734996167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3734996167
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.336214358
Short name T222
Test name
Test status
Simulation time 22710100973 ps
CPU time 32.97 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:42 PM PST 24
Peak memory 214000 kb
Host smart-c68d6c85-3c26-4903-b524-9c18ccd78c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336214358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.336214358
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3886857310
Short name T104
Test name
Test status
Simulation time 3045454737 ps
CPU time 45.94 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:57:08 PM PST 24
Peak memory 215112 kb
Host smart-3f5c1f5c-3d0e-4efe-a32f-dd2a3386bd49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886857310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3886857310
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2856386278
Short name T107
Test name
Test status
Simulation time 44572366253 ps
CPU time 1812.61 seconds
Started Feb 21 12:56:06 PM PST 24
Finished Feb 21 01:26:19 PM PST 24
Peak memory 241840 kb
Host smart-cebdd411-86c8-4783-a2e6-34cf680bdf40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856386278 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2856386278
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.845606347
Short name T276
Test name
Test status
Simulation time 881632769 ps
CPU time 7.36 seconds
Started Feb 21 12:56:05 PM PST 24
Finished Feb 21 12:56:14 PM PST 24
Peak memory 211216 kb
Host smart-9bf146da-5dc0-4e0f-be31-058ee2977217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845606347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.845606347
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3150786569
Short name T52
Test name
Test status
Simulation time 18944721527 ps
CPU time 197.56 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:59:39 PM PST 24
Peak memory 220908 kb
Host smart-e2efa164-96b7-411a-9fe2-fe6dc6e23c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150786569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3150786569
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1673200098
Short name T227
Test name
Test status
Simulation time 1642191882 ps
CPU time 11.93 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:32 PM PST 24
Peak memory 211760 kb
Host smart-ec085c20-1561-435c-bdaa-3a28e4000139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673200098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1673200098
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3321007465
Short name T269
Test name
Test status
Simulation time 2227327424 ps
CPU time 8.61 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:28 PM PST 24
Peak memory 211320 kb
Host smart-36cbd089-b179-429c-8c33-1b388e49995a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321007465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3321007465
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3887776190
Short name T344
Test name
Test status
Simulation time 1937468558 ps
CPU time 21.44 seconds
Started Feb 21 12:56:06 PM PST 24
Finished Feb 21 12:56:28 PM PST 24
Peak memory 213248 kb
Host smart-fa636b5a-97e5-4d54-a0e1-d22010821164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887776190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3887776190
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1465741368
Short name T334
Test name
Test status
Simulation time 534287515 ps
CPU time 7.87 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:56:31 PM PST 24
Peak memory 211224 kb
Host smart-95412e0b-5108-4e15-aa84-471aa168970e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465741368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1465741368
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.671911953
Short name T164
Test name
Test status
Simulation time 4253137267 ps
CPU time 33.26 seconds
Started Feb 21 12:56:12 PM PST 24
Finished Feb 21 12:56:46 PM PST 24
Peak memory 213240 kb
Host smart-bbea1c4d-2377-44bb-a23d-543707827d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671911953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.671911953
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3513757571
Short name T184
Test name
Test status
Simulation time 3401017925 ps
CPU time 14.75 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:24 PM PST 24
Peak memory 211348 kb
Host smart-79483eef-1c10-488a-8061-7669236e38da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513757571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3513757571
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2414415647
Short name T266
Test name
Test status
Simulation time 6200956595 ps
CPU time 18.95 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 12:56:34 PM PST 24
Peak memory 214416 kb
Host smart-db5e98b2-7a8c-469d-a969-82c503f83783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414415647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2414415647
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.303725307
Short name T241
Test name
Test status
Simulation time 879938359 ps
CPU time 25.87 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:47 PM PST 24
Peak memory 214812 kb
Host smart-fd8e4dfe-9fc6-42d5-91ac-141cf4f46adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303725307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.303725307
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1757458857
Short name T57
Test name
Test status
Simulation time 199205372858 ps
CPU time 8450.32 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 03:17:13 PM PST 24
Peak memory 237216 kb
Host smart-15c21c92-a096-4075-bafd-bf9d876ae13a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757458857 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1757458857
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.972633796
Short name T149
Test name
Test status
Simulation time 3612859367 ps
CPU time 9.55 seconds
Started Feb 21 12:56:03 PM PST 24
Finished Feb 21 12:56:13 PM PST 24
Peak memory 211360 kb
Host smart-a644eacd-2107-48f7-bef1-60f270b67d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972633796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.972633796
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2573692240
Short name T273
Test name
Test status
Simulation time 23154308982 ps
CPU time 253.64 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 01:00:35 PM PST 24
Peak memory 238060 kb
Host smart-369fe86e-997d-422b-ba18-2050f15b609f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573692240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2573692240
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1019433156
Short name T23
Test name
Test status
Simulation time 5050773509 ps
CPU time 32.21 seconds
Started Feb 21 12:56:18 PM PST 24
Finished Feb 21 12:56:51 PM PST 24
Peak memory 212312 kb
Host smart-d2d6e084-ee39-42ed-a33f-74082591eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019433156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1019433156
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3601957021
Short name T101
Test name
Test status
Simulation time 257724345 ps
CPU time 5.76 seconds
Started Feb 21 12:56:18 PM PST 24
Finished Feb 21 12:56:24 PM PST 24
Peak memory 211268 kb
Host smart-5e56f3e4-ac50-49db-acd6-e31c709ccc33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3601957021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3601957021
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.925085425
Short name T261
Test name
Test status
Simulation time 50096897353 ps
CPU time 38.04 seconds
Started Feb 21 12:56:07 PM PST 24
Finished Feb 21 12:56:46 PM PST 24
Peak memory 213756 kb
Host smart-cc6036ec-4566-4cc6-bc78-32c2ed216549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925085425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.925085425
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3902706013
Short name T167
Test name
Test status
Simulation time 5772525703 ps
CPU time 43.06 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:57:05 PM PST 24
Peak memory 217224 kb
Host smart-b9101dfa-c568-4e46-b8f3-bb96846b47e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902706013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3902706013
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3079112186
Short name T17
Test name
Test status
Simulation time 64983847308 ps
CPU time 1990.12 seconds
Started Feb 21 12:56:07 PM PST 24
Finished Feb 21 01:29:18 PM PST 24
Peak memory 235964 kb
Host smart-441db1a5-1e5b-424a-ba7b-754c83d37fe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079112186 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3079112186
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4171892104
Short name T290
Test name
Test status
Simulation time 2100153328 ps
CPU time 8.53 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:10 PM PST 24
Peak memory 211208 kb
Host smart-0eed70a4-ef44-476b-ae5a-f89b8c8a400b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171892104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4171892104
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2874098221
Short name T304
Test name
Test status
Simulation time 7525769404 ps
CPU time 15.42 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:17 PM PST 24
Peak memory 212456 kb
Host smart-279fe1d7-9280-4d3d-9b16-e20d3f44354d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874098221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2874098221
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3797173987
Short name T142
Test name
Test status
Simulation time 33626518708 ps
CPU time 17.21 seconds
Started Feb 21 12:56:03 PM PST 24
Finished Feb 21 12:56:21 PM PST 24
Peak memory 211360 kb
Host smart-f09147d4-76a2-4dae-bce8-0f430b0f8998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797173987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3797173987
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3416008576
Short name T307
Test name
Test status
Simulation time 13701517725 ps
CPU time 33.35 seconds
Started Feb 21 12:56:02 PM PST 24
Finished Feb 21 12:56:36 PM PST 24
Peak memory 214028 kb
Host smart-0deb892b-4bc2-4c41-9972-e38a1bb3d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416008576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3416008576
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3230128486
Short name T139
Test name
Test status
Simulation time 2691998555 ps
CPU time 35.87 seconds
Started Feb 21 12:56:03 PM PST 24
Finished Feb 21 12:56:39 PM PST 24
Peak memory 214728 kb
Host smart-64a8d9f3-ef89-45ea-b3d5-d020d321bfcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230128486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3230128486
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.291116483
Short name T206
Test name
Test status
Simulation time 1632653803 ps
CPU time 14.13 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:26 PM PST 24
Peak memory 211220 kb
Host smart-bf123cc3-578a-4b6b-8057-c904ff7c0856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291116483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.291116483
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3527202639
Short name T97
Test name
Test status
Simulation time 192460172287 ps
CPU time 321.97 seconds
Started Feb 21 12:56:13 PM PST 24
Finished Feb 21 01:01:36 PM PST 24
Peak memory 233936 kb
Host smart-1c35e775-5746-4291-9427-4694c240e9cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527202639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3527202639
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.577704085
Short name T281
Test name
Test status
Simulation time 417634486 ps
CPU time 9.39 seconds
Started Feb 21 12:56:13 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 211836 kb
Host smart-6147aad2-f536-4f72-bbac-d9a067f757af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577704085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.577704085
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.592118262
Short name T317
Test name
Test status
Simulation time 20111872823 ps
CPU time 12.37 seconds
Started Feb 21 12:56:21 PM PST 24
Finished Feb 21 12:56:36 PM PST 24
Peak memory 211280 kb
Host smart-bc6f7a52-4496-455a-88c0-a17157edb158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=592118262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.592118262
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.933089696
Short name T182
Test name
Test status
Simulation time 8133865684 ps
CPU time 34.14 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:55 PM PST 24
Peak memory 214096 kb
Host smart-0ade37e9-47d6-4bee-9def-2bc083e1ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933089696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.933089696
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3313874058
Short name T231
Test name
Test status
Simulation time 11364453996 ps
CPU time 50.91 seconds
Started Feb 21 12:55:59 PM PST 24
Finished Feb 21 12:56:50 PM PST 24
Peak memory 214488 kb
Host smart-1609ab86-08d3-4b57-abf6-eaf0b50c5ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313874058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3313874058
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1353820981
Short name T170
Test name
Test status
Simulation time 171911615 ps
CPU time 4.18 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:45 PM PST 24
Peak memory 211188 kb
Host smart-e48fb2f0-d60d-41cc-81e2-8606b3c93689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353820981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1353820981
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1258933838
Short name T210
Test name
Test status
Simulation time 15649688459 ps
CPU time 231.52 seconds
Started Feb 21 12:55:33 PM PST 24
Finished Feb 21 12:59:25 PM PST 24
Peak memory 236924 kb
Host smart-51f7f184-8b5f-419f-97c7-0a54eba0c389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258933838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1258933838
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.134443521
Short name T255
Test name
Test status
Simulation time 1542589234 ps
CPU time 18.76 seconds
Started Feb 21 12:55:34 PM PST 24
Finished Feb 21 12:55:53 PM PST 24
Peak memory 211628 kb
Host smart-c81366bc-5090-49cc-a3e7-d0f17fab7f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134443521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.134443521
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.235366399
Short name T226
Test name
Test status
Simulation time 192152426 ps
CPU time 5.39 seconds
Started Feb 21 12:55:34 PM PST 24
Finished Feb 21 12:55:40 PM PST 24
Peak memory 211224 kb
Host smart-2e9d3644-9776-4aad-b0b5-ae4f2503ca42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235366399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.235366399
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1814437420
Short name T36
Test name
Test status
Simulation time 1694354728 ps
CPU time 50.51 seconds
Started Feb 21 12:55:33 PM PST 24
Finished Feb 21 12:56:24 PM PST 24
Peak memory 232264 kb
Host smart-cfe2f527-d5fd-40dd-980c-913f14183c17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814437420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1814437420
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.792993145
Short name T280
Test name
Test status
Simulation time 13992421103 ps
CPU time 28.96 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:56:07 PM PST 24
Peak memory 213712 kb
Host smart-50edcd0a-e618-41e0-8028-b4afa2b4f855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792993145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.792993145
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.49774627
Short name T225
Test name
Test status
Simulation time 72271238649 ps
CPU time 95.64 seconds
Started Feb 21 12:55:33 PM PST 24
Finished Feb 21 12:57:09 PM PST 24
Peak memory 214736 kb
Host smart-64d51ded-31d5-4a5b-85ed-cc37576af773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49774627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.rom_ctrl_stress_all.49774627
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1228449345
Short name T38
Test name
Test status
Simulation time 4521377167 ps
CPU time 11.77 seconds
Started Feb 21 12:56:00 PM PST 24
Finished Feb 21 12:56:12 PM PST 24
Peak memory 211344 kb
Host smart-d89fea93-37d3-4129-a25f-14279b73ba08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228449345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1228449345
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1032847797
Short name T31
Test name
Test status
Simulation time 8061394874 ps
CPU time 122.81 seconds
Started Feb 21 12:56:12 PM PST 24
Finished Feb 21 12:58:16 PM PST 24
Peak memory 236880 kb
Host smart-f50732e3-ce35-4491-93be-58d3f2e7e5ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032847797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1032847797
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2269854313
Short name T161
Test name
Test status
Simulation time 498057657 ps
CPU time 12.83 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:22 PM PST 24
Peak memory 211660 kb
Host smart-55249163-e9f6-4b41-a602-d123d860ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269854313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2269854313
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1713175032
Short name T209
Test name
Test status
Simulation time 7383648357 ps
CPU time 11.79 seconds
Started Feb 21 12:56:09 PM PST 24
Finished Feb 21 12:56:21 PM PST 24
Peak memory 211344 kb
Host smart-2efc55de-b1c1-4cf7-950c-b48bdc0894d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713175032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1713175032
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2311555719
Short name T234
Test name
Test status
Simulation time 2310174806 ps
CPU time 25.87 seconds
Started Feb 21 12:56:09 PM PST 24
Finished Feb 21 12:56:36 PM PST 24
Peak memory 213324 kb
Host smart-d82ff071-9e93-4615-91fa-7fbf4c67e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311555719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2311555719
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.706585800
Short name T153
Test name
Test status
Simulation time 4779918471 ps
CPU time 9.51 seconds
Started Feb 21 12:56:13 PM PST 24
Finished Feb 21 12:56:24 PM PST 24
Peak memory 212512 kb
Host smart-56798174-1b27-4cff-a75f-d6046c4cdd8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706585800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.706585800
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2753133327
Short name T13
Test name
Test status
Simulation time 23124672705 ps
CPU time 843.02 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 01:10:15 PM PST 24
Peak memory 228476 kb
Host smart-b97f6e6b-001f-4655-827b-4cea5b91fab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753133327 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2753133327
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2952775317
Short name T264
Test name
Test status
Simulation time 1091863358 ps
CPU time 10.73 seconds
Started Feb 21 12:56:12 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 211228 kb
Host smart-dd25aa41-e534-4900-9b0e-2d654a6411f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952775317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2952775317
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1725189745
Short name T168
Test name
Test status
Simulation time 8074723299 ps
CPU time 33.41 seconds
Started Feb 21 12:56:03 PM PST 24
Finished Feb 21 12:56:36 PM PST 24
Peak memory 212012 kb
Host smart-c91efc1e-cdea-4c3d-be29-36c7989ad1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725189745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1725189745
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3312358799
Short name T174
Test name
Test status
Simulation time 603154364 ps
CPU time 9.16 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 211236 kb
Host smart-f515ea55-f245-43c9-90a5-13e3a6f5d57c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312358799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3312358799
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2039309339
Short name T305
Test name
Test status
Simulation time 4458206380 ps
CPU time 26.06 seconds
Started Feb 21 12:56:16 PM PST 24
Finished Feb 21 12:56:43 PM PST 24
Peak memory 213756 kb
Host smart-c6913241-7e32-4034-8366-20e04b122c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039309339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2039309339
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1419957792
Short name T249
Test name
Test status
Simulation time 57054799341 ps
CPU time 30.08 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:56:53 PM PST 24
Peak memory 216252 kb
Host smart-8034958d-7650-411d-b36e-8ec9b76f0a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419957792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1419957792
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4208124105
Short name T286
Test name
Test status
Simulation time 2956219242 ps
CPU time 8.66 seconds
Started Feb 21 12:56:21 PM PST 24
Finished Feb 21 12:56:32 PM PST 24
Peak memory 211236 kb
Host smart-7c928d7f-b98d-4c2e-8da5-6cb4ce94ac25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208124105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4208124105
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2684265105
Short name T233
Test name
Test status
Simulation time 4092240306 ps
CPU time 16.03 seconds
Started Feb 21 12:56:13 PM PST 24
Finished Feb 21 12:56:30 PM PST 24
Peak memory 211788 kb
Host smart-684976c8-3e76-4e98-815f-4b15087c8988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684265105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2684265105
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.979264234
Short name T240
Test name
Test status
Simulation time 3327316699 ps
CPU time 13.36 seconds
Started Feb 21 12:56:01 PM PST 24
Finished Feb 21 12:56:15 PM PST 24
Peak memory 211280 kb
Host smart-79082d12-67a7-4c9e-a7f9-eca831dacd00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979264234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.979264234
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2802300798
Short name T46
Test name
Test status
Simulation time 3741383864 ps
CPU time 35.77 seconds
Started Feb 21 12:56:09 PM PST 24
Finished Feb 21 12:56:45 PM PST 24
Peak memory 213116 kb
Host smart-73f2db4b-c6c1-41d6-bbcd-51ceaec78bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802300798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2802300798
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1005389353
Short name T275
Test name
Test status
Simulation time 2301014406 ps
CPU time 18.8 seconds
Started Feb 21 12:56:13 PM PST 24
Finished Feb 21 12:56:32 PM PST 24
Peak memory 213532 kb
Host smart-2febba00-1f8a-4521-9060-02f60c4bf3d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005389353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1005389353
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1270883206
Short name T220
Test name
Test status
Simulation time 266382898383 ps
CPU time 2314.11 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 01:34:49 PM PST 24
Peak memory 236952 kb
Host smart-8f15c6ac-14e2-4994-bfa9-2b0eedd41add
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270883206 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1270883206
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1282258534
Short name T65
Test name
Test status
Simulation time 5566495390 ps
CPU time 10.6 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 12:56:25 PM PST 24
Peak memory 211340 kb
Host smart-3172704e-cdcd-4b2e-9641-a6146f10a037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282258534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1282258534
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2512412034
Short name T246
Test name
Test status
Simulation time 3509221123 ps
CPU time 28.99 seconds
Started Feb 21 12:56:09 PM PST 24
Finished Feb 21 12:56:39 PM PST 24
Peak memory 211720 kb
Host smart-fd35713f-fd63-45d2-b123-cdb41f48ee8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512412034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2512412034
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1329587736
Short name T340
Test name
Test status
Simulation time 1415686478 ps
CPU time 13.67 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 211192 kb
Host smart-49f5e33b-431f-425c-8038-ba50a9d4b73f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329587736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1329587736
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1987468072
Short name T217
Test name
Test status
Simulation time 3042306656 ps
CPU time 26.8 seconds
Started Feb 21 12:56:00 PM PST 24
Finished Feb 21 12:56:27 PM PST 24
Peak memory 212916 kb
Host smart-5e0854bb-4ae1-4827-bed1-6e638ac7a80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987468072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1987468072
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2224234956
Short name T272
Test name
Test status
Simulation time 5250491811 ps
CPU time 29.4 seconds
Started Feb 21 12:56:21 PM PST 24
Finished Feb 21 12:56:53 PM PST 24
Peak memory 219448 kb
Host smart-fa0e65fc-e55b-41b0-982c-c88c82e4fe01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224234956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2224234956
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1651245505
Short name T115
Test name
Test status
Simulation time 1814851056 ps
CPU time 14.5 seconds
Started Feb 21 12:56:07 PM PST 24
Finished Feb 21 12:56:22 PM PST 24
Peak memory 211268 kb
Host smart-e28a498c-fc53-4f5f-95dd-bdb86c7f7635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651245505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1651245505
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2017539459
Short name T15
Test name
Test status
Simulation time 5843242835 ps
CPU time 94.78 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 12:57:49 PM PST 24
Peak memory 239364 kb
Host smart-07e94a87-876d-45ea-9fff-b50e9e99b828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017539459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2017539459
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.190141647
Short name T157
Test name
Test status
Simulation time 6288251811 ps
CPU time 28.87 seconds
Started Feb 21 12:56:09 PM PST 24
Finished Feb 21 12:56:39 PM PST 24
Peak memory 212056 kb
Host smart-c1272f64-823a-4b0a-a439-78e1affbde8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190141647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.190141647
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.601877514
Short name T270
Test name
Test status
Simulation time 3834842258 ps
CPU time 16.49 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:28 PM PST 24
Peak memory 211320 kb
Host smart-1a54202b-ed33-4d63-9927-8672fa11b837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601877514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.601877514
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.641975179
Short name T159
Test name
Test status
Simulation time 5657374866 ps
CPU time 25.82 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:35 PM PST 24
Peak memory 213992 kb
Host smart-c8a67c40-b1b7-458d-8a8b-a61c330de170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641975179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.641975179
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1733951926
Short name T192
Test name
Test status
Simulation time 12574937827 ps
CPU time 61.78 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 12:57:16 PM PST 24
Peak memory 216736 kb
Host smart-4c0302a7-5ba5-4d0b-8572-507cc8bccfbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733951926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1733951926
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3606273611
Short name T320
Test name
Test status
Simulation time 1200346042 ps
CPU time 11.35 seconds
Started Feb 21 12:56:12 PM PST 24
Finished Feb 21 12:56:24 PM PST 24
Peak memory 211200 kb
Host smart-481355c8-ec19-4a0d-b1e9-a2fe32bac8cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606273611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3606273611
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1450362168
Short name T11
Test name
Test status
Simulation time 5639714512 ps
CPU time 135.87 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 12:58:31 PM PST 24
Peak memory 228452 kb
Host smart-413bff94-6e90-4383-8729-6ebc8d7f70bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450362168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1450362168
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3587485299
Short name T268
Test name
Test status
Simulation time 16473120711 ps
CPU time 32.22 seconds
Started Feb 21 12:56:05 PM PST 24
Finished Feb 21 12:56:37 PM PST 24
Peak memory 212040 kb
Host smart-e33d31d5-952d-4e50-865f-11b2cfb6f918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587485299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3587485299
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3375745140
Short name T236
Test name
Test status
Simulation time 98488457 ps
CPU time 5.58 seconds
Started Feb 21 12:56:04 PM PST 24
Finished Feb 21 12:56:10 PM PST 24
Peak memory 211284 kb
Host smart-641b4f1d-20cc-4449-829c-63780e858d2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375745140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3375745140
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.185068480
Short name T324
Test name
Test status
Simulation time 188083251 ps
CPU time 9.95 seconds
Started Feb 21 12:56:12 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 213332 kb
Host smart-17d9a044-84c2-4a5c-a339-a83d3e65a996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185068480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.185068480
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2802084383
Short name T267
Test name
Test status
Simulation time 20617576320 ps
CPU time 82.14 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:57:46 PM PST 24
Peak memory 214696 kb
Host smart-5b611078-8cf2-4df8-a7b9-fbacf702c259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802084383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2802084383
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2207258938
Short name T56
Test name
Test status
Simulation time 128292681915 ps
CPU time 10607.5 seconds
Started Feb 21 12:56:13 PM PST 24
Finished Feb 21 03:53:02 PM PST 24
Peak memory 246660 kb
Host smart-101ca7ea-91d3-4f6f-9a2e-0b260a710c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207258938 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2207258938
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2611805683
Short name T154
Test name
Test status
Simulation time 464941510 ps
CPU time 7.26 seconds
Started Feb 21 12:56:06 PM PST 24
Finished Feb 21 12:56:14 PM PST 24
Peak memory 211300 kb
Host smart-3885702a-baff-4df1-8582-5a557ca51841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611805683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2611805683
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3173204559
Short name T49
Test name
Test status
Simulation time 19763950812 ps
CPU time 240.08 seconds
Started Feb 21 12:56:14 PM PST 24
Finished Feb 21 01:00:14 PM PST 24
Peak memory 225188 kb
Host smart-5e09fc07-8be0-45ac-b0e8-b861b50d3fa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173204559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3173204559
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.369329496
Short name T173
Test name
Test status
Simulation time 20834828272 ps
CPU time 26.26 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:48 PM PST 24
Peak memory 212056 kb
Host smart-b128d3a5-baef-4ecc-bd87-a900805d5e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369329496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.369329496
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1612723590
Short name T148
Test name
Test status
Simulation time 605970327 ps
CPU time 9.09 seconds
Started Feb 21 12:56:16 PM PST 24
Finished Feb 21 12:56:26 PM PST 24
Peak memory 211228 kb
Host smart-a09c036a-116d-4479-aca1-cb47200fac2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612723590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1612723590
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4085549715
Short name T111
Test name
Test status
Simulation time 6418845474 ps
CPU time 28.86 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:49 PM PST 24
Peak memory 214200 kb
Host smart-daaaefca-b8cd-4651-aa7e-791e83129735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085549715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4085549715
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2174924785
Short name T345
Test name
Test status
Simulation time 11021898059 ps
CPU time 61.64 seconds
Started Feb 21 12:56:10 PM PST 24
Finished Feb 21 12:57:12 PM PST 24
Peak memory 214116 kb
Host smart-0ced325d-3575-465c-847a-2ee5bf27e3d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174924785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2174924785
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.326267522
Short name T188
Test name
Test status
Simulation time 736965488 ps
CPU time 8.98 seconds
Started Feb 21 12:56:04 PM PST 24
Finished Feb 21 12:56:14 PM PST 24
Peak memory 211252 kb
Host smart-61a3a2b4-d494-42a3-a1ed-81e5e3bcee0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326267522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.326267522
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1844392089
Short name T33
Test name
Test status
Simulation time 64468782262 ps
CPU time 340.29 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 01:02:03 PM PST 24
Peak memory 220856 kb
Host smart-fda82a73-b9bb-4300-a50f-7b52c13109b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844392089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1844392089
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.742868856
Short name T180
Test name
Test status
Simulation time 252665553 ps
CPU time 10.65 seconds
Started Feb 21 12:56:08 PM PST 24
Finished Feb 21 12:56:20 PM PST 24
Peak memory 211984 kb
Host smart-ed11a34b-f50b-456a-8a17-11592733037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742868856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.742868856
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1247725881
Short name T117
Test name
Test status
Simulation time 3828267153 ps
CPU time 10.97 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:31 PM PST 24
Peak memory 211312 kb
Host smart-c57565f0-9f14-478c-b39d-cab4e8d914f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247725881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1247725881
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1200649929
Short name T238
Test name
Test status
Simulation time 1361370826 ps
CPU time 18.08 seconds
Started Feb 21 12:56:09 PM PST 24
Finished Feb 21 12:56:28 PM PST 24
Peak memory 212940 kb
Host smart-178c6c1a-8360-4b25-aea3-fd16e0ec22cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200649929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1200649929
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2347584442
Short name T108
Test name
Test status
Simulation time 365443202 ps
CPU time 17.41 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:38 PM PST 24
Peak memory 213516 kb
Host smart-23098f46-7a1e-4c54-b4d0-19bbc52b311a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347584442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2347584442
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1752540671
Short name T341
Test name
Test status
Simulation time 3110731376 ps
CPU time 8.62 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:30 PM PST 24
Peak memory 211352 kb
Host smart-d2e8f5b7-8e51-4223-96b1-04e779d86804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752540671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1752540671
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1834666025
Short name T215
Test name
Test status
Simulation time 2455477619 ps
CPU time 23.12 seconds
Started Feb 21 12:56:19 PM PST 24
Finished Feb 21 12:56:44 PM PST 24
Peak memory 211736 kb
Host smart-a86a9050-7fa1-4972-bbb2-7a8902b6d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834666025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1834666025
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2257577993
Short name T201
Test name
Test status
Simulation time 192577766 ps
CPU time 10.22 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:56:33 PM PST 24
Peak memory 213444 kb
Host smart-336725e4-e3a1-4e91-88bf-6b2150c79fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257577993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2257577993
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3784972842
Short name T125
Test name
Test status
Simulation time 5580066491 ps
CPU time 38.38 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:57:00 PM PST 24
Peak memory 216712 kb
Host smart-cb52d100-132e-4002-81a3-970df8318c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784972842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3784972842
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2102288637
Short name T37
Test name
Test status
Simulation time 333194668 ps
CPU time 4.23 seconds
Started Feb 21 12:56:18 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 211280 kb
Host smart-223c359f-fa4a-4e61-8879-9a879d5f127b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102288637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2102288637
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4222642646
Short name T211
Test name
Test status
Simulation time 497212910 ps
CPU time 12.92 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:25 PM PST 24
Peak memory 211700 kb
Host smart-f0e1bd5d-50d4-41e5-8c3c-2f13b16b00ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222642646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4222642646
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1021215477
Short name T318
Test name
Test status
Simulation time 3052816087 ps
CPU time 10.63 seconds
Started Feb 21 12:56:11 PM PST 24
Finished Feb 21 12:56:23 PM PST 24
Peak memory 211280 kb
Host smart-7424a34a-f62e-45c2-9e18-2b1a3ae7d330
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021215477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1021215477
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.742530463
Short name T20
Test name
Test status
Simulation time 1016212519 ps
CPU time 13.36 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:56:35 PM PST 24
Peak memory 212652 kb
Host smart-894ff4b8-a6b1-440a-bc44-e8faca9ce58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742530463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.742530463
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3752829223
Short name T140
Test name
Test status
Simulation time 584058607 ps
CPU time 15.95 seconds
Started Feb 21 12:56:20 PM PST 24
Finished Feb 21 12:56:38 PM PST 24
Peak memory 213056 kb
Host smart-9bb8c4e5-519e-43a5-8748-c7962a9a270f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752829223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3752829223
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3959894207
Short name T330
Test name
Test status
Simulation time 85855720 ps
CPU time 4.35 seconds
Started Feb 21 12:55:33 PM PST 24
Finished Feb 21 12:55:37 PM PST 24
Peak memory 211240 kb
Host smart-9c1d98e9-e626-43b6-b1a4-06f708b202c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959894207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3959894207
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3537777086
Short name T309
Test name
Test status
Simulation time 122334638749 ps
CPU time 188.47 seconds
Started Feb 21 12:55:33 PM PST 24
Finished Feb 21 12:58:42 PM PST 24
Peak memory 229716 kb
Host smart-ea39d7e2-4d5b-4bad-94d4-5c3ea7adb957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537777086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3537777086
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3547797720
Short name T202
Test name
Test status
Simulation time 13507363947 ps
CPU time 25.16 seconds
Started Feb 21 12:55:35 PM PST 24
Finished Feb 21 12:56:00 PM PST 24
Peak memory 212088 kb
Host smart-6983e74e-9819-4084-9558-ea0a2732e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547797720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3547797720
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.37326975
Short name T342
Test name
Test status
Simulation time 3523066794 ps
CPU time 16.07 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 12:55:56 PM PST 24
Peak memory 211304 kb
Host smart-8ae80566-624a-4711-8306-1c0be5d9acca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37326975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.37326975
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3465682602
Short name T147
Test name
Test status
Simulation time 2529848578 ps
CPU time 23.93 seconds
Started Feb 21 12:55:34 PM PST 24
Finished Feb 21 12:55:58 PM PST 24
Peak memory 213624 kb
Host smart-418eec42-a92f-41f5-b98d-f6977f17a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465682602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3465682602
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4041632102
Short name T2
Test name
Test status
Simulation time 2198924807 ps
CPU time 38.65 seconds
Started Feb 21 12:55:36 PM PST 24
Finished Feb 21 12:56:15 PM PST 24
Peak memory 213960 kb
Host smart-7c33d00d-b230-46ad-a215-cf3e7ac15524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041632102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4041632102
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2419408572
Short name T337
Test name
Test status
Simulation time 573733678 ps
CPU time 7.69 seconds
Started Feb 21 12:55:32 PM PST 24
Finished Feb 21 12:55:40 PM PST 24
Peak memory 211160 kb
Host smart-d76ced13-b983-43f1-ba79-ea58637b8cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419408572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2419408572
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.923945732
Short name T310
Test name
Test status
Simulation time 177261552 ps
CPU time 9.44 seconds
Started Feb 21 12:55:32 PM PST 24
Finished Feb 21 12:55:42 PM PST 24
Peak memory 211600 kb
Host smart-6a260603-2b52-4568-a5b2-ceffdef59305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923945732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.923945732
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3198879113
Short name T296
Test name
Test status
Simulation time 2627663343 ps
CPU time 6.23 seconds
Started Feb 21 12:55:31 PM PST 24
Finished Feb 21 12:55:38 PM PST 24
Peak memory 211360 kb
Host smart-9539dea1-0ab6-4868-ab8f-96533299ac85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198879113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3198879113
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3544381815
Short name T58
Test name
Test status
Simulation time 274609190 ps
CPU time 12.01 seconds
Started Feb 21 12:55:42 PM PST 24
Finished Feb 21 12:55:54 PM PST 24
Peak memory 212324 kb
Host smart-92086257-f433-47a8-809c-ccae88e210b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544381815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3544381815
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2689745647
Short name T78
Test name
Test status
Simulation time 837101400 ps
CPU time 12.87 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:54 PM PST 24
Peak memory 211972 kb
Host smart-1137d510-a3ee-4293-801e-58f3763c067c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689745647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2689745647
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.312319090
Short name T291
Test name
Test status
Simulation time 88243377 ps
CPU time 4.19 seconds
Started Feb 21 12:55:37 PM PST 24
Finished Feb 21 12:55:42 PM PST 24
Peak memory 211252 kb
Host smart-643fbf2b-0ed1-4f78-a3f0-0f2f0f3502c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312319090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.312319090
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.628116869
Short name T141
Test name
Test status
Simulation time 4234016584 ps
CPU time 33.8 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:56:12 PM PST 24
Peak memory 211856 kb
Host smart-14b923a6-8ff0-4338-b26e-afdba50b0a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628116869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.628116869
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4132603670
Short name T232
Test name
Test status
Simulation time 2629719184 ps
CPU time 14.06 seconds
Started Feb 21 12:55:33 PM PST 24
Finished Feb 21 12:55:47 PM PST 24
Peak memory 211376 kb
Host smart-03814711-442a-467b-bac5-f23c77d7d0c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4132603670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4132603670
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2556011146
Short name T319
Test name
Test status
Simulation time 758972582 ps
CPU time 9.92 seconds
Started Feb 21 12:55:36 PM PST 24
Finished Feb 21 12:55:47 PM PST 24
Peak memory 213720 kb
Host smart-64636b26-7342-4de0-9071-81ea6e7c9eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556011146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2556011146
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2433927792
Short name T282
Test name
Test status
Simulation time 3559061712 ps
CPU time 31.26 seconds
Started Feb 21 12:55:32 PM PST 24
Finished Feb 21 12:56:04 PM PST 24
Peak memory 213248 kb
Host smart-9fc903e3-74b9-455a-bc8d-416e046988f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433927792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2433927792
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2962294984
Short name T262
Test name
Test status
Simulation time 156841159506 ps
CPU time 1399.87 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 01:18:58 PM PST 24
Peak memory 237692 kb
Host smart-75856b52-5c2d-4a9f-89b6-5f1e357b8ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962294984 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2962294984
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1546545878
Short name T160
Test name
Test status
Simulation time 5789664204 ps
CPU time 11.94 seconds
Started Feb 21 12:55:35 PM PST 24
Finished Feb 21 12:55:47 PM PST 24
Peak memory 211372 kb
Host smart-efe19c52-c141-41f0-bb41-62ef676c95bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546545878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1546545878
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1103644161
Short name T314
Test name
Test status
Simulation time 12122458970 ps
CPU time 27.39 seconds
Started Feb 21 12:55:32 PM PST 24
Finished Feb 21 12:56:00 PM PST 24
Peak memory 212288 kb
Host smart-3c00bf86-2124-48f9-a072-8918791633a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103644161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1103644161
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3457138487
Short name T21
Test name
Test status
Simulation time 96885339 ps
CPU time 5.18 seconds
Started Feb 21 12:55:34 PM PST 24
Finished Feb 21 12:55:39 PM PST 24
Peak memory 211232 kb
Host smart-26be0d14-83f7-42a9-a1da-9850360bd8c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457138487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3457138487
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1001787098
Short name T335
Test name
Test status
Simulation time 2529589411 ps
CPU time 24.26 seconds
Started Feb 21 12:55:36 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 213088 kb
Host smart-cb3700f1-3133-4366-a61f-e696d5b2f83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001787098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1001787098
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.143193451
Short name T260
Test name
Test status
Simulation time 49497917916 ps
CPU time 101.13 seconds
Started Feb 21 12:55:42 PM PST 24
Finished Feb 21 12:57:23 PM PST 24
Peak memory 217804 kb
Host smart-0e66355a-234c-4aa7-a516-518e53ceab58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143193451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.143193451
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2180577507
Short name T194
Test name
Test status
Simulation time 1203580392 ps
CPU time 10.94 seconds
Started Feb 21 12:55:33 PM PST 24
Finished Feb 21 12:55:44 PM PST 24
Peak memory 211228 kb
Host smart-501f38f8-7246-4dd9-8081-43a1c6fb584b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180577507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2180577507
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1760496596
Short name T51
Test name
Test status
Simulation time 6090377302 ps
CPU time 187.28 seconds
Started Feb 21 12:55:39 PM PST 24
Finished Feb 21 12:58:47 PM PST 24
Peak memory 228344 kb
Host smart-48799948-68fb-4738-a04f-fde74efddf64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760496596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1760496596
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1257942992
Short name T28
Test name
Test status
Simulation time 6200616791 ps
CPU time 18.94 seconds
Started Feb 21 12:55:38 PM PST 24
Finished Feb 21 12:55:57 PM PST 24
Peak memory 211380 kb
Host smart-fc7de537-b532-426a-9b47-d625b0e0a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257942992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1257942992
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3157109243
Short name T152
Test name
Test status
Simulation time 12645616650 ps
CPU time 15.74 seconds
Started Feb 21 12:55:34 PM PST 24
Finished Feb 21 12:55:50 PM PST 24
Peak memory 211356 kb
Host smart-464b6075-c0f8-4def-b9f8-adf6f46020d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157109243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3157109243
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3036580642
Short name T279
Test name
Test status
Simulation time 754834353 ps
CPU time 10.17 seconds
Started Feb 21 12:55:40 PM PST 24
Finished Feb 21 12:55:50 PM PST 24
Peak memory 213772 kb
Host smart-6dbca9e8-b46e-4429-93df-129c4afcf86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036580642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3036580642
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1808795461
Short name T42
Test name
Test status
Simulation time 377933626 ps
CPU time 6.58 seconds
Started Feb 21 12:55:30 PM PST 24
Finished Feb 21 12:55:37 PM PST 24
Peak memory 211092 kb
Host smart-4717ec02-cfc6-49c8-9b7a-b079d21e01a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808795461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1808795461
Directory /workspace/9.rom_ctrl_stress_all/latest
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