Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

601869

1

T1

11

T3

1

T4

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	170658	1			T1	26		T4	28		T5	27
values[0x0]	230106	1			T3	1		T36	4		T13	15336
values[0x1]	265629	1			T3	2		T36	2		T13	17440

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

635502

1

T1

11

T3

1

T4

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2917	1			T13	174		T14	533		T129	1
valid_sources[0x01]	2996	1			T13	380		T14	506		T15	6
valid_sources[0x02]	2494	1			T13	14		T14	539		T129	1
valid_sources[0x03]	2627	1			T12	1		T13	554		T31	1
valid_sources[0x04]	3048	1			T13	116		T59	1		T14	523
valid_sources[0x05]	2776	1			T13	120		T14	537		T15	70
valid_sources[0x06]	2573	1			T12	1		T13	212		T14	496
valid_sources[0x07]	2751	1			T13	83		T14	514		T15	10
valid_sources[0x08]	2928	1			T5	1		T13	512		T14	522
valid_sources[0x09]	3167	1			T13	203		T57	1		T14	565
valid_sources[0x0a]	3395	1			T3	2		T16	1		T13	30
valid_sources[0x0b]	2341	1			T13	261		T59	1		T14	552
valid_sources[0x0c]	2293	1			T16	1		T13	176		T14	549
valid_sources[0x0d]	2728	1			T13	309		T14	517		T129	1
valid_sources[0x0e]	2175	1			T6	2		T13	7		T14	557
valid_sources[0x0f]	2704	1			T13	3		T14	567		T15	552
valid_sources[0x10]	2531	1			T16	1		T13	6		T14	569
valid_sources[0x11]	2694	1			T13	160		T14	511		T15	158
valid_sources[0x12]	2627	1			T6	1		T13	539		T59	1
valid_sources[0x13]	2643	1			T13	205		T32	26		T14	533
valid_sources[0x14]	3076	1			T13	266		T14	526		T15	4
valid_sources[0x15]	2597	1			T13	191		T14	520		T79	1
valid_sources[0x16]	3082	1			T13	231		T14	518		T15	30
valid_sources[0x17]	2019	1			T13	78		T14	539		T15	63
valid_sources[0x18]	2156	1			T16	5		T13	8		T14	512
valid_sources[0x19]	2306	1			T12	1		T13	9		T14	560
valid_sources[0x1a]	2483	1			T13	132		T14	517		T42	5
valid_sources[0x1b]	2432	1			T6	1		T13	374		T59	1
valid_sources[0x1c]	3147	1			T6	1		T13	524		T59	1
valid_sources[0x1d]	2479	1			T13	211		T14	571		T129	1
valid_sources[0x1e]	2545	1			T13	321		T14	477		T129	1
valid_sources[0x1f]	2311	1			T13	25		T14	578		T45	128
valid_sources[0x20]	2641	1			T13	294		T14	559		T49	25
valid_sources[0x21]	2225	1			T13	161		T14	534		T130	3
valid_sources[0x22]	2174	1			T13	68		T57	1		T14	569
valid_sources[0x23]	2576	1			T13	33		T14	532		T15	192
valid_sources[0x24]	2231	1			T13	229		T14	518		T15	1
valid_sources[0x25]	2811	1			T13	358		T14	522		T42	1
valid_sources[0x26]	2693	1			T13	360		T14	510		T131	1
valid_sources[0x27]	3309	1			T6	2		T12	1		T13	373
valid_sources[0x28]	3021	1			T13	342		T14	469		T15	203
valid_sources[0x29]	2416	1			T13	124		T14	518		T41	1
valid_sources[0x2a]	2619	1			T12	1		T13	39		T14	586
valid_sources[0x2b]	2901	1			T13	250		T14	557		T15	4
valid_sources[0x2c]	2512	1			T13	99		T57	1		T14	558
valid_sources[0x2d]	2516	1			T12	1		T13	246		T14	568
valid_sources[0x2e]	2738	1			T13	75		T31	2		T14	515
valid_sources[0x2f]	2922	1			T16	1		T13	209		T14	549
valid_sources[0x30]	2882	1			T13	697		T14	522		T15	185
valid_sources[0x31]	2277	1			T13	131		T14	506		T129	2
valid_sources[0x32]	2500	1			T13	13		T14	476		T15	339
valid_sources[0x33]	3151	1			T13	3		T14	532		T129	1
valid_sources[0x34]	2633	1			T13	19		T14	549		T79	2
valid_sources[0x35]	3131	1			T12	1		T13	287		T57	2
valid_sources[0x36]	2240	1			T13	106		T59	1		T14	522
valid_sources[0x37]	2518	1			T30	2		T13	40		T14	511
valid_sources[0x38]	2421	1			T1	2		T13	50		T31	1
valid_sources[0x39]	2206	1			T16	2		T13	125		T31	7
valid_sources[0x3a]	2367	1			T6	3		T13	158		T31	2
valid_sources[0x3b]	2808	1			T1	1		T13	156		T14	545
valid_sources[0x3c]	2853	1			T13	6		T14	578		T15	6
valid_sources[0x3d]	2607	1			T13	12		T14	554		T15	10
valid_sources[0x3e]	3108	1			T13	415		T14	544		T15	4
valid_sources[0x3f]	2179	1			T1	1		T13	119		T14	512
valid_sources[0x40]	2152	1			T1	1		T13	31		T14	590
valid_sources[0x41]	2667	1			T13	17		T14	532		T130	3
valid_sources[0x42]	3075	1			T13	308		T14	586		T48	21
valid_sources[0x43]	2553	1			T13	218		T14	527		T107	3
valid_sources[0x44]	2863	1			T13	239		T14	542		T15	75
valid_sources[0x45]	3295	1			T1	1		T13	279		T14	543
valid_sources[0x46]	2458	1			T12	1		T13	567		T14	488
valid_sources[0x47]	1876	1			T13	106		T14	524		T15	2
valid_sources[0x48]	2301	1			T13	122		T14	493		T15	5
valid_sources[0x49]	2824	1			T9	1		T13	276		T57	1
valid_sources[0x4a]	2224	1			T13	12		T59	1		T14	504
valid_sources[0x4b]	3016	1			T10	128		T13	235		T14	546
valid_sources[0x4c]	2127	1			T13	9		T14	552		T79	1
valid_sources[0x4d]	2590	1			T6	2		T13	31		T14	571
valid_sources[0x4e]	2598	1			T16	1		T12	1		T13	117
valid_sources[0x4f]	2040	1			T1	1		T13	81		T14	544
valid_sources[0x50]	2623	1			T13	188		T59	1		T14	546
valid_sources[0x51]	2518	1			T16	2		T13	192		T14	500
valid_sources[0x52]	2178	1			T13	8		T14	562		T41	1
valid_sources[0x53]	2919	1			T13	319		T31	3		T14	536
valid_sources[0x54]	2805	1			T13	12		T59	1		T14	581
valid_sources[0x55]	2082	1			T5	1		T13	3		T14	517
valid_sources[0x56]	3199	1			T5	1		T12	1		T13	382
valid_sources[0x57]	2501	1			T13	238		T14	513		T129	1
valid_sources[0x58]	2148	1			T13	184		T14	544		T15	7
valid_sources[0x59]	2497	1			T13	287		T14	559		T79	1
valid_sources[0x5a]	2830	1			T30	1		T13	26		T14	537
valid_sources[0x5b]	2201	1			T13	26		T14	553		T15	14
valid_sources[0x5c]	2458	1			T13	9		T14	515		T15	2
valid_sources[0x5d]	2336	1			T5	2		T13	81		T14	557
valid_sources[0x5e]	2319	1			T13	136		T14	519		T15	17
valid_sources[0x5f]	3416	1			T13	268		T59	1		T14	548
valid_sources[0x60]	2629	1			T13	223		T57	1		T14	524
valid_sources[0x61]	2654	1			T13	89		T14	501		T46	7
valid_sources[0x62]	2673	1			T13	278		T14	571		T15	162
valid_sources[0x63]	2283	1			T13	81		T14	516		T107	5
valid_sources[0x64]	2847	1			T13	92		T14	526		T28	1
valid_sources[0x65]	2697	1			T13	108		T14	551		T15	14
valid_sources[0x66]	2594	1			T13	97		T14	559		T46	4
valid_sources[0x67]	2156	1			T36	6		T13	20		T14	490
valid_sources[0x68]	3003	1			T13	342		T14	534		T15	49
valid_sources[0x69]	2455	1			T13	66		T14	535		T15	4
valid_sources[0x6a]	2475	1			T13	382		T14	528		T107	8
valid_sources[0x6b]	3093	1			T1	2		T5	1		T13	446
valid_sources[0x6c]	2679	1			T13	237		T14	532		T40	2
valid_sources[0x6d]	2558	1			T13	85		T14	550		T79	1
valid_sources[0x6e]	2316	1			T1	1		T5	2		T13	189
valid_sources[0x6f]	2268	1			T12	1		T13	25		T14	540
valid_sources[0x70]	3107	1			T13	184		T14	571		T41	2
valid_sources[0x71]	2329	1			T13	17		T14	531		T41	1
valid_sources[0x72]	2364	1			T1	1		T13	119		T59	1
valid_sources[0x73]	3687	1			T12	1		T13	318		T14	586
valid_sources[0x74]	2267	1			T13	54		T57	1		T59	1
valid_sources[0x75]	2838	1			T12	2		T13	11		T14	574
valid_sources[0x76]	2571	1			T13	21		T14	524		T15	1
valid_sources[0x77]	3050	1			T13	176		T59	1		T14	497
valid_sources[0x78]	2416	1			T9	2		T13	18		T14	537
valid_sources[0x79]	2861	1			T13	478		T14	560		T15	3
valid_sources[0x7a]	2191	1			T5	1		T13	224		T14	562
valid_sources[0x7b]	2407	1			T12	1		T13	85		T31	2
valid_sources[0x7c]	2565	1			T1	1		T13	23		T14	585
valid_sources[0x7d]	2645	1			T6	1		T13	24		T57	1
valid_sources[0x7e]	3272	1			T13	118		T14	559		T15	38
valid_sources[0x7f]	2001	1			T12	1		T13	93		T14	525
valid_sources[0x80]	2642	1			T13	26		T14	542		T42	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

153036

1

T1

11

T4

16

T5

8

values[0x0]

all_enables

biggest_size

224954

1

T36

2

T13

15013

T14

46910

values[0x1]

all_enables

biggest_size

223879

1

T3

1

T36

1

T13

14606

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

580450

1

T1

3

T2

11

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	180542	1			T1	3		T2	158		T4	6
values[0x0]	227307	1			T13	16380		T14	48799		T15	5478
values[0x1]	326121	1			T13	23312		T14	69553		T15	8139

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59734	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

674236

1

T1

3

T2

103

T4

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2773	1			T8	4		T10	1		T13	200
valid_sources[0x01]	2838	1			T7	1		T8	1		T10	1
valid_sources[0x02]	2875	1			T13	248		T61	2		T14	610
valid_sources[0x03]	2783	1			T8	1		T20	17		T13	187
valid_sources[0x04]	2715	1			T10	1		T11	3		T13	182
valid_sources[0x05]	2934	1			T8	1		T13	187		T61	1
valid_sources[0x06]	2824	1			T8	1		T19	2		T13	173
valid_sources[0x07]	2799	1			T6	2		T8	1		T10	2
valid_sources[0x08]	2882	1			T10	3		T19	1		T13	201
valid_sources[0x09]	2919	1			T8	6		T10	2		T13	228
valid_sources[0x0a]	2776	1			T10	3		T11	1		T13	179
valid_sources[0x0b]	2880	1			T12	2		T13	174		T14	564
valid_sources[0x0c]	2780	1			T11	1		T13	166		T61	2
valid_sources[0x0d]	2816	1			T2	1		T11	1		T13	170
valid_sources[0x0e]	2973	1			T2	1		T8	7		T10	1
valid_sources[0x0f]	2899	1			T7	1		T10	1		T16	1
valid_sources[0x10]	2885	1			T6	3		T8	2		T10	1
valid_sources[0x11]	2934	1			T2	4		T6	1		T7	4
valid_sources[0x12]	2984	1			T16	1		T11	2		T12	6
valid_sources[0x13]	2699	1			T13	189		T61	1		T14	564
valid_sources[0x14]	2795	1			T7	4		T13	182		T14	551
valid_sources[0x15]	2807	1			T10	7		T16	1		T19	1
valid_sources[0x16]	2795	1			T7	2		T13	200		T61	1
valid_sources[0x17]	2777	1			T2	1		T6	2		T7	10
valid_sources[0x18]	2838	1			T6	3		T8	3		T13	207
valid_sources[0x19]	2904	1			T2	3		T8	8		T10	4
valid_sources[0x1a]	2794	1			T2	4		T7	1		T20	11
valid_sources[0x1b]	2873	1			T10	1		T16	2		T13	179
valid_sources[0x1c]	2794	1			T7	1		T8	1		T13	215
valid_sources[0x1d]	2832	1			T2	1		T11	2		T13	204
valid_sources[0x1e]	2820	1			T6	2		T8	1		T10	4
valid_sources[0x1f]	2805	1			T8	1		T10	1		T20	23
valid_sources[0x20]	2833	1			T7	10		T13	213		T57	1
valid_sources[0x21]	3027	1			T8	10		T10	3		T13	203
valid_sources[0x22]	2976	1			T8	1		T16	1		T13	191
valid_sources[0x23]	2877	1			T8	3		T10	5		T20	3
valid_sources[0x24]	2858	1			T4	1		T10	2		T13	180
valid_sources[0x25]	2877	1			T7	4		T10	1		T11	1
valid_sources[0x26]	2936	1			T7	2		T13	252		T58	2
valid_sources[0x27]	2939	1			T8	2		T10	2		T11	1
valid_sources[0x28]	2854	1			T19	2		T13	210		T14	599
valid_sources[0x29]	2981	1			T7	5		T8	2		T10	1
valid_sources[0x2a]	2786	1			T4	1		T7	7		T8	1
valid_sources[0x2b]	2804	1			T2	4		T7	4		T8	4
valid_sources[0x2c]	2905	1			T8	2		T10	2		T11	2
valid_sources[0x2d]	2952	1			T8	1		T10	6		T11	1
valid_sources[0x2e]	2862	1			T6	1		T10	1		T16	1
valid_sources[0x2f]	2798	1			T1	1		T8	1		T10	1
valid_sources[0x30]	2813	1			T16	1		T12	1		T13	214
valid_sources[0x31]	2858	1			T2	5		T8	1		T19	1
valid_sources[0x32]	2977	1			T10	1		T13	202		T57	1
valid_sources[0x33]	2656	1			T8	1		T10	2		T13	206
valid_sources[0x34]	2823	1			T7	2		T8	1		T13	200
valid_sources[0x35]	2889	1			T8	4		T10	6		T13	238
valid_sources[0x36]	2849	1			T2	12		T10	2		T11	2
valid_sources[0x37]	2674	1			T6	2		T10	4		T16	2
valid_sources[0x38]	2809	1			T7	1		T8	2		T13	211
valid_sources[0x39]	3022	1			T7	3		T10	3		T108	50
valid_sources[0x3a]	2921	1			T7	1		T8	1		T10	3
valid_sources[0x3b]	2935	1			T10	3		T12	3		T13	217
valid_sources[0x3c]	2947	1			T8	1		T13	204		T61	1
valid_sources[0x3d]	2866	1			T8	2		T10	1		T16	1
valid_sources[0x3e]	2860	1			T2	6		T8	3		T16	1
valid_sources[0x3f]	2847	1			T16	1		T13	232		T58	1
valid_sources[0x40]	2860	1			T10	4		T11	4		T13	158
valid_sources[0x41]	2909	1			T16	2		T19	1		T13	216
valid_sources[0x42]	2744	1			T7	1		T20	21		T11	1
valid_sources[0x43]	2785	1			T13	165		T14	592		T132	1
valid_sources[0x44]	3009	1			T8	2		T11	1		T13	199
valid_sources[0x45]	2858	1			T13	203		T57	1		T61	1
valid_sources[0x46]	2931	1			T8	2		T10	2		T16	1
valid_sources[0x47]	2731	1			T19	1		T13	166		T57	1
valid_sources[0x48]	2838	1			T13	184		T57	1		T61	1
valid_sources[0x49]	2794	1			T7	2		T10	1		T13	231
valid_sources[0x4a]	2973	1			T6	1		T8	1		T11	5
valid_sources[0x4b]	2835	1			T11	2		T13	251		T61	2
valid_sources[0x4c]	2828	1			T8	3		T10	1		T16	1
valid_sources[0x4d]	2911	1			T8	1		T10	1		T16	4
valid_sources[0x4e]	2852	1			T16	2		T12	5		T13	213
valid_sources[0x4f]	2801	1			T7	2		T8	2		T13	175
valid_sources[0x50]	2910	1			T6	1		T8	1		T16	2
valid_sources[0x51]	2844	1			T8	1		T10	2		T13	159
valid_sources[0x52]	2771	1			T2	5		T10	2		T13	224
valid_sources[0x53]	2810	1			T8	1		T16	1		T13	224
valid_sources[0x54]	2933	1			T7	1		T10	1		T16	1
valid_sources[0x55]	2837	1			T8	2		T10	2		T16	1
valid_sources[0x56]	2699	1			T8	4		T10	3		T11	5
valid_sources[0x57]	3020	1			T6	2		T10	2		T20	9
valid_sources[0x58]	2833	1			T8	1		T11	4		T13	197
valid_sources[0x59]	2950	1			T19	1		T13	213		T58	1
valid_sources[0x5a]	2968	1			T10	7		T11	4		T13	185
valid_sources[0x5b]	2840	1			T7	1		T13	205		T57	1
valid_sources[0x5c]	2813	1			T8	1		T10	2		T19	1
valid_sources[0x5d]	2884	1			T8	5		T19	1		T13	222
valid_sources[0x5e]	2842	1			T6	1		T10	1		T19	1
valid_sources[0x5f]	2940	1			T10	2		T13	206		T58	1
valid_sources[0x60]	2913	1			T8	1		T16	2		T12	1
valid_sources[0x61]	2871	1			T8	1		T13	162		T58	1
valid_sources[0x62]	2828	1			T8	4		T11	1		T13	208
valid_sources[0x63]	2922	1			T2	1		T7	1		T13	191
valid_sources[0x64]	2838	1			T5	1		T8	4		T10	2
valid_sources[0x65]	2885	1			T7	8		T8	1		T13	224
valid_sources[0x66]	2865	1			T2	2		T8	1		T13	227
valid_sources[0x67]	2861	1			T7	3		T8	5		T20	31
valid_sources[0x68]	2966	1			T13	211		T57	2		T58	3
valid_sources[0x69]	2813	1			T7	2		T8	3		T10	3
valid_sources[0x6a]	3044	1			T7	1		T8	1		T19	1
valid_sources[0x6b]	2874	1			T8	2		T10	3		T20	15
valid_sources[0x6c]	2944	1			T8	6		T13	211		T58	1
valid_sources[0x6d]	2731	1			T8	1		T10	7		T13	192
valid_sources[0x6e]	2949	1			T20	26		T11	2		T13	188
valid_sources[0x6f]	2937	1			T8	4		T11	1		T13	200
valid_sources[0x70]	2865	1			T8	2		T10	1		T11	9
valid_sources[0x71]	2876	1			T8	1		T10	2		T16	2
valid_sources[0x72]	2764	1			T8	2		T13	214		T58	1
valid_sources[0x73]	2906	1			T2	1		T7	3		T16	1
valid_sources[0x74]	2953	1			T8	2		T13	218		T58	2
valid_sources[0x75]	2822	1			T4	2		T8	3		T13	183
valid_sources[0x76]	2903	1			T2	15		T7	1		T8	1
valid_sources[0x77]	2942	1			T8	2		T10	2		T12	10
valid_sources[0x78]	2940	1			T7	2		T10	1		T108	34
valid_sources[0x79]	3020	1			T6	1		T8	2		T10	5
valid_sources[0x7a]	2852	1			T13	178		T61	1		T14	588
valid_sources[0x7b]	2781	1			T2	1		T6	2		T8	3
valid_sources[0x7c]	2834	1			T8	3		T13	185		T14	616
valid_sources[0x7d]	2828	1			T8	2		T13	219		T61	1
valid_sources[0x7e]	2646	1			T10	2		T16	2		T13	177
valid_sources[0x7f]	2828	1			T11	1		T13	198		T14	643
valid_sources[0x80]	2837	1			T16	1		T13	170		T14	569

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

148068

1

T1

3

T2

11

T4

6

values[0x0]

all_enables

biggest_size

215658

1

T13

15571

T14

46422

T15

5152

values[0x1]

all_enables

biggest_size

216724

1

T13

15831

T14

46572

T15

5295