Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1651276

1

T2

147

T6

56

T7

156

full_word

696750

1

T1

2

T2

11

T4

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2347736	1			T1	2		T2	158		T4	4
auto[TlIntgErrCmd]	93	1			T62	7		T63	6		T64	2
auto[TlIntgErrData]	99	1			T62	5		T63	2		T64	5
auto[TlIntgErrBoth]	98	1			T62	8		T63	2		T64	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297876

1

T1

2

T2

158

T4

4

auto[1]

2050150

1

T13

143266

T14

432102

T15

53395

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	135564	1			T2	147		T6	56		T7	156
auto[TlIntgErrNone]	partial	auto[1]	1515448	1			T13	104612		T14	317685		T15	40199
auto[TlIntgErrNone]	full_word	auto[0]	162185	1			T1	2		T2	11		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	534539	1			T13	38654		T14	114417		T15	13196
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T62	5		T63	4		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T62	1		T63	2		T64	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T121	1		T119	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T62	1		T112	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T62	5		T63	1		T64	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T63	1		T64	3		T112	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T119	1		T122	2		T123	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T64	1		T117	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T62	1		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T62	7		T63	1		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T114	1		T124	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T121	1		T126	1		T127	2