Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	138261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1382896

1

T1

13

T2

18

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	382067	1			T1	38		T2	32		T3	21
values[0x0]	527666	1			T9	2		T10	1		T34	5
values[0x1]	611424	1			T9	2		T10	4		T34	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62132	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1459025

1

T1

17

T2

23

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5529	1			T12	152		T13	62		T14	200
valid_sources[0x01]	5689	1			T12	179		T13	105		T124	8
valid_sources[0x02]	6030	1			T7	2		T11	9		T12	180
valid_sources[0x03]	6318	1			T12	166		T13	95		T29	1
valid_sources[0x04]	5499	1			T21	1		T12	137		T13	110
valid_sources[0x05]	6005	1			T12	150		T13	62		T104	1
valid_sources[0x06]	5821	1			T5	32		T12	156		T13	68
valid_sources[0x07]	5338	1			T12	166		T13	84		T14	177
valid_sources[0x08]	6917	1			T12	169		T13	82		T125	1
valid_sources[0x09]	6919	1			T12	158		T18	32		T13	85
valid_sources[0x0a]	6401	1			T12	141		T13	103		T30	2
valid_sources[0x0b]	6625	1			T2	3		T12	152		T13	70
valid_sources[0x0c]	5891	1			T7	1		T11	1		T12	168
valid_sources[0x0d]	5782	1			T7	4		T12	178		T13	115
valid_sources[0x0e]	5335	1			T9	4		T12	147		T13	82
valid_sources[0x0f]	5116	1			T21	1		T12	176		T13	50
valid_sources[0x10]	6243	1			T12	156		T13	87		T126	1
valid_sources[0x11]	6185	1			T12	148		T13	105		T104	1
valid_sources[0x12]	5385	1			T12	186		T13	81		T46	1
valid_sources[0x13]	5212	1			T12	148		T13	72		T14	161
valid_sources[0x14]	6047	1			T7	2		T12	125		T13	78
valid_sources[0x15]	6355	1			T12	203		T13	64		T14	164
valid_sources[0x16]	6208	1			T12	171		T13	82		T104	1
valid_sources[0x17]	5625	1			T12	169		T13	63		T38	1
valid_sources[0x18]	6271	1			T12	144		T13	62		T29	1
valid_sources[0x19]	5193	1			T12	165		T13	71		T54	1
valid_sources[0x1a]	5857	1			T12	151		T13	82		T14	188
valid_sources[0x1b]	6733	1			T12	154		T13	66		T38	1
valid_sources[0x1c]	5408	1			T12	179		T13	79		T125	1
valid_sources[0x1d]	6083	1			T1	1		T12	166		T13	79
valid_sources[0x1e]	5512	1			T12	168		T13	87		T14	168
valid_sources[0x1f]	6189	1			T21	1		T12	166		T13	70
valid_sources[0x20]	5536	1			T2	2		T11	4		T12	175
valid_sources[0x21]	4711	1			T12	168		T13	92		T29	1
valid_sources[0x22]	5668	1			T7	1		T12	173		T13	66
valid_sources[0x23]	4754	1			T12	173		T13	79		T24	4
valid_sources[0x24]	5507	1			T21	2		T12	176		T13	96
valid_sources[0x25]	6383	1			T12	170		T13	62		T20	1
valid_sources[0x26]	5377	1			T12	169		T13	81		T38	1
valid_sources[0x27]	6886	1			T7	2		T12	166		T13	82
valid_sources[0x28]	6463	1			T1	1		T12	160		T13	93
valid_sources[0x29]	5422	1			T12	168		T13	54		T14	170
valid_sources[0x2a]	6292	1			T12	161		T13	77		T14	167
valid_sources[0x2b]	5482	1			T12	160		T13	67		T38	1
valid_sources[0x2c]	5952	1			T12	154		T13	74		T31	4
valid_sources[0x2d]	5649	1			T3	1		T12	180		T13	66
valid_sources[0x2e]	5704	1			T12	183		T13	78		T38	1
valid_sources[0x2f]	5407	1			T12	181		T13	86		T46	1
valid_sources[0x30]	5655	1			T12	162		T13	98		T14	189
valid_sources[0x31]	6020	1			T12	144		T13	81		T14	178
valid_sources[0x32]	5483	1			T12	186		T13	49		T127	2
valid_sources[0x33]	6537	1			T12	162		T13	82		T14	154
valid_sources[0x34]	5957	1			T1	1		T12	160		T13	69
valid_sources[0x35]	5772	1			T12	190		T13	55		T38	1
valid_sources[0x36]	6081	1			T12	174		T13	74		T38	1
valid_sources[0x37]	6029	1			T2	5		T12	175		T13	83
valid_sources[0x38]	5830	1			T11	32		T12	171		T13	102
valid_sources[0x39]	5349	1			T21	1		T12	168		T13	63
valid_sources[0x3a]	5601	1			T1	1		T3	3		T12	166
valid_sources[0x3b]	5575	1			T1	1		T21	1		T12	150
valid_sources[0x3c]	5623	1			T12	169		T13	82		T32	1
valid_sources[0x3d]	5226	1			T12	168		T13	61		T104	1
valid_sources[0x3e]	5116	1			T11	9		T12	152		T13	72
valid_sources[0x3f]	6164	1			T1	1		T12	178		T13	90
valid_sources[0x40]	5928	1			T1	3		T12	154		T13	60
valid_sources[0x41]	5478	1			T12	133		T13	61		T14	154
valid_sources[0x42]	5974	1			T12	142		T13	79		T46	2
valid_sources[0x43]	5819	1			T12	152		T13	75		T14	177
valid_sources[0x44]	6522	1			T11	5		T12	196		T13	70
valid_sources[0x45]	5161	1			T21	1		T12	165		T13	77
valid_sources[0x46]	5602	1			T12	137		T13	77		T14	201
valid_sources[0x47]	4795	1			T2	2		T3	1		T12	158
valid_sources[0x48]	5426	1			T12	163		T13	67		T14	163
valid_sources[0x49]	6099	1			T12	194		T13	74		T14	170
valid_sources[0x4a]	5473	1			T2	3		T12	144		T13	84
valid_sources[0x4b]	5532	1			T12	160		T13	79		T104	1
valid_sources[0x4c]	6777	1			T12	171		T13	73		T124	3
valid_sources[0x4d]	5549	1			T12	195		T13	91		T14	196
valid_sources[0x4e]	6012	1			T11	2		T12	197		T13	80
valid_sources[0x4f]	5158	1			T12	124		T13	77		T104	1
valid_sources[0x50]	6370	1			T12	158		T13	88		T104	1
valid_sources[0x51]	6005	1			T12	183		T13	89		T37	1
valid_sources[0x52]	6776	1			T12	158		T13	100		T29	1
valid_sources[0x53]	6208	1			T12	207		T13	68		T37	2
valid_sources[0x54]	5576	1			T1	1		T7	2		T21	1
valid_sources[0x55]	5821	1			T1	1		T12	138		T13	100
valid_sources[0x56]	5152	1			T12	126		T13	71		T14	162
valid_sources[0x57]	5562	1			T12	150		T13	109		T14	146
valid_sources[0x58]	5109	1			T12	187		T13	92		T14	210
valid_sources[0x59]	6392	1			T12	163		T13	67		T104	1
valid_sources[0x5a]	6117	1			T11	27		T12	159		T13	51
valid_sources[0x5b]	6751	1			T12	160		T13	76		T20	1
valid_sources[0x5c]	6460	1			T21	1		T12	155		T13	85
valid_sources[0x5d]	5775	1			T7	11		T12	162		T13	84
valid_sources[0x5e]	5943	1			T12	190		T13	95		T14	160
valid_sources[0x5f]	6218	1			T7	4		T12	174		T13	71
valid_sources[0x60]	7185	1			T12	173		T13	92		T31	2
valid_sources[0x61]	5902	1			T12	169		T13	90		T30	1
valid_sources[0x62]	6605	1			T12	163		T13	82		T20	1
valid_sources[0x63]	6716	1			T12	189		T13	84		T37	1
valid_sources[0x64]	6110	1			T1	1		T7	2		T12	146
valid_sources[0x65]	7377	1			T12	154		T13	77		T14	185
valid_sources[0x66]	5833	1			T12	182		T13	95		T38	1
valid_sources[0x67]	6288	1			T12	144		T13	68		T24	1
valid_sources[0x68]	5288	1			T21	1		T12	165		T13	86
valid_sources[0x69]	6457	1			T2	2		T21	2		T12	165
valid_sources[0x6a]	5708	1			T7	2		T12	136		T13	73
valid_sources[0x6b]	6036	1			T12	174		T13	66		T104	1
valid_sources[0x6c]	5841	1			T12	152		T13	66		T20	1
valid_sources[0x6d]	6346	1			T12	164		T13	67		T20	1
valid_sources[0x6e]	6350	1			T1	1		T12	178		T13	82
valid_sources[0x6f]	6421	1			T12	183		T13	80		T24	2
valid_sources[0x70]	6411	1			T7	6		T11	9		T12	153
valid_sources[0x71]	4877	1			T1	1		T34	7		T12	171
valid_sources[0x72]	5823	1			T12	141		T13	91		T55	1
valid_sources[0x73]	5532	1			T12	164		T13	87		T14	143
valid_sources[0x74]	5149	1			T12	182		T13	67		T55	1
valid_sources[0x75]	6467	1			T12	180		T13	71		T14	170
valid_sources[0x76]	6543	1			T12	147		T13	52		T125	1
valid_sources[0x77]	6443	1			T12	157		T13	73		T124	4
valid_sources[0x78]	6130	1			T3	1		T12	139		T13	51
valid_sources[0x79]	5093	1			T7	2		T12	168		T13	72
valid_sources[0x7a]	5857	1			T21	1		T12	169		T13	53
valid_sources[0x7b]	5384	1			T2	6		T12	169		T13	57
valid_sources[0x7c]	6748	1			T7	6		T21	1		T12	154
valid_sources[0x7d]	7973	1			T1	1		T21	1		T12	165
valid_sources[0x7e]	6088	1			T12	155		T13	91		T14	182
valid_sources[0x7f]	5215	1			T1	1		T10	2		T12	174
valid_sources[0x80]	5800	1			T7	2		T21	1		T12	178

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

351056

1

T1

13

T2

18

T3

12

values[0x0]

all_enables

biggest_size

516535

1

T9

1

T34

2

T12

14388

values[0x1]

all_enables

biggest_size

515305

1

T10

1

T12

14231

T13

6683

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	316385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1361856

1

T1

6

T2

8

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	384575	1			T1	6		T2	73		T3	6
values[0x0]	535645	1			T12	14376		T13	8066		T14	17286
values[0x1]	758021	1			T12	20534		T13	11517		T14	24598

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1557953

1

T1

6

T2

49

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6012	1			T11	1		T21	2		T101	1
valid_sources[0x01]	7388	1			T2	1		T11	1		T18	2
valid_sources[0x02]	6777	1			T5	1		T11	2		T12	263
valid_sources[0x03]	6957	1			T2	1		T11	2		T12	321
valid_sources[0x04]	6636	1			T11	1		T12	176		T47	2
valid_sources[0x05]	6035	1			T11	1		T45	4		T47	1
valid_sources[0x06]	6212	1			T7	3		T12	315		T47	1
valid_sources[0x07]	6295	1			T2	1		T5	1		T11	1
valid_sources[0x08]	6741	1			T2	1		T12	567		T47	1
valid_sources[0x09]	6239	1			T11	1		T47	2		T65	2
valid_sources[0x0a]	6300	1			T5	1		T7	3		T11	1
valid_sources[0x0b]	6633	1			T2	1		T5	1		T7	1
valid_sources[0x0c]	6125	1			T5	2		T11	1		T45	2
valid_sources[0x0d]	7076	1			T5	1		T12	71		T19	1
valid_sources[0x0e]	6156	1			T5	1		T7	1		T11	1
valid_sources[0x0f]	6051	1			T7	1		T11	1		T12	217
valid_sources[0x10]	6378	1			T5	1		T18	1		T104	1
valid_sources[0x11]	6668	1			T2	1		T11	1		T12	119
valid_sources[0x12]	6779	1			T11	2		T13	504		T47	4
valid_sources[0x13]	6243	1			T2	2		T11	2		T12	107
valid_sources[0x14]	6300	1			T11	2		T21	10		T47	2
valid_sources[0x15]	6093	1			T7	1		T12	25		T104	1
valid_sources[0x16]	6116	1			T11	2		T13	211		T47	1
valid_sources[0x17]	6263	1			T2	1		T7	1		T11	2
valid_sources[0x18]	6292	1			T7	1		T11	3		T12	355
valid_sources[0x19]	6263	1			T5	2		T11	2		T47	1
valid_sources[0x1a]	6653	1			T2	1		T5	1		T12	176
valid_sources[0x1b]	6357	1			T11	2		T13	295		T45	14
valid_sources[0x1c]	5806	1			T1	1		T2	1		T12	15
valid_sources[0x1d]	6560	1			T11	1		T47	2		T19	1
valid_sources[0x1e]	7083	1			T5	1		T19	1		T101	2
valid_sources[0x1f]	6194	1			T5	1		T11	3		T12	233
valid_sources[0x20]	6493	1			T2	1		T11	1		T12	166
valid_sources[0x21]	5946	1			T5	1		T11	4		T47	1
valid_sources[0x22]	6334	1			T2	1		T5	1		T7	1
valid_sources[0x23]	6293	1			T11	2		T12	169		T13	46
valid_sources[0x24]	5747	1			T18	1		T47	2		T104	2
valid_sources[0x25]	8296	1			T12	194		T13	907		T19	1
valid_sources[0x26]	7065	1			T7	2		T11	2		T12	430
valid_sources[0x27]	7190	1			T3	1		T11	4		T47	3
valid_sources[0x28]	6820	1			T7	5		T11	1		T12	94
valid_sources[0x29]	6752	1			T2	1		T7	4		T11	1
valid_sources[0x2a]	5871	1			T2	1		T7	7		T11	1
valid_sources[0x2b]	5806	1			T5	1		T11	1		T47	1
valid_sources[0x2c]	8567	1			T2	1		T12	1421		T18	1
valid_sources[0x2d]	6812	1			T5	1		T7	6		T11	1
valid_sources[0x2e]	6632	1			T18	1		T47	1		T19	1
valid_sources[0x2f]	6286	1			T5	2		T11	2		T12	171
valid_sources[0x30]	6678	1			T5	1		T7	1		T12	764
valid_sources[0x31]	6407	1			T5	1		T11	1		T47	1
valid_sources[0x32]	7560	1			T2	1		T7	3		T11	3
valid_sources[0x33]	5989	1			T7	2		T12	41		T47	1
valid_sources[0x34]	6240	1			T102	1		T128	1		T66	9
valid_sources[0x35]	6234	1			T11	1		T12	340		T13	75
valid_sources[0x36]	6869	1			T12	58		T18	1		T47	1
valid_sources[0x37]	6358	1			T2	1		T7	2		T11	1
valid_sources[0x38]	6400	1			T7	3		T21	3		T12	286
valid_sources[0x39]	6959	1			T7	2		T11	1		T12	135
valid_sources[0x3a]	6478	1			T5	1		T11	1		T47	1
valid_sources[0x3b]	6294	1			T11	3		T12	373		T18	2
valid_sources[0x3c]	5943	1			T2	1		T5	1		T7	1
valid_sources[0x3d]	7101	1			T11	1		T13	130		T101	2
valid_sources[0x3e]	5797	1			T18	3		T45	1		T47	2
valid_sources[0x3f]	5836	1			T7	2		T104	1		T102	4
valid_sources[0x40]	6471	1			T11	3		T12	520		T45	3
valid_sources[0x41]	6191	1			T18	3		T13	13		T47	2
valid_sources[0x42]	8948	1			T11	1		T13	370		T65	2
valid_sources[0x43]	6214	1			T2	1		T13	132		T45	6
valid_sources[0x44]	6518	1			T7	2		T13	298		T47	1
valid_sources[0x45]	6389	1			T5	1		T11	1		T13	167
valid_sources[0x46]	6724	1			T7	5		T11	2		T12	381
valid_sources[0x47]	7440	1			T7	4		T11	2		T12	1599
valid_sources[0x48]	6223	1			T11	3		T13	242		T47	1
valid_sources[0x49]	6118	1			T7	1		T13	166		T47	1
valid_sources[0x4a]	6196	1			T11	2		T47	1		T102	1
valid_sources[0x4b]	6593	1			T7	2		T11	3		T13	356
valid_sources[0x4c]	6939	1			T5	1		T11	3		T12	10
valid_sources[0x4d]	6562	1			T5	2		T11	2		T47	2
valid_sources[0x4e]	6650	1			T12	679		T18	1		T45	7
valid_sources[0x4f]	6177	1			T2	1		T20	12		T101	2
valid_sources[0x50]	7267	1			T2	3		T7	8		T11	1
valid_sources[0x51]	7168	1			T5	1		T12	438		T13	177
valid_sources[0x52]	6464	1			T5	1		T11	2		T12	252
valid_sources[0x53]	5826	1			T7	6		T19	2		T101	3
valid_sources[0x54]	6843	1			T7	1		T12	592		T13	177
valid_sources[0x55]	6158	1			T2	1		T11	2		T12	390
valid_sources[0x56]	6305	1			T7	7		T11	2		T12	288
valid_sources[0x57]	6416	1			T7	3		T11	2		T12	418
valid_sources[0x58]	6650	1			T5	1		T11	2		T12	132
valid_sources[0x59]	6054	1			T2	1		T11	1		T21	13
valid_sources[0x5a]	6126	1			T11	1		T12	114		T18	1
valid_sources[0x5b]	5944	1			T5	1		T19	1		T104	1
valid_sources[0x5c]	7027	1			T7	2		T12	108		T65	1
valid_sources[0x5d]	6705	1			T5	1		T11	4		T12	346
valid_sources[0x5e]	9265	1			T2	2		T7	2		T11	3
valid_sources[0x5f]	7078	1			T5	1		T7	1		T12	537
valid_sources[0x60]	6026	1			T2	2		T11	1		T47	3
valid_sources[0x61]	6784	1			T7	2		T11	1		T12	198
valid_sources[0x62]	5672	1			T11	1		T18	3		T101	1
valid_sources[0x63]	6347	1			T7	2		T12	115		T47	2
valid_sources[0x64]	7206	1			T6	12		T12	259		T13	283
valid_sources[0x65]	6587	1			T5	1		T13	390		T47	3
valid_sources[0x66]	6598	1			T11	2		T104	2		T101	3
valid_sources[0x67]	6821	1			T5	1		T13	102		T47	1
valid_sources[0x68]	6413	1			T5	1		T11	1		T12	263
valid_sources[0x69]	7663	1			T11	1		T21	1		T12	1123
valid_sources[0x6a]	6320	1			T11	2		T18	1		T65	1
valid_sources[0x6b]	6366	1			T11	1		T45	18		T47	4
valid_sources[0x6c]	6967	1			T2	1		T13	185		T45	3
valid_sources[0x6d]	6631	1			T7	1		T47	2		T129	4
valid_sources[0x6e]	7019	1			T3	1		T5	1		T7	2
valid_sources[0x6f]	7411	1			T2	1		T7	3		T11	4
valid_sources[0x70]	6277	1			T5	1		T11	4		T13	160
valid_sources[0x71]	6064	1			T7	1		T11	1		T47	2
valid_sources[0x72]	6380	1			T11	2		T12	115		T45	5
valid_sources[0x73]	7494	1			T2	2		T5	1		T11	1
valid_sources[0x74]	6030	1			T11	4		T18	2		T45	1
valid_sources[0x75]	7548	1			T2	1		T11	1		T13	522
valid_sources[0x76]	5984	1			T2	1		T11	2		T12	161
valid_sources[0x77]	6201	1			T12	145		T47	2		T19	1
valid_sources[0x78]	6918	1			T1	2		T5	1		T11	2
valid_sources[0x79]	5946	1			T7	1		T11	2		T12	29
valid_sources[0x7a]	6134	1			T5	1		T7	1		T11	1
valid_sources[0x7b]	5819	1			T2	1		T5	1		T11	1
valid_sources[0x7c]	6576	1			T11	2		T12	148		T13	199
valid_sources[0x7d]	6795	1			T2	1		T12	39		T47	2
valid_sources[0x7e]	6366	1			T7	2		T47	2		T19	1
valid_sources[0x7f]	6085	1			T11	1		T47	1		T101	2
valid_sources[0x80]	7118	1			T11	1		T12	291		T47	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

343828

1

T1

6

T2

8

T3

6

values[0x0]

all_enables

biggest_size

509407

1

T12

13654

T13

7698

T14

16487

values[0x1]

all_enables

biggest_size

508621

1

T12

13506

T13

7530

T14

16780