Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3769578

1

T2

65

T5

80

T7

186

full_word

1629742

1

T1

4

T2

8

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5399040	1			T1	4		T2	73		T3	4
auto[TlIntgErrCmd]	110	1			T48	4		T49	7		T50	8
auto[TlIntgErrData]	83	1			T48	4		T49	7		T50	7
auto[TlIntgErrBoth]	87	1			T48	2		T49	6		T50	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657501

1

T1

4

T2

73

T3

4

auto[1]

4741819

1

T12

131601

T13

68992

T14

144024

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	281011	1			T2	65		T5	80		T7	186
auto[TlIntgErrNone]	partial	auto[1]	3488314	1			T12	97751		T13	50577		T14	103913
auto[TlIntgErrNone]	full_word	auto[0]	376345	1			T1	4		T2	8		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	1253370	1			T12	33850		T13	18415		T14	40111
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T48	2		T49	3		T50	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T48	2		T49	4		T50	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T50	2		T115	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T117	2		T118	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T48	2		T49	2		T50	4
auto[TlIntgErrData]	partial	auto[1]	33	1			T48	1		T49	5		T50	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T50	1		T113	2		T114	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T48	1		T50	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T48	1		T49	2		T50	3
auto[TlIntgErrBoth]	partial	auto[1]	34	1			T48	1		T49	3		T50	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T49	1		T113	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T109	1		T115	2		T120	1