Unified Coverage Report :: Module

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender	100.00	100.00					100.00

Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00	95.35		100.00	100.00	100.00	u_compare

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	217756957	217587650	0	0

OutputsKnown_A

Name	Attempts	Real Successes
Total	217756957	217587650
T1	248335	244590
T2	131234	131074
T3	311093	310895
T4	79217	76914
T5	99738	99608
T6	472696	472443
T7	739777	739416
T8	378809	378680
T9	16412	16348
T10	102666	102606