Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	107972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1096895

1

T1

38

T6

1

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	302495	1			T1	64		T2	1		T3	1
values[0x0]	418119	1			T7	7		T8	10750		T11	5
values[0x1]	484253	1			T7	6		T8	12233		T11	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1155952

1

T1

40

T6

1

T7

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4765	1			T1	1		T8	179		T20	2
valid_sources[0x01]	4262	1			T8	1		T79	6		T25	2
valid_sources[0x02]	5338	1			T1	1		T8	3		T9	1
valid_sources[0x03]	3819	1			T8	124		T47	1		T75	1
valid_sources[0x04]	3737	1			T8	60		T16	120		T17	161
valid_sources[0x05]	4688	1			T75	1		T16	329		T114	32
valid_sources[0x06]	6369	1			T1	1		T8	118		T75	1
valid_sources[0x07]	4670	1			T8	147		T16	332		T17	169
valid_sources[0x08]	4650	1			T8	6		T80	1		T16	355
valid_sources[0x09]	4350	1			T8	96		T21	1		T78	1
valid_sources[0x0a]	4919	1			T1	1		T8	2		T75	4
valid_sources[0x0b]	4484	1			T1	2		T75	1		T115	1
valid_sources[0x0c]	6001	1			T8	428		T10	1		T21	1
valid_sources[0x0d]	5222	1			T8	53		T78	2		T16	73
valid_sources[0x0e]	4925	1			T8	96		T16	579		T17	194
valid_sources[0x0f]	4770	1			T1	1		T8	83		T9	1
valid_sources[0x10]	4872	1			T75	1		T80	1		T16	399
valid_sources[0x11]	4225	1			T8	141		T20	1		T75	2
valid_sources[0x12]	4080	1			T8	5		T47	1		T28	2
valid_sources[0x13]	4179	1			T8	7		T76	3		T59	6
valid_sources[0x14]	4367	1			T8	98		T9	1		T16	130
valid_sources[0x15]	4639	1			T1	1		T8	455		T9	1
valid_sources[0x16]	4592	1			T1	1		T78	1		T115	1
valid_sources[0x17]	5419	1			T8	218		T9	2		T59	2
valid_sources[0x18]	4708	1			T8	3		T28	1		T80	1
valid_sources[0x19]	5335	1			T75	1		T59	1		T16	142
valid_sources[0x1a]	5161	1			T8	3		T9	1		T25	1
valid_sources[0x1b]	4698	1			T75	1		T16	281		T17	128
valid_sources[0x1c]	4149	1			T1	1		T9	1		T101	3
valid_sources[0x1d]	5060	1			T8	538		T20	4		T16	455
valid_sources[0x1e]	5429	1			T8	220		T115	1		T16	679
valid_sources[0x1f]	4877	1			T8	129		T10	2		T20	3
valid_sources[0x20]	4288	1			T8	21		T16	399		T116	1
valid_sources[0x21]	5234	1			T8	218		T16	291		T17	181
valid_sources[0x22]	5167	1			T1	1		T8	73		T25	1
valid_sources[0x23]	5455	1			T8	436		T10	1		T75	1
valid_sources[0x24]	4459	1			T1	1		T8	116		T115	2
valid_sources[0x25]	4016	1			T63	3		T28	1		T16	96
valid_sources[0x26]	4222	1			T10	1		T59	1		T115	1
valid_sources[0x27]	4901	1			T8	139		T59	6		T78	1
valid_sources[0x28]	4217	1			T8	17		T16	235		T17	199
valid_sources[0x29]	4064	1			T8	5		T10	1		T75	1
valid_sources[0x2a]	4859	1			T8	61		T75	1		T28	1
valid_sources[0x2b]	4122	1			T8	182		T80	1		T16	126
valid_sources[0x2c]	4761	1			T9	1		T101	1		T27	2
valid_sources[0x2d]	4355	1			T8	8		T16	255		T117	1
valid_sources[0x2e]	4255	1			T80	2		T16	91		T44	1
valid_sources[0x2f]	5311	1			T16	157		T17	235		T118	1
valid_sources[0x30]	4946	1			T8	388		T16	7		T17	222
valid_sources[0x31]	4125	1			T8	93		T75	1		T78	1
valid_sources[0x32]	4556	1			T8	187		T78	1		T79	2
valid_sources[0x33]	4977	1			T75	1		T25	2		T80	1
valid_sources[0x34]	4542	1			T16	239		T116	1		T17	93
valid_sources[0x35]	4347	1			T16	221		T116	1		T17	201
valid_sources[0x36]	4805	1			T8	86		T75	1		T16	314
valid_sources[0x37]	4855	1			T1	1		T8	4		T9	1
valid_sources[0x38]	5379	1			T9	1		T16	538		T17	122
valid_sources[0x39]	4295	1			T1	1		T16	321		T116	2
valid_sources[0x3a]	3951	1			T76	2		T78	1		T16	106
valid_sources[0x3b]	5379	1			T8	209		T101	1		T16	388
valid_sources[0x3c]	4084	1			T8	18		T28	1		T16	62
valid_sources[0x3d]	4689	1			T8	237		T16	27		T29	1
valid_sources[0x3e]	5621	1			T1	1		T8	277		T75	1
valid_sources[0x3f]	5071	1			T8	166		T16	187		T119	1
valid_sources[0x40]	4104	1			T8	1		T10	1		T16	220
valid_sources[0x41]	4776	1			T8	19		T21	1		T47	1
valid_sources[0x42]	5918	1			T1	1		T8	140		T75	1
valid_sources[0x43]	4494	1			T78	1		T101	7		T16	591
valid_sources[0x44]	5608	1			T8	772		T28	1		T80	1
valid_sources[0x45]	4523	1			T8	12		T101	1		T16	131
valid_sources[0x46]	4909	1			T8	136		T9	2		T76	4
valid_sources[0x47]	4284	1			T8	201		T16	230		T116	2
valid_sources[0x48]	4652	1			T8	13		T27	1		T16	724
valid_sources[0x49]	4722	1			T1	1		T8	82		T21	1
valid_sources[0x4a]	4622	1			T78	1		T16	222		T119	1
valid_sources[0x4b]	4119	1			T16	339		T17	149		T49	1
valid_sources[0x4c]	4516	1			T1	1		T8	10		T62	17
valid_sources[0x4d]	4636	1			T8	74		T20	17		T115	1
valid_sources[0x4e]	3805	1			T1	1		T8	82		T78	3
valid_sources[0x4f]	4614	1			T1	1		T75	1		T16	312
valid_sources[0x50]	4850	1			T1	1		T8	8		T75	1
valid_sources[0x51]	4611	1			T8	69		T28	1		T16	181
valid_sources[0x52]	4442	1			T76	2		T78	3		T16	441
valid_sources[0x53]	3625	1			T9	1		T63	4		T28	1
valid_sources[0x54]	4340	1			T8	329		T16	18		T17	217
valid_sources[0x55]	3901	1			T3	1		T8	416		T75	2
valid_sources[0x56]	6204	1			T8	285		T59	4		T16	467
valid_sources[0x57]	5202	1			T8	559		T75	2		T16	238
valid_sources[0x58]	4441	1			T115	1		T16	177		T45	2
valid_sources[0x59]	5068	1			T1	1		T59	1		T16	413
valid_sources[0x5a]	4391	1			T8	227		T28	1		T16	199
valid_sources[0x5b]	5182	1			T8	454		T48	9		T16	77
valid_sources[0x5c]	4425	1			T8	151		T75	2		T78	2
valid_sources[0x5d]	4151	1			T8	19		T21	1		T59	1
valid_sources[0x5e]	5117	1			T8	14		T75	1		T16	175
valid_sources[0x5f]	5461	1			T101	1		T16	671		T116	1
valid_sources[0x60]	5530	1			T8	164		T9	1		T75	1
valid_sources[0x61]	5380	1			T1	1		T78	1		T27	1
valid_sources[0x62]	4782	1			T8	30		T10	2		T16	344
valid_sources[0x63]	4995	1			T1	1		T8	119		T76	4
valid_sources[0x64]	4504	1			T1	1		T8	206		T101	1
valid_sources[0x65]	4503	1			T16	425		T17	109		T49	245
valid_sources[0x66]	5846	1			T8	411		T75	2		T16	595
valid_sources[0x67]	4558	1			T2	1		T59	2		T16	265
valid_sources[0x68]	3975	1			T8	2		T101	2		T16	357
valid_sources[0x69]	4899	1			T8	285		T78	1		T101	1
valid_sources[0x6a]	4095	1			T75	1		T16	156		T116	3
valid_sources[0x6b]	5103	1			T10	3		T75	1		T16	333
valid_sources[0x6c]	4331	1			T8	71		T16	25		T120	1
valid_sources[0x6d]	3454	1			T8	3		T59	1		T92	128
valid_sources[0x6e]	4867	1			T1	1		T8	2		T15	19
valid_sources[0x6f]	4301	1			T75	1		T78	1		T16	126
valid_sources[0x70]	5036	1			T8	286		T21	1		T59	2
valid_sources[0x71]	4229	1			T1	1		T8	2		T75	1
valid_sources[0x72]	4599	1			T9	1		T76	1		T16	180
valid_sources[0x73]	4118	1			T8	19		T75	1		T16	263
valid_sources[0x74]	4764	1			T8	238		T75	1		T80	1
valid_sources[0x75]	5187	1			T8	304		T75	1		T48	3
valid_sources[0x76]	4580	1			T8	209		T19	32		T16	220
valid_sources[0x77]	4604	1			T101	1		T16	171		T116	1
valid_sources[0x78]	4835	1			T8	99		T64	1		T16	248
valid_sources[0x79]	5472	1			T115	1		T16	621		T17	157
valid_sources[0x7a]	4307	1			T76	4		T16	291		T17	256
valid_sources[0x7b]	4678	1			T8	107		T9	2		T75	1
valid_sources[0x7c]	4191	1			T1	1		T8	299		T101	1
valid_sources[0x7d]	4518	1			T8	57		T10	1		T75	1
valid_sources[0x7e]	3965	1			T115	2		T16	397		T119	1
valid_sources[0x7f]	4824	1			T8	118		T76	2		T27	1
valid_sources[0x80]	3904	1			T27	1		T115	1		T16	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

277814

1

T1

38

T6

1

T8

7047

values[0x0]

all_enables

biggest_size

409541

1

T7

2

T8

10549

T11

2

values[0x1]

all_enables

biggest_size

409540

1

T7

1

T8

10398

T11

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	252714	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1080151

1

T1

9

T4

2

T5

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	305748	1			T1	125		T4	58		T5	258
values[0x0]	424813	1			T8	10089		T16	26197		T17	15717
values[0x1]	602304	1			T8	14031		T16	36339		T17	22507

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	96519	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1236346

1

T1

71

T4

33

T5

153

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5138	1			T8	139		T19	2		T16	295
valid_sources[0x01]	4726	1			T8	108		T59	4		T91	2
valid_sources[0x02]	4993	1			T1	1		T8	123		T10	2
valid_sources[0x03]	5253	1			T8	105		T19	1		T59	1
valid_sources[0x04]	5280	1			T8	97		T19	1		T100	1
valid_sources[0x05]	4963	1			T8	166		T19	1		T59	1
valid_sources[0x06]	4986	1			T1	1		T8	110		T76	4
valid_sources[0x07]	5708	1			T1	1		T4	1		T8	94
valid_sources[0x08]	5727	1			T8	90		T19	1		T59	1
valid_sources[0x09]	5287	1			T1	1		T4	1		T8	105
valid_sources[0x0a]	5319	1			T1	1		T8	95		T76	2
valid_sources[0x0b]	5619	1			T1	1		T5	20		T8	133
valid_sources[0x0c]	5307	1			T8	143		T14	1		T16	319
valid_sources[0x0d]	6120	1			T8	137		T33	2		T59	2
valid_sources[0x0e]	5201	1			T1	1		T8	107		T19	1
valid_sources[0x0f]	5040	1			T1	1		T8	136		T19	1
valid_sources[0x10]	5254	1			T4	1		T5	10		T8	145
valid_sources[0x11]	5349	1			T8	119		T33	2		T59	1
valid_sources[0x12]	5004	1			T1	1		T8	124		T75	2
valid_sources[0x13]	5109	1			T8	122		T10	2		T59	2
valid_sources[0x14]	4856	1			T1	1		T8	125		T19	1
valid_sources[0x15]	4966	1			T1	1		T4	1		T8	104
valid_sources[0x16]	5156	1			T8	94		T76	2		T59	1
valid_sources[0x17]	5589	1			T8	97		T19	2		T14	1
valid_sources[0x18]	4992	1			T8	134		T10	3		T75	11
valid_sources[0x19]	5173	1			T8	98		T10	1		T59	1
valid_sources[0x1a]	4928	1			T8	122		T101	1		T115	1
valid_sources[0x1b]	4953	1			T8	156		T19	1		T33	1
valid_sources[0x1c]	4971	1			T1	1		T4	1		T8	128
valid_sources[0x1d]	4932	1			T8	155		T115	1		T16	311
valid_sources[0x1e]	5835	1			T8	109		T59	2		T92	9
valid_sources[0x1f]	4946	1			T1	1		T8	131		T19	1
valid_sources[0x20]	5539	1			T8	137		T92	3		T16	344
valid_sources[0x21]	5037	1			T1	1		T8	143		T12	2
valid_sources[0x22]	5204	1			T4	1		T8	85		T59	1
valid_sources[0x23]	5647	1			T4	1		T8	100		T59	1
valid_sources[0x24]	5085	1			T8	149		T10	1		T101	1
valid_sources[0x25]	5197	1			T8	102		T59	1		T91	16
valid_sources[0x26]	5423	1			T1	2		T8	99		T10	1
valid_sources[0x27]	5462	1			T1	1		T8	180		T59	1
valid_sources[0x28]	5122	1			T4	1		T8	115		T101	1
valid_sources[0x29]	5311	1			T8	91		T75	4		T76	2
valid_sources[0x2a]	5075	1			T1	3		T8	112		T75	8
valid_sources[0x2b]	5856	1			T1	1		T4	1		T8	116
valid_sources[0x2c]	4829	1			T1	1		T8	139		T10	1
valid_sources[0x2d]	4926	1			T1	2		T8	137		T19	2
valid_sources[0x2e]	5309	1			T8	145		T19	1		T59	3
valid_sources[0x2f]	5396	1			T1	3		T8	110		T19	1
valid_sources[0x30]	5277	1			T1	1		T8	135		T101	1
valid_sources[0x31]	5380	1			T8	118		T33	1		T115	1
valid_sources[0x32]	4859	1			T4	1		T8	84		T59	2
valid_sources[0x33]	6338	1			T8	154		T19	1		T75	1
valid_sources[0x34]	5100	1			T1	2		T8	133		T12	6
valid_sources[0x35]	5026	1			T8	142		T10	2		T33	1
valid_sources[0x36]	5064	1			T1	1		T8	135		T19	1
valid_sources[0x37]	5928	1			T1	2		T8	93		T75	9
valid_sources[0x38]	5810	1			T8	150		T10	4		T19	1
valid_sources[0x39]	4831	1			T8	123		T10	3		T14	6
valid_sources[0x3a]	5339	1			T1	1		T8	91		T10	6
valid_sources[0x3b]	5262	1			T8	149		T12	4		T76	3
valid_sources[0x3c]	5136	1			T8	116		T12	5		T59	2
valid_sources[0x3d]	5128	1			T8	115		T10	3		T75	1
valid_sources[0x3e]	5283	1			T8	121		T33	2		T100	1
valid_sources[0x3f]	6500	1			T1	1		T8	117		T75	2
valid_sources[0x40]	5334	1			T8	144		T16	348		T121	2
valid_sources[0x41]	5179	1			T1	1		T8	119		T10	1
valid_sources[0x42]	5515	1			T4	2		T8	123		T33	1
valid_sources[0x43]	5466	1			T8	124		T10	1		T59	1
valid_sources[0x44]	4947	1			T8	101		T59	1		T100	1
valid_sources[0x45]	4716	1			T8	109		T115	1		T92	1
valid_sources[0x46]	5973	1			T8	113		T33	1		T75	1
valid_sources[0x47]	5075	1			T8	116		T59	1		T100	1
valid_sources[0x48]	5109	1			T8	129		T77	2		T91	7
valid_sources[0x49]	5229	1			T8	79		T10	2		T19	2
valid_sources[0x4a]	5079	1			T1	1		T8	137		T33	2
valid_sources[0x4b]	5118	1			T1	1		T8	133		T33	1
valid_sources[0x4c]	5406	1			T1	1		T4	1		T8	150
valid_sources[0x4d]	5290	1			T8	139		T33	1		T92	2
valid_sources[0x4e]	4959	1			T1	1		T8	158		T75	6
valid_sources[0x4f]	5094	1			T1	2		T8	135		T75	1
valid_sources[0x50]	5230	1			T1	1		T8	107		T59	2
valid_sources[0x51]	5189	1			T8	147		T59	1		T115	1
valid_sources[0x52]	6095	1			T8	141		T75	4		T77	3
valid_sources[0x53]	5364	1			T8	81		T59	2		T101	1
valid_sources[0x54]	5868	1			T1	1		T8	140		T19	1
valid_sources[0x55]	5428	1			T1	1		T8	120		T19	1
valid_sources[0x56]	4761	1			T8	120		T59	1		T77	1
valid_sources[0x57]	6401	1			T4	2		T8	138		T10	1
valid_sources[0x58]	5251	1			T8	136		T19	1		T16	293
valid_sources[0x59]	5752	1			T1	1		T8	141		T100	3
valid_sources[0x5a]	4850	1			T8	115		T59	1		T27	5
valid_sources[0x5b]	4595	1			T8	89		T115	1		T92	2
valid_sources[0x5c]	5064	1			T8	105		T10	1		T59	1
valid_sources[0x5d]	5367	1			T8	97		T59	1		T100	2
valid_sources[0x5e]	4731	1			T4	1		T8	114		T100	2
valid_sources[0x5f]	4800	1			T1	1		T8	106		T10	1
valid_sources[0x60]	5878	1			T8	92		T10	2		T76	1
valid_sources[0x61]	5191	1			T8	110		T33	1		T59	1
valid_sources[0x62]	4753	1			T8	114		T115	2		T91	1
valid_sources[0x63]	5371	1			T4	1		T8	101		T10	1
valid_sources[0x64]	4945	1			T8	104		T10	2		T59	1
valid_sources[0x65]	4973	1			T1	1		T5	22		T8	129
valid_sources[0x66]	4699	1			T4	2		T8	83		T12	1
valid_sources[0x67]	5177	1			T1	1		T5	22		T8	114
valid_sources[0x68]	5379	1			T4	1		T8	144		T59	2
valid_sources[0x69]	5132	1			T8	145		T19	1		T59	1
valid_sources[0x6a]	5169	1			T1	1		T8	157		T59	1
valid_sources[0x6b]	5127	1			T8	89		T59	1		T80	1
valid_sources[0x6c]	4724	1			T1	1		T8	113		T33	1
valid_sources[0x6d]	4821	1			T8	113		T33	1		T59	1
valid_sources[0x6e]	4872	1			T8	98		T19	1		T33	1
valid_sources[0x6f]	5182	1			T8	102		T10	1		T75	3
valid_sources[0x70]	4779	1			T1	1		T8	94		T75	7
valid_sources[0x71]	5202	1			T1	1		T8	162		T19	2
valid_sources[0x72]	5484	1			T8	119		T92	1		T80	2
valid_sources[0x73]	5069	1			T1	1		T8	162		T10	1
valid_sources[0x74]	5205	1			T8	106		T19	1		T76	5
valid_sources[0x75]	4865	1			T1	1		T8	120		T19	1
valid_sources[0x76]	5005	1			T1	1		T8	162		T12	3
valid_sources[0x77]	6082	1			T8	136		T10	1		T59	1
valid_sources[0x78]	5386	1			T1	1		T8	135		T33	1
valid_sources[0x79]	4708	1			T8	131		T19	2		T33	1
valid_sources[0x7a]	4931	1			T1	1		T8	132		T12	2
valid_sources[0x7b]	5126	1			T8	125		T59	1		T91	5
valid_sources[0x7c]	4723	1			T8	131		T115	2		T48	1
valid_sources[0x7d]	5130	1			T4	2		T8	126		T19	1
valid_sources[0x7e]	5176	1			T1	1		T8	157		T19	2
valid_sources[0x7f]	5746	1			T8	145		T59	3		T79	8
valid_sources[0x80]	4611	1			T8	137		T10	2		T75	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

271940

1

T1

9

T4

2

T5

22

values[0x0]

all_enables

biggest_size

404110

1

T8

9598

T16

24995

T17

14936

values[0x1]

all_enables

biggest_size

404101

1

T8

9461

T16

25327

T17

15084