Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3023828

1

T1

116

T4

56

T5

236

full_word

1295560

1

T1

9

T4

2

T5

22

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4319058	1			T1	125		T4	58		T5	258
auto[TlIntgErrCmd]	100	1			T56	8		T57	5		T58	4
auto[TlIntgErrData]	117	1			T56	3		T57	9		T58	10
auto[TlIntgErrBoth]	113	1			T56	9		T57	6		T58	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

528401

1

T1

125

T4

58

T5

258

auto[1]

3790987

1

T8

89908

T16

220077

T17

146835

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	229577	1			T1	116		T4	56		T5	236
auto[TlIntgErrNone]	partial	auto[1]	2793946	1			T8	66301		T16	159073		T17	109325
auto[TlIntgErrNone]	full_word	auto[0]	298671	1			T1	9		T4	2		T5	22
auto[TlIntgErrNone]	full_word	auto[1]	996864	1			T8	23607		T16	61004		T17	37510
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T56	5		T57	3		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T56	1		T57	2		T58	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T56	1		T108	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T56	1		T108	1		T109	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T56	3		T57	5		T58	6
auto[TlIntgErrData]	partial	auto[1]	50	1			T57	4		T58	3		T106	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T58	1		T104	2		T107	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T110	1		T111	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T56	1		T57	3		T58	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T56	8		T57	3		T58	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T108	2		T112	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T58	1		T107	1		T113	1