Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130265	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1298379

1

T3

8

T4

39

T5

29591

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	357208	1			T3	27		T4	64		T5	8137
values[0x0]	494668	1			T5	11213		T7	3		T8	5
values[0x1]	576768	1			T5	13012		T8	5		T33	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58372	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1370272

1

T3

14

T4

45

T5

31125

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5812	1			T5	129		T11	269		T12	209
valid_sources[0x01]	5931	1			T4	2		T5	150		T9	1
valid_sources[0x02]	5017	1			T5	102		T60	4		T11	589
valid_sources[0x03]	5014	1			T5	123		T11	7		T109	3
valid_sources[0x04]	5336	1			T5	133		T11	499		T109	20
valid_sources[0x05]	6574	1			T5	113		T60	1		T20	3
valid_sources[0x06]	5008	1			T5	120		T11	482		T41	1
valid_sources[0x07]	5148	1			T5	112		T11	252		T12	280
valid_sources[0x08]	6039	1			T4	1		T5	133		T11	1171
valid_sources[0x09]	5660	1			T5	126		T11	781		T41	1
valid_sources[0x0a]	5057	1			T5	128		T10	1		T15	1
valid_sources[0x0b]	5564	1			T5	140		T11	368		T12	151
valid_sources[0x0c]	6206	1			T5	125		T11	959		T41	2
valid_sources[0x0d]	5839	1			T5	175		T11	914		T44	1
valid_sources[0x0e]	5796	1			T5	148		T57	1		T11	422
valid_sources[0x0f]	5361	1			T5	133		T11	839		T21	1
valid_sources[0x10]	6499	1			T5	151		T11	1067		T12	287
valid_sources[0x11]	5518	1			T4	1		T5	157		T11	343
valid_sources[0x12]	5906	1			T5	114		T20	1		T11	1070
valid_sources[0x13]	6026	1			T3	1		T5	144		T11	1059
valid_sources[0x14]	5887	1			T5	126		T15	1		T11	1030
valid_sources[0x15]	5392	1			T4	1		T5	142		T11	538
valid_sources[0x16]	5329	1			T5	112		T11	466		T110	1
valid_sources[0x17]	5813	1			T4	2		T5	137		T11	678
valid_sources[0x18]	6500	1			T4	1		T5	154		T11	767
valid_sources[0x19]	5074	1			T5	129		T11	474		T111	1
valid_sources[0x1a]	5959	1			T5	109		T11	442		T112	1
valid_sources[0x1b]	5722	1			T4	1		T5	117		T11	680
valid_sources[0x1c]	4767	1			T5	139		T11	86		T25	1
valid_sources[0x1d]	4956	1			T5	118		T9	1		T34	1
valid_sources[0x1e]	5541	1			T5	116		T9	1		T15	1
valid_sources[0x1f]	5767	1			T3	1		T5	138		T11	736
valid_sources[0x20]	5587	1			T5	114		T11	734		T39	2
valid_sources[0x21]	5650	1			T5	160		T11	426		T37	1
valid_sources[0x22]	5531	1			T5	138		T11	422		T25	4
valid_sources[0x23]	5211	1			T5	124		T11	471		T39	1
valid_sources[0x24]	5924	1			T5	136		T11	829		T21	1
valid_sources[0x25]	5001	1			T5	128		T9	1		T15	1
valid_sources[0x26]	5013	1			T5	132		T11	461		T12	240
valid_sources[0x27]	5904	1			T5	97		T15	1		T11	1361
valid_sources[0x28]	5545	1			T5	154		T20	1		T11	667
valid_sources[0x29]	4665	1			T5	127		T11	296		T37	1
valid_sources[0x2a]	5737	1			T4	1		T5	143		T14	32
valid_sources[0x2b]	5543	1			T5	109		T15	2		T11	127
valid_sources[0x2c]	5668	1			T5	150		T9	1		T11	433
valid_sources[0x2d]	4303	1			T5	132		T11	219		T12	132
valid_sources[0x2e]	5621	1			T5	105		T11	558		T21	1
valid_sources[0x2f]	5718	1			T5	154		T10	1		T11	781
valid_sources[0x30]	6429	1			T3	1		T5	140		T60	1
valid_sources[0x31]	7089	1			T5	104		T10	1		T11	1387
valid_sources[0x32]	6494	1			T4	1		T5	138		T11	559
valid_sources[0x33]	6194	1			T4	1		T5	145		T11	966
valid_sources[0x34]	5177	1			T5	149		T10	2		T11	539
valid_sources[0x35]	5168	1			T4	1		T5	138		T15	1
valid_sources[0x36]	5665	1			T5	121		T11	1308		T12	90
valid_sources[0x37]	5822	1			T5	129		T11	964		T38	6
valid_sources[0x38]	5094	1			T5	119		T11	242		T41	1
valid_sources[0x39]	5517	1			T5	131		T10	2		T33	1
valid_sources[0x3a]	6240	1			T5	120		T11	1070		T110	1
valid_sources[0x3b]	6018	1			T5	111		T7	1		T11	558
valid_sources[0x3c]	5633	1			T5	113		T34	2		T11	724
valid_sources[0x3d]	6340	1			T3	3		T5	134		T10	1
valid_sources[0x3e]	5673	1			T5	119		T11	551		T12	143
valid_sources[0x3f]	4962	1			T5	130		T11	689		T23	1
valid_sources[0x40]	5572	1			T5	124		T11	662		T37	1
valid_sources[0x41]	5069	1			T5	117		T11	939		T110	2
valid_sources[0x42]	5572	1			T5	128		T11	593		T112	1
valid_sources[0x43]	5826	1			T3	2		T5	146		T10	1
valid_sources[0x44]	5481	1			T3	1		T5	112		T9	1
valid_sources[0x45]	6297	1			T5	109		T11	1363		T113	1
valid_sources[0x46]	5403	1			T5	101		T11	650		T72	1
valid_sources[0x47]	5830	1			T5	118		T60	1		T11	830
valid_sources[0x48]	6060	1			T5	98		T11	623		T12	241
valid_sources[0x49]	5776	1			T5	126		T9	1		T11	984
valid_sources[0x4a]	5917	1			T5	129		T11	722		T12	255
valid_sources[0x4b]	5601	1			T5	140		T11	910		T12	140
valid_sources[0x4c]	4112	1			T5	90		T11	18		T21	1
valid_sources[0x4d]	5901	1			T4	1		T5	120		T9	1
valid_sources[0x4e]	5440	1			T5	141		T11	1132		T12	164
valid_sources[0x4f]	6073	1			T5	108		T7	1		T11	524
valid_sources[0x50]	5324	1			T5	95		T11	472		T38	6
valid_sources[0x51]	5247	1			T5	121		T9	2		T11	258
valid_sources[0x52]	5622	1			T5	142		T11	577		T12	151
valid_sources[0x53]	7128	1			T5	141		T20	1		T11	1890
valid_sources[0x54]	6331	1			T3	1		T5	119		T9	1
valid_sources[0x55]	5012	1			T5	105		T11	784		T110	1
valid_sources[0x56]	5455	1			T5	151		T11	267		T37	1
valid_sources[0x57]	5523	1			T4	3		T5	127		T11	702
valid_sources[0x58]	5332	1			T3	1		T5	134		T11	322
valid_sources[0x59]	5331	1			T5	155		T60	4		T11	656
valid_sources[0x5a]	4876	1			T5	117		T20	1		T11	497
valid_sources[0x5b]	6292	1			T5	106		T15	2		T57	2
valid_sources[0x5c]	5310	1			T4	1		T5	134		T11	488
valid_sources[0x5d]	4852	1			T5	119		T11	111		T12	174
valid_sources[0x5e]	5788	1			T4	2		T5	141		T11	993
valid_sources[0x5f]	5364	1			T5	124		T11	1017		T37	2
valid_sources[0x60]	5027	1			T5	128		T10	1		T11	372
valid_sources[0x61]	5451	1			T4	2		T5	131		T11	1182
valid_sources[0x62]	4931	1			T5	138		T11	273		T111	1
valid_sources[0x63]	6199	1			T4	1		T5	122		T11	1141
valid_sources[0x64]	5122	1			T5	128		T9	2		T10	2
valid_sources[0x65]	4603	1			T5	111		T11	530		T12	34
valid_sources[0x66]	5581	1			T3	1		T5	123		T11	871
valid_sources[0x67]	5564	1			T5	140		T9	1		T15	1
valid_sources[0x68]	5170	1			T4	1		T5	113		T10	1
valid_sources[0x69]	5818	1			T5	94		T11	778		T110	1
valid_sources[0x6a]	5550	1			T5	151		T11	601		T21	1
valid_sources[0x6b]	5809	1			T4	1		T5	145		T34	1
valid_sources[0x6c]	6548	1			T5	130		T11	1322		T41	5
valid_sources[0x6d]	5121	1			T5	130		T11	97		T12	55
valid_sources[0x6e]	6447	1			T5	127		T11	604		T12	155
valid_sources[0x6f]	5316	1			T4	1		T5	114		T11	944
valid_sources[0x70]	5135	1			T5	133		T9	1		T11	670
valid_sources[0x71]	4984	1			T5	132		T6	32		T11	215
valid_sources[0x72]	5340	1			T5	139		T11	356		T12	217
valid_sources[0x73]	5668	1			T5	118		T11	239		T37	1
valid_sources[0x74]	6463	1			T4	1		T5	101		T20	1
valid_sources[0x75]	5566	1			T5	138		T10	1		T11	602
valid_sources[0x76]	5759	1			T4	3		T5	114		T10	2
valid_sources[0x77]	5127	1			T5	101		T57	1		T11	387
valid_sources[0x78]	5631	1			T5	126		T20	2		T11	1180
valid_sources[0x79]	6225	1			T4	1		T5	137		T11	1031
valid_sources[0x7a]	6395	1			T4	1		T5	106		T9	1
valid_sources[0x7b]	5072	1			T5	117		T11	666		T12	133
valid_sources[0x7c]	5600	1			T5	120		T11	603		T72	1
valid_sources[0x7d]	5909	1			T5	118		T11	1075		T44	1
valid_sources[0x7e]	5866	1			T5	106		T15	1		T11	374
valid_sources[0x7f]	5307	1			T5	122		T9	1		T11	711
valid_sources[0x80]	5271	1			T5	129		T11	408		T12	230

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

328565

1

T3

8

T4

39

T5

7571

values[0x0]

all_enables

biggest_size

484401

1

T5

10971

T8

1

T34

2

values[0x1]

all_enables

biggest_size

485413

1

T5

11049

T11

59497

T43

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	294148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1296955

1

T1

21

T2

3

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	361864	1			T1	207		T2	51		T3	3
values[0x0]	508537	1			T5	11957		T11	63683		T12	14666
values[0x1]	720702	1			T5	17238		T11	90544		T12	20923

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	111733	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1479370

1

T1

117

T2

24

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7039	1			T4	2		T5	162		T6	1
valid_sources[0x01]	5966	1			T5	137		T9	1		T15	2
valid_sources[0x02]	6543	1			T5	173		T63	2		T95	3
valid_sources[0x03]	6422	1			T5	145		T10	1		T63	2
valid_sources[0x04]	7709	1			T5	155		T63	3		T14	2
valid_sources[0x05]	6132	1			T5	157		T10	1		T63	3
valid_sources[0x06]	6348	1			T4	1		T5	142		T63	3
valid_sources[0x07]	5621	1			T4	1		T5	152		T6	1
valid_sources[0x08]	5647	1			T5	112		T63	2		T11	825
valid_sources[0x09]	6461	1			T5	124		T6	1		T9	1
valid_sources[0x0a]	6182	1			T4	4		T5	140		T63	2
valid_sources[0x0b]	5937	1			T5	147		T9	1		T15	2
valid_sources[0x0c]	7166	1			T4	2		T5	145		T16	15
valid_sources[0x0d]	6155	1			T5	142		T6	2		T10	1
valid_sources[0x0e]	6227	1			T4	2		T5	140		T15	1
valid_sources[0x0f]	6839	1			T4	1		T5	152		T9	2
valid_sources[0x10]	6173	1			T4	1		T5	153		T10	1
valid_sources[0x11]	6588	1			T4	1		T5	147		T9	1
valid_sources[0x12]	5824	1			T5	128		T10	1		T63	1
valid_sources[0x13]	6193	1			T4	1		T5	141		T15	5
valid_sources[0x14]	5987	1			T5	160		T63	1		T14	2
valid_sources[0x15]	7497	1			T5	132		T11	784		T114	6
valid_sources[0x16]	5957	1			T4	2		T5	138		T63	2
valid_sources[0x17]	6078	1			T4	1		T5	150		T6	1
valid_sources[0x18]	5923	1			T5	135		T11	693		T12	156
valid_sources[0x19]	6295	1			T5	156		T63	1		T11	752
valid_sources[0x1a]	6086	1			T5	160		T63	1		T11	828
valid_sources[0x1b]	7376	1			T5	130		T63	2		T11	733
valid_sources[0x1c]	5813	1			T5	157		T63	1		T11	757
valid_sources[0x1d]	6659	1			T5	142		T6	1		T63	3
valid_sources[0x1e]	6205	1			T1	11		T4	1		T5	159
valid_sources[0x1f]	5496	1			T5	151		T9	5		T10	1
valid_sources[0x20]	6528	1			T4	1		T5	147		T63	3
valid_sources[0x21]	6088	1			T5	129		T60	1		T11	738
valid_sources[0x22]	5857	1			T4	2		T5	148		T6	2
valid_sources[0x23]	5352	1			T5	125		T10	1		T63	1
valid_sources[0x24]	7110	1			T5	168		T10	1		T14	1
valid_sources[0x25]	5586	1			T4	1		T5	150		T6	1
valid_sources[0x26]	5550	1			T5	129		T11	814		T73	1
valid_sources[0x27]	7150	1			T5	159		T63	1		T14	2
valid_sources[0x28]	6809	1			T5	162		T63	1		T60	1
valid_sources[0x29]	6913	1			T4	1		T5	139		T10	1
valid_sources[0x2a]	5233	1			T5	138		T11	743		T12	157
valid_sources[0x2b]	5829	1			T1	4		T5	156		T63	2
valid_sources[0x2c]	5789	1			T3	3		T5	146		T63	1
valid_sources[0x2d]	6322	1			T1	3		T5	147		T11	770
valid_sources[0x2e]	6669	1			T4	1		T5	143		T6	1
valid_sources[0x2f]	6146	1			T4	1		T5	155		T11	749
valid_sources[0x30]	6087	1			T4	1		T5	156		T6	1
valid_sources[0x31]	6742	1			T4	1		T5	134		T6	1
valid_sources[0x32]	6136	1			T4	2		T5	163		T63	2
valid_sources[0x33]	5455	1			T5	139		T63	1		T11	789
valid_sources[0x34]	6175	1			T5	167		T9	1		T63	1
valid_sources[0x35]	6773	1			T5	137		T10	1		T63	2
valid_sources[0x36]	5960	1			T5	171		T11	751		T110	2
valid_sources[0x37]	6421	1			T4	1		T5	158		T10	1
valid_sources[0x38]	5794	1			T5	164		T63	1		T11	785
valid_sources[0x39]	5869	1			T4	1		T5	132		T95	11
valid_sources[0x3a]	6727	1			T5	164		T14	1		T11	728
valid_sources[0x3b]	6407	1			T5	134		T9	1		T63	1
valid_sources[0x3c]	6238	1			T5	162		T6	1		T9	1
valid_sources[0x3d]	6222	1			T5	151		T6	3		T63	1
valid_sources[0x3e]	5956	1			T4	1		T5	156		T10	1
valid_sources[0x3f]	6198	1			T5	135		T6	2		T10	1
valid_sources[0x40]	5813	1			T4	1		T5	151		T9	3
valid_sources[0x41]	6781	1			T5	157		T11	789		T110	6
valid_sources[0x42]	6680	1			T5	165		T10	1		T63	2
valid_sources[0x43]	6378	1			T5	121		T9	1		T63	2
valid_sources[0x44]	5764	1			T4	1		T5	180		T6	2
valid_sources[0x45]	5722	1			T5	148		T10	1		T11	718
valid_sources[0x46]	5811	1			T4	1		T5	136		T15	1
valid_sources[0x47]	7288	1			T5	128		T10	2		T95	6
valid_sources[0x48]	6435	1			T5	139		T60	1		T11	749
valid_sources[0x49]	6055	1			T1	4		T4	2		T5	152
valid_sources[0x4a]	6159	1			T4	2		T5	147		T10	2
valid_sources[0x4b]	6321	1			T4	1		T5	146		T63	1
valid_sources[0x4c]	5705	1			T4	1		T5	141		T63	1
valid_sources[0x4d]	5529	1			T4	1		T5	146		T9	1
valid_sources[0x4e]	5661	1			T5	134		T6	3		T63	1
valid_sources[0x4f]	6731	1			T4	1		T5	139		T9	1
valid_sources[0x50]	6667	1			T5	115		T63	1		T14	1
valid_sources[0x51]	6669	1			T5	166		T63	2		T11	785
valid_sources[0x52]	5964	1			T5	136		T63	2		T14	3
valid_sources[0x53]	6749	1			T5	134		T11	701		T72	3
valid_sources[0x54]	5542	1			T1	58		T5	130		T14	2
valid_sources[0x55]	6331	1			T4	2		T5	142		T63	1
valid_sources[0x56]	6339	1			T5	142		T11	699		T72	4
valid_sources[0x57]	7783	1			T4	1		T5	135		T95	2
valid_sources[0x58]	7042	1			T5	167		T10	1		T11	736
valid_sources[0x59]	6727	1			T4	1		T5	156		T63	4
valid_sources[0x5a]	5751	1			T5	155		T11	801		T21	1
valid_sources[0x5b]	5962	1			T4	1		T5	149		T6	1
valid_sources[0x5c]	5438	1			T4	1		T5	177		T6	1
valid_sources[0x5d]	7475	1			T4	3		T5	146		T63	1
valid_sources[0x5e]	7204	1			T1	11		T5	143		T11	773
valid_sources[0x5f]	5427	1			T5	129		T63	3		T60	1
valid_sources[0x60]	5788	1			T5	139		T15	2		T11	785
valid_sources[0x61]	5664	1			T4	3		T5	152		T63	1
valid_sources[0x62]	6332	1			T4	1		T5	164		T6	2
valid_sources[0x63]	5630	1			T4	1		T5	139		T63	1
valid_sources[0x64]	5823	1			T4	1		T5	140		T10	1
valid_sources[0x65]	6278	1			T4	2		T5	160		T63	4
valid_sources[0x66]	5517	1			T5	175		T63	1		T11	730
valid_sources[0x67]	6116	1			T4	2		T5	135		T63	2
valid_sources[0x68]	6424	1			T5	114		T6	3		T10	2
valid_sources[0x69]	6026	1			T5	131		T6	1		T9	1
valid_sources[0x6a]	5738	1			T4	1		T5	145		T14	2
valid_sources[0x6b]	5979	1			T4	1		T5	152		T6	1
valid_sources[0x6c]	5928	1			T1	1		T5	131		T60	3
valid_sources[0x6d]	6596	1			T4	1		T5	155		T63	1
valid_sources[0x6e]	6271	1			T5	145		T11	806		T72	3
valid_sources[0x6f]	7170	1			T5	159		T63	1		T60	1
valid_sources[0x70]	6428	1			T4	2		T5	163		T10	1
valid_sources[0x71]	6607	1			T5	137		T63	2		T11	752
valid_sources[0x72]	6630	1			T4	2		T5	132		T63	1
valid_sources[0x73]	6578	1			T5	155		T6	1		T63	1
valid_sources[0x74]	5550	1			T5	163		T10	1		T63	2
valid_sources[0x75]	5930	1			T5	156		T6	1		T9	2
valid_sources[0x76]	5939	1			T5	168		T6	1		T11	788
valid_sources[0x77]	5458	1			T4	2		T5	156		T6	1
valid_sources[0x78]	5547	1			T4	1		T5	161		T60	2
valid_sources[0x79]	6419	1			T5	163		T14	1		T11	720
valid_sources[0x7a]	6117	1			T5	158		T63	2		T14	1
valid_sources[0x7b]	6632	1			T4	1		T5	150		T63	1
valid_sources[0x7c]	6664	1			T5	167		T14	1		T95	3
valid_sources[0x7d]	6283	1			T4	1		T5	130		T9	5
valid_sources[0x7e]	5751	1			T4	2		T5	146		T63	1
valid_sources[0x7f]	5723	1			T5	170		T63	2		T11	775
valid_sources[0x80]	5604	1			T4	1		T5	151		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

326744

1

T1

21

T2

3

T3

3

values[0x0]

all_enables

biggest_size

484033

1

T5

11375

T11

60578

T12

13932

values[0x1]

all_enables

biggest_size

486178

1

T5

11632

T11

60592

T12

13924