Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3546550

1

T1

186

T2

48

T4

116

full_word

1549969

1

T1

21

T2

3

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5096209	1			T1	207		T2	51		T3	2
auto[TlIntgErrCmd]	101	1			T54	1		T55	5		T56	7
auto[TlIntgErrData]	101	1			T54	3		T55	10		T56	6
auto[TlIntgErrBoth]	108	1			T54	6		T55	5		T56	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620454

1

T1

207

T2

51

T3

2

auto[1]

4476065

1

T5

106777

T11

560249

T12

133627

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	262565	1			T1	186		T2	48		T4	116
auto[TlIntgErrNone]	partial	auto[1]	3283699	1			T5	78532		T11	411683		T12	98973
auto[TlIntgErrNone]	full_word	auto[0]	357761	1			T1	21		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	1192184	1			T5	28245		T11	148566		T12	34654
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T54	1		T55	3		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T55	2		T56	5		T101	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T103	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T104	1		T105	1		T100	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T54	1		T55	6		T56	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T54	1		T55	4		T56	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T56	1		T100	1		T106	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T54	1		T97	1		T107	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T54	3		T55	1		T56	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T54	3		T55	4		T56	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T56	1		T99	1		T103	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T104	1		T108	1		-	-