Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
10 |
10 |
100.00 |
Total Bits 0->1 |
5 |
5 |
100.00 |
Total Bits 1->0 |
5 |
5 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
10 |
10 |
100.00 |
Port Bits 0->1 |
5 |
5 |
100.00 |
Port Bits 1->0 |
5 |
5 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T5,T6 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[0] |
Yes |
Yes |
*T7,*T8,*T33 |
Yes |
T7,T8,T33 |
INPUT |
oh_i[17:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
addr_i[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T5,T7,T8 |
Yes |
T5,T7,T8 |
INPUT |
err_o |
Yes |
Yes |
T30,T31,T32 |
Yes |
T30,T31,T32 |
OUTPUT |
*Tests covering at least one bit in the range