Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_rom_adv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_rom_adv_0.1/rtl/prim_rom_adv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_rom 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 75.00 100.00 gen_rom_scramble_enabled.u_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_rom 88.89 66.67 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_rom_adv
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS4033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rom_adv_0.1/rtl/prim_rom_adv.sv' or '../src/lowrisc_prim_rom_adv_0.1/rtl/prim_rom_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
40 1 1
41 1 1
43 1 1


Branch Coverage for Module : prim_rom_adv
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 40 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_rom_adv_0.1/rtl/prim_rom_adv.sv' or '../src/lowrisc_prim_rom_adv_0.1/rtl/prim_rom_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 40 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_rom_adv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
noXOnCsI 197485304 197485304 0 0


noXOnCsI
NameAttemptsReal SuccessesFailuresIncomplete
Total 197485304 197485304 0 0
T1 9327 9327 0 0
T2 111284 111284 0 0
T3 460412 460412 0 0
T4 147834 147834 0 0
T5 211541 211541 0 0
T6 11744 11744 0 0
T7 119447 119447 0 0
T8 208128 208128 0 0
T9 28401 28401 0 0
T10 334921 334921 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%