Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
87.50 87.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_tlul_cg 87.50 1 100 1 64 64




Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance rom_ctrl_tlul_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group Instance rom_ctrl_tlul_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regs_req_check 3 0 3 100.00 100 1 1 0
cp_rom_invalid_condition 2 1 1 50.00 100 1 1 0
cp_rom_req_check 3 0 3 100.00 100 1 1 0


Summary for Variable cp_regs_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_regs_req_check

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 1726582 1 T2 1 T3 64 T7 2
req_and_done 7 1 T80 1 T111 2 T101 1
req_before_done 12 1 T17 1 T82 2 T83 3



Summary for Variable cp_rom_invalid_condition

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_rom_invalid_condition

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
check_invalid 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
check_valid 193393237 1 T1 8563 T2 202105 T3 19662



Summary for Variable cp_rom_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rom_req_check

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 2004313 1 T2 6 T3 102 T4 2
req_and_done 71 1 T4 1 T6 1 T24 1
req_before_done 276 1 T18 1 T11 1 T22 4

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