Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	82448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

806173

1

T1

7

T2

14

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	225013	1			T2	28		T3	64		T7	39
values[0x0]	306973	1			T1	8		T5	3		T8	4
values[0x1]	356635	1			T1	11		T5	2		T8	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

850320

1

T1

8

T2

15

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3279	1			T127	1		T30	1		T48	4
valid_sources[0x01]	2849	1			T87	1		T37	1		T15	153
valid_sources[0x02]	3476	1			T128	1		T129	1		T15	151
valid_sources[0x03]	3329	1			T3	64		T7	1		T88	3
valid_sources[0x04]	2870	1			T7	1		T19	3		T30	1
valid_sources[0x05]	3958	1			T15	166		T130	1		T16	409
valid_sources[0x06]	3884	1			T8	1		T90	1		T131	1
valid_sources[0x07]	3520	1			T2	1		T127	2		T42	1
valid_sources[0x08]	3706	1			T18	1		T45	1		T128	1
valid_sources[0x09]	3436	1			T34	1		T45	1		T15	172
valid_sources[0x0a]	3621	1			T48	3		T15	163		T16	447
valid_sources[0x0b]	2930	1			T2	4		T37	1		T88	2
valid_sources[0x0c]	3788	1			T74	7		T132	2		T15	159
valid_sources[0x0d]	2812	1			T7	1		T127	1		T76	2
valid_sources[0x0e]	3413	1			T7	1		T50	38		T15	116
valid_sources[0x0f]	3196	1			T88	1		T15	152		T64	2
valid_sources[0x10]	3753	1			T38	1		T127	3		T45	3
valid_sources[0x11]	3668	1			T87	1		T51	1		T45	1
valid_sources[0x12]	4156	1			T48	1		T129	4		T15	156
valid_sources[0x13]	3284	1			T131	1		T133	6		T15	147
valid_sources[0x14]	3979	1			T18	1		T87	2		T88	1
valid_sources[0x15]	3715	1			T127	3		T75	1		T134	1
valid_sources[0x16]	3473	1			T15	131		T16	399		T135	2
valid_sources[0x17]	3280	1			T12	10		T136	1		T15	144
valid_sources[0x18]	3172	1			T42	1		T134	2		T15	142
valid_sources[0x19]	3276	1			T127	1		T48	1		T129	2
valid_sources[0x1a]	3218	1			T1	1		T15	126		T130	1
valid_sources[0x1b]	2899	1			T7	1		T37	2		T88	2
valid_sources[0x1c]	3455	1			T1	1		T129	1		T15	158
valid_sources[0x1d]	3446	1			T7	1		T127	1		T128	1
valid_sources[0x1e]	2773	1			T10	1		T131	1		T15	131
valid_sources[0x1f]	2893	1			T90	2		T134	1		T15	140
valid_sources[0x20]	3535	1			T23	2		T87	1		T129	1
valid_sources[0x21]	3773	1			T76	1		T42	1		T136	2
valid_sources[0x22]	3019	1			T89	1		T131	2		T42	2
valid_sources[0x23]	3573	1			T88	2		T90	1		T136	5
valid_sources[0x24]	3289	1			T51	2		T129	2		T134	1
valid_sources[0x25]	3086	1			T7	1		T127	2		T15	193
valid_sources[0x26]	2926	1			T14	1		T128	1		T15	201
valid_sources[0x27]	3541	1			T33	1		T18	1		T14	1
valid_sources[0x28]	3459	1			T110	32		T131	1		T44	1
valid_sources[0x29]	3978	1			T30	2		T48	2		T15	150
valid_sources[0x2a]	3025	1			T75	1		T137	1		T129	2
valid_sources[0x2b]	3353	1			T127	2		T30	1		T133	2
valid_sources[0x2c]	3602	1			T134	1		T15	141		T64	1
valid_sources[0x2d]	2865	1			T127	2		T15	162		T138	1
valid_sources[0x2e]	3979	1			T127	2		T129	1		T15	156
valid_sources[0x2f]	4023	1			T73	1		T19	2		T23	2
valid_sources[0x30]	3777	1			T18	1		T139	1		T30	1
valid_sources[0x31]	3313	1			T15	123		T140	8		T16	424
valid_sources[0x32]	3464	1			T15	130		T16	397		T141	1
valid_sources[0x33]	3314	1			T14	2		T30	1		T42	1
valid_sources[0x34]	3589	1			T1	1		T23	1		T22	10
valid_sources[0x35]	3451	1			T19	1		T45	1		T48	1
valid_sources[0x36]	3364	1			T7	1		T27	1		T136	3
valid_sources[0x37]	3627	1			T88	1		T45	1		T136	1
valid_sources[0x38]	3733	1			T88	2		T48	2		T136	2
valid_sources[0x39]	3104	1			T14	2		T51	2		T45	5
valid_sources[0x3a]	3293	1			T15	150		T61	6		T138	1
valid_sources[0x3b]	3050	1			T131	1		T15	173		T64	2
valid_sources[0x3c]	3388	1			T127	1		T136	1		T142	18
valid_sources[0x3d]	3262	1			T30	1		T15	169		T16	422
valid_sources[0x3e]	3874	1			T51	1		T131	1		T45	2
valid_sources[0x3f]	3836	1			T23	1		T22	2		T14	1
valid_sources[0x40]	3018	1			T30	2		T51	3		T131	2
valid_sources[0x41]	3001	1			T88	1		T90	1		T15	145
valid_sources[0x42]	3655	1			T8	2		T127	3		T131	1
valid_sources[0x43]	3345	1			T127	1		T15	160		T64	1
valid_sources[0x44]	3976	1			T23	3		T42	1		T15	124
valid_sources[0x45]	3655	1			T2	6		T127	1		T48	1
valid_sources[0x46]	3533	1			T18	1		T90	4		T131	1
valid_sources[0x47]	2888	1			T1	1		T2	4		T88	1
valid_sources[0x48]	2573	1			T14	1		T127	1		T131	1
valid_sources[0x49]	2981	1			T7	1		T42	2		T15	146
valid_sources[0x4a]	3707	1			T136	1		T15	152		T60	1
valid_sources[0x4b]	3168	1			T129	1		T15	130		T130	1
valid_sources[0x4c]	4268	1			T45	1		T15	117		T60	2
valid_sources[0x4d]	3061	1			T7	1		T15	163		T130	1
valid_sources[0x4e]	3287	1			T26	1		T87	1		T127	1
valid_sources[0x4f]	3189	1			T129	2		T143	5		T15	154
valid_sources[0x50]	3002	1			T18	2		T87	1		T127	2
valid_sources[0x51]	3884	1			T14	1		T15	137		T64	1
valid_sources[0x52]	3168	1			T14	3		T76	1		T42	1
valid_sources[0x53]	2980	1			T87	1		T127	1		T45	6
valid_sources[0x54]	3430	1			T1	1		T136	2		T15	157
valid_sources[0x55]	3357	1			T7	1		T88	2		T131	1
valid_sources[0x56]	2940	1			T45	1		T15	165		T138	2
valid_sources[0x57]	3268	1			T18	1		T34	1		T15	153
valid_sources[0x58]	2893	1			T2	9		T88	1		T128	1
valid_sources[0x59]	3110	1			T14	1		T133	2		T15	97
valid_sources[0x5a]	3976	1			T22	1		T15	166		T64	2
valid_sources[0x5b]	3476	1			T14	1		T88	1		T127	1
valid_sources[0x5c]	2624	1			T8	1		T45	3		T136	1
valid_sources[0x5d]	3445	1			T30	1		T76	1		T129	3
valid_sources[0x5e]	3759	1			T42	1		T15	137		T59	1
valid_sources[0x5f]	3675	1			T136	1		T134	1		T15	132
valid_sources[0x60]	2880	1			T7	1		T127	2		T48	1
valid_sources[0x61]	3703	1			T48	3		T137	1		T77	1
valid_sources[0x62]	3362	1			T87	1		T131	1		T34	6
valid_sources[0x63]	3029	1			T14	1		T88	1		T30	1
valid_sources[0x64]	3561	1			T89	10		T15	124		T16	372
valid_sources[0x65]	2896	1			T44	1		T15	148		T64	2
valid_sources[0x66]	3132	1			T22	21		T89	3		T75	1
valid_sources[0x67]	3157	1			T144	1		T34	3		T42	3
valid_sources[0x68]	3370	1			T7	1		T8	1		T14	1
valid_sources[0x69]	3707	1			T145	1		T15	166		T64	3
valid_sources[0x6a]	3044	1			T48	1		T29	1		T15	142
valid_sources[0x6b]	3341	1			T45	4		T15	154		T60	1
valid_sources[0x6c]	3700	1			T7	1		T127	1		T15	127
valid_sources[0x6d]	3521	1			T19	1		T129	1		T134	1
valid_sources[0x6e]	3541	1			T7	1		T51	1		T45	4
valid_sources[0x6f]	3327	1			T89	6		T44	2		T15	144
valid_sources[0x70]	3181	1			T131	1		T48	5		T133	1
valid_sources[0x71]	3652	1			T44	1		T15	141		T16	363
valid_sources[0x72]	2841	1			T14	1		T129	1		T143	6
valid_sources[0x73]	3481	1			T23	6		T129	1		T15	132
valid_sources[0x74]	3268	1			T42	1		T15	151		T60	1
valid_sources[0x75]	3549	1			T1	1		T90	2		T30	1
valid_sources[0x76]	3243	1			T1	1		T18	1		T133	2
valid_sources[0x77]	3804	1			T2	1		T127	1		T15	156
valid_sources[0x78]	2825	1			T136	1		T134	1		T15	188
valid_sources[0x79]	3645	1			T23	2		T87	1		T90	1
valid_sources[0x7a]	3518	1			T127	1		T131	1		T134	2
valid_sources[0x7b]	3317	1			T19	1		T90	2		T76	1
valid_sources[0x7c]	3678	1			T76	2		T131	1		T42	2
valid_sources[0x7d]	3089	1			T127	1		T45	2		T15	157
valid_sources[0x7e]	3715	1			T1	1		T127	1		T128	3
valid_sources[0x7f]	4351	1			T23	3		T89	2		T75	1
valid_sources[0x80]	3447	1			T7	1		T23	2		T127	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

204351

1

T2

14

T3

28

T7

24

values[0x0]

all_enables

biggest_size

300363

1

T1

5

T5

2

T8

1

values[0x1]

all_enables

biggest_size

301459

1

T1

2

T37

1

T74

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	193416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

805276

1

T2

6

T3

13

T4

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	238455	1			T2	6		T3	117		T4	103
values[0x0]	314944	1			T15	13394		T16	38728		T17	18864
values[0x1]	445293	1			T15	18607		T16	54326		T17	27311

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

924201

1

T2

6

T3

58

T4

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4298	1			T3	1		T6	8		T7	1
valid_sources[0x01]	3613	1			T25	2		T87	1		T45	1
valid_sources[0x02]	3645	1			T4	1		T24	2		T22	12
valid_sources[0x03]	3605	1			T3	1		T109	2		T43	6
valid_sources[0x04]	3623	1			T6	4		T109	1		T41	1
valid_sources[0x05]	3613	1			T24	5		T13	1		T109	2
valid_sources[0x06]	4046	1			T3	1		T4	2		T6	1
valid_sources[0x07]	4669	1			T3	1		T18	2		T109	2
valid_sources[0x08]	3962	1			T25	1		T22	6		T131	1
valid_sources[0x09]	3857	1			T24	2		T13	2		T41	1
valid_sources[0x0a]	3745	1			T4	1		T6	6		T18	1
valid_sources[0x0b]	3965	1			T3	4		T18	3		T22	9
valid_sources[0x0c]	3602	1			T4	1		T6	4		T25	1
valid_sources[0x0d]	3762	1			T3	1		T19	1		T25	1
valid_sources[0x0e]	3675	1			T4	1		T6	2		T18	1
valid_sources[0x0f]	3478	1			T3	1		T4	1		T13	3
valid_sources[0x10]	3863	1			T18	1		T13	1		T109	1
valid_sources[0x11]	3950	1			T25	1		T22	4		T109	3
valid_sources[0x12]	3772	1			T13	2		T41	1		T43	1
valid_sources[0x13]	3738	1			T3	1		T25	1		T109	3
valid_sources[0x14]	3616	1			T11	5		T13	1		T109	1
valid_sources[0x15]	3665	1			T13	1		T45	2		T48	4
valid_sources[0x16]	3774	1			T25	2		T22	1		T13	1
valid_sources[0x17]	3846	1			T4	2		T6	5		T13	2
valid_sources[0x18]	3595	1			T4	1		T25	1		T13	1
valid_sources[0x19]	3833	1			T4	1		T109	1		T127	9
valid_sources[0x1a]	3966	1			T110	1		T41	2		T43	1
valid_sources[0x1b]	3786	1			T6	2		T18	1		T24	10
valid_sources[0x1c]	3704	1			T4	3		T6	1		T25	3
valid_sources[0x1d]	3602	1			T13	1		T89	1		T136	1
valid_sources[0x1e]	4329	1			T18	2		T13	1		T110	2
valid_sources[0x1f]	3602	1			T4	2		T6	2		T127	2
valid_sources[0x20]	3719	1			T24	9		T25	1		T87	3
valid_sources[0x21]	3648	1			T6	1		T25	1		T22	3
valid_sources[0x22]	3600	1			T3	1		T13	1		T109	1
valid_sources[0x23]	4691	1			T3	1		T4	3		T6	1
valid_sources[0x24]	3813	1			T6	9		T13	2		T109	3
valid_sources[0x25]	3855	1			T109	2		T51	3		T131	2
valid_sources[0x26]	3772	1			T18	1		T13	1		T109	1
valid_sources[0x27]	3595	1			T2	2		T4	1		T18	1
valid_sources[0x28]	4376	1			T7	1		T18	1		T87	2
valid_sources[0x29]	3988	1			T6	5		T87	2		T109	3
valid_sources[0x2a]	4142	1			T3	1		T109	1		T45	1
valid_sources[0x2b]	3582	1			T3	1		T22	3		T109	1
valid_sources[0x2c]	4088	1			T4	1		T109	2		T89	1
valid_sources[0x2d]	3494	1			T4	1		T109	1		T89	1
valid_sources[0x2e]	3532	1			T4	3		T19	3		T13	3
valid_sources[0x2f]	3762	1			T6	3		T18	1		T41	1
valid_sources[0x30]	3522	1			T3	1		T6	2		T13	1
valid_sources[0x31]	3621	1			T3	1		T4	1		T6	3
valid_sources[0x32]	3873	1			T22	2		T13	2		T110	1
valid_sources[0x33]	3532	1			T3	4		T4	1		T6	1
valid_sources[0x34]	3905	1			T6	3		T24	2		T109	7
valid_sources[0x35]	3855	1			T3	1		T24	6		T109	1
valid_sources[0x36]	4151	1			T2	1		T3	1		T18	1
valid_sources[0x37]	3725	1			T3	1		T6	4		T18	1
valid_sources[0x38]	3980	1			T6	3		T87	2		T13	1
valid_sources[0x39]	5112	1			T4	1		T18	1		T22	3
valid_sources[0x3a]	4012	1			T3	2		T4	1		T6	4
valid_sources[0x3b]	4055	1			T6	2		T25	4		T87	1
valid_sources[0x3c]	3518	1			T4	1		T13	1		T131	1
valid_sources[0x3d]	3690	1			T6	4		T109	4		T131	1
valid_sources[0x3e]	3843	1			T6	1		T13	1		T109	2
valid_sources[0x3f]	4148	1			T6	6		T25	1		T22	1
valid_sources[0x40]	3839	1			T4	1		T6	6		T11	1
valid_sources[0x41]	4211	1			T3	2		T4	1		T25	6
valid_sources[0x42]	4638	1			T6	4		T109	1		T43	1
valid_sources[0x43]	4073	1			T3	2		T4	1		T6	1
valid_sources[0x44]	4540	1			T4	1		T6	2		T109	2
valid_sources[0x45]	3857	1			T3	1		T4	1		T11	3
valid_sources[0x46]	4290	1			T25	1		T41	1		T43	1
valid_sources[0x47]	3596	1			T6	1		T25	5		T22	2
valid_sources[0x48]	3652	1			T4	2		T12	2		T13	1
valid_sources[0x49]	4088	1			T3	1		T6	2		T87	2
valid_sources[0x4a]	3935	1			T4	1		T24	3		T87	4
valid_sources[0x4b]	3603	1			T109	7		T89	1		T43	3
valid_sources[0x4c]	3616	1			T4	2		T6	2		T18	1
valid_sources[0x4d]	3611	1			T6	9		T24	3		T47	9
valid_sources[0x4e]	4103	1			T3	1		T43	2		T45	2
valid_sources[0x4f]	4992	1			T18	1		T25	4		T87	5
valid_sources[0x50]	3484	1			T3	2		T6	1		T22	2
valid_sources[0x51]	3683	1			T6	2		T18	1		T25	1
valid_sources[0x52]	3626	1			T6	6		T24	1		T25	1
valid_sources[0x53]	3935	1			T3	1		T6	3		T13	1
valid_sources[0x54]	4545	1			T3	3		T6	2		T25	2
valid_sources[0x55]	4866	1			T87	1		T43	3		T48	4
valid_sources[0x56]	3866	1			T18	1		T25	2		T109	2
valid_sources[0x57]	3691	1			T3	1		T6	3		T13	1
valid_sources[0x58]	3869	1			T3	1		T25	1		T13	1
valid_sources[0x59]	3675	1			T3	1		T4	1		T6	2
valid_sources[0x5a]	3949	1			T25	2		T87	1		T90	2
valid_sources[0x5b]	4342	1			T4	2		T18	1		T13	3
valid_sources[0x5c]	4065	1			T6	4		T25	2		T13	1
valid_sources[0x5d]	3743	1			T3	1		T4	1		T6	2
valid_sources[0x5e]	3638	1			T6	1		T19	3		T109	3
valid_sources[0x5f]	3768	1			T6	4		T13	1		T109	3
valid_sources[0x60]	3732	1			T3	2		T6	6		T22	1
valid_sources[0x61]	3796	1			T3	1		T4	1		T24	8
valid_sources[0x62]	3734	1			T3	1		T4	1		T25	2
valid_sources[0x63]	3894	1			T25	2		T89	1		T43	3
valid_sources[0x64]	4221	1			T24	6		T13	1		T109	6
valid_sources[0x65]	3713	1			T3	1		T13	3		T109	5
valid_sources[0x66]	3753	1			T3	1		T6	6		T25	1
valid_sources[0x67]	4571	1			T6	2		T24	3		T25	1
valid_sources[0x68]	3684	1			T4	1		T24	1		T22	3
valid_sources[0x69]	3802	1			T4	1		T6	1		T109	2
valid_sources[0x6a]	3667	1			T4	1		T24	9		T13	1
valid_sources[0x6b]	3589	1			T6	1		T24	1		T25	1
valid_sources[0x6c]	3720	1			T3	1		T4	2		T6	3
valid_sources[0x6d]	3859	1			T4	2		T109	2		T89	1
valid_sources[0x6e]	4066	1			T6	10		T109	1		T41	1
valid_sources[0x6f]	3492	1			T3	1		T87	2		T127	2
valid_sources[0x70]	3816	1			T3	1		T6	1		T13	2
valid_sources[0x71]	3665	1			T6	10		T25	2		T22	4
valid_sources[0x72]	3769	1			T4	1		T87	1		T41	2
valid_sources[0x73]	3717	1			T3	2		T4	1		T25	1
valid_sources[0x74]	3678	1			T3	2		T4	1		T6	4
valid_sources[0x75]	3960	1			T25	1		T13	3		T109	7
valid_sources[0x76]	3977	1			T3	1		T4	1		T6	1
valid_sources[0x77]	4220	1			T25	2		T13	1		T89	1
valid_sources[0x78]	3721	1			T6	1		T109	2		T127	3
valid_sources[0x79]	3765	1			T109	2		T41	1		T146	76
valid_sources[0x7a]	3716	1			T3	1		T25	5		T22	1
valid_sources[0x7b]	3793	1			T2	3		T6	1		T89	1
valid_sources[0x7c]	3902	1			T13	1		T110	7		T41	1
valid_sources[0x7d]	3972	1			T4	1		T22	1		T13	2
valid_sources[0x7e]	3743	1			T87	1		T89	2		T43	1
valid_sources[0x7f]	3506	1			T6	2		T25	1		T11	13
valid_sources[0x80]	3783	1			T6	3		T25	4		T22	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

204605

1

T2

6

T3

13

T4

8

values[0x0]

all_enables

biggest_size

299741

1

T15

12807

T16

36814

T17

17910

values[0x1]

all_enables

biggest_size

300930

1

T15

12832

T16

36969

T17

18126