Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2198734

1

T3

104

T4

95

T6

307

full_word

962121

1

T2

4

T3

13

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3160525	1			T2	4		T3	117		T4	103
auto[TlIntgErrCmd]	119	1			T66	9		T67	3		T68	6
auto[TlIntgErrData]	110	1			T66	4		T67	8		T68	2
auto[TlIntgErrBoth]	101	1			T66	7		T67	9		T68	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

397230

1

T2

4

T3

117

T4

103

auto[1]

2763625

1

T15

110689

T16

340202

T17

171257

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	173351	1			T3	104		T4	95		T6	307
auto[TlIntgErrNone]	partial	auto[1]	2025087	1			T15	79599		T16	249521		T17	126716
auto[TlIntgErrNone]	full_word	auto[0]	223722	1			T2	4		T3	13		T4	8
auto[TlIntgErrNone]	full_word	auto[1]	738365	1			T15	31090		T16	90681		T17	44541
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T66	4		T67	1		T68	4
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T66	5		T67	1		T68	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T67	1		T122	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T68	1		T112	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T66	2		T67	4		T68	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T66	2		T67	2		T68	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T67	2		T124	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T116	1		T122	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T66	4		T67	3		T124	5
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T66	3		T67	5		T68	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T67	1		T115	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T118	1		T114	1		T119	1