Module Definition
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Module : prim_prince
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_prince 100.00 100.00



Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_prince

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 75.00 100.00 gen_rom_scramble_enabled.u_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_prince
TotalCoveredPercent
Totals 6 6 100.00
Total Bits 162 162 100.00
Total Bits 0->1 81 81 100.00
Total Bits 1->0 81 81 100.00

Ports 6 6 100.00
Port Bits 162 162 100.00
Port Bits 0->1 81 81 100.00
Port Bits 1->0 81 81 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
valid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_i[12:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_i[63:13] Unreachable Unreachable Unreachable INPUT
key_i[127:0] Unreachable Unreachable Unreachable INPUT
dec_i Unreachable Unreachable Unreachable INPUT
valid_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

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