Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.38	97.04	92.80	97.88	100.00	98.69	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	451	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
123	1	1
124	1	1
125	1	1
126	1	1
129	1	1
221	1	1
267	1	1
322	1	1
423	8	8
424	8	8
426	8	8
427	8	8
429	8	8
430	8	8
434	1	1
436	1	1
439	1	1
440	1	1
441	1	1
442	1	1
447	1	1
451	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       221
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       267
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T19
1	1	Covered	T2,T3,T4

 LINE       427
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       427
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       427
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T35,T36
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       436
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T23
1	0	Covered	T2,T7,T9

 LINE       447
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T37

 LINE       451
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T23
0	1	0	Covered	T2,T7,T9
1	0	0	Covered	T34,T35,T36

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T6	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rom_tl_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_tl_o.a_ready	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T16,T17	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T19,T38	Yes	T2,T19,T38	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T7	Yes	T2,T3,T7	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T7	OUTPUT
keymgr_data_o.valid	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T2,T7,T9	Yes	T1,T2,T5	OUTPUT
kmac_data_i.error	No	Yes	T9,T10,T26	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T7,T19	Yes	T2,T3,T7	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T7,T33	Yes	T2,T3,T7	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	221	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	173091908	172913397	0	0
BusRomIndicesMatch_A	173080729	172907647	0	0
FpvSecCmFifoRptrCheck_A	173091908	0	0	0
FpvSecCmFifoWptrCheck_A	173091908	0	0	0
FpvSecCmRegWeOnehotCheck_A	173091908	80	0	0
KeymgrDataODataKnown_A	173091908	40983651	0	0
KeymgrDataODataKnown_AKnownEnable	173091908	172913397	0	0
KeymgrDataOValidKnown_A	173091908	172913397	0	0
KeymgrValidChk_A	173091908	0	0	318
KmacDataODataKnown_A	173091908	131805509	0	0
KmacDataODataKnown_AKnownEnable	173091908	172913397	0	0
KmacDataOValidKnown_A	173091908	172913397	0	0
PwrmgrDataChk_A	173091908	0	0	318
PwrmgrDataOKnown_A	173091908	172913397	0	0
RegsTlOAReadyKnown_A	173091908	172913397	0	0
RegsTlODDataKnown_A	173091908	5940935	0	0
RegsTlODDataKnown_AKnownEnable	173091908	172913397	0	0
RegsTlODValidKnown_A	173091908	172913397	0	0
RomTlOAReadyKnown_A	173091908	172913397	0	0
RomTlODDataKnown_A	173091908	11002914	0	0
RomTlODDataKnown_AKnownEnable	173091908	172913397	0	0
RomTlODValidKnown_A	173091908	172913397	0	0
StabilityChkKmac_A	173091908	131803048	0	0
StabilityChkkeymgr_A	173091908	40982503	0	0
TlAccessChk_A	173091908	131929746	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	173091908	80	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	173091908	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	173091908	551	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	173091908	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173080729	172907647	0	0
T1	8563	8478	0	0
T2	202088	201844	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276175	275854	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	80	0	0
T34	175016	20	0	0
T35	0	20	0	0
T36	0	20	0	0
T39	0	10	0	0
T40	0	10	0	0
T41	9180	0	0	0
T42	370667	0	0	0
T43	119179	0	0	0
T44	100575	0	0	0
T45	116593	0	0	0
T46	44852	0	0	0
T47	106935	0	0	0
T48	724158	0	0	0
T49	206390	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	40983651	0	0
T1	8563	273	0	0
T2	202105	19107	0	0
T3	19662	2377	0	0
T4	9149	870	0	0
T5	214653	281	0	0
T6	143437	1282	0	0
T7	276182	17504	0	0
T8	90266	64	0	0
T9	107146	130	0	0
T10	237811	137	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	0	0	318

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	131805509	0	0
T1	8563	8184	0	0
T2	202105	199759	0	0
T3	19662	17024	0	0
T4	9149	8184	0	0
T5	214653	214227	0	0
T6	143437	142013	0	0
T7	276182	273862	0	0
T8	90266	90057	0	0
T9	107146	106779	0	0
T10	237811	237376	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	0	0	318

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	5940935	0	0
T1	8563	74	0	0
T2	202105	28	0	0
T3	19662	300	0	0
T4	9149	0	0	0
T5	214653	5	0	0
T6	143437	0	0	0
T7	276182	39	0	0
T8	90266	23	0	0
T9	107146	5	0	0
T10	237811	3	0	0
T26	0	8	0	0
T33	0	1	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	11002914	0	0
T2	202105	6	0	0
T3	19662	117	0	0
T4	9149	103	0	0
T5	214653	0	0	0
T6	143437	330	0	0
T7	276182	3	0	0
T8	90266	0	0	0
T9	107146	0	0	0
T10	237811	0	0	0
T18	0	379	0	0
T19	0	67	0	0
T23	0	3	0	0
T24	0	211	0	0
T25	0	166	0	0
T26	204406	0	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	172913397	0	0
T1	8563	8478	0	0
T2	202105	201847	0	0
T3	19662	19445	0	0
T4	9149	9075	0	0
T5	214653	214596	0	0
T6	143437	143375	0	0
T7	276182	275856	0	0
T8	90266	90198	0	0
T9	107146	107012	0	0
T10	237811	237670	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	131803048	0	0
T1	8563	8183	0	0
T2	202105	199755	0	0
T3	19662	17021	0	0
T4	9149	8183	0	0
T5	214653	214226	0	0
T6	143437	142012	0	0
T7	276182	273857	0	0
T8	90266	90056	0	0
T9	107146	106777	0	0
T10	237811	237374	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	40982503	0	0
T1	8563	272	0	0
T2	202105	19095	0	0
T3	19662	2375	0	0
T4	9149	869	0	0
T5	214653	280	0	0
T6	143437	1281	0	0
T7	276182	17491	0	0
T8	90266	63	0	0
T9	107146	129	0	0
T10	237811	136	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	131929746	0	0
T1	8563	8205	0	0
T2	202105	199936	0	0
T3	19662	17068	0	0
T4	9149	8205	0	0
T5	214653	214315	0	0
T6	143437	142093	0	0
T7	276182	274105	0	0
T8	90266	90134	0	0
T9	107146	106882	0	0
T10	237811	237533	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	80	0	0
T34	175016	20	0	0
T35	0	20	0	0
T36	0	20	0	0
T39	0	10	0	0
T40	0	10	0	0
T41	9180	0	0	0
T42	370667	0	0	0
T43	119179	0	0	0
T44	100575	0	0	0
T45	116593	0	0	0
T46	44852	0	0	0
T47	106935	0	0	0
T48	724158	0	0	0
T49	206390	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	551	0	0
T2	202105	15	0	0
T3	19662	0	0	0
T4	9149	0	0	0
T5	214653	0	0	0
T6	143437	0	0	0
T7	276182	16	0	0
T8	90266	0	0	0
T9	107146	0	0	0
T10	237811	0	0	0
T12	0	5	0	0
T14	0	20	0	0
T19	0	11	0	0
T23	0	10	0	0
T26	204406	0	0	0
T30	0	9	0	0
T34	0	20	0	0
T50	0	5	0	0
T51	0	10	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173091908	0	0	0