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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.43 97.04 92.65 97.88 100.00 98.37 97.89 98.14


Total test records in report: 466
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T301 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.576129012 Mar 10 01:24:31 PM PDT 24 Mar 10 02:34:22 PM PDT 24 98290782740 ps
T302 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.643890815 Mar 10 01:23:20 PM PDT 24 Mar 10 01:23:26 PM PDT 24 758320941 ps
T303 /workspace/coverage/default/4.rom_ctrl_alert_test.2685800015 Mar 10 01:23:21 PM PDT 24 Mar 10 01:23:26 PM PDT 24 86229043 ps
T304 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1227935527 Mar 10 01:24:27 PM PDT 24 Mar 10 01:24:37 PM PDT 24 173452878 ps
T305 /workspace/coverage/default/22.rom_ctrl_stress_all.578333642 Mar 10 01:23:48 PM PDT 24 Mar 10 01:24:16 PM PDT 24 1936779926 ps
T306 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.956272086 Mar 10 01:23:45 PM PDT 24 Mar 10 01:23:58 PM PDT 24 5010326614 ps
T307 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3719517659 Mar 10 01:24:29 PM PDT 24 Mar 10 01:24:55 PM PDT 24 10436214843 ps
T308 /workspace/coverage/default/9.rom_ctrl_smoke.294265473 Mar 10 01:23:27 PM PDT 24 Mar 10 01:23:51 PM PDT 24 13267782959 ps
T309 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1610993598 Mar 10 01:24:19 PM PDT 24 Mar 10 01:24:50 PM PDT 24 6693671870 ps
T310 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.76203855 Mar 10 01:23:22 PM PDT 24 Mar 10 01:26:22 PM PDT 24 16941452472 ps
T311 /workspace/coverage/default/31.rom_ctrl_smoke.815737288 Mar 10 01:24:15 PM PDT 24 Mar 10 01:24:45 PM PDT 24 5744506608 ps
T312 /workspace/coverage/default/5.rom_ctrl_smoke.1850372268 Mar 10 01:23:24 PM PDT 24 Mar 10 01:23:46 PM PDT 24 1584394160 ps
T313 /workspace/coverage/default/2.rom_ctrl_stress_all.2870651970 Mar 10 01:23:29 PM PDT 24 Mar 10 01:24:05 PM PDT 24 12793498997 ps
T314 /workspace/coverage/default/3.rom_ctrl_alert_test.207853123 Mar 10 01:23:25 PM PDT 24 Mar 10 01:23:32 PM PDT 24 2041135985 ps
T315 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1937757549 Mar 10 01:24:21 PM PDT 24 Mar 10 01:24:51 PM PDT 24 13652584187 ps
T316 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3575031915 Mar 10 01:23:37 PM PDT 24 Mar 10 01:24:10 PM PDT 24 4251723115 ps
T317 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1679503261 Mar 10 01:24:18 PM PDT 24 Mar 10 01:24:23 PM PDT 24 191750023 ps
T318 /workspace/coverage/default/7.rom_ctrl_smoke.3720992368 Mar 10 01:23:28 PM PDT 24 Mar 10 01:23:50 PM PDT 24 7371953961 ps
T319 /workspace/coverage/default/12.rom_ctrl_alert_test.678689488 Mar 10 01:23:40 PM PDT 24 Mar 10 01:23:56 PM PDT 24 1889689714 ps
T320 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2310307072 Mar 10 01:24:31 PM PDT 24 Mar 10 01:24:42 PM PDT 24 3280438217 ps
T321 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1295595410 Mar 10 01:23:38 PM PDT 24 Mar 10 01:23:47 PM PDT 24 2089662014 ps
T322 /workspace/coverage/default/22.rom_ctrl_alert_test.1760354152 Mar 10 01:23:54 PM PDT 24 Mar 10 01:24:07 PM PDT 24 14426967212 ps
T323 /workspace/coverage/default/24.rom_ctrl_alert_test.683541840 Mar 10 01:24:02 PM PDT 24 Mar 10 01:24:17 PM PDT 24 7573804613 ps
T324 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4013319737 Mar 10 01:24:03 PM PDT 24 Mar 10 01:24:14 PM PDT 24 11421354778 ps
T325 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2873164876 Mar 10 01:23:44 PM PDT 24 Mar 10 01:24:00 PM PDT 24 1716927877 ps
T326 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1325860768 Mar 10 01:23:33 PM PDT 24 Mar 10 01:23:48 PM PDT 24 1070396290 ps
T327 /workspace/coverage/default/15.rom_ctrl_stress_all.4282118587 Mar 10 01:23:41 PM PDT 24 Mar 10 01:23:48 PM PDT 24 128772112 ps
T328 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.482422012 Mar 10 01:23:40 PM PDT 24 Mar 10 01:23:52 PM PDT 24 1656490727 ps
T329 /workspace/coverage/default/33.rom_ctrl_smoke.101325438 Mar 10 01:24:11 PM PDT 24 Mar 10 01:24:42 PM PDT 24 11016159844 ps
T330 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1224967771 Mar 10 01:23:58 PM PDT 24 Mar 10 01:24:22 PM PDT 24 32906999494 ps
T331 /workspace/coverage/default/33.rom_ctrl_alert_test.377623722 Mar 10 01:24:12 PM PDT 24 Mar 10 01:24:28 PM PDT 24 9114692092 ps
T332 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.509808464 Mar 10 01:23:47 PM PDT 24 Mar 10 01:26:13 PM PDT 24 7641204468 ps
T333 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3042473046 Mar 10 01:24:10 PM PDT 24 Mar 10 01:24:21 PM PDT 24 6112068636 ps
T334 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2792534611 Mar 10 01:24:06 PM PDT 24 Mar 10 01:28:26 PM PDT 24 159201712785 ps
T335 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4232780016 Mar 10 01:23:50 PM PDT 24 Mar 10 01:25:06 PM PDT 24 4513700262 ps
T336 /workspace/coverage/default/43.rom_ctrl_stress_all.3149759645 Mar 10 01:24:23 PM PDT 24 Mar 10 01:24:40 PM PDT 24 1739383881 ps
T337 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2149012762 Mar 10 01:24:07 PM PDT 24 Mar 10 02:17:35 PM PDT 24 271592981401 ps
T338 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3606196729 Mar 10 01:24:26 PM PDT 24 Mar 10 01:24:34 PM PDT 24 1808493623 ps
T339 /workspace/coverage/default/30.rom_ctrl_stress_all.740784287 Mar 10 01:24:08 PM PDT 24 Mar 10 01:24:41 PM PDT 24 4009845088 ps
T340 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4265318801 Mar 10 01:23:39 PM PDT 24 Mar 10 01:23:52 PM PDT 24 1315818483 ps
T341 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.451658706 Mar 10 01:24:26 PM PDT 24 Mar 10 01:25:39 PM PDT 24 1313091700 ps
T342 /workspace/coverage/default/36.rom_ctrl_smoke.2420336169 Mar 10 01:24:20 PM PDT 24 Mar 10 01:24:56 PM PDT 24 6885665775 ps
T343 /workspace/coverage/default/35.rom_ctrl_stress_all.4216252014 Mar 10 01:24:14 PM PDT 24 Mar 10 01:24:39 PM PDT 24 1223319640 ps
T344 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2651360286 Mar 10 01:24:10 PM PDT 24 Mar 10 02:51:07 PM PDT 24 85709908184 ps
T345 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3605785305 Mar 10 01:23:38 PM PDT 24 Mar 10 01:23:44 PM PDT 24 409034666 ps
T346 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2596537578 Mar 10 01:24:17 PM PDT 24 Mar 10 01:24:31 PM PDT 24 5237544831 ps
T347 /workspace/coverage/default/1.rom_ctrl_alert_test.1689981386 Mar 10 01:23:17 PM PDT 24 Mar 10 01:23:28 PM PDT 24 1137042353 ps
T348 /workspace/coverage/default/37.rom_ctrl_stress_all.2354538156 Mar 10 01:24:20 PM PDT 24 Mar 10 01:24:45 PM PDT 24 5081001066 ps
T349 /workspace/coverage/default/7.rom_ctrl_alert_test.3714675872 Mar 10 01:23:28 PM PDT 24 Mar 10 01:23:32 PM PDT 24 438785417 ps
T350 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.663651639 Mar 10 01:24:15 PM PDT 24 Mar 10 01:24:46 PM PDT 24 32831715942 ps
T351 /workspace/coverage/default/32.rom_ctrl_stress_all.3633526375 Mar 10 01:24:09 PM PDT 24 Mar 10 01:25:44 PM PDT 24 18161603538 ps
T352 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2074508679 Mar 10 01:23:21 PM PDT 24 Mar 10 01:23:56 PM PDT 24 8054341640 ps
T353 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.933197136 Mar 10 01:24:02 PM PDT 24 Mar 10 01:27:31 PM PDT 24 37519350171 ps
T354 /workspace/coverage/default/27.rom_ctrl_stress_all.684064921 Mar 10 01:24:00 PM PDT 24 Mar 10 01:24:41 PM PDT 24 3552614774 ps
T355 /workspace/coverage/default/10.rom_ctrl_alert_test.236282909 Mar 10 01:23:37 PM PDT 24 Mar 10 01:23:53 PM PDT 24 1848457821 ps
T356 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1155112374 Mar 10 01:24:30 PM PDT 24 Mar 10 01:24:49 PM PDT 24 5815527241 ps
T357 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1620591361 Mar 10 01:24:25 PM PDT 24 Mar 10 01:24:32 PM PDT 24 138711284 ps
T358 /workspace/coverage/default/45.rom_ctrl_alert_test.649784010 Mar 10 01:24:26 PM PDT 24 Mar 10 01:24:42 PM PDT 24 8100835103 ps
T359 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3837441777 Mar 10 01:23:50 PM PDT 24 Mar 10 01:26:49 PM PDT 24 54241996210 ps
T360 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.387347216 Mar 10 01:24:20 PM PDT 24 Mar 10 01:24:53 PM PDT 24 13296858165 ps
T361 /workspace/coverage/default/39.rom_ctrl_stress_all.4031425201 Mar 10 01:24:20 PM PDT 24 Mar 10 01:24:44 PM PDT 24 1366472295 ps
T362 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.420361116 Mar 10 01:23:59 PM PDT 24 Mar 10 01:24:23 PM PDT 24 39615532986 ps
T363 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.864916745 Mar 10 01:23:55 PM PDT 24 Mar 10 01:24:04 PM PDT 24 667757276 ps
T364 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3521749547 Mar 10 01:23:22 PM PDT 24 Mar 10 01:23:51 PM PDT 24 6453378770 ps
T365 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3940689859 Mar 10 01:23:54 PM PDT 24 Mar 10 01:24:02 PM PDT 24 522900400 ps
T366 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.189854652 Mar 10 01:24:26 PM PDT 24 Mar 10 01:24:51 PM PDT 24 2461337562 ps
T367 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2998942232 Mar 10 01:24:14 PM PDT 24 Mar 10 01:24:32 PM PDT 24 1823506086 ps
T368 /workspace/coverage/default/24.rom_ctrl_smoke.3167330744 Mar 10 01:23:54 PM PDT 24 Mar 10 01:24:17 PM PDT 24 5194467207 ps
T369 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1150465524 Mar 10 01:23:19 PM PDT 24 Mar 10 01:23:33 PM PDT 24 6478808827 ps
T370 /workspace/coverage/default/36.rom_ctrl_alert_test.904660887 Mar 10 01:24:14 PM PDT 24 Mar 10 01:24:18 PM PDT 24 171495459 ps
T371 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2581228737 Mar 10 01:24:06 PM PDT 24 Mar 10 01:24:17 PM PDT 24 906917310 ps
T50 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.619690391 Mar 10 01:02:56 PM PDT 24 Mar 10 01:03:00 PM PDT 24 86503620 ps
T47 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4075102606 Mar 10 01:02:00 PM PDT 24 Mar 10 01:03:17 PM PDT 24 3651503056 ps
T51 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.929801314 Mar 10 01:02:56 PM PDT 24 Mar 10 01:03:01 PM PDT 24 398829239 ps
T48 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2172469453 Mar 10 01:03:01 PM PDT 24 Mar 10 01:04:20 PM PDT 24 30064881562 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2463850273 Mar 10 01:03:01 PM PDT 24 Mar 10 01:03:11 PM PDT 24 284488523 ps
T89 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1547194954 Mar 10 01:02:56 PM PDT 24 Mar 10 01:03:03 PM PDT 24 385347014 ps
T373 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4007513894 Mar 10 01:02:52 PM PDT 24 Mar 10 01:02:59 PM PDT 24 356349794 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.646248588 Mar 10 01:02:50 PM PDT 24 Mar 10 01:03:04 PM PDT 24 2153962212 ps
T375 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.150427758 Mar 10 01:02:56 PM PDT 24 Mar 10 01:03:02 PM PDT 24 634977452 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2079309720 Mar 10 01:02:17 PM PDT 24 Mar 10 01:02:31 PM PDT 24 1395403326 ps
T61 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3421065022 Mar 10 01:02:58 PM PDT 24 Mar 10 01:03:04 PM PDT 24 2595542892 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3169116076 Mar 10 01:02:10 PM PDT 24 Mar 10 01:02:57 PM PDT 24 37484525222 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2743164591 Mar 10 01:03:01 PM PDT 24 Mar 10 01:03:08 PM PDT 24 378363812 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3630117500 Mar 10 01:02:00 PM PDT 24 Mar 10 01:02:15 PM PDT 24 6906668795 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1741476550 Mar 10 01:02:11 PM PDT 24 Mar 10 01:02:21 PM PDT 24 768599567 ps
T62 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2935343524 Mar 10 01:02:55 PM PDT 24 Mar 10 01:03:07 PM PDT 24 1392512014 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2744471583 Mar 10 01:02:57 PM PDT 24 Mar 10 01:03:39 PM PDT 24 7924714137 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2444261311 Mar 10 01:02:50 PM PDT 24 Mar 10 01:03:03 PM PDT 24 5347019259 ps
T49 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3961077356 Mar 10 01:02:17 PM PDT 24 Mar 10 01:02:55 PM PDT 24 1405155072 ps
T64 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4274119964 Mar 10 01:02:53 PM PDT 24 Mar 10 01:03:21 PM PDT 24 2010400371 ps
T377 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4121495245 Mar 10 01:02:28 PM PDT 24 Mar 10 01:02:44 PM PDT 24 1860932187 ps
T91 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3890614350 Mar 10 01:02:18 PM PDT 24 Mar 10 01:02:23 PM PDT 24 921799456 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1252969283 Mar 10 01:02:11 PM PDT 24 Mar 10 01:02:15 PM PDT 24 347166541 ps
T100 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3320640585 Mar 10 01:02:55 PM PDT 24 Mar 10 01:04:06 PM PDT 24 1717612918 ps
T65 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3232484266 Mar 10 01:02:22 PM PDT 24 Mar 10 01:02:37 PM PDT 24 1844714517 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.475783160 Mar 10 01:02:12 PM PDT 24 Mar 10 01:02:17 PM PDT 24 88347739 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3746035407 Mar 10 01:02:05 PM PDT 24 Mar 10 01:03:14 PM PDT 24 227765093 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2814994332 Mar 10 01:02:24 PM PDT 24 Mar 10 01:02:37 PM PDT 24 1973265444 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1303469884 Mar 10 01:02:01 PM PDT 24 Mar 10 01:02:08 PM PDT 24 376984611 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2399867536 Mar 10 01:02:16 PM PDT 24 Mar 10 01:02:26 PM PDT 24 3941290126 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1339681438 Mar 10 01:02:45 PM PDT 24 Mar 10 01:03:13 PM PDT 24 2946044047 ps
T382 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3870415253 Mar 10 01:02:59 PM PDT 24 Mar 10 01:03:10 PM PDT 24 2561845204 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2592929499 Mar 10 01:02:17 PM PDT 24 Mar 10 01:02:24 PM PDT 24 271865480 ps
T384 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.149822537 Mar 10 01:02:19 PM PDT 24 Mar 10 01:02:30 PM PDT 24 7091961204 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.56500128 Mar 10 01:03:02 PM PDT 24 Mar 10 01:03:06 PM PDT 24 426488896 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4058610340 Mar 10 01:02:56 PM PDT 24 Mar 10 01:03:12 PM PDT 24 2117592179 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4265498297 Mar 10 01:02:17 PM PDT 24 Mar 10 01:02:36 PM PDT 24 1499706744 ps
T68 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.489179852 Mar 10 01:02:00 PM PDT 24 Mar 10 01:02:28 PM PDT 24 2230875380 ps
T92 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2485802157 Mar 10 01:02:23 PM PDT 24 Mar 10 01:02:34 PM PDT 24 15672031272 ps
T388 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2917308232 Mar 10 01:02:19 PM PDT 24 Mar 10 01:02:27 PM PDT 24 776609389 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3921255200 Mar 10 01:02:04 PM PDT 24 Mar 10 01:02:09 PM PDT 24 98027723 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3513319928 Mar 10 01:02:50 PM PDT 24 Mar 10 01:02:54 PM PDT 24 297401867 ps
T104 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.259744172 Mar 10 01:02:13 PM PDT 24 Mar 10 01:02:53 PM PDT 24 680035162 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3345755356 Mar 10 01:02:46 PM PDT 24 Mar 10 01:02:51 PM PDT 24 108063674 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3120981218 Mar 10 01:02:13 PM PDT 24 Mar 10 01:02:19 PM PDT 24 789652231 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.982931128 Mar 10 01:02:51 PM PDT 24 Mar 10 01:03:36 PM PDT 24 11424220698 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1597168220 Mar 10 01:02:01 PM PDT 24 Mar 10 01:03:37 PM PDT 24 48416083772 ps
T93 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3165537882 Mar 10 01:03:01 PM PDT 24 Mar 10 01:04:12 PM PDT 24 7848030667 ps
T105 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1506006376 Mar 10 01:02:58 PM PDT 24 Mar 10 01:04:18 PM PDT 24 8287545737 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1960064072 Mar 10 01:02:10 PM PDT 24 Mar 10 01:02:19 PM PDT 24 2391651969 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2085802668 Mar 10 01:02:04 PM PDT 24 Mar 10 01:02:19 PM PDT 24 2405790652 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2718305022 Mar 10 01:02:11 PM PDT 24 Mar 10 01:02:27 PM PDT 24 2146531621 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1966906342 Mar 10 01:02:05 PM PDT 24 Mar 10 01:02:16 PM PDT 24 2288658270 ps
T397 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1696192699 Mar 10 01:02:53 PM PDT 24 Mar 10 01:03:42 PM PDT 24 4343939648 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3215273585 Mar 10 01:02:05 PM PDT 24 Mar 10 01:02:19 PM PDT 24 938517230 ps
T76 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3671681230 Mar 10 01:02:14 PM PDT 24 Mar 10 01:02:48 PM PDT 24 1119782789 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2169271565 Mar 10 01:02:54 PM PDT 24 Mar 10 01:03:06 PM PDT 24 4860611476 ps
T77 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1044021833 Mar 10 01:02:24 PM PDT 24 Mar 10 01:02:53 PM PDT 24 6165049455 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1871684721 Mar 10 01:02:16 PM PDT 24 Mar 10 01:02:22 PM PDT 24 359718252 ps
T109 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1251272862 Mar 10 01:02:23 PM PDT 24 Mar 10 01:03:03 PM PDT 24 1587714114 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.648695486 Mar 10 01:02:05 PM PDT 24 Mar 10 01:02:15 PM PDT 24 3767545907 ps
T402 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3743433767 Mar 10 01:02:50 PM PDT 24 Mar 10 01:03:03 PM PDT 24 3165320704 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.98021900 Mar 10 01:02:16 PM PDT 24 Mar 10 01:02:28 PM PDT 24 1169549333 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4105663139 Mar 10 01:02:56 PM PDT 24 Mar 10 01:03:01 PM PDT 24 171418842 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.278719700 Mar 10 01:02:22 PM PDT 24 Mar 10 01:02:32 PM PDT 24 913528050 ps
T78 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1073987663 Mar 10 01:02:49 PM PDT 24 Mar 10 01:04:02 PM PDT 24 86527589175 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2800989986 Mar 10 01:01:59 PM PDT 24 Mar 10 01:02:09 PM PDT 24 3792191196 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2374107697 Mar 10 01:02:17 PM PDT 24 Mar 10 01:02:39 PM PDT 24 8479492576 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2822083601 Mar 10 01:01:58 PM PDT 24 Mar 10 01:02:15 PM PDT 24 12620503483 ps
T101 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.63462396 Mar 10 01:02:50 PM PDT 24 Mar 10 01:04:05 PM PDT 24 1428284097 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2982915070 Mar 10 01:03:01 PM PDT 24 Mar 10 01:03:13 PM PDT 24 2470010096 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1120191114 Mar 10 01:02:00 PM PDT 24 Mar 10 01:02:15 PM PDT 24 14989139157 ps
T79 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3820548924 Mar 10 01:02:39 PM PDT 24 Mar 10 01:04:13 PM PDT 24 45357136459 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2703008735 Mar 10 01:02:05 PM PDT 24 Mar 10 01:02:10 PM PDT 24 168079605 ps
T411 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2382109815 Mar 10 01:02:39 PM PDT 24 Mar 10 01:02:43 PM PDT 24 89296158 ps
T412 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.346999222 Mar 10 01:02:23 PM PDT 24 Mar 10 01:02:30 PM PDT 24 232566267 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3869867966 Mar 10 01:02:12 PM PDT 24 Mar 10 01:02:21 PM PDT 24 122459719 ps
T87 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3226719305 Mar 10 01:02:23 PM PDT 24 Mar 10 01:03:20 PM PDT 24 11055391261 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2532759384 Mar 10 01:02:24 PM PDT 24 Mar 10 01:02:38 PM PDT 24 6381717455 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1812940150 Mar 10 01:02:29 PM PDT 24 Mar 10 01:02:42 PM PDT 24 5391473427 ps
T416 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3288533674 Mar 10 01:02:50 PM PDT 24 Mar 10 01:02:54 PM PDT 24 333558350 ps
T417 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2014645368 Mar 10 01:02:15 PM PDT 24 Mar 10 01:03:25 PM PDT 24 202324284 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1331516649 Mar 10 01:02:54 PM PDT 24 Mar 10 01:03:04 PM PDT 24 16559790011 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.703357458 Mar 10 01:01:59 PM PDT 24 Mar 10 01:02:04 PM PDT 24 379417272 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1994768338 Mar 10 01:02:50 PM PDT 24 Mar 10 01:03:37 PM PDT 24 7432835358 ps
T80 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3394585365 Mar 10 01:02:19 PM PDT 24 Mar 10 01:02:53 PM PDT 24 1065917964 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3784989328 Mar 10 01:02:06 PM PDT 24 Mar 10 01:02:19 PM PDT 24 6686608521 ps
T420 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.131971855 Mar 10 01:02:24 PM PDT 24 Mar 10 01:02:33 PM PDT 24 7328030161 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1697160982 Mar 10 01:03:01 PM PDT 24 Mar 10 01:03:11 PM PDT 24 1053755763 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1565971452 Mar 10 01:02:05 PM PDT 24 Mar 10 01:02:13 PM PDT 24 91529215 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.182836559 Mar 10 01:02:01 PM PDT 24 Mar 10 01:02:14 PM PDT 24 5821426345 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2693119543 Mar 10 01:02:22 PM PDT 24 Mar 10 01:03:06 PM PDT 24 3597576934 ps
T82 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3995825254 Mar 10 01:02:58 PM PDT 24 Mar 10 01:03:41 PM PDT 24 3960806110 ps
T424 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1467454001 Mar 10 01:02:50 PM PDT 24 Mar 10 01:03:02 PM PDT 24 1307355603 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.772601828 Mar 10 01:02:06 PM PDT 24 Mar 10 01:02:15 PM PDT 24 564349794 ps
T426 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1326329090 Mar 10 01:02:45 PM PDT 24 Mar 10 01:03:50 PM PDT 24 34437382770 ps
T427 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.16319996 Mar 10 01:02:52 PM PDT 24 Mar 10 01:03:06 PM PDT 24 1666766614 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2656671041 Mar 10 01:02:11 PM PDT 24 Mar 10 01:02:15 PM PDT 24 308172177 ps
T429 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.897577372 Mar 10 01:02:29 PM PDT 24 Mar 10 01:02:33 PM PDT 24 88838920 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3160423572 Mar 10 01:02:54 PM PDT 24 Mar 10 01:03:06 PM PDT 24 4122395915 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.928542939 Mar 10 01:02:10 PM PDT 24 Mar 10 01:02:21 PM PDT 24 1068348431 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1219940450 Mar 10 01:02:06 PM PDT 24 Mar 10 01:02:16 PM PDT 24 4189930973 ps
T433 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3939698307 Mar 10 01:02:52 PM PDT 24 Mar 10 01:03:56 PM PDT 24 15192228026 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3018681792 Mar 10 01:02:35 PM PDT 24 Mar 10 01:02:50 PM PDT 24 7484292065 ps
T435 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3144595675 Mar 10 01:02:22 PM PDT 24 Mar 10 01:02:29 PM PDT 24 553140116 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2329515200 Mar 10 01:02:06 PM PDT 24 Mar 10 01:02:20 PM PDT 24 3310744318 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.104741334 Mar 10 01:02:01 PM PDT 24 Mar 10 01:02:17 PM PDT 24 8633487492 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2667684258 Mar 10 01:02:13 PM PDT 24 Mar 10 01:02:23 PM PDT 24 3377565393 ps
T439 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1118333413 Mar 10 01:02:57 PM PDT 24 Mar 10 01:03:07 PM PDT 24 1860129057 ps
T102 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3617589587 Mar 10 01:02:57 PM PDT 24 Mar 10 01:04:04 PM PDT 24 803073767 ps
T106 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3650636285 Mar 10 01:02:32 PM PDT 24 Mar 10 01:03:17 PM PDT 24 5874022306 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1961704569 Mar 10 01:02:50 PM PDT 24 Mar 10 01:03:05 PM PDT 24 6481259648 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2218523846 Mar 10 01:02:04 PM PDT 24 Mar 10 01:02:18 PM PDT 24 1466612567 ps
T441 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.586030477 Mar 10 01:02:45 PM PDT 24 Mar 10 01:02:53 PM PDT 24 185540587 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3338569517 Mar 10 01:02:11 PM PDT 24 Mar 10 01:02:23 PM PDT 24 2703000148 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3475901305 Mar 10 01:02:05 PM PDT 24 Mar 10 01:02:21 PM PDT 24 17787392983 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3776498397 Mar 10 01:02:24 PM PDT 24 Mar 10 01:03:07 PM PDT 24 2196703954 ps
T445 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3490387086 Mar 10 01:02:51 PM PDT 24 Mar 10 01:03:11 PM PDT 24 8539926954 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2811518545 Mar 10 01:02:50 PM PDT 24 Mar 10 01:04:01 PM PDT 24 2387347504 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.709297199 Mar 10 01:02:51 PM PDT 24 Mar 10 01:02:58 PM PDT 24 371946689 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1657017320 Mar 10 01:02:22 PM PDT 24 Mar 10 01:02:31 PM PDT 24 2750077839 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3890938370 Mar 10 01:02:15 PM PDT 24 Mar 10 01:02:28 PM PDT 24 1634103176 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2809129899 Mar 10 01:02:45 PM PDT 24 Mar 10 01:03:31 PM PDT 24 1919923499 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3369952645 Mar 10 01:02:00 PM PDT 24 Mar 10 01:02:12 PM PDT 24 11945323392 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1830683272 Mar 10 01:02:06 PM PDT 24 Mar 10 01:03:27 PM PDT 24 9366289434 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2557321211 Mar 10 01:02:28 PM PDT 24 Mar 10 01:02:38 PM PDT 24 860949173 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1920176203 Mar 10 01:02:12 PM PDT 24 Mar 10 01:02:24 PM PDT 24 9796930810 ps
T452 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1756117847 Mar 10 01:02:23 PM PDT 24 Mar 10 01:02:27 PM PDT 24 171122183 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1355973658 Mar 10 01:02:12 PM PDT 24 Mar 10 01:02:25 PM PDT 24 3265747203 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3583915757 Mar 10 01:02:05 PM PDT 24 Mar 10 01:02:11 PM PDT 24 85790214 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.326355294 Mar 10 01:02:16 PM PDT 24 Mar 10 01:03:33 PM PDT 24 2271459800 ps
T455 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3325664389 Mar 10 01:02:46 PM PDT 24 Mar 10 01:03:03 PM PDT 24 8668589443 ps
T456 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.856582772 Mar 10 01:02:54 PM PDT 24 Mar 10 01:03:03 PM PDT 24 767281239 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.868140297 Mar 10 01:02:18 PM PDT 24 Mar 10 01:02:23 PM PDT 24 89407699 ps
T458 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3196368926 Mar 10 01:02:16 PM PDT 24 Mar 10 01:02:30 PM PDT 24 1823898629 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3011001221 Mar 10 01:02:00 PM PDT 24 Mar 10 01:02:13 PM PDT 24 946463528 ps
T460 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1747597926 Mar 10 01:02:44 PM PDT 24 Mar 10 01:02:54 PM PDT 24 260178581 ps
T461 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2692458766 Mar 10 01:02:40 PM PDT 24 Mar 10 01:02:45 PM PDT 24 104529715 ps
T462 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.394733480 Mar 10 01:02:52 PM PDT 24 Mar 10 01:03:00 PM PDT 24 2255654765 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3639673295 Mar 10 01:02:24 PM PDT 24 Mar 10 01:03:59 PM PDT 24 25165697090 ps
T463 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.66110812 Mar 10 01:02:58 PM PDT 24 Mar 10 01:03:13 PM PDT 24 1940379102 ps
T464 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.238112274 Mar 10 01:02:10 PM PDT 24 Mar 10 01:02:24 PM PDT 24 3142585517 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2546284428 Mar 10 01:02:06 PM PDT 24 Mar 10 01:03:19 PM PDT 24 2149218184 ps
T465 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.23087372 Mar 10 01:02:33 PM PDT 24 Mar 10 01:02:54 PM PDT 24 2218958134 ps
T466 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3678628686 Mar 10 01:02:23 PM PDT 24 Mar 10 01:02:28 PM PDT 24 88250936 ps

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1915861379
Short name T1
Test name
Test status
Simulation time 34897469392 ps
CPU time 5079.4 seconds
Started Mar 10 01:24:11 PM PDT 24
Finished Mar 10 02:48:52 PM PDT 24
Peak memory 235544 kb
Host smart-147bfd31-38b1-4cee-ad67-b634a7addefd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915861379 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1915861379
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2811111394
Short name T27
Test name
Test status
Simulation time 54073180804 ps
CPU time 252.9 seconds
Started Mar 10 01:23:50 PM PDT 24
Finished Mar 10 01:28:03 PM PDT 24
Peak memory 227836 kb
Host smart-587cd5a0-b5bb-45b4-a4d8-82399d7ef285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811111394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2811111394
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1830874731
Short name T26
Test name
Test status
Simulation time 3152028862 ps
CPU time 28.07 seconds
Started Mar 10 01:23:22 PM PDT 24
Finished Mar 10 01:23:50 PM PDT 24
Peak memory 211528 kb
Host smart-39903be0-65d2-4b76-a933-ded442564869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830874731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1830874731
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3746035407
Short name T107
Test name
Test status
Simulation time 227765093 ps
CPU time 68.81 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:03:14 PM PDT 24
Peak memory 211592 kb
Host smart-9d785419-f2cf-4c5c-83c2-0aca8fb8bffa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746035407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3746035407
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.447985279
Short name T15
Test name
Test status
Simulation time 2884581985 ps
CPU time 30.34 seconds
Started Mar 10 01:24:12 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 212640 kb
Host smart-e9ff24ed-4c77-49ac-887e-93c882e9cd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447985279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.447985279
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3747784558
Short name T19
Test name
Test status
Simulation time 273173566 ps
CPU time 51.99 seconds
Started Mar 10 01:23:21 PM PDT 24
Finished Mar 10 01:24:13 PM PDT 24
Peak memory 236036 kb
Host smart-cd81e643-c255-4577-b36e-9ff817ce124a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747784558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3747784558
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3487178895
Short name T2
Test name
Test status
Simulation time 3370650323 ps
CPU time 36.94 seconds
Started Mar 10 01:24:32 PM PDT 24
Finished Mar 10 01:25:09 PM PDT 24
Peak memory 213032 kb
Host smart-88ba4ce1-e2eb-4e25-8a1e-dc7ec0acf795
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487178895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3487178895
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.489179852
Short name T68
Test name
Test status
Simulation time 2230875380 ps
CPU time 28.03 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:02:28 PM PDT 24
Peak memory 210820 kb
Host smart-b6ace44c-deec-4a9c-8e3f-08f28b463f7c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489179852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.489179852
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1506006376
Short name T105
Test name
Test status
Simulation time 8287545737 ps
CPU time 80.01 seconds
Started Mar 10 01:02:58 PM PDT 24
Finished Mar 10 01:04:18 PM PDT 24
Peak memory 210848 kb
Host smart-84682d19-0e99-4c10-bc86-88a88d0a743e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506006376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1506006376
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.63462396
Short name T101
Test name
Test status
Simulation time 1428284097 ps
CPU time 74.83 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:04:05 PM PDT 24
Peak memory 211348 kb
Host smart-643cf6d3-a246-449c-a12f-f4b9163b6fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63462396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_int
g_err.63462396
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1523835546
Short name T53
Test name
Test status
Simulation time 1025342595 ps
CPU time 8.09 seconds
Started Mar 10 01:23:39 PM PDT 24
Finished Mar 10 01:23:48 PM PDT 24
Peak memory 210912 kb
Host smart-00c00ef1-a5e5-4f92-aa8d-a0def94eac1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523835546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1523835546
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3820548924
Short name T79
Test name
Test status
Simulation time 45357136459 ps
CPU time 92.76 seconds
Started Mar 10 01:02:39 PM PDT 24
Finished Mar 10 01:04:13 PM PDT 24
Peak memory 210868 kb
Host smart-c37e0d9c-1ec0-4d22-bb0e-eb64b8403a0b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820548924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3820548924
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1758596761
Short name T270
Test name
Test status
Simulation time 693137690 ps
CPU time 9.53 seconds
Started Mar 10 01:23:19 PM PDT 24
Finished Mar 10 01:23:29 PM PDT 24
Peak memory 211592 kb
Host smart-d36e684c-28d8-48aa-bd29-aa3876fe6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758596761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1758596761
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.4070308359
Short name T4
Test name
Test status
Simulation time 30229329616 ps
CPU time 1917.9 seconds
Started Mar 10 01:23:49 PM PDT 24
Finished Mar 10 01:55:47 PM PDT 24
Peak memory 235564 kb
Host smart-02b09bb6-39ba-410d-8b05-a208482e4e96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070308359 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.4070308359
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3421065022
Short name T61
Test name
Test status
Simulation time 2595542892 ps
CPU time 5.58 seconds
Started Mar 10 01:02:58 PM PDT 24
Finished Mar 10 01:03:04 PM PDT 24
Peak memory 210804 kb
Host smart-04c0804b-1325-44da-86fd-75a96647ef19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421065022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3421065022
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1994768338
Short name T110
Test name
Test status
Simulation time 7432835358 ps
CPU time 46.36 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:03:37 PM PDT 24
Peak memory 211656 kb
Host smart-452a698f-ea0c-4880-abdf-4b6d7cd4bf94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994768338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1994768338
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3941113656
Short name T14
Test name
Test status
Simulation time 4209413928 ps
CPU time 170.55 seconds
Started Mar 10 01:24:23 PM PDT 24
Finished Mar 10 01:27:14 PM PDT 24
Peak memory 227392 kb
Host smart-30c8326a-d52e-41e4-9112-7c93edf6b087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941113656 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3941113656
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3784920956
Short name T58
Test name
Test status
Simulation time 8153725315 ps
CPU time 22.44 seconds
Started Mar 10 01:23:46 PM PDT 24
Finished Mar 10 01:24:09 PM PDT 24
Peak memory 213260 kb
Host smart-8bdd47c3-6214-44d1-a258-6077892acab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784920956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3784920956
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3369952645
Short name T449
Test name
Test status
Simulation time 11945323392 ps
CPU time 11.81 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:02:12 PM PDT 24
Peak memory 210812 kb
Host smart-b8a2e1fb-e357-4d37-a6a3-c39bea8902a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369952645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3369952645
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.182836559
Short name T422
Test name
Test status
Simulation time 5821426345 ps
CPU time 12.89 seconds
Started Mar 10 01:02:01 PM PDT 24
Finished Mar 10 01:02:14 PM PDT 24
Peak memory 210800 kb
Host smart-f171b97d-c33d-4fea-8c24-9f2f9ad3efd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182836559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.182836559
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3630117500
Short name T98
Test name
Test status
Simulation time 6906668795 ps
CPU time 15.79 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:02:15 PM PDT 24
Peak memory 210836 kb
Host smart-43d7bb05-ae88-4322-b522-d5bd58928c00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630117500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3630117500
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1120191114
Short name T409
Test name
Test status
Simulation time 14989139157 ps
CPU time 14.67 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:02:15 PM PDT 24
Peak memory 214812 kb
Host smart-88c50c40-1a85-4b89-8ccf-4fe3861d9dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120191114 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1120191114
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2800989986
Short name T85
Test name
Test status
Simulation time 3792191196 ps
CPU time 10.27 seconds
Started Mar 10 01:01:59 PM PDT 24
Finished Mar 10 01:02:09 PM PDT 24
Peak memory 210900 kb
Host smart-90ed861b-8ca6-413c-9704-3668c69ae348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800989986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2800989986
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.104741334
Short name T437
Test name
Test status
Simulation time 8633487492 ps
CPU time 16.12 seconds
Started Mar 10 01:02:01 PM PDT 24
Finished Mar 10 01:02:17 PM PDT 24
Peak memory 210728 kb
Host smart-5a8bf8cb-167b-4245-a53b-d7e958bd3a4b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104741334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.104741334
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.703357458
Short name T418
Test name
Test status
Simulation time 379417272 ps
CPU time 4.22 seconds
Started Mar 10 01:01:59 PM PDT 24
Finished Mar 10 01:02:04 PM PDT 24
Peak memory 210656 kb
Host smart-1e37b710-0f73-4ac3-b05d-554d6ec2c398
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703357458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
703357458
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1597168220
Short name T393
Test name
Test status
Simulation time 48416083772 ps
CPU time 95.46 seconds
Started Mar 10 01:02:01 PM PDT 24
Finished Mar 10 01:03:37 PM PDT 24
Peak memory 210860 kb
Host smart-0dce80d0-db6c-4054-b79c-666315541200
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597168220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1597168220
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2822083601
Short name T407
Test name
Test status
Simulation time 12620503483 ps
CPU time 16.95 seconds
Started Mar 10 01:01:58 PM PDT 24
Finished Mar 10 01:02:15 PM PDT 24
Peak memory 210876 kb
Host smart-ecb2efc7-d603-40b2-8db9-35502517da2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822083601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2822083601
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1303469884
Short name T380
Test name
Test status
Simulation time 376984611 ps
CPU time 7.7 seconds
Started Mar 10 01:02:01 PM PDT 24
Finished Mar 10 01:02:08 PM PDT 24
Peak memory 213892 kb
Host smart-a8cbcded-16d6-4400-a537-f41f849ec2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303469884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1303469884
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4075102606
Short name T47
Test name
Test status
Simulation time 3651503056 ps
CPU time 77.19 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:03:17 PM PDT 24
Peak memory 210788 kb
Host smart-977f4d2c-6069-45c3-a2b2-addb3dc568f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075102606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4075102606
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3475901305
Short name T443
Test name
Test status
Simulation time 17787392983 ps
CPU time 15.44 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:02:21 PM PDT 24
Peak memory 210784 kb
Host smart-02375df6-c510-4921-a4ac-108ed6f64ae9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475901305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3475901305
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3583915757
Short name T454
Test name
Test status
Simulation time 85790214 ps
CPU time 4.67 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:02:11 PM PDT 24
Peak memory 210728 kb
Host smart-85d382f5-e1ed-46f5-b075-d115655a829f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583915757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3583915757
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1565971452
Short name T81
Test name
Test status
Simulation time 91529215 ps
CPU time 7.31 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:02:13 PM PDT 24
Peak memory 210636 kb
Host smart-9b934f37-8932-4645-89d3-397b8fcd7ebd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565971452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1565971452
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3921255200
Short name T389
Test name
Test status
Simulation time 98027723 ps
CPU time 4.72 seconds
Started Mar 10 01:02:04 PM PDT 24
Finished Mar 10 01:02:09 PM PDT 24
Peak memory 213448 kb
Host smart-7950693c-294d-44da-b3bc-6077e7b34be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921255200 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3921255200
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2329515200
Short name T436
Test name
Test status
Simulation time 3310744318 ps
CPU time 14.37 seconds
Started Mar 10 01:02:06 PM PDT 24
Finished Mar 10 01:02:20 PM PDT 24
Peak memory 210856 kb
Host smart-c597bcab-e052-483f-a349-8097ad50f898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329515200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2329515200
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.648695486
Short name T401
Test name
Test status
Simulation time 3767545907 ps
CPU time 9.5 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:02:15 PM PDT 24
Peak memory 210688 kb
Host smart-0c74914f-991c-4240-a14f-d8a0b315bcf6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648695486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.648695486
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3784989328
Short name T419
Test name
Test status
Simulation time 6686608521 ps
CPU time 12.73 seconds
Started Mar 10 01:02:06 PM PDT 24
Finished Mar 10 01:02:19 PM PDT 24
Peak memory 210752 kb
Host smart-c611ae73-4693-47c5-91e3-5da7b484d801
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784989328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3784989328
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.772601828
Short name T425
Test name
Test status
Simulation time 564349794 ps
CPU time 9.05 seconds
Started Mar 10 01:02:06 PM PDT 24
Finished Mar 10 01:02:15 PM PDT 24
Peak memory 210744 kb
Host smart-ba8643ed-4166-4ed3-85cf-5039ab65b7bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772601828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.772601828
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3011001221
Short name T459
Test name
Test status
Simulation time 946463528 ps
CPU time 13.73 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:02:13 PM PDT 24
Peak memory 215272 kb
Host smart-5fca6cc8-81b8-4399-ae70-cd08c124ad96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011001221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3011001221
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2692458766
Short name T461
Test name
Test status
Simulation time 104529715 ps
CPU time 4.98 seconds
Started Mar 10 01:02:40 PM PDT 24
Finished Mar 10 01:02:45 PM PDT 24
Peak memory 213780 kb
Host smart-c0119791-c283-4c0d-9ab4-f83b112ecc6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692458766 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2692458766
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3018681792
Short name T434
Test name
Test status
Simulation time 7484292065 ps
CPU time 14.89 seconds
Started Mar 10 01:02:35 PM PDT 24
Finished Mar 10 01:02:50 PM PDT 24
Peak memory 210796 kb
Host smart-dcc967ba-7cd4-45ad-b1e1-678e4ef94804
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018681792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3018681792
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2382109815
Short name T411
Test name
Test status
Simulation time 89296158 ps
CPU time 4.27 seconds
Started Mar 10 01:02:39 PM PDT 24
Finished Mar 10 01:02:43 PM PDT 24
Peak memory 210760 kb
Host smart-92d2cf2d-7869-48c5-bee9-e74f7191532c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382109815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2382109815
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.23087372
Short name T465
Test name
Test status
Simulation time 2218958134 ps
CPU time 20.33 seconds
Started Mar 10 01:02:33 PM PDT 24
Finished Mar 10 01:02:54 PM PDT 24
Peak memory 215128 kb
Host smart-c1c6a1ad-1d03-456e-8c69-30841cfbb6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23087372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.23087372
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3650636285
Short name T106
Test name
Test status
Simulation time 5874022306 ps
CPU time 44.2 seconds
Started Mar 10 01:02:32 PM PDT 24
Finished Mar 10 01:03:17 PM PDT 24
Peak memory 211408 kb
Host smart-2524e5f0-5d96-4cc9-8fe6-ea7e8849c9ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650636285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3650636285
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3345755356
Short name T391
Test name
Test status
Simulation time 108063674 ps
CPU time 5.12 seconds
Started Mar 10 01:02:46 PM PDT 24
Finished Mar 10 01:02:51 PM PDT 24
Peak memory 213840 kb
Host smart-35ea597a-561c-46b0-8352-f8790a4fa079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345755356 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3345755356
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1961704569
Short name T83
Test name
Test status
Simulation time 6481259648 ps
CPU time 14.5 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:03:05 PM PDT 24
Peak memory 210808 kb
Host smart-b3fa26be-8855-410f-abe7-2f72d9dfd217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961704569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1961704569
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1326329090
Short name T426
Test name
Test status
Simulation time 34437382770 ps
CPU time 65.36 seconds
Started Mar 10 01:02:45 PM PDT 24
Finished Mar 10 01:03:50 PM PDT 24
Peak memory 210888 kb
Host smart-80afbd4e-2a37-4847-aa28-ce5065bcbcc9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326329090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1326329090
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3325664389
Short name T455
Test name
Test status
Simulation time 8668589443 ps
CPU time 17.45 seconds
Started Mar 10 01:02:46 PM PDT 24
Finished Mar 10 01:03:03 PM PDT 24
Peak memory 210852 kb
Host smart-8a002cbf-5ff8-4fad-aead-80ac7b5868e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325664389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3325664389
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1747597926
Short name T460
Test name
Test status
Simulation time 260178581 ps
CPU time 10.1 seconds
Started Mar 10 01:02:44 PM PDT 24
Finished Mar 10 01:02:54 PM PDT 24
Peak memory 215072 kb
Host smart-72c325c9-04d3-4f40-81dc-e11f4ee825d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747597926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1747597926
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2809129899
Short name T108
Test name
Test status
Simulation time 1919923499 ps
CPU time 45.87 seconds
Started Mar 10 01:02:45 PM PDT 24
Finished Mar 10 01:03:31 PM PDT 24
Peak memory 210948 kb
Host smart-a51c2990-96d4-49ed-82f6-64821fb8f3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809129899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2809129899
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.394733480
Short name T462
Test name
Test status
Simulation time 2255654765 ps
CPU time 8.67 seconds
Started Mar 10 01:02:52 PM PDT 24
Finished Mar 10 01:03:00 PM PDT 24
Peak memory 214424 kb
Host smart-9cfa91b4-85ca-4d0e-955c-def31c59849c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394733480 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.394733480
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3743433767
Short name T402
Test name
Test status
Simulation time 3165320704 ps
CPU time 13.28 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:03:03 PM PDT 24
Peak memory 210860 kb
Host smart-3c6ce351-2850-4ff6-9271-71c95740314a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743433767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3743433767
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1339681438
Short name T67
Test name
Test status
Simulation time 2946044047 ps
CPU time 27.95 seconds
Started Mar 10 01:02:45 PM PDT 24
Finished Mar 10 01:03:13 PM PDT 24
Peak memory 210976 kb
Host smart-f8d2683d-63dd-45b7-8392-ef9265fae586
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339681438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1339681438
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1467454001
Short name T424
Test name
Test status
Simulation time 1307355603 ps
CPU time 11.99 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:03:02 PM PDT 24
Peak memory 210756 kb
Host smart-1e8f611a-1ae7-4adb-85ca-71a523fe3baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467454001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1467454001
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.586030477
Short name T441
Test name
Test status
Simulation time 185540587 ps
CPU time 7.57 seconds
Started Mar 10 01:02:45 PM PDT 24
Finished Mar 10 01:02:53 PM PDT 24
Peak memory 215004 kb
Host smart-503298f6-0878-48bd-ab41-7ae85ae7bcae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586030477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.586030477
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.16319996
Short name T427
Test name
Test status
Simulation time 1666766614 ps
CPU time 13.66 seconds
Started Mar 10 01:02:52 PM PDT 24
Finished Mar 10 01:03:06 PM PDT 24
Peak memory 211984 kb
Host smart-8de2e538-9659-4f5b-84dd-104c16599196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319996 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.16319996
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1331516649
Short name T88
Test name
Test status
Simulation time 16559790011 ps
CPU time 10.26 seconds
Started Mar 10 01:02:54 PM PDT 24
Finished Mar 10 01:03:04 PM PDT 24
Peak memory 210812 kb
Host smart-14736c6b-3b4d-4e23-9977-bd4916f4a004
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331516649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1331516649
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3939698307
Short name T433
Test name
Test status
Simulation time 15192228026 ps
CPU time 64.23 seconds
Started Mar 10 01:02:52 PM PDT 24
Finished Mar 10 01:03:56 PM PDT 24
Peak memory 210868 kb
Host smart-d0b848c5-0ded-4229-9d9f-9faf1d6fca72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939698307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3939698307
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.709297199
Short name T446
Test name
Test status
Simulation time 371946689 ps
CPU time 6.66 seconds
Started Mar 10 01:02:51 PM PDT 24
Finished Mar 10 01:02:58 PM PDT 24
Peak memory 210744 kb
Host smart-1f9c5e02-c42d-4e93-93e7-7466f8052d33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709297199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.709297199
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.646248588
Short name T374
Test name
Test status
Simulation time 2153962212 ps
CPU time 13.27 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:03:04 PM PDT 24
Peak memory 214848 kb
Host smart-5dbb6abf-6452-407f-8995-9bddc5f3a9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646248588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.646248588
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2811518545
Short name T111
Test name
Test status
Simulation time 2387347504 ps
CPU time 71.51 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:04:01 PM PDT 24
Peak memory 211432 kb
Host smart-29cc4b10-c001-4b5f-96f6-ef5462e008a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811518545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2811518545
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4007513894
Short name T373
Test name
Test status
Simulation time 356349794 ps
CPU time 7.28 seconds
Started Mar 10 01:02:52 PM PDT 24
Finished Mar 10 01:02:59 PM PDT 24
Peak memory 214908 kb
Host smart-4892c70e-404e-4fa7-9fdd-52fc75ec0049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007513894 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4007513894
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2169271565
Short name T399
Test name
Test status
Simulation time 4860611476 ps
CPU time 11.93 seconds
Started Mar 10 01:02:54 PM PDT 24
Finished Mar 10 01:03:06 PM PDT 24
Peak memory 210896 kb
Host smart-c28178ad-4754-4dc2-ba42-9472ed7d763b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169271565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2169271565
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4274119964
Short name T64
Test name
Test status
Simulation time 2010400371 ps
CPU time 27.99 seconds
Started Mar 10 01:02:53 PM PDT 24
Finished Mar 10 01:03:21 PM PDT 24
Peak memory 210752 kb
Host smart-57935900-81c6-4166-818f-446129dee581
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274119964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4274119964
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3288533674
Short name T416
Test name
Test status
Simulation time 333558350 ps
CPU time 4.22 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:02:54 PM PDT 24
Peak memory 210748 kb
Host smart-bfdf478e-c871-4860-8e89-a1d4648223ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288533674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3288533674
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2444261311
Short name T376
Test name
Test status
Simulation time 5347019259 ps
CPU time 13.62 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:03:03 PM PDT 24
Peak memory 215428 kb
Host smart-c54b2af6-6e92-4c95-a27c-322bea712ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444261311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2444261311
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1696192699
Short name T397
Test name
Test status
Simulation time 4343939648 ps
CPU time 48.49 seconds
Started Mar 10 01:02:53 PM PDT 24
Finished Mar 10 01:03:42 PM PDT 24
Peak memory 212764 kb
Host smart-52dc71c3-60ef-4609-8bff-4e3eaa3bebab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696192699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1696192699
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3160423572
Short name T430
Test name
Test status
Simulation time 4122395915 ps
CPU time 11.86 seconds
Started Mar 10 01:02:54 PM PDT 24
Finished Mar 10 01:03:06 PM PDT 24
Peak memory 214232 kb
Host smart-a27f4fc8-1576-48d2-a8c9-36947fb77ff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160423572 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3160423572
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3513319928
Short name T390
Test name
Test status
Simulation time 297401867 ps
CPU time 4.12 seconds
Started Mar 10 01:02:50 PM PDT 24
Finished Mar 10 01:02:54 PM PDT 24
Peak memory 210744 kb
Host smart-5d9d1426-785c-4c3c-b92f-237bd56641f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513319928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3513319928
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1073987663
Short name T78
Test name
Test status
Simulation time 86527589175 ps
CPU time 73.11 seconds
Started Mar 10 01:02:49 PM PDT 24
Finished Mar 10 01:04:02 PM PDT 24
Peak memory 210884 kb
Host smart-6141179c-3ab6-48ed-be75-5472a40bb216
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073987663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1073987663
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.856582772
Short name T456
Test name
Test status
Simulation time 767281239 ps
CPU time 9.05 seconds
Started Mar 10 01:02:54 PM PDT 24
Finished Mar 10 01:03:03 PM PDT 24
Peak memory 210740 kb
Host smart-bd99283c-8bcd-4ec8-b81c-8b1be253d576
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856582772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.856582772
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3490387086
Short name T445
Test name
Test status
Simulation time 8539926954 ps
CPU time 20 seconds
Started Mar 10 01:02:51 PM PDT 24
Finished Mar 10 01:03:11 PM PDT 24
Peak memory 214240 kb
Host smart-3980f2e7-8358-4f17-989d-76e8c193e53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490387086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3490387086
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4058610340
Short name T386
Test name
Test status
Simulation time 2117592179 ps
CPU time 16.03 seconds
Started Mar 10 01:02:56 PM PDT 24
Finished Mar 10 01:03:12 PM PDT 24
Peak memory 212816 kb
Host smart-88459c1a-24d9-4f26-bfb6-d47650b7d1e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058610340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4058610340
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.982931128
Short name T75
Test name
Test status
Simulation time 11424220698 ps
CPU time 44.24 seconds
Started Mar 10 01:02:51 PM PDT 24
Finished Mar 10 01:03:36 PM PDT 24
Peak memory 210864 kb
Host smart-b3d168df-a22b-4a02-b1bc-e1432a122df5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982931128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.982931128
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.619690391
Short name T50
Test name
Test status
Simulation time 86503620 ps
CPU time 4.19 seconds
Started Mar 10 01:02:56 PM PDT 24
Finished Mar 10 01:03:00 PM PDT 24
Peak memory 210780 kb
Host smart-be37edc1-96ee-40de-9b15-f71839def39f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619690391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.619690391
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1118333413
Short name T439
Test name
Test status
Simulation time 1860129057 ps
CPU time 9.8 seconds
Started Mar 10 01:02:57 PM PDT 24
Finished Mar 10 01:03:07 PM PDT 24
Peak memory 214784 kb
Host smart-2cb33cc0-c13b-4e3e-b648-908d9ea8b434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118333413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1118333413
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.150427758
Short name T375
Test name
Test status
Simulation time 634977452 ps
CPU time 6.19 seconds
Started Mar 10 01:02:56 PM PDT 24
Finished Mar 10 01:03:02 PM PDT 24
Peak memory 214476 kb
Host smart-198f041f-17b6-4560-af8a-5790e80b3970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150427758 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.150427758
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2935343524
Short name T62
Test name
Test status
Simulation time 1392512014 ps
CPU time 12.52 seconds
Started Mar 10 01:02:55 PM PDT 24
Finished Mar 10 01:03:07 PM PDT 24
Peak memory 210764 kb
Host smart-95f60712-cac7-4f0c-a9eb-783bb0a74d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935343524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2935343524
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3995825254
Short name T82
Test name
Test status
Simulation time 3960806110 ps
CPU time 43.75 seconds
Started Mar 10 01:02:58 PM PDT 24
Finished Mar 10 01:03:41 PM PDT 24
Peak memory 210928 kb
Host smart-14ba63a1-ae7f-4d12-af5c-06b3e96ce582
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995825254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3995825254
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4105663139
Short name T404
Test name
Test status
Simulation time 171418842 ps
CPU time 4.31 seconds
Started Mar 10 01:02:56 PM PDT 24
Finished Mar 10 01:03:01 PM PDT 24
Peak memory 210760 kb
Host smart-b03c8777-7bcf-4c65-8fe6-24acfa34d6d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105663139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4105663139
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3870415253
Short name T382
Test name
Test status
Simulation time 2561845204 ps
CPU time 11.02 seconds
Started Mar 10 01:02:59 PM PDT 24
Finished Mar 10 01:03:10 PM PDT 24
Peak memory 215000 kb
Host smart-eec0481a-7ea1-472a-a020-bf6d5870b27e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870415253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3870415253
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3617589587
Short name T102
Test name
Test status
Simulation time 803073767 ps
CPU time 67.72 seconds
Started Mar 10 01:02:57 PM PDT 24
Finished Mar 10 01:04:04 PM PDT 24
Peak memory 212356 kb
Host smart-b260383d-6f8c-41b9-add3-8351a7b63438
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617589587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3617589587
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.56500128
Short name T385
Test name
Test status
Simulation time 426488896 ps
CPU time 4.36 seconds
Started Mar 10 01:03:02 PM PDT 24
Finished Mar 10 01:03:06 PM PDT 24
Peak memory 212260 kb
Host smart-8f5b63d8-4bb0-4159-b684-a2a97fe6ac39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56500128 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.56500128
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.929801314
Short name T51
Test name
Test status
Simulation time 398829239 ps
CPU time 5.67 seconds
Started Mar 10 01:02:56 PM PDT 24
Finished Mar 10 01:03:01 PM PDT 24
Peak memory 210688 kb
Host smart-1950661e-975d-4f18-8b5a-3212c9cf4b56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929801314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.929801314
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2744471583
Short name T63
Test name
Test status
Simulation time 7924714137 ps
CPU time 42.36 seconds
Started Mar 10 01:02:57 PM PDT 24
Finished Mar 10 01:03:39 PM PDT 24
Peak memory 210964 kb
Host smart-9962c49d-d012-41bb-b2d3-c8d5e56c86ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744471583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2744471583
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1547194954
Short name T89
Test name
Test status
Simulation time 385347014 ps
CPU time 6.83 seconds
Started Mar 10 01:02:56 PM PDT 24
Finished Mar 10 01:03:03 PM PDT 24
Peak memory 210768 kb
Host smart-877760e0-37d8-4053-b04e-45ffeee772f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547194954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1547194954
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.66110812
Short name T463
Test name
Test status
Simulation time 1940379102 ps
CPU time 15.34 seconds
Started Mar 10 01:02:58 PM PDT 24
Finished Mar 10 01:03:13 PM PDT 24
Peak memory 214852 kb
Host smart-cce719ee-f99b-4188-a6d7-0a664e424615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66110812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.66110812
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3320640585
Short name T100
Test name
Test status
Simulation time 1717612918 ps
CPU time 71.13 seconds
Started Mar 10 01:02:55 PM PDT 24
Finished Mar 10 01:04:06 PM PDT 24
Peak memory 210740 kb
Host smart-af4be026-34ca-4334-813d-41e80a7715d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320640585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3320640585
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2982915070
Short name T408
Test name
Test status
Simulation time 2470010096 ps
CPU time 11.51 seconds
Started Mar 10 01:03:01 PM PDT 24
Finished Mar 10 01:03:13 PM PDT 24
Peak memory 214408 kb
Host smart-07962d29-cf8d-43ed-bfe7-b970d92b0ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982915070 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2982915070
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2743164591
Short name T97
Test name
Test status
Simulation time 378363812 ps
CPU time 6.62 seconds
Started Mar 10 01:03:01 PM PDT 24
Finished Mar 10 01:03:08 PM PDT 24
Peak memory 210740 kb
Host smart-4a2c2386-f4a6-48cd-8dca-887e9c4692dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743164591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2743164591
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3165537882
Short name T93
Test name
Test status
Simulation time 7848030667 ps
CPU time 70.43 seconds
Started Mar 10 01:03:01 PM PDT 24
Finished Mar 10 01:04:12 PM PDT 24
Peak memory 210800 kb
Host smart-d6d47953-6e60-4214-84fa-b075a747220f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165537882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3165537882
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1697160982
Short name T421
Test name
Test status
Simulation time 1053755763 ps
CPU time 9.42 seconds
Started Mar 10 01:03:01 PM PDT 24
Finished Mar 10 01:03:11 PM PDT 24
Peak memory 210796 kb
Host smart-8f730232-008f-444f-bbae-5ec9b071b6bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697160982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1697160982
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2463850273
Short name T372
Test name
Test status
Simulation time 284488523 ps
CPU time 9.32 seconds
Started Mar 10 01:03:01 PM PDT 24
Finished Mar 10 01:03:11 PM PDT 24
Peak memory 213796 kb
Host smart-f414b882-ff1e-4efb-93fc-e79d1ec4d4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463850273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2463850273
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2172469453
Short name T48
Test name
Test status
Simulation time 30064881562 ps
CPU time 79.69 seconds
Started Mar 10 01:03:01 PM PDT 24
Finished Mar 10 01:04:20 PM PDT 24
Peak memory 210916 kb
Host smart-8f7c5b0c-70b6-449d-b209-6e4e3c72d450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172469453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2172469453
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.475783160
Short name T66
Test name
Test status
Simulation time 88347739 ps
CPU time 4.33 seconds
Started Mar 10 01:02:12 PM PDT 24
Finished Mar 10 01:02:17 PM PDT 24
Peak memory 210708 kb
Host smart-65314804-1f76-444f-811d-2566384bd20e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475783160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.475783160
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2085802668
Short name T394
Test name
Test status
Simulation time 2405790652 ps
CPU time 15.04 seconds
Started Mar 10 01:02:04 PM PDT 24
Finished Mar 10 01:02:19 PM PDT 24
Peak memory 210720 kb
Host smart-f0168422-bd91-4e23-b1ec-9a4455e6f598
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085802668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2085802668
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1219940450
Short name T432
Test name
Test status
Simulation time 4189930973 ps
CPU time 9.43 seconds
Started Mar 10 01:02:06 PM PDT 24
Finished Mar 10 01:02:16 PM PDT 24
Peak memory 210856 kb
Host smart-2cb9f79a-9229-4f5d-a4cd-6c39c41cd70d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219940450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1219940450
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2399867536
Short name T381
Test name
Test status
Simulation time 3941290126 ps
CPU time 10.25 seconds
Started Mar 10 01:02:16 PM PDT 24
Finished Mar 10 01:02:26 PM PDT 24
Peak memory 214356 kb
Host smart-01cc171b-2402-4014-9f1d-7f4f2302c1e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399867536 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2399867536
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2218523846
Short name T440
Test name
Test status
Simulation time 1466612567 ps
CPU time 12.91 seconds
Started Mar 10 01:02:04 PM PDT 24
Finished Mar 10 01:02:18 PM PDT 24
Peak memory 210668 kb
Host smart-67a9ca02-54f4-4818-b674-c7e518ed845b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218523846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2218523846
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2703008735
Short name T410
Test name
Test status
Simulation time 168079605 ps
CPU time 4.12 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:02:10 PM PDT 24
Peak memory 210608 kb
Host smart-4b7344aa-1e30-49e2-9d4b-063ed0f42a4a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703008735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2703008735
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1966906342
Short name T396
Test name
Test status
Simulation time 2288658270 ps
CPU time 11.05 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:02:16 PM PDT 24
Peak memory 210808 kb
Host smart-949258f3-e12f-40f3-8964-84dcd11161ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966906342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1966906342
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1830683272
Short name T450
Test name
Test status
Simulation time 9366289434 ps
CPU time 79.88 seconds
Started Mar 10 01:02:06 PM PDT 24
Finished Mar 10 01:03:27 PM PDT 24
Peak memory 210876 kb
Host smart-eda05665-66a0-4537-9fa3-e8006c342880
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830683272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1830683272
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1920176203
Short name T451
Test name
Test status
Simulation time 9796930810 ps
CPU time 12.48 seconds
Started Mar 10 01:02:12 PM PDT 24
Finished Mar 10 01:02:24 PM PDT 24
Peak memory 210888 kb
Host smart-43527655-4e9c-4d8b-b2aa-c023c99b09c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920176203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1920176203
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3215273585
Short name T398
Test name
Test status
Simulation time 938517230 ps
CPU time 13.22 seconds
Started Mar 10 01:02:05 PM PDT 24
Finished Mar 10 01:02:19 PM PDT 24
Peak memory 215152 kb
Host smart-2ec433a0-afce-476b-a626-12a13b8fa72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215273585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3215273585
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2546284428
Short name T103
Test name
Test status
Simulation time 2149218184 ps
CPU time 72.67 seconds
Started Mar 10 01:02:06 PM PDT 24
Finished Mar 10 01:03:19 PM PDT 24
Peak memory 210956 kb
Host smart-3b5b4183-7105-45e0-8396-f3acd120c3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546284428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2546284428
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.928542939
Short name T431
Test name
Test status
Simulation time 1068348431 ps
CPU time 10.7 seconds
Started Mar 10 01:02:10 PM PDT 24
Finished Mar 10 01:02:21 PM PDT 24
Peak memory 210708 kb
Host smart-a0efcef6-1884-43de-9081-52890d25150a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928542939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.928542939
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2667684258
Short name T438
Test name
Test status
Simulation time 3377565393 ps
CPU time 9.35 seconds
Started Mar 10 01:02:13 PM PDT 24
Finished Mar 10 01:02:23 PM PDT 24
Peak memory 210828 kb
Host smart-8b92dd05-03de-4589-9d14-c88b9e38ddda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667684258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2667684258
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2079309720
Short name T95
Test name
Test status
Simulation time 1395403326 ps
CPU time 13.62 seconds
Started Mar 10 01:02:17 PM PDT 24
Finished Mar 10 01:02:31 PM PDT 24
Peak memory 210680 kb
Host smart-c475ec76-ab73-4283-8d46-985d4932c612
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079309720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2079309720
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3338569517
Short name T442
Test name
Test status
Simulation time 2703000148 ps
CPU time 11.84 seconds
Started Mar 10 01:02:11 PM PDT 24
Finished Mar 10 01:02:23 PM PDT 24
Peak memory 213396 kb
Host smart-e080c290-de7a-4b9e-afbd-281f8fee8fde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338569517 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3338569517
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2656671041
Short name T428
Test name
Test status
Simulation time 308172177 ps
CPU time 4.14 seconds
Started Mar 10 01:02:11 PM PDT 24
Finished Mar 10 01:02:15 PM PDT 24
Peak memory 210620 kb
Host smart-133c3b26-35c2-49e6-9d82-ad41ec9a338d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656671041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2656671041
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.98021900
Short name T403
Test name
Test status
Simulation time 1169549333 ps
CPU time 10.68 seconds
Started Mar 10 01:02:16 PM PDT 24
Finished Mar 10 01:02:28 PM PDT 24
Peak memory 210688 kb
Host smart-b66ac48e-a0a8-4637-befd-d514881eac58
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98021900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_
mem_partial_access.98021900
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2718305022
Short name T395
Test name
Test status
Simulation time 2146531621 ps
CPU time 15.63 seconds
Started Mar 10 01:02:11 PM PDT 24
Finished Mar 10 01:02:27 PM PDT 24
Peak memory 210600 kb
Host smart-df492f69-61e4-464f-b883-11f8aadd289f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718305022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2718305022
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4265498297
Short name T387
Test name
Test status
Simulation time 1499706744 ps
CPU time 18.94 seconds
Started Mar 10 01:02:17 PM PDT 24
Finished Mar 10 01:02:36 PM PDT 24
Peak memory 210716 kb
Host smart-5e2dc583-f38e-4c89-86ca-3213e51a73ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265498297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4265498297
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1741476550
Short name T90
Test name
Test status
Simulation time 768599567 ps
CPU time 10.43 seconds
Started Mar 10 01:02:11 PM PDT 24
Finished Mar 10 01:02:21 PM PDT 24
Peak memory 210828 kb
Host smart-1c0c0dd3-7c80-43fb-9539-c87ec5749eed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741476550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1741476550
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2374107697
Short name T406
Test name
Test status
Simulation time 8479492576 ps
CPU time 21.68 seconds
Started Mar 10 01:02:17 PM PDT 24
Finished Mar 10 01:02:39 PM PDT 24
Peak memory 216556 kb
Host smart-897f1ea2-c925-41bf-b718-b7574cea4be9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374107697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2374107697
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.326355294
Short name T112
Test name
Test status
Simulation time 2271459800 ps
CPU time 76.66 seconds
Started Mar 10 01:02:16 PM PDT 24
Finished Mar 10 01:03:33 PM PDT 24
Peak memory 212508 kb
Host smart-261e621b-ddaf-42a6-9e0d-06841b0d337e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326355294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.326355294
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.238112274
Short name T464
Test name
Test status
Simulation time 3142585517 ps
CPU time 13.92 seconds
Started Mar 10 01:02:10 PM PDT 24
Finished Mar 10 01:02:24 PM PDT 24
Peak memory 210744 kb
Host smart-d62d83aa-ab6e-4144-b532-9550f163776a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238112274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.238112274
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3120981218
Short name T392
Test name
Test status
Simulation time 789652231 ps
CPU time 5.9 seconds
Started Mar 10 01:02:13 PM PDT 24
Finished Mar 10 01:02:19 PM PDT 24
Peak memory 210708 kb
Host smart-ae66f48b-8c9f-4fab-8467-c91962d745ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120981218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3120981218
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.868140297
Short name T457
Test name
Test status
Simulation time 89407699 ps
CPU time 5.78 seconds
Started Mar 10 01:02:18 PM PDT 24
Finished Mar 10 01:02:23 PM PDT 24
Peak memory 210596 kb
Host smart-c7f9010a-819b-4e30-a0a7-dec4f9ff8d4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868140297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.868140297
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2592929499
Short name T383
Test name
Test status
Simulation time 271865480 ps
CPU time 6.45 seconds
Started Mar 10 01:02:17 PM PDT 24
Finished Mar 10 01:02:24 PM PDT 24
Peak memory 219024 kb
Host smart-6378fc1b-108e-4028-8843-39a940aecd0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592929499 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2592929499
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1960064072
Short name T94
Test name
Test status
Simulation time 2391651969 ps
CPU time 8.08 seconds
Started Mar 10 01:02:10 PM PDT 24
Finished Mar 10 01:02:19 PM PDT 24
Peak memory 210868 kb
Host smart-04e3ca41-c3aa-441f-8d59-eb93aea1e00d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960064072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1960064072
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1355973658
Short name T453
Test name
Test status
Simulation time 3265747203 ps
CPU time 13.12 seconds
Started Mar 10 01:02:12 PM PDT 24
Finished Mar 10 01:02:25 PM PDT 24
Peak memory 210744 kb
Host smart-df668425-12c2-4e9d-ad64-b3fb263b2c87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355973658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1355973658
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1252969283
Short name T378
Test name
Test status
Simulation time 347166541 ps
CPU time 4.17 seconds
Started Mar 10 01:02:11 PM PDT 24
Finished Mar 10 01:02:15 PM PDT 24
Peak memory 210660 kb
Host smart-f71cb879-928f-4bd7-bade-60e397ae561a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252969283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1252969283
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3169116076
Short name T96
Test name
Test status
Simulation time 37484525222 ps
CPU time 47.24 seconds
Started Mar 10 01:02:10 PM PDT 24
Finished Mar 10 01:02:57 PM PDT 24
Peak memory 210864 kb
Host smart-f76bb741-3247-4d8b-9632-68da6369564f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169116076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3169116076
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1871684721
Short name T400
Test name
Test status
Simulation time 359718252 ps
CPU time 5.4 seconds
Started Mar 10 01:02:16 PM PDT 24
Finished Mar 10 01:02:22 PM PDT 24
Peak memory 210764 kb
Host smart-a40299a9-72ac-4a56-a8c3-52c978e7ffc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871684721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1871684721
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3869867966
Short name T413
Test name
Test status
Simulation time 122459719 ps
CPU time 8.89 seconds
Started Mar 10 01:02:12 PM PDT 24
Finished Mar 10 01:02:21 PM PDT 24
Peak memory 214900 kb
Host smart-6b971e3c-b97d-4976-8a64-3535fdd6f0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869867966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3869867966
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.259744172
Short name T104
Test name
Test status
Simulation time 680035162 ps
CPU time 39.65 seconds
Started Mar 10 01:02:13 PM PDT 24
Finished Mar 10 01:02:53 PM PDT 24
Peak memory 212180 kb
Host smart-afb5aaa3-a1c5-43d1-8ec2-5301bf194f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259744172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.259744172
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3890938370
Short name T448
Test name
Test status
Simulation time 1634103176 ps
CPU time 13.2 seconds
Started Mar 10 01:02:15 PM PDT 24
Finished Mar 10 01:02:28 PM PDT 24
Peak memory 213400 kb
Host smart-c9d9c901-9def-45f9-b477-0e70d0521ca3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890938370 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3890938370
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3196368926
Short name T458
Test name
Test status
Simulation time 1823898629 ps
CPU time 13.8 seconds
Started Mar 10 01:02:16 PM PDT 24
Finished Mar 10 01:02:30 PM PDT 24
Peak memory 210624 kb
Host smart-cdf75f47-73f9-4afd-82b9-d8266b50a957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196368926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3196368926
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3671681230
Short name T76
Test name
Test status
Simulation time 1119782789 ps
CPU time 33.53 seconds
Started Mar 10 01:02:14 PM PDT 24
Finished Mar 10 01:02:48 PM PDT 24
Peak memory 210772 kb
Host smart-a9e1879b-af1a-486e-80cc-6f93313fe408
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671681230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3671681230
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3890614350
Short name T91
Test name
Test status
Simulation time 921799456 ps
CPU time 4.38 seconds
Started Mar 10 01:02:18 PM PDT 24
Finished Mar 10 01:02:23 PM PDT 24
Peak memory 210720 kb
Host smart-6fd1bd7c-33aa-472b-84f2-77ef6b28c8f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890614350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3890614350
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2917308232
Short name T388
Test name
Test status
Simulation time 776609389 ps
CPU time 7.61 seconds
Started Mar 10 01:02:19 PM PDT 24
Finished Mar 10 01:02:27 PM PDT 24
Peak memory 214992 kb
Host smart-73dce006-fa3d-4e61-adec-67cd95b7b21a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917308232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2917308232
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2014645368
Short name T417
Test name
Test status
Simulation time 202324284 ps
CPU time 69.24 seconds
Started Mar 10 01:02:15 PM PDT 24
Finished Mar 10 01:03:25 PM PDT 24
Peak memory 210824 kb
Host smart-63d4d426-bbd8-46b1-8b69-53dca536273c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014645368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2014645368
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2532759384
Short name T414
Test name
Test status
Simulation time 6381717455 ps
CPU time 13.86 seconds
Started Mar 10 01:02:24 PM PDT 24
Finished Mar 10 01:02:38 PM PDT 24
Peak memory 215072 kb
Host smart-0d66d529-a90b-45a2-8965-0411b4c64325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532759384 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2532759384
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2557321211
Short name T84
Test name
Test status
Simulation time 860949173 ps
CPU time 9.44 seconds
Started Mar 10 01:02:28 PM PDT 24
Finished Mar 10 01:02:38 PM PDT 24
Peak memory 210704 kb
Host smart-a6d2e460-efeb-4dc8-ac1f-e01b4a025f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557321211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2557321211
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3394585365
Short name T80
Test name
Test status
Simulation time 1065917964 ps
CPU time 33.75 seconds
Started Mar 10 01:02:19 PM PDT 24
Finished Mar 10 01:02:53 PM PDT 24
Peak memory 210824 kb
Host smart-65d8cb50-4169-4362-8e43-2af95fa27554
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394585365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3394585365
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1756117847
Short name T452
Test name
Test status
Simulation time 171122183 ps
CPU time 4.19 seconds
Started Mar 10 01:02:23 PM PDT 24
Finished Mar 10 01:02:27 PM PDT 24
Peak memory 210780 kb
Host smart-6b3da177-6dfb-4ea0-b044-7cff7f2ba287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756117847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1756117847
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.149822537
Short name T384
Test name
Test status
Simulation time 7091961204 ps
CPU time 11.16 seconds
Started Mar 10 01:02:19 PM PDT 24
Finished Mar 10 01:02:30 PM PDT 24
Peak memory 215408 kb
Host smart-f2ef28b7-54f7-4161-bf43-a624fadd8b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149822537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.149822537
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3961077356
Short name T49
Test name
Test status
Simulation time 1405155072 ps
CPU time 37.45 seconds
Started Mar 10 01:02:17 PM PDT 24
Finished Mar 10 01:02:55 PM PDT 24
Peak memory 210836 kb
Host smart-275a98ab-0325-4c11-bc09-5c6e21c5e86e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961077356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3961077356
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4121495245
Short name T377
Test name
Test status
Simulation time 1860932187 ps
CPU time 15.51 seconds
Started Mar 10 01:02:28 PM PDT 24
Finished Mar 10 01:02:44 PM PDT 24
Peak memory 218988 kb
Host smart-035060a1-d1b6-4079-9e06-f9c84c9bcc3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121495245 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4121495245
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3232484266
Short name T65
Test name
Test status
Simulation time 1844714517 ps
CPU time 14.82 seconds
Started Mar 10 01:02:22 PM PDT 24
Finished Mar 10 01:02:37 PM PDT 24
Peak memory 210700 kb
Host smart-2bb1a52e-f766-4ee9-92c5-0b42a77fec84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232484266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3232484266
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1044021833
Short name T77
Test name
Test status
Simulation time 6165049455 ps
CPU time 29.33 seconds
Started Mar 10 01:02:24 PM PDT 24
Finished Mar 10 01:02:53 PM PDT 24
Peak memory 211932 kb
Host smart-bbc50d58-971b-4f62-a24c-1f13a79d1f5d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044021833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1044021833
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.131971855
Short name T420
Test name
Test status
Simulation time 7328030161 ps
CPU time 8.75 seconds
Started Mar 10 01:02:24 PM PDT 24
Finished Mar 10 01:02:33 PM PDT 24
Peak memory 210908 kb
Host smart-a46c9510-aadf-41f1-8fef-1feab7d07769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131971855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.131971855
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2814994332
Short name T379
Test name
Test status
Simulation time 1973265444 ps
CPU time 13.25 seconds
Started Mar 10 01:02:24 PM PDT 24
Finished Mar 10 01:02:37 PM PDT 24
Peak memory 216140 kb
Host smart-bf9461cb-cd79-4ad2-88d0-48f9a6365fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814994332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2814994332
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2693119543
Short name T423
Test name
Test status
Simulation time 3597576934 ps
CPU time 43.66 seconds
Started Mar 10 01:02:22 PM PDT 24
Finished Mar 10 01:03:06 PM PDT 24
Peak memory 212056 kb
Host smart-7e633762-fe40-4bf8-8fe9-4e6ab94b2caf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693119543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2693119543
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1657017320
Short name T447
Test name
Test status
Simulation time 2750077839 ps
CPU time 8.47 seconds
Started Mar 10 01:02:22 PM PDT 24
Finished Mar 10 01:02:31 PM PDT 24
Peak memory 214476 kb
Host smart-6a554712-5d22-439d-88df-638a9bb01c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657017320 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1657017320
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3678628686
Short name T466
Test name
Test status
Simulation time 88250936 ps
CPU time 4.21 seconds
Started Mar 10 01:02:23 PM PDT 24
Finished Mar 10 01:02:28 PM PDT 24
Peak memory 210692 kb
Host smart-59ea4a70-9223-4fab-8b5e-e9e952bb6942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678628686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3678628686
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3639673295
Short name T86
Test name
Test status
Simulation time 25165697090 ps
CPU time 95.66 seconds
Started Mar 10 01:02:24 PM PDT 24
Finished Mar 10 01:03:59 PM PDT 24
Peak memory 210776 kb
Host smart-c5134384-217f-40a6-8ab2-930277ec3109
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639673295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3639673295
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2485802157
Short name T92
Test name
Test status
Simulation time 15672031272 ps
CPU time 10.88 seconds
Started Mar 10 01:02:23 PM PDT 24
Finished Mar 10 01:02:34 PM PDT 24
Peak memory 210908 kb
Host smart-0602e600-cc2b-467a-9472-b443ed227afb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485802157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2485802157
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3144595675
Short name T435
Test name
Test status
Simulation time 553140116 ps
CPU time 6.25 seconds
Started Mar 10 01:02:22 PM PDT 24
Finished Mar 10 01:02:29 PM PDT 24
Peak memory 214132 kb
Host smart-2b9c847a-ec1e-47da-adf1-923ce4c5bd94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144595675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3144595675
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3776498397
Short name T444
Test name
Test status
Simulation time 2196703954 ps
CPU time 42.78 seconds
Started Mar 10 01:02:24 PM PDT 24
Finished Mar 10 01:03:07 PM PDT 24
Peak memory 211092 kb
Host smart-a7e949d9-56fb-41ad-a29e-5d9b1d60545f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776498397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3776498397
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1812940150
Short name T415
Test name
Test status
Simulation time 5391473427 ps
CPU time 12.56 seconds
Started Mar 10 01:02:29 PM PDT 24
Finished Mar 10 01:02:42 PM PDT 24
Peak memory 214116 kb
Host smart-b21d0deb-21db-444a-a797-9ce8b587d644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812940150 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1812940150
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.278719700
Short name T405
Test name
Test status
Simulation time 913528050 ps
CPU time 9.89 seconds
Started Mar 10 01:02:22 PM PDT 24
Finished Mar 10 01:02:32 PM PDT 24
Peak memory 210688 kb
Host smart-3f7c3eb6-1e6f-492a-a8ff-f615a56ec6b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278719700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.278719700
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3226719305
Short name T87
Test name
Test status
Simulation time 11055391261 ps
CPU time 56.87 seconds
Started Mar 10 01:02:23 PM PDT 24
Finished Mar 10 01:03:20 PM PDT 24
Peak memory 210896 kb
Host smart-2e2d58bb-3218-4b8a-a1c6-0a84a3736325
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226719305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3226719305
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.897577372
Short name T429
Test name
Test status
Simulation time 88838920 ps
CPU time 4.24 seconds
Started Mar 10 01:02:29 PM PDT 24
Finished Mar 10 01:02:33 PM PDT 24
Peak memory 210756 kb
Host smart-0ed4c267-7ba4-44b8-929b-f47b40eeca95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897577372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.897577372
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.346999222
Short name T412
Test name
Test status
Simulation time 232566267 ps
CPU time 6.29 seconds
Started Mar 10 01:02:23 PM PDT 24
Finished Mar 10 01:02:30 PM PDT 24
Peak memory 214620 kb
Host smart-93a03e57-d68c-4bae-a997-d77854f4c0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346999222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.346999222
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1251272862
Short name T109
Test name
Test status
Simulation time 1587714114 ps
CPU time 39.56 seconds
Started Mar 10 01:02:23 PM PDT 24
Finished Mar 10 01:03:03 PM PDT 24
Peak memory 210772 kb
Host smart-b2b67dae-7163-4ae9-b3a7-cde320680b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251272862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1251272862
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3623688865
Short name T151
Test name
Test status
Simulation time 21196833213 ps
CPU time 16.97 seconds
Started Mar 10 01:23:21 PM PDT 24
Finished Mar 10 01:23:39 PM PDT 24
Peak memory 211016 kb
Host smart-2b3bc71c-7a2f-4990-8caa-74a2f31e0e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623688865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3623688865
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2881115757
Short name T285
Test name
Test status
Simulation time 53844150056 ps
CPU time 154.92 seconds
Started Mar 10 01:23:23 PM PDT 24
Finished Mar 10 01:25:58 PM PDT 24
Peak memory 236460 kb
Host smart-a602b9d4-d673-4737-9ffa-19b508fab3c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881115757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2881115757
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2869387150
Short name T195
Test name
Test status
Simulation time 1413611738 ps
CPU time 13.47 seconds
Started Mar 10 01:23:19 PM PDT 24
Finished Mar 10 01:23:33 PM PDT 24
Peak memory 210728 kb
Host smart-7ff78a91-13aa-408e-8269-8eab8c821237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869387150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2869387150
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2579206058
Short name T36
Test name
Test status
Simulation time 852153413 ps
CPU time 99.57 seconds
Started Mar 10 01:23:20 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 232280 kb
Host smart-bdbbc00d-86ef-430b-95ce-bd739b80bdeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579206058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2579206058
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1551369593
Short name T263
Test name
Test status
Simulation time 12160590890 ps
CPU time 26.61 seconds
Started Mar 10 01:23:19 PM PDT 24
Finished Mar 10 01:23:46 PM PDT 24
Peak memory 213768 kb
Host smart-d5961655-bbf5-4115-80fc-6baed1ef229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551369593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1551369593
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2905041980
Short name T16
Test name
Test status
Simulation time 947838308 ps
CPU time 11 seconds
Started Mar 10 01:23:19 PM PDT 24
Finished Mar 10 01:23:30 PM PDT 24
Peak memory 219068 kb
Host smart-2b6545f0-3ac7-4ebd-b1f0-59e4f38215ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905041980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2905041980
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1689981386
Short name T347
Test name
Test status
Simulation time 1137042353 ps
CPU time 10.99 seconds
Started Mar 10 01:23:17 PM PDT 24
Finished Mar 10 01:23:28 PM PDT 24
Peak memory 210952 kb
Host smart-6f4c5ecb-1c40-4c96-a03a-d93a4bb3de8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689981386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1689981386
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1683428215
Short name T180
Test name
Test status
Simulation time 50606688168 ps
CPU time 362.77 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:29:32 PM PDT 24
Peak memory 234504 kb
Host smart-a931166b-6052-41da-b1ed-e29317375b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683428215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1683428215
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.643890815
Short name T302
Test name
Test status
Simulation time 758320941 ps
CPU time 5.65 seconds
Started Mar 10 01:23:20 PM PDT 24
Finished Mar 10 01:23:26 PM PDT 24
Peak memory 210768 kb
Host smart-f504a43d-560d-467a-8b87-8ff3822c0ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643890815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.643890815
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1665500472
Short name T31
Test name
Test status
Simulation time 708335020 ps
CPU time 102.64 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:25:12 PM PDT 24
Peak memory 232092 kb
Host smart-98c15539-d373-468c-9526-cab9ab0b14c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665500472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1665500472
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2176070905
Short name T186
Test name
Test status
Simulation time 3078459291 ps
CPU time 26.66 seconds
Started Mar 10 01:23:18 PM PDT 24
Finished Mar 10 01:23:45 PM PDT 24
Peak memory 212656 kb
Host smart-2c46bbf5-a7cd-4a59-b5c6-fd8f2f10fd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176070905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2176070905
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1074995687
Short name T280
Test name
Test status
Simulation time 28134761524 ps
CPU time 62.43 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:24:32 PM PDT 24
Peak memory 215712 kb
Host smart-44bc4b5b-5c16-4048-b04f-8f3f0ba91841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074995687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1074995687
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.236282909
Short name T355
Test name
Test status
Simulation time 1848457821 ps
CPU time 15.14 seconds
Started Mar 10 01:23:37 PM PDT 24
Finished Mar 10 01:23:53 PM PDT 24
Peak memory 210792 kb
Host smart-c196da21-d817-4174-bf95-fac293065e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236282909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.236282909
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4168041505
Short name T257
Test name
Test status
Simulation time 10996554861 ps
CPU time 135.79 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:25:56 PM PDT 24
Peak memory 228176 kb
Host smart-f6356e15-27bb-4c3a-bb89-7427fcb7fb90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168041505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4168041505
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3761969497
Short name T224
Test name
Test status
Simulation time 2733683658 ps
CPU time 25.45 seconds
Started Mar 10 01:23:41 PM PDT 24
Finished Mar 10 01:24:07 PM PDT 24
Peak memory 211324 kb
Host smart-ee833c02-2567-420c-916e-d26ae008afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761969497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3761969497
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3605785305
Short name T345
Test name
Test status
Simulation time 409034666 ps
CPU time 5.81 seconds
Started Mar 10 01:23:38 PM PDT 24
Finished Mar 10 01:23:44 PM PDT 24
Peak memory 210824 kb
Host smart-90ac8e63-bac8-4fd8-a83d-65eff3828081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605785305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3605785305
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.543055929
Short name T268
Test name
Test status
Simulation time 191453951 ps
CPU time 10.72 seconds
Started Mar 10 01:23:38 PM PDT 24
Finished Mar 10 01:23:49 PM PDT 24
Peak memory 213300 kb
Host smart-e15b8dab-5021-40fe-ad4c-422b130c4fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543055929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.543055929
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1825020272
Short name T275
Test name
Test status
Simulation time 4053940201 ps
CPU time 49.75 seconds
Started Mar 10 01:23:43 PM PDT 24
Finished Mar 10 01:24:33 PM PDT 24
Peak memory 219152 kb
Host smart-de4f6dbb-8753-4241-8253-aedfc09a4114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825020272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1825020272
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.992412382
Short name T150
Test name
Test status
Simulation time 332627424 ps
CPU time 4.26 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:23:44 PM PDT 24
Peak memory 210856 kb
Host smart-bdfcb3b9-221d-4782-8731-240c70e5b88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992412382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.992412382
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1325860768
Short name T326
Test name
Test status
Simulation time 1070396290 ps
CPU time 14.81 seconds
Started Mar 10 01:23:33 PM PDT 24
Finished Mar 10 01:23:48 PM PDT 24
Peak memory 210816 kb
Host smart-0c85b82e-bc15-4a81-b4d6-eca82c89646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325860768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1325860768
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2264300473
Short name T167
Test name
Test status
Simulation time 2223948533 ps
CPU time 17.88 seconds
Started Mar 10 01:23:37 PM PDT 24
Finished Mar 10 01:23:55 PM PDT 24
Peak memory 210820 kb
Host smart-097a0a7b-4499-4f28-a216-8533dcb691c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264300473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2264300473
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3428908832
Short name T168
Test name
Test status
Simulation time 4337403438 ps
CPU time 23.61 seconds
Started Mar 10 01:23:39 PM PDT 24
Finished Mar 10 01:24:03 PM PDT 24
Peak memory 213332 kb
Host smart-0424c4b2-e240-4ab5-b7f5-469d26e6fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428908832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3428908832
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1673710529
Short name T159
Test name
Test status
Simulation time 422956148 ps
CPU time 21.01 seconds
Started Mar 10 01:23:35 PM PDT 24
Finished Mar 10 01:23:56 PM PDT 24
Peak memory 213372 kb
Host smart-9243b06b-9905-4e42-8f8b-96c6f54c2922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673710529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1673710529
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1393083877
Short name T42
Test name
Test status
Simulation time 57440398843 ps
CPU time 2198.71 seconds
Started Mar 10 01:23:42 PM PDT 24
Finished Mar 10 02:00:21 PM PDT 24
Peak memory 243680 kb
Host smart-a6fff380-6ebb-4187-a25a-025f06969e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393083877 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1393083877
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.678689488
Short name T319
Test name
Test status
Simulation time 1889689714 ps
CPU time 16.07 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:23:56 PM PDT 24
Peak memory 210900 kb
Host smart-f8d9f694-11e7-469e-98d6-2b26cf54baa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678689488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.678689488
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.340463825
Short name T193
Test name
Test status
Simulation time 22490053300 ps
CPU time 199.4 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:27:00 PM PDT 24
Peak memory 236476 kb
Host smart-34fc35fa-6474-44b3-bcef-c937982dcf5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340463825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.340463825
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1525705143
Short name T123
Test name
Test status
Simulation time 175183596 ps
CPU time 9.46 seconds
Started Mar 10 01:23:33 PM PDT 24
Finished Mar 10 01:23:42 PM PDT 24
Peak memory 211300 kb
Host smart-3660b542-789d-490c-bce8-6bbdbdd9d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525705143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1525705143
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.690601515
Short name T164
Test name
Test status
Simulation time 97444806 ps
CPU time 5.57 seconds
Started Mar 10 01:23:33 PM PDT 24
Finished Mar 10 01:23:39 PM PDT 24
Peak memory 210808 kb
Host smart-feaa86cd-9e68-4228-86b8-09bcf86d0272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690601515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.690601515
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3005699901
Short name T198
Test name
Test status
Simulation time 12362601071 ps
CPU time 25.86 seconds
Started Mar 10 01:23:39 PM PDT 24
Finished Mar 10 01:24:05 PM PDT 24
Peak memory 219084 kb
Host smart-7f88194a-edd2-4ae4-b6fa-ab89e34dbee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005699901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3005699901
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.463831257
Short name T176
Test name
Test status
Simulation time 1723469704 ps
CPU time 21.02 seconds
Started Mar 10 01:23:35 PM PDT 24
Finished Mar 10 01:23:56 PM PDT 24
Peak memory 210696 kb
Host smart-df7bbd54-3aab-439b-bf02-63e2ac878fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463831257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.463831257
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3120570958
Short name T152
Test name
Test status
Simulation time 15336762935 ps
CPU time 174.11 seconds
Started Mar 10 01:23:43 PM PDT 24
Finished Mar 10 01:26:37 PM PDT 24
Peak memory 233804 kb
Host smart-541342a2-4ade-44be-88f3-7e2fad93ebf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120570958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3120570958
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.482422012
Short name T328
Test name
Test status
Simulation time 1656490727 ps
CPU time 12.37 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:23:52 PM PDT 24
Peak memory 211436 kb
Host smart-fd36de66-ef96-495b-8ff7-d2c9b494984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482422012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.482422012
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2986104529
Short name T181
Test name
Test status
Simulation time 3850348889 ps
CPU time 16.23 seconds
Started Mar 10 01:23:41 PM PDT 24
Finished Mar 10 01:23:57 PM PDT 24
Peak memory 210764 kb
Host smart-1cc1b482-20e8-469c-8b41-fc6653a181f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986104529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2986104529
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2831520744
Short name T209
Test name
Test status
Simulation time 3894474877 ps
CPU time 39.24 seconds
Started Mar 10 01:23:38 PM PDT 24
Finished Mar 10 01:24:17 PM PDT 24
Peak memory 212768 kb
Host smart-9d8d5fee-ad9e-4b4e-9441-68ad8fa650c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831520744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2831520744
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1948058294
Short name T188
Test name
Test status
Simulation time 12985966631 ps
CPU time 84.03 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:25:05 PM PDT 24
Peak memory 216928 kb
Host smart-8e1318a0-8315-450d-9f18-81669e9419dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948058294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1948058294
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1413250697
Short name T46
Test name
Test status
Simulation time 18050786567 ps
CPU time 7479.92 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 03:28:21 PM PDT 24
Peak memory 227364 kb
Host smart-0ae50705-cab0-488b-addb-26454d0f9d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413250697 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1413250697
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2810645753
Short name T200
Test name
Test status
Simulation time 172070417 ps
CPU time 4.22 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:23:44 PM PDT 24
Peak memory 210916 kb
Host smart-59ba1468-49b2-4b71-ae59-d1935d90c704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810645753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2810645753
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3107860950
Short name T191
Test name
Test status
Simulation time 1994107291 ps
CPU time 121.19 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 239460 kb
Host smart-353d77cd-8d3c-4476-8322-08b719da9e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107860950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3107860950
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1178825591
Short name T221
Test name
Test status
Simulation time 12178488248 ps
CPU time 28.27 seconds
Started Mar 10 01:23:42 PM PDT 24
Finished Mar 10 01:24:10 PM PDT 24
Peak memory 211884 kb
Host smart-f88bc7a0-6622-44d2-a80c-53e4516d29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178825591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1178825591
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1478217121
Short name T5
Test name
Test status
Simulation time 4970811596 ps
CPU time 13.25 seconds
Started Mar 10 01:23:41 PM PDT 24
Finished Mar 10 01:23:54 PM PDT 24
Peak memory 210872 kb
Host smart-f7c3283f-7279-47bb-80e5-cc1c07f8433b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478217121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1478217121
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4194882937
Short name T244
Test name
Test status
Simulation time 352569162 ps
CPU time 10.17 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:23:50 PM PDT 24
Peak memory 212688 kb
Host smart-f38b8bb4-efd4-4d49-8283-d17030e354cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194882937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4194882937
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1667650896
Short name T170
Test name
Test status
Simulation time 242360021 ps
CPU time 8.74 seconds
Started Mar 10 01:23:40 PM PDT 24
Finished Mar 10 01:23:49 PM PDT 24
Peak memory 210880 kb
Host smart-f49cd1aa-9063-4405-8a9c-35b17d3bbda7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667650896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1667650896
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1248008012
Short name T99
Test name
Test status
Simulation time 80287944208 ps
CPU time 815.08 seconds
Started Mar 10 01:23:46 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 230004 kb
Host smart-d7b681f8-001b-425e-ae9c-3f74c331a63f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248008012 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1248008012
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4272831893
Short name T214
Test name
Test status
Simulation time 7353845230 ps
CPU time 15.06 seconds
Started Mar 10 01:23:42 PM PDT 24
Finished Mar 10 01:23:57 PM PDT 24
Peak memory 210996 kb
Host smart-f03fced6-6d66-4004-b28e-246ade0e8316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272831893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4272831893
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.509808464
Short name T332
Test name
Test status
Simulation time 7641204468 ps
CPU time 145.97 seconds
Started Mar 10 01:23:47 PM PDT 24
Finished Mar 10 01:26:13 PM PDT 24
Peak memory 237136 kb
Host smart-61e38bdf-c019-48f4-b8e9-f201f9e3ed83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509808464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.509808464
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3575031915
Short name T316
Test name
Test status
Simulation time 4251723115 ps
CPU time 32.82 seconds
Started Mar 10 01:23:37 PM PDT 24
Finished Mar 10 01:24:10 PM PDT 24
Peak memory 211588 kb
Host smart-208440bf-e831-4a53-8361-e1efe1f56505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575031915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3575031915
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1295595410
Short name T321
Test name
Test status
Simulation time 2089662014 ps
CPU time 8.66 seconds
Started Mar 10 01:23:38 PM PDT 24
Finished Mar 10 01:23:47 PM PDT 24
Peak memory 210712 kb
Host smart-c7fa48c1-03c4-4944-b0fc-408c8b463af6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295595410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1295595410
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3331139549
Short name T23
Test name
Test status
Simulation time 41121048946 ps
CPU time 29.06 seconds
Started Mar 10 01:23:43 PM PDT 24
Finished Mar 10 01:24:12 PM PDT 24
Peak memory 213680 kb
Host smart-a07c91fc-4e63-4c6b-8e0d-4849b88478cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331139549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3331139549
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4282118587
Short name T327
Test name
Test status
Simulation time 128772112 ps
CPU time 7.62 seconds
Started Mar 10 01:23:41 PM PDT 24
Finished Mar 10 01:23:48 PM PDT 24
Peak memory 210900 kb
Host smart-11c4184c-8157-4228-862b-7083a1273a0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282118587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4282118587
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2014086474
Short name T281
Test name
Test status
Simulation time 1148179675 ps
CPU time 11.38 seconds
Started Mar 10 01:23:47 PM PDT 24
Finished Mar 10 01:23:58 PM PDT 24
Peak memory 210868 kb
Host smart-12fcf769-1ae0-4b18-89e3-cead650e7140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014086474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2014086474
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.212782327
Short name T185
Test name
Test status
Simulation time 27699614576 ps
CPU time 111.68 seconds
Started Mar 10 01:23:50 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 236476 kb
Host smart-89f3087d-d60f-4a2c-873a-4333bcbd3563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212782327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.212782327
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.569945529
Short name T22
Test name
Test status
Simulation time 175682858 ps
CPU time 9.69 seconds
Started Mar 10 01:23:46 PM PDT 24
Finished Mar 10 01:23:56 PM PDT 24
Peak memory 211756 kb
Host smart-6efeb9a8-4935-49a4-ab78-437489626765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569945529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.569945529
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2873164876
Short name T325
Test name
Test status
Simulation time 1716927877 ps
CPU time 15.29 seconds
Started Mar 10 01:23:44 PM PDT 24
Finished Mar 10 01:24:00 PM PDT 24
Peak memory 210716 kb
Host smart-7c987fa2-1b03-4535-b657-ced8d9f0f019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873164876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2873164876
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2834054850
Short name T259
Test name
Test status
Simulation time 2872175262 ps
CPU time 27.75 seconds
Started Mar 10 01:23:48 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 213296 kb
Host smart-8d8a87dd-84fa-4ede-a15e-6881456bd717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834054850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2834054850
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.14485341
Short name T115
Test name
Test status
Simulation time 45523794331 ps
CPU time 69.23 seconds
Started Mar 10 01:23:50 PM PDT 24
Finished Mar 10 01:24:59 PM PDT 24
Peak memory 216816 kb
Host smart-76ffa2f2-11ef-47ed-aabd-b98061b481d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14485341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.rom_ctrl_stress_all.14485341
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3497390662
Short name T242
Test name
Test status
Simulation time 3891831634 ps
CPU time 15.81 seconds
Started Mar 10 01:23:48 PM PDT 24
Finished Mar 10 01:24:04 PM PDT 24
Peak memory 211004 kb
Host smart-c8067c79-d6ba-4b8f-ab47-69b0505e841a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497390662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3497390662
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4232780016
Short name T335
Test name
Test status
Simulation time 4513700262 ps
CPU time 75.77 seconds
Started Mar 10 01:23:50 PM PDT 24
Finished Mar 10 01:25:06 PM PDT 24
Peak memory 237476 kb
Host smart-732b1b6b-ecc6-4646-8f1a-ce4bb9b4e8b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232780016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4232780016
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2029034864
Short name T218
Test name
Test status
Simulation time 12883988756 ps
CPU time 28.26 seconds
Started Mar 10 01:23:47 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 211736 kb
Host smart-8c678efb-7e58-492b-96a5-bffb129b5171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029034864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2029034864
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.956272086
Short name T306
Test name
Test status
Simulation time 5010326614 ps
CPU time 12.27 seconds
Started Mar 10 01:23:45 PM PDT 24
Finished Mar 10 01:23:58 PM PDT 24
Peak memory 210860 kb
Host smart-0512ad6f-2d5b-405e-90ef-5285f3569b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956272086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.956272086
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1627382799
Short name T118
Test name
Test status
Simulation time 3486918712 ps
CPU time 20.65 seconds
Started Mar 10 01:23:47 PM PDT 24
Finished Mar 10 01:24:08 PM PDT 24
Peak memory 212368 kb
Host smart-7717ec92-ce84-413a-83ba-2ef2d8744964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627382799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1627382799
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3818696273
Short name T236
Test name
Test status
Simulation time 10366688348 ps
CPU time 32.48 seconds
Started Mar 10 01:23:46 PM PDT 24
Finished Mar 10 01:24:19 PM PDT 24
Peak memory 215456 kb
Host smart-e05a394e-082c-48ef-891b-f72b105af328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818696273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3818696273
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.697705753
Short name T35
Test name
Test status
Simulation time 182780211 ps
CPU time 4.2 seconds
Started Mar 10 01:23:49 PM PDT 24
Finished Mar 10 01:23:53 PM PDT 24
Peak memory 210952 kb
Host smart-a71133f1-b235-4969-876f-040341d4e592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697705753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.697705753
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3303430511
Short name T137
Test name
Test status
Simulation time 32767924940 ps
CPU time 275.95 seconds
Started Mar 10 01:23:45 PM PDT 24
Finished Mar 10 01:28:22 PM PDT 24
Peak memory 236480 kb
Host smart-287f49a9-a944-4de2-b053-fa1b308c6398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303430511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3303430511
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.647750818
Short name T56
Test name
Test status
Simulation time 660406404 ps
CPU time 11.64 seconds
Started Mar 10 01:23:46 PM PDT 24
Finished Mar 10 01:23:58 PM PDT 24
Peak memory 211468 kb
Host smart-03a8bece-2ce9-40a8-8329-df722bafdfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647750818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.647750818
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.842516348
Short name T217
Test name
Test status
Simulation time 1532581352 ps
CPU time 9.58 seconds
Started Mar 10 01:23:48 PM PDT 24
Finished Mar 10 01:23:58 PM PDT 24
Peak memory 210776 kb
Host smart-209c35c7-29e1-41b7-9cb1-cd4dc80a5516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842516348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.842516348
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.240045241
Short name T194
Test name
Test status
Simulation time 1550665043 ps
CPU time 13.48 seconds
Started Mar 10 01:23:51 PM PDT 24
Finished Mar 10 01:24:04 PM PDT 24
Peak memory 219068 kb
Host smart-8af9d7ca-38e4-44be-bc65-baf6d860d745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240045241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.240045241
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.614257391
Short name T153
Test name
Test status
Simulation time 1184313781 ps
CPU time 11.35 seconds
Started Mar 10 01:23:51 PM PDT 24
Finished Mar 10 01:24:02 PM PDT 24
Peak memory 210848 kb
Host smart-ebf1a463-e755-46df-a319-d63d4492e214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614257391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.614257391
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1370749840
Short name T163
Test name
Test status
Simulation time 2026469519 ps
CPU time 15.7 seconds
Started Mar 10 01:23:48 PM PDT 24
Finished Mar 10 01:24:03 PM PDT 24
Peak memory 211144 kb
Host smart-a428fdab-1bf8-4d2d-9b34-d89438b11804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370749840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1370749840
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3568715565
Short name T288
Test name
Test status
Simulation time 1416759752 ps
CPU time 8.26 seconds
Started Mar 10 01:23:47 PM PDT 24
Finished Mar 10 01:23:56 PM PDT 24
Peak memory 210824 kb
Host smart-398420e7-aaf2-4529-9649-0040688ab7ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568715565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3568715565
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.115350439
Short name T274
Test name
Test status
Simulation time 2968269515 ps
CPU time 26.47 seconds
Started Mar 10 01:23:52 PM PDT 24
Finished Mar 10 01:24:18 PM PDT 24
Peak memory 213204 kb
Host smart-d4616bce-0b49-42cb-86f2-e6fc84292736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115350439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.115350439
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1806910929
Short name T231
Test name
Test status
Simulation time 9391981238 ps
CPU time 102.39 seconds
Started Mar 10 01:23:49 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 215744 kb
Host smart-b0bd9f39-bf31-4fb9-a448-f65ea13c3bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806910929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1806910929
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.71563457
Short name T230
Test name
Test status
Simulation time 810052183 ps
CPU time 9.03 seconds
Started Mar 10 01:23:22 PM PDT 24
Finished Mar 10 01:23:31 PM PDT 24
Peak memory 210904 kb
Host smart-9bac56cc-2874-4adb-aacd-f7cb431be339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71563457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.71563457
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.76203855
Short name T310
Test name
Test status
Simulation time 16941452472 ps
CPU time 179.47 seconds
Started Mar 10 01:23:22 PM PDT 24
Finished Mar 10 01:26:22 PM PDT 24
Peak memory 237316 kb
Host smart-14efc6d5-dd63-4ef9-9860-ea3913fe24f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76203855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_cor
rupt_sig_fatal_chk.76203855
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1765960553
Short name T146
Test name
Test status
Simulation time 3176585864 ps
CPU time 15.17 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:42 PM PDT 24
Peak memory 211548 kb
Host smart-a473a0c3-55de-4640-9442-e51ca11d9aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765960553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1765960553
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1150465524
Short name T369
Test name
Test status
Simulation time 6478808827 ps
CPU time 14.02 seconds
Started Mar 10 01:23:19 PM PDT 24
Finished Mar 10 01:23:33 PM PDT 24
Peak memory 210884 kb
Host smart-54897b7f-0675-4db3-8485-929ffbf5269d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150465524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1150465524
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4077903317
Short name T37
Test name
Test status
Simulation time 887725681 ps
CPU time 57.58 seconds
Started Mar 10 01:23:21 PM PDT 24
Finished Mar 10 01:24:19 PM PDT 24
Peak memory 230628 kb
Host smart-fa811fdc-7494-4ffb-8353-01d80809985c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077903317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4077903317
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2337688883
Short name T69
Test name
Test status
Simulation time 14681902516 ps
CPU time 35.74 seconds
Started Mar 10 01:23:21 PM PDT 24
Finished Mar 10 01:23:57 PM PDT 24
Peak memory 213300 kb
Host smart-5b11672b-622c-44af-bba2-72272eff2b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337688883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2337688883
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2870651970
Short name T313
Test name
Test status
Simulation time 12793498997 ps
CPU time 35.95 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:24:05 PM PDT 24
Peak memory 213628 kb
Host smart-361d20e5-ee5f-4092-82cd-62a263d6c295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870651970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2870651970
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4123934837
Short name T43
Test name
Test status
Simulation time 85358360109 ps
CPU time 1785.74 seconds
Started Mar 10 01:23:24 PM PDT 24
Finished Mar 10 01:53:10 PM PDT 24
Peak memory 244764 kb
Host smart-e7c35752-abab-4c0a-8604-4061966072d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123934837 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.4123934837
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2217664005
Short name T256
Test name
Test status
Simulation time 130685492 ps
CPU time 5.29 seconds
Started Mar 10 01:23:52 PM PDT 24
Finished Mar 10 01:23:57 PM PDT 24
Peak memory 210972 kb
Host smart-4fdc630c-5baa-4db1-805a-5b1ef94aaf7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217664005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2217664005
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1559996588
Short name T38
Test name
Test status
Simulation time 111488688122 ps
CPU time 290.19 seconds
Started Mar 10 01:23:49 PM PDT 24
Finished Mar 10 01:28:40 PM PDT 24
Peak memory 238472 kb
Host smart-8189eb96-8c6d-44f0-b67a-7adf6bce1e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559996588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1559996588
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.849128429
Short name T25
Test name
Test status
Simulation time 1103809054 ps
CPU time 16.42 seconds
Started Mar 10 01:23:53 PM PDT 24
Finished Mar 10 01:24:09 PM PDT 24
Peak memory 211412 kb
Host smart-5ec80194-cab6-43fa-b5c7-fa821a8f47a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849128429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.849128429
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2168915453
Short name T203
Test name
Test status
Simulation time 564140846 ps
CPU time 5.64 seconds
Started Mar 10 01:23:49 PM PDT 24
Finished Mar 10 01:23:55 PM PDT 24
Peak memory 210816 kb
Host smart-0fb0bb88-6e62-4479-bbcf-2abd1fa4627b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168915453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2168915453
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3633879938
Short name T17
Test name
Test status
Simulation time 8621038293 ps
CPU time 25.12 seconds
Started Mar 10 01:23:53 PM PDT 24
Finished Mar 10 01:24:19 PM PDT 24
Peak memory 213624 kb
Host smart-efe447cd-dfda-4831-bd55-142a245e1cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633879938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3633879938
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2902662661
Short name T210
Test name
Test status
Simulation time 10811075550 ps
CPU time 30.56 seconds
Started Mar 10 01:23:47 PM PDT 24
Finished Mar 10 01:24:17 PM PDT 24
Peak memory 214856 kb
Host smart-b7414f3b-6f7a-4b7b-9042-0c989508d3c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902662661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2902662661
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1116944536
Short name T239
Test name
Test status
Simulation time 14464802788 ps
CPU time 11.07 seconds
Started Mar 10 01:23:48 PM PDT 24
Finished Mar 10 01:24:00 PM PDT 24
Peak memory 210928 kb
Host smart-8e88dc35-d7f2-4ac9-bb5b-4b0a146378c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116944536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1116944536
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3837441777
Short name T359
Test name
Test status
Simulation time 54241996210 ps
CPU time 178.89 seconds
Started Mar 10 01:23:50 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 225788 kb
Host smart-c1c7a30c-1057-4866-b47d-2146d5d76c72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837441777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3837441777
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.864916745
Short name T363
Test name
Test status
Simulation time 667757276 ps
CPU time 9.38 seconds
Started Mar 10 01:23:55 PM PDT 24
Finished Mar 10 01:24:04 PM PDT 24
Peak memory 211368 kb
Host smart-1f3bd806-9913-4e89-b8c6-0004732767a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864916745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.864916745
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.85272045
Short name T124
Test name
Test status
Simulation time 4303351077 ps
CPU time 12.03 seconds
Started Mar 10 01:23:52 PM PDT 24
Finished Mar 10 01:24:04 PM PDT 24
Peak memory 210904 kb
Host smart-f0b2834e-40a6-436c-a019-97b9816ee7bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85272045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.85272045
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.222020878
Short name T72
Test name
Test status
Simulation time 1761537352 ps
CPU time 13.86 seconds
Started Mar 10 01:23:49 PM PDT 24
Finished Mar 10 01:24:03 PM PDT 24
Peak memory 210800 kb
Host smart-a9ed60bf-4aca-4505-85dc-fd320fa48218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222020878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.222020878
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2037115431
Short name T158
Test name
Test status
Simulation time 39506558862 ps
CPU time 99.22 seconds
Started Mar 10 01:23:50 PM PDT 24
Finished Mar 10 01:25:30 PM PDT 24
Peak memory 218988 kb
Host smart-9857689e-987c-4a8a-8535-deac555f7f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037115431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2037115431
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1760354152
Short name T322
Test name
Test status
Simulation time 14426967212 ps
CPU time 13.05 seconds
Started Mar 10 01:23:54 PM PDT 24
Finished Mar 10 01:24:07 PM PDT 24
Peak memory 211004 kb
Host smart-fd46612f-6fb7-4950-bc14-cd6592485955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760354152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1760354152
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2236275375
Short name T24
Test name
Test status
Simulation time 27604060160 ps
CPU time 347.83 seconds
Started Mar 10 01:23:58 PM PDT 24
Finished Mar 10 01:29:46 PM PDT 24
Peak memory 233468 kb
Host smart-00434345-356e-4f8d-8a85-3fa3980a572f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236275375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2236275375
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1224967771
Short name T330
Test name
Test status
Simulation time 32906999494 ps
CPU time 23.77 seconds
Started Mar 10 01:23:58 PM PDT 24
Finished Mar 10 01:24:22 PM PDT 24
Peak memory 211732 kb
Host smart-1a4b4bb6-a493-426c-baf6-e153eb9f2b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224967771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1224967771
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2184662652
Short name T18
Test name
Test status
Simulation time 5563978931 ps
CPU time 14.44 seconds
Started Mar 10 01:23:51 PM PDT 24
Finished Mar 10 01:24:06 PM PDT 24
Peak memory 210800 kb
Host smart-ab724ea3-0991-412b-84f3-c20006397557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184662652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2184662652
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.923266931
Short name T149
Test name
Test status
Simulation time 8335233480 ps
CPU time 27.22 seconds
Started Mar 10 01:23:51 PM PDT 24
Finished Mar 10 01:24:18 PM PDT 24
Peak memory 212968 kb
Host smart-ac8dfa13-7969-4927-b53a-ae837cc96e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923266931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.923266931
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.578333642
Short name T305
Test name
Test status
Simulation time 1936779926 ps
CPU time 27.47 seconds
Started Mar 10 01:23:48 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 212756 kb
Host smart-362b9110-a0f8-4966-a82c-51fec60f4cf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578333642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.578333642
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2566412999
Short name T141
Test name
Test status
Simulation time 3278680707 ps
CPU time 14.12 seconds
Started Mar 10 01:23:54 PM PDT 24
Finished Mar 10 01:24:08 PM PDT 24
Peak memory 210972 kb
Host smart-04ff00a8-6f33-4e61-816f-c5cae3a29b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566412999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2566412999
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.761805187
Short name T219
Test name
Test status
Simulation time 35802054789 ps
CPU time 345.23 seconds
Started Mar 10 01:23:57 PM PDT 24
Finished Mar 10 01:29:42 PM PDT 24
Peak memory 236744 kb
Host smart-8d5d0bcd-7424-4143-9226-6e6b44b81c88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761805187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.761805187
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.290778139
Short name T122
Test name
Test status
Simulation time 3294510336 ps
CPU time 15.44 seconds
Started Mar 10 01:23:57 PM PDT 24
Finished Mar 10 01:24:12 PM PDT 24
Peak memory 211492 kb
Host smart-775b9198-1cc2-4c22-a758-2fcb70e70f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290778139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.290778139
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3940689859
Short name T365
Test name
Test status
Simulation time 522900400 ps
CPU time 7.22 seconds
Started Mar 10 01:23:54 PM PDT 24
Finished Mar 10 01:24:02 PM PDT 24
Peak memory 210720 kb
Host smart-c17d5bba-f687-40a8-8d0e-309d062667d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940689859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3940689859
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3576115106
Short name T240
Test name
Test status
Simulation time 2968914380 ps
CPU time 19.4 seconds
Started Mar 10 01:23:54 PM PDT 24
Finished Mar 10 01:24:13 PM PDT 24
Peak memory 212740 kb
Host smart-9cf629ec-78eb-45e1-845d-fbd9a8de0869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576115106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3576115106
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3793591314
Short name T216
Test name
Test status
Simulation time 7032789403 ps
CPU time 33.73 seconds
Started Mar 10 01:23:55 PM PDT 24
Finished Mar 10 01:24:29 PM PDT 24
Peak memory 215380 kb
Host smart-158b0118-d3b8-4d20-9730-e09b1395665c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793591314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3793591314
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.683541840
Short name T323
Test name
Test status
Simulation time 7573804613 ps
CPU time 15.07 seconds
Started Mar 10 01:24:02 PM PDT 24
Finished Mar 10 01:24:17 PM PDT 24
Peak memory 210928 kb
Host smart-e3033363-0a2e-4ee4-8ad4-c85e22d8d946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683541840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.683541840
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.860621099
Short name T300
Test name
Test status
Simulation time 29089772825 ps
CPU time 168.64 seconds
Started Mar 10 01:23:57 PM PDT 24
Finished Mar 10 01:26:46 PM PDT 24
Peak memory 232684 kb
Host smart-0ba39a44-65e5-4521-b56d-ce7abacd73d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860621099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.860621099
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.420361116
Short name T362
Test name
Test status
Simulation time 39615532986 ps
CPU time 23.98 seconds
Started Mar 10 01:23:59 PM PDT 24
Finished Mar 10 01:24:23 PM PDT 24
Peak memory 211744 kb
Host smart-6c05441e-b129-480b-a1cc-e410ebebfd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420361116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.420361116
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1645112148
Short name T284
Test name
Test status
Simulation time 98646138 ps
CPU time 5.45 seconds
Started Mar 10 01:23:55 PM PDT 24
Finished Mar 10 01:24:01 PM PDT 24
Peak memory 210812 kb
Host smart-e0bbb2da-294c-4a2c-a351-12159b181775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645112148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1645112148
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3167330744
Short name T368
Test name
Test status
Simulation time 5194467207 ps
CPU time 23.13 seconds
Started Mar 10 01:23:54 PM PDT 24
Finished Mar 10 01:24:17 PM PDT 24
Peak memory 212988 kb
Host smart-33782398-5255-4826-a9e2-d1bf78a0ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167330744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3167330744
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2213124941
Short name T255
Test name
Test status
Simulation time 2467009255 ps
CPU time 12.87 seconds
Started Mar 10 01:23:55 PM PDT 24
Finished Mar 10 01:24:08 PM PDT 24
Peak memory 210952 kb
Host smart-501f91fe-7d15-4f76-8e32-e762fbe70cea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213124941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2213124941
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1700346554
Short name T297
Test name
Test status
Simulation time 1583824433 ps
CPU time 13.49 seconds
Started Mar 10 01:24:01 PM PDT 24
Finished Mar 10 01:24:14 PM PDT 24
Peak memory 210840 kb
Host smart-91b0c7e3-da73-4a4e-88fc-a353830ee228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700346554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1700346554
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.933197136
Short name T353
Test name
Test status
Simulation time 37519350171 ps
CPU time 207.51 seconds
Started Mar 10 01:24:02 PM PDT 24
Finished Mar 10 01:27:31 PM PDT 24
Peak memory 240460 kb
Host smart-9adebc9a-dd14-422b-a8a8-64778327196d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933197136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.933197136
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2346955898
Short name T248
Test name
Test status
Simulation time 2850493041 ps
CPU time 26.78 seconds
Started Mar 10 01:24:04 PM PDT 24
Finished Mar 10 01:24:31 PM PDT 24
Peak memory 211412 kb
Host smart-81924fe0-1ead-4bba-9eb3-242b5681b2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346955898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2346955898
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.103407581
Short name T139
Test name
Test status
Simulation time 170897427 ps
CPU time 5.67 seconds
Started Mar 10 01:24:02 PM PDT 24
Finished Mar 10 01:24:08 PM PDT 24
Peak memory 210716 kb
Host smart-031ea0c0-cfe7-4c09-ba68-919583a8cde3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103407581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.103407581
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.211120072
Short name T205
Test name
Test status
Simulation time 3002387799 ps
CPU time 22.82 seconds
Started Mar 10 01:24:02 PM PDT 24
Finished Mar 10 01:24:25 PM PDT 24
Peak memory 213576 kb
Host smart-cbcf5918-4e12-45cf-9c0b-b873669d2622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211120072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.211120072
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2632040542
Short name T129
Test name
Test status
Simulation time 8335442733 ps
CPU time 20.12 seconds
Started Mar 10 01:24:03 PM PDT 24
Finished Mar 10 01:24:24 PM PDT 24
Peak memory 210812 kb
Host smart-fda79239-4203-4d3e-82c2-ab883288c65c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632040542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2632040542
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3139988285
Short name T187
Test name
Test status
Simulation time 3764969415 ps
CPU time 10.73 seconds
Started Mar 10 01:24:02 PM PDT 24
Finished Mar 10 01:24:14 PM PDT 24
Peak memory 210940 kb
Host smart-89c23c0f-3340-4bd7-872d-1c43d8131b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139988285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3139988285
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.970498724
Short name T266
Test name
Test status
Simulation time 29050393284 ps
CPU time 234.85 seconds
Started Mar 10 01:24:03 PM PDT 24
Finished Mar 10 01:27:59 PM PDT 24
Peak memory 240248 kb
Host smart-26f3697d-eb03-4ad4-8dff-71b01c54ecc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970498724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.970498724
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1414468215
Short name T157
Test name
Test status
Simulation time 10374249897 ps
CPU time 30.8 seconds
Started Mar 10 01:24:02 PM PDT 24
Finished Mar 10 01:24:33 PM PDT 24
Peak memory 211744 kb
Host smart-c26b850f-210b-4955-b4aa-8cfbff3574e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414468215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1414468215
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4013319737
Short name T324
Test name
Test status
Simulation time 11421354778 ps
CPU time 10.44 seconds
Started Mar 10 01:24:03 PM PDT 24
Finished Mar 10 01:24:14 PM PDT 24
Peak memory 210772 kb
Host smart-a78c0877-5879-463c-8391-6f58e8106af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013319737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4013319737
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2296519058
Short name T264
Test name
Test status
Simulation time 919738875 ps
CPU time 16.34 seconds
Started Mar 10 01:24:02 PM PDT 24
Finished Mar 10 01:24:19 PM PDT 24
Peak memory 213096 kb
Host smart-a227abce-f4a8-4641-aee0-decc88be6e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296519058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2296519058
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2076079245
Short name T197
Test name
Test status
Simulation time 47480725017 ps
CPU time 84.28 seconds
Started Mar 10 01:24:01 PM PDT 24
Finished Mar 10 01:25:26 PM PDT 24
Peak memory 217124 kb
Host smart-71ee3f54-9d1c-49f2-8236-58b9a2e5e89c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076079245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2076079245
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1222080997
Short name T143
Test name
Test status
Simulation time 2140722953 ps
CPU time 16.64 seconds
Started Mar 10 01:24:08 PM PDT 24
Finished Mar 10 01:24:25 PM PDT 24
Peak memory 210940 kb
Host smart-f372533e-846f-4636-9710-52db0834f9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222080997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1222080997
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2792534611
Short name T334
Test name
Test status
Simulation time 159201712785 ps
CPU time 260.13 seconds
Started Mar 10 01:24:06 PM PDT 24
Finished Mar 10 01:28:26 PM PDT 24
Peak memory 236812 kb
Host smart-894ae6cb-1aa7-4740-a326-8cf619585ed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792534611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2792534611
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3764015164
Short name T213
Test name
Test status
Simulation time 2759915108 ps
CPU time 14.15 seconds
Started Mar 10 01:24:04 PM PDT 24
Finished Mar 10 01:24:19 PM PDT 24
Peak memory 211528 kb
Host smart-f4796e0d-58ad-4d78-9468-599838b29209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764015164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3764015164
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.5162250
Short name T265
Test name
Test status
Simulation time 627449901 ps
CPU time 9.59 seconds
Started Mar 10 01:24:08 PM PDT 24
Finished Mar 10 01:24:18 PM PDT 24
Peak memory 210852 kb
Host smart-430fc477-e23c-4f2b-8bab-0aa53f28c9ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5162250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.5162250
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.459957016
Short name T6
Test name
Test status
Simulation time 9268806970 ps
CPU time 25.09 seconds
Started Mar 10 01:24:01 PM PDT 24
Finished Mar 10 01:24:27 PM PDT 24
Peak memory 213212 kb
Host smart-75446c05-0e6f-401a-9f37-c2ae5643b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459957016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.459957016
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.684064921
Short name T354
Test name
Test status
Simulation time 3552614774 ps
CPU time 41.04 seconds
Started Mar 10 01:24:00 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 215648 kb
Host smart-b5f3eeaf-7e30-4c82-8626-924c7cf3c87e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684064921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.684064921
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2149012762
Short name T337
Test name
Test status
Simulation time 271592981401 ps
CPU time 3207.39 seconds
Started Mar 10 01:24:07 PM PDT 24
Finished Mar 10 02:17:35 PM PDT 24
Peak memory 254836 kb
Host smart-8f3454e7-fdf0-43af-8ed5-a6f37616518a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149012762 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2149012762
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2219580800
Short name T173
Test name
Test status
Simulation time 175139661 ps
CPU time 4.22 seconds
Started Mar 10 01:24:09 PM PDT 24
Finished Mar 10 01:24:14 PM PDT 24
Peak memory 210972 kb
Host smart-79114633-ee25-4fce-b341-2d675cb782d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219580800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2219580800
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.924294018
Short name T128
Test name
Test status
Simulation time 88264598289 ps
CPU time 221.46 seconds
Started Mar 10 01:24:04 PM PDT 24
Finished Mar 10 01:27:47 PM PDT 24
Peak memory 232760 kb
Host smart-5ebab0cd-d693-4e45-bb2c-34b07fff92d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924294018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.924294018
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1714409660
Short name T261
Test name
Test status
Simulation time 3759136252 ps
CPU time 31.69 seconds
Started Mar 10 01:24:09 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 211468 kb
Host smart-2d274dc4-6140-4908-b484-408b38d76503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714409660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1714409660
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2581228737
Short name T371
Test name
Test status
Simulation time 906917310 ps
CPU time 10.77 seconds
Started Mar 10 01:24:06 PM PDT 24
Finished Mar 10 01:24:17 PM PDT 24
Peak memory 210828 kb
Host smart-9ad80505-5388-4655-9e7c-b4c1e18ba68c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2581228737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2581228737
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2670654697
Short name T229
Test name
Test status
Simulation time 11531256609 ps
CPU time 27.91 seconds
Started Mar 10 01:24:05 PM PDT 24
Finished Mar 10 01:24:33 PM PDT 24
Peak memory 219120 kb
Host smart-c713aaef-7837-4a19-ab5f-6c2ae51d7e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670654697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2670654697
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3597023869
Short name T290
Test name
Test status
Simulation time 550832082 ps
CPU time 30.04 seconds
Started Mar 10 01:24:09 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 214128 kb
Host smart-97192a1b-b863-41c5-8dca-24cba6069079
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597023869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3597023869
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1564694831
Short name T287
Test name
Test status
Simulation time 9162963451 ps
CPU time 15.31 seconds
Started Mar 10 01:24:09 PM PDT 24
Finished Mar 10 01:24:24 PM PDT 24
Peak memory 211004 kb
Host smart-2692bee7-0d60-42e3-9328-ad92956e5d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564694831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1564694831
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2526642957
Short name T279
Test name
Test status
Simulation time 123883007754 ps
CPU time 282.23 seconds
Started Mar 10 01:24:08 PM PDT 24
Finished Mar 10 01:28:50 PM PDT 24
Peak memory 212172 kb
Host smart-b5850f9b-8fdb-425b-a6fd-c2ccb9b27423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526642957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2526642957
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2299844203
Short name T278
Test name
Test status
Simulation time 3293103627 ps
CPU time 29.11 seconds
Started Mar 10 01:24:11 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 211380 kb
Host smart-026a1e6c-437b-48a7-8e6a-2bd9e1d98c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299844203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2299844203
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2331256825
Short name T120
Test name
Test status
Simulation time 1241564244 ps
CPU time 9.63 seconds
Started Mar 10 01:24:05 PM PDT 24
Finished Mar 10 01:24:15 PM PDT 24
Peak memory 210720 kb
Host smart-a50e30ac-3ca5-43be-9b87-9647f2f8b030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331256825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2331256825
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.477581942
Short name T253
Test name
Test status
Simulation time 19262136398 ps
CPU time 24.17 seconds
Started Mar 10 01:24:06 PM PDT 24
Finished Mar 10 01:24:31 PM PDT 24
Peak memory 214000 kb
Host smart-89d3b256-d552-42c9-87e5-8652fbc6b1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477581942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.477581942
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2254495514
Short name T254
Test name
Test status
Simulation time 2134114486 ps
CPU time 15.38 seconds
Started Mar 10 01:24:04 PM PDT 24
Finished Mar 10 01:24:20 PM PDT 24
Peak memory 210900 kb
Host smart-a6df2a9b-3f40-4708-9ce5-8025f009730e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254495514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2254495514
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1043246936
Short name T45
Test name
Test status
Simulation time 30825476065 ps
CPU time 578.87 seconds
Started Mar 10 01:24:05 PM PDT 24
Finished Mar 10 01:33:44 PM PDT 24
Peak memory 227296 kb
Host smart-3392d8f5-61c4-45ac-bad7-59580d19d9f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043246936 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1043246936
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.207853123
Short name T314
Test name
Test status
Simulation time 2041135985 ps
CPU time 7.75 seconds
Started Mar 10 01:23:25 PM PDT 24
Finished Mar 10 01:23:32 PM PDT 24
Peak memory 210892 kb
Host smart-f1211457-70ed-4598-8046-436ff437954b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207853123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.207853123
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3605624143
Short name T140
Test name
Test status
Simulation time 11032815307 ps
CPU time 117.89 seconds
Started Mar 10 01:23:23 PM PDT 24
Finished Mar 10 01:25:21 PM PDT 24
Peak memory 238932 kb
Host smart-55f9288f-cb40-4152-9f27-f1f9198c0198
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605624143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3605624143
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2074508679
Short name T352
Test name
Test status
Simulation time 8054341640 ps
CPU time 34.54 seconds
Started Mar 10 01:23:21 PM PDT 24
Finished Mar 10 01:23:56 PM PDT 24
Peak memory 212176 kb
Host smart-82d6c0a3-2e87-4d87-9b50-42154a0087b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074508679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2074508679
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2261463787
Short name T126
Test name
Test status
Simulation time 349520634 ps
CPU time 7.53 seconds
Started Mar 10 01:23:23 PM PDT 24
Finished Mar 10 01:23:30 PM PDT 24
Peak memory 210704 kb
Host smart-18e9b4a1-d223-4fd5-a42e-43cca38fd65a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261463787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2261463787
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3251976037
Short name T289
Test name
Test status
Simulation time 27973628492 ps
CPU time 31.23 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:58 PM PDT 24
Peak memory 213920 kb
Host smart-ff03f478-74e9-4112-80b4-a476dcae0f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251976037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3251976037
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3297007744
Short name T10
Test name
Test status
Simulation time 15097191625 ps
CPU time 31.89 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:59 PM PDT 24
Peak memory 214560 kb
Host smart-234e1766-370c-4377-bddb-8f612160dbda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297007744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3297007744
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1700647065
Short name T207
Test name
Test status
Simulation time 125993362449 ps
CPU time 7293.38 seconds
Started Mar 10 01:23:22 PM PDT 24
Finished Mar 10 03:24:56 PM PDT 24
Peak memory 235604 kb
Host smart-f8a7b660-da6e-4650-8edb-3871fe3d44bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700647065 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1700647065
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.83523379
Short name T222
Test name
Test status
Simulation time 333508606 ps
CPU time 4.24 seconds
Started Mar 10 01:24:11 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 210936 kb
Host smart-09793910-7b4f-4374-8235-0dbfbee6a8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83523379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.83523379
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.176384462
Short name T135
Test name
Test status
Simulation time 21557389669 ps
CPU time 113.95 seconds
Started Mar 10 01:24:05 PM PDT 24
Finished Mar 10 01:25:59 PM PDT 24
Peak memory 236336 kb
Host smart-7e6b28cd-1652-4437-8905-3876a959ad25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176384462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.176384462
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4201395558
Short name T166
Test name
Test status
Simulation time 693289884 ps
CPU time 9.6 seconds
Started Mar 10 01:24:06 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 211436 kb
Host smart-acb40633-6a71-49bc-a1f7-07629d5647a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201395558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4201395558
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2570249894
Short name T250
Test name
Test status
Simulation time 1114991192 ps
CPU time 9.14 seconds
Started Mar 10 01:24:06 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 210780 kb
Host smart-d01c5b80-a0e9-4c5d-9dfa-e8cd1b341b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570249894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2570249894
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1717783003
Short name T70
Test name
Test status
Simulation time 674692535 ps
CPU time 10.22 seconds
Started Mar 10 01:24:07 PM PDT 24
Finished Mar 10 01:24:17 PM PDT 24
Peak memory 213192 kb
Host smart-265528a2-c115-4da1-acae-a2b88aeab223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717783003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1717783003
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.740784287
Short name T339
Test name
Test status
Simulation time 4009845088 ps
CPU time 33.14 seconds
Started Mar 10 01:24:08 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 212756 kb
Host smart-deeb418d-9d91-4e4e-9d94-9f366c49a1a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740784287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.740784287
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3076559206
Short name T271
Test name
Test status
Simulation time 4245478655 ps
CPU time 16.02 seconds
Started Mar 10 01:24:18 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 210904 kb
Host smart-79d3797f-a763-4e03-9608-f3131cc54ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076559206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3076559206
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1249371316
Short name T252
Test name
Test status
Simulation time 151627868948 ps
CPU time 246.96 seconds
Started Mar 10 01:24:09 PM PDT 24
Finished Mar 10 01:28:17 PM PDT 24
Peak memory 211144 kb
Host smart-9d6ab4b9-3342-4740-a160-57f05966c0ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249371316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1249371316
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.736807488
Short name T260
Test name
Test status
Simulation time 5873575026 ps
CPU time 19.03 seconds
Started Mar 10 01:24:07 PM PDT 24
Finished Mar 10 01:24:27 PM PDT 24
Peak memory 211912 kb
Host smart-54030379-05ff-4828-8a27-f96b77038922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736807488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.736807488
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3042473046
Short name T333
Test name
Test status
Simulation time 6112068636 ps
CPU time 10.05 seconds
Started Mar 10 01:24:10 PM PDT 24
Finished Mar 10 01:24:21 PM PDT 24
Peak memory 210936 kb
Host smart-49819b28-ba2a-4f89-83bf-f3cd8e8cef87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042473046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3042473046
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.815737288
Short name T311
Test name
Test status
Simulation time 5744506608 ps
CPU time 28.94 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 214516 kb
Host smart-292f6666-5786-42d6-8804-c2975b0633ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815737288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.815737288
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.380378411
Short name T7
Test name
Test status
Simulation time 633483022 ps
CPU time 35.56 seconds
Started Mar 10 01:24:12 PM PDT 24
Finished Mar 10 01:24:48 PM PDT 24
Peak memory 219076 kb
Host smart-09d15b41-820b-425c-be24-41f6dbdb2d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380378411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.380378411
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.488256961
Short name T247
Test name
Test status
Simulation time 36103780093 ps
CPU time 1370.77 seconds
Started Mar 10 01:24:09 PM PDT 24
Finished Mar 10 01:47:01 PM PDT 24
Peak memory 235544 kb
Host smart-b1625b7e-85a0-466e-a152-c6bb076d79a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488256961 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.488256961
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1789615922
Short name T196
Test name
Test status
Simulation time 12245501926 ps
CPU time 11.45 seconds
Started Mar 10 01:24:11 PM PDT 24
Finished Mar 10 01:24:23 PM PDT 24
Peak memory 210956 kb
Host smart-0b1a4e3b-6fa1-4b16-b80f-4ba025926ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789615922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1789615922
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3299550870
Short name T127
Test name
Test status
Simulation time 47636896755 ps
CPU time 248.22 seconds
Started Mar 10 01:24:12 PM PDT 24
Finished Mar 10 01:28:20 PM PDT 24
Peak memory 234488 kb
Host smart-60f48549-dd6c-4685-bdfc-506e8e76eb3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299550870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3299550870
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2952375403
Short name T189
Test name
Test status
Simulation time 175602758 ps
CPU time 9.47 seconds
Started Mar 10 01:24:18 PM PDT 24
Finished Mar 10 01:24:27 PM PDT 24
Peak memory 211392 kb
Host smart-b8feea62-31a4-4bbe-952c-912f4638cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952375403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2952375403
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3416357137
Short name T161
Test name
Test status
Simulation time 1430512092 ps
CPU time 13.38 seconds
Started Mar 10 01:24:16 PM PDT 24
Finished Mar 10 01:24:29 PM PDT 24
Peak memory 210652 kb
Host smart-d1018878-2ee6-465e-a52b-c6325c8d363d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416357137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3416357137
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.95256477
Short name T119
Test name
Test status
Simulation time 11714416410 ps
CPU time 13.77 seconds
Started Mar 10 01:24:13 PM PDT 24
Finished Mar 10 01:24:27 PM PDT 24
Peak memory 213300 kb
Host smart-c4584eca-1cac-4404-84f1-772c291913c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95256477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.95256477
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3633526375
Short name T351
Test name
Test status
Simulation time 18161603538 ps
CPU time 94.74 seconds
Started Mar 10 01:24:09 PM PDT 24
Finished Mar 10 01:25:44 PM PDT 24
Peak memory 219092 kb
Host smart-8285427f-b6f2-40d1-8acb-2a6b654244ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633526375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3633526375
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.377623722
Short name T331
Test name
Test status
Simulation time 9114692092 ps
CPU time 16.03 seconds
Started Mar 10 01:24:12 PM PDT 24
Finished Mar 10 01:24:28 PM PDT 24
Peak memory 210988 kb
Host smart-8703c2a8-e2ec-42bf-8c89-8890f9359e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377623722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.377623722
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2234832010
Short name T291
Test name
Test status
Simulation time 19989488023 ps
CPU time 212.2 seconds
Started Mar 10 01:24:11 PM PDT 24
Finished Mar 10 01:27:43 PM PDT 24
Peak memory 238936 kb
Host smart-e1e83377-aef2-4cc4-a96b-db7acf5e61d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234832010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2234832010
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3524855425
Short name T21
Test name
Test status
Simulation time 622129191 ps
CPU time 9.67 seconds
Started Mar 10 01:24:10 PM PDT 24
Finished Mar 10 01:24:20 PM PDT 24
Peak memory 213296 kb
Host smart-e4ebd364-1d27-456e-b8cb-83cfc4bca735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524855425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3524855425
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3006725441
Short name T136
Test name
Test status
Simulation time 175934197 ps
CPU time 5.7 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:24:21 PM PDT 24
Peak memory 210652 kb
Host smart-8b568596-e5df-4e84-843f-1da234a7c05d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006725441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3006725441
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.101325438
Short name T329
Test name
Test status
Simulation time 11016159844 ps
CPU time 30.27 seconds
Started Mar 10 01:24:11 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 213416 kb
Host smart-fa3c63c4-6bd9-40a8-b810-4cdb8d3ed314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101325438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.101325438
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2829661890
Short name T172
Test name
Test status
Simulation time 11756328315 ps
CPU time 28.62 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:24:44 PM PDT 24
Peak memory 218980 kb
Host smart-905926e9-9b74-4357-a977-7a10e93730d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829661890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2829661890
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2651360286
Short name T344
Test name
Test status
Simulation time 85709908184 ps
CPU time 5216.39 seconds
Started Mar 10 01:24:10 PM PDT 24
Finished Mar 10 02:51:07 PM PDT 24
Peak memory 232836 kb
Host smart-906e7eee-cdbc-47de-8fb3-833688389f12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651360286 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2651360286
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.24555682
Short name T223
Test name
Test status
Simulation time 1663688776 ps
CPU time 14.02 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 210804 kb
Host smart-400da3aa-5312-41e6-9672-e1091edd6b4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.24555682
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1905449070
Short name T165
Test name
Test status
Simulation time 48089133662 ps
CPU time 485.63 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:32:21 PM PDT 24
Peak memory 229332 kb
Host smart-ab99db15-3dc8-4b08-801b-7b5161733775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905449070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1905449070
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2596537578
Short name T346
Test name
Test status
Simulation time 5237544831 ps
CPU time 13.37 seconds
Started Mar 10 01:24:17 PM PDT 24
Finished Mar 10 01:24:31 PM PDT 24
Peak memory 211772 kb
Host smart-52e992f4-ce02-4643-bf8d-27eef2d5832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596537578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2596537578
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1679503261
Short name T317
Test name
Test status
Simulation time 191750023 ps
CPU time 5.39 seconds
Started Mar 10 01:24:18 PM PDT 24
Finished Mar 10 01:24:23 PM PDT 24
Peak memory 210720 kb
Host smart-3e2dd11b-ba6c-4e5f-a091-767d78ed421f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679503261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1679503261
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3095249060
Short name T179
Test name
Test status
Simulation time 37537506576 ps
CPU time 72.95 seconds
Started Mar 10 01:24:16 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 214644 kb
Host smart-165a4e2e-a1a3-43a1-b000-6175c7f57690
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095249060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3095249060
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3560736744
Short name T220
Test name
Test status
Simulation time 4097320538 ps
CPU time 10.98 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:24:26 PM PDT 24
Peak memory 210940 kb
Host smart-55cc866a-f258-49e4-bb7a-7a2a43bf5eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560736744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3560736744
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.807207794
Short name T28
Test name
Test status
Simulation time 23245416911 ps
CPU time 238.36 seconds
Started Mar 10 01:24:14 PM PDT 24
Finished Mar 10 01:28:13 PM PDT 24
Peak memory 224240 kb
Host smart-a192588a-0344-4548-88ea-710a5cd0c64a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807207794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.807207794
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1610993598
Short name T309
Test name
Test status
Simulation time 6693671870 ps
CPU time 30.81 seconds
Started Mar 10 01:24:19 PM PDT 24
Finished Mar 10 01:24:50 PM PDT 24
Peak memory 211696 kb
Host smart-f09c6adf-c602-4606-a21b-e73d2c30339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610993598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1610993598
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.597911503
Short name T286
Test name
Test status
Simulation time 213603407 ps
CPU time 5.7 seconds
Started Mar 10 01:24:17 PM PDT 24
Finished Mar 10 01:24:23 PM PDT 24
Peak memory 210748 kb
Host smart-90401630-2b5f-4a88-9541-e7025f807703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597911503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.597911503
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1826573560
Short name T190
Test name
Test status
Simulation time 522400357 ps
CPU time 13.3 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:24:28 PM PDT 24
Peak memory 212096 kb
Host smart-cda04df6-1a5f-4869-94b4-8ac82e197814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826573560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1826573560
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4216252014
Short name T343
Test name
Test status
Simulation time 1223319640 ps
CPU time 25.21 seconds
Started Mar 10 01:24:14 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 212996 kb
Host smart-f03d16e0-28e2-407a-b654-264246a7802e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216252014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4216252014
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.904660887
Short name T370
Test name
Test status
Simulation time 171495459 ps
CPU time 4.25 seconds
Started Mar 10 01:24:14 PM PDT 24
Finished Mar 10 01:24:18 PM PDT 24
Peak memory 210884 kb
Host smart-a768d45f-b0ce-4158-8b12-d9f1d7864fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904660887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.904660887
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4294732353
Short name T211
Test name
Test status
Simulation time 2191965556 ps
CPU time 65.55 seconds
Started Mar 10 01:24:18 PM PDT 24
Finished Mar 10 01:25:24 PM PDT 24
Peak memory 211140 kb
Host smart-3b2646ed-ab84-48f2-b9e6-c05cb41f2d60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294732353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4294732353
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2630103386
Short name T8
Test name
Test status
Simulation time 825499284 ps
CPU time 12.66 seconds
Started Mar 10 01:24:16 PM PDT 24
Finished Mar 10 01:24:29 PM PDT 24
Peak memory 210924 kb
Host smart-6d0ac463-30bd-4394-9787-9cec24cf4fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630103386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2630103386
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.881660551
Short name T277
Test name
Test status
Simulation time 1544414233 ps
CPU time 14.36 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 210796 kb
Host smart-c768042a-699b-4b0d-b3c8-9fe3921d2ac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881660551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.881660551
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2420336169
Short name T342
Test name
Test status
Simulation time 6885665775 ps
CPU time 35.64 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:56 PM PDT 24
Peak memory 213624 kb
Host smart-b00c5597-d88e-49db-8c4d-dcc4063f49ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420336169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2420336169
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4033522947
Short name T208
Test name
Test status
Simulation time 3161699497 ps
CPU time 21.69 seconds
Started Mar 10 01:24:17 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 212472 kb
Host smart-381a1fb1-74fc-4886-8e1d-4c4cba2ce1c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033522947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4033522947
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.27599884
Short name T44
Test name
Test status
Simulation time 68413723805 ps
CPU time 9837.98 seconds
Started Mar 10 01:24:18 PM PDT 24
Finished Mar 10 04:08:17 PM PDT 24
Peak memory 230228 kb
Host smart-5750f698-8ba7-45e3-97d4-80153d33ff01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599884 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.27599884
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2411043662
Short name T267
Test name
Test status
Simulation time 85419567 ps
CPU time 4.37 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:24:19 PM PDT 24
Peak memory 210936 kb
Host smart-02e35283-baa7-454b-b2cb-9ff541543171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411043662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2411043662
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.32304931
Short name T40
Test name
Test status
Simulation time 50649887375 ps
CPU time 478.34 seconds
Started Mar 10 01:24:16 PM PDT 24
Finished Mar 10 01:32:14 PM PDT 24
Peak memory 233640 kb
Host smart-8eb73888-5049-4002-a5ea-5fcbf528a39c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32304931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_co
rrupt_sig_fatal_chk.32304931
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.663651639
Short name T350
Test name
Test status
Simulation time 32831715942 ps
CPU time 31.32 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:24:46 PM PDT 24
Peak memory 211760 kb
Host smart-42bcbdc7-a96e-4841-8b0d-7c1a5373197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663651639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.663651639
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2608437948
Short name T204
Test name
Test status
Simulation time 367956881 ps
CPU time 5.28 seconds
Started Mar 10 01:24:16 PM PDT 24
Finished Mar 10 01:24:22 PM PDT 24
Peak memory 210840 kb
Host smart-03a2e4cb-da9e-4ea9-9cde-7f3276624451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608437948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2608437948
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3042108022
Short name T296
Test name
Test status
Simulation time 33671774142 ps
CPU time 40.68 seconds
Started Mar 10 01:24:17 PM PDT 24
Finished Mar 10 01:24:58 PM PDT 24
Peak memory 213552 kb
Host smart-bafd883c-bb31-4f92-a7bd-ac29fe88a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042108022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3042108022
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2354538156
Short name T348
Test name
Test status
Simulation time 5081001066 ps
CPU time 24.51 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 218972 kb
Host smart-e2623926-35c7-47b6-b6a5-200f3550dbb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354538156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2354538156
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1394846704
Short name T34
Test name
Test status
Simulation time 2684396574 ps
CPU time 12.54 seconds
Started Mar 10 01:24:19 PM PDT 24
Finished Mar 10 01:24:32 PM PDT 24
Peak memory 210908 kb
Host smart-d27aa75f-525e-4b66-a914-313b9a1147f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394846704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1394846704
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1417757541
Short name T199
Test name
Test status
Simulation time 8643337360 ps
CPU time 143.32 seconds
Started Mar 10 01:24:15 PM PDT 24
Finished Mar 10 01:26:39 PM PDT 24
Peak memory 228700 kb
Host smart-fce36e02-3fd4-43c4-8d48-37f7948adf86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417757541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1417757541
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2749264773
Short name T169
Test name
Test status
Simulation time 11598447445 ps
CPU time 26.67 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 211820 kb
Host smart-6897fc52-7338-4702-bf32-e1ca0a89e527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749264773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2749264773
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2998942232
Short name T367
Test name
Test status
Simulation time 1823506086 ps
CPU time 17.28 seconds
Started Mar 10 01:24:14 PM PDT 24
Finished Mar 10 01:24:32 PM PDT 24
Peak memory 210716 kb
Host smart-42b2559a-9c29-4f83-87c8-70ef225c2ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998942232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2998942232
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4100119675
Short name T142
Test name
Test status
Simulation time 234778498 ps
CPU time 10.04 seconds
Started Mar 10 01:24:19 PM PDT 24
Finished Mar 10 01:24:29 PM PDT 24
Peak memory 212720 kb
Host smart-c6475ff6-50c9-4853-a333-937b77d8369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100119675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4100119675
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.620808547
Short name T144
Test name
Test status
Simulation time 428346743 ps
CPU time 24.9 seconds
Started Mar 10 01:24:18 PM PDT 24
Finished Mar 10 01:24:43 PM PDT 24
Peak memory 214664 kb
Host smart-2e09f651-f961-4cc5-b5b4-104f439b259b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620808547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.620808547
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.333600399
Short name T182
Test name
Test status
Simulation time 1470574449 ps
CPU time 6.89 seconds
Started Mar 10 01:24:21 PM PDT 24
Finished Mar 10 01:24:28 PM PDT 24
Peak memory 210824 kb
Host smart-546bb7b4-e481-4268-94b8-59621d7d6d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333600399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.333600399
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3505169711
Short name T238
Test name
Test status
Simulation time 23696692492 ps
CPU time 294.64 seconds
Started Mar 10 01:24:21 PM PDT 24
Finished Mar 10 01:29:16 PM PDT 24
Peak memory 238360 kb
Host smart-1b3fcc46-8a94-4824-86ab-8f5469427694
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505169711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3505169711
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1937757549
Short name T315
Test name
Test status
Simulation time 13652584187 ps
CPU time 30 seconds
Started Mar 10 01:24:21 PM PDT 24
Finished Mar 10 01:24:51 PM PDT 24
Peak memory 211696 kb
Host smart-d82da8f1-54bd-4efe-ae84-e021a983799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937757549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1937757549
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2434094667
Short name T295
Test name
Test status
Simulation time 8280077251 ps
CPU time 17.52 seconds
Started Mar 10 01:24:23 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 210780 kb
Host smart-116c8050-9a54-4e77-a597-f5127bc4f534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434094667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2434094667
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4277405174
Short name T258
Test name
Test status
Simulation time 10342728088 ps
CPU time 29.47 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:50 PM PDT 24
Peak memory 213176 kb
Host smart-420a2a38-a38f-4712-9e17-e8807d1d9d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277405174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4277405174
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4031425201
Short name T361
Test name
Test status
Simulation time 1366472295 ps
CPU time 24.28 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:44 PM PDT 24
Peak memory 219060 kb
Host smart-ec6c2a4f-b610-43e0-92fe-ab3712a0ba9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031425201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4031425201
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2685800015
Short name T303
Test name
Test status
Simulation time 86229043 ps
CPU time 4.23 seconds
Started Mar 10 01:23:21 PM PDT 24
Finished Mar 10 01:23:26 PM PDT 24
Peak memory 210824 kb
Host smart-fd84ccba-4983-4fc0-b799-110d29a6eeda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685800015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2685800015
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1107006494
Short name T184
Test name
Test status
Simulation time 10242286098 ps
CPU time 170.17 seconds
Started Mar 10 01:23:22 PM PDT 24
Finished Mar 10 01:26:12 PM PDT 24
Peak memory 224716 kb
Host smart-78ece325-7380-4b44-93ae-e34a7eb7734d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107006494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1107006494
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3521749547
Short name T364
Test name
Test status
Simulation time 6453378770 ps
CPU time 28.21 seconds
Started Mar 10 01:23:22 PM PDT 24
Finished Mar 10 01:23:51 PM PDT 24
Peak memory 211736 kb
Host smart-84c01fe0-9f5b-4ba1-8eeb-c5ee8776cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521749547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3521749547
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3817125796
Short name T145
Test name
Test status
Simulation time 11478295557 ps
CPU time 16.87 seconds
Started Mar 10 01:23:24 PM PDT 24
Finished Mar 10 01:23:41 PM PDT 24
Peak memory 210832 kb
Host smart-d19e88ec-cd6e-4397-b8ca-96af8c30ff0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817125796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3817125796
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3353369343
Short name T3
Test name
Test status
Simulation time 7930932161 ps
CPU time 61.81 seconds
Started Mar 10 01:23:23 PM PDT 24
Finished Mar 10 01:24:25 PM PDT 24
Peak memory 236132 kb
Host smart-739a5254-4f7c-4e0b-bebc-02abd9ce9a57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353369343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3353369343
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1403582680
Short name T251
Test name
Test status
Simulation time 526684008 ps
CPU time 13.81 seconds
Started Mar 10 01:23:24 PM PDT 24
Finished Mar 10 01:23:39 PM PDT 24
Peak memory 212916 kb
Host smart-dc24b2a5-8629-4114-9815-e09c465cef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403582680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1403582680
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1504257632
Short name T269
Test name
Test status
Simulation time 9150908698 ps
CPU time 45.65 seconds
Started Mar 10 01:23:22 PM PDT 24
Finished Mar 10 01:24:08 PM PDT 24
Peak memory 213228 kb
Host smart-0d096f41-0dfa-4b42-8138-0f151fba34f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504257632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1504257632
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1296423006
Short name T32
Test name
Test status
Simulation time 741096892 ps
CPU time 7.74 seconds
Started Mar 10 01:24:21 PM PDT 24
Finished Mar 10 01:24:29 PM PDT 24
Peak memory 210792 kb
Host smart-43ea4907-dae9-4c71-98ce-efe5d1eb65e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296423006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1296423006
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4005650811
Short name T249
Test name
Test status
Simulation time 2460701130 ps
CPU time 163.16 seconds
Started Mar 10 01:24:23 PM PDT 24
Finished Mar 10 01:27:06 PM PDT 24
Peak memory 236236 kb
Host smart-7abe84c9-2c69-45eb-b3a8-23e9e31f599e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005650811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4005650811
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3317793523
Short name T59
Test name
Test status
Simulation time 4254293502 ps
CPU time 17.41 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 211732 kb
Host smart-861a2f2e-35cc-4d82-8f3d-9cc6fbf1fa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317793523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3317793523
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4225587844
Short name T132
Test name
Test status
Simulation time 2283277209 ps
CPU time 12.22 seconds
Started Mar 10 01:24:23 PM PDT 24
Finished Mar 10 01:24:35 PM PDT 24
Peak memory 210892 kb
Host smart-33214ba3-fb74-469b-9c18-665de1f140dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225587844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4225587844
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.970003804
Short name T113
Test name
Test status
Simulation time 72657106429 ps
CPU time 32.46 seconds
Started Mar 10 01:24:22 PM PDT 24
Finished Mar 10 01:24:55 PM PDT 24
Peak memory 213388 kb
Host smart-318f5b00-7ce4-4bfc-a550-5370f2d008d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970003804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.970003804
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.193800850
Short name T162
Test name
Test status
Simulation time 26227021490 ps
CPU time 46.56 seconds
Started Mar 10 01:24:23 PM PDT 24
Finished Mar 10 01:25:10 PM PDT 24
Peak memory 213568 kb
Host smart-4d013ced-e51f-424d-bf81-848f36c1d9ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193800850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.193800850
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.872055684
Short name T52
Test name
Test status
Simulation time 1229632035 ps
CPU time 11.85 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:43 PM PDT 24
Peak memory 210832 kb
Host smart-f28f1ec2-6675-43df-8e2d-453d3089bef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872055684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.872055684
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2481319180
Short name T30
Test name
Test status
Simulation time 1854646003 ps
CPU time 111.8 seconds
Started Mar 10 01:24:21 PM PDT 24
Finished Mar 10 01:26:13 PM PDT 24
Peak memory 212608 kb
Host smart-46a7177f-166a-4173-99b6-f890b93d0586
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481319180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2481319180
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.387347216
Short name T360
Test name
Test status
Simulation time 13296858165 ps
CPU time 32.77 seconds
Started Mar 10 01:24:20 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 211816 kb
Host smart-c2f97894-fdba-41d4-b398-f8089ba547c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387347216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.387347216
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2003675344
Short name T237
Test name
Test status
Simulation time 186643842 ps
CPU time 5.4 seconds
Started Mar 10 01:24:21 PM PDT 24
Finished Mar 10 01:24:27 PM PDT 24
Peak memory 210720 kb
Host smart-42785f18-da15-4a20-b3cb-2c436f7accc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003675344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2003675344
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3900007142
Short name T192
Test name
Test status
Simulation time 378764874 ps
CPU time 10.33 seconds
Started Mar 10 01:24:23 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 212872 kb
Host smart-081b8de9-6846-4b3d-b1d7-c6a772936609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900007142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3900007142
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3275849312
Short name T299
Test name
Test status
Simulation time 4341417221 ps
CPU time 53.05 seconds
Started Mar 10 01:24:21 PM PDT 24
Finished Mar 10 01:25:14 PM PDT 24
Peak memory 216036 kb
Host smart-8ae98575-6890-49aa-aeee-098cc10e206b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275849312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3275849312
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1382309143
Short name T54
Test name
Test status
Simulation time 508077233 ps
CPU time 5.99 seconds
Started Mar 10 01:24:24 PM PDT 24
Finished Mar 10 01:24:30 PM PDT 24
Peak memory 210836 kb
Host smart-ce59433b-04f1-4bf4-a678-9deaaa782780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382309143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1382309143
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.96703592
Short name T130
Test name
Test status
Simulation time 7110478954 ps
CPU time 91.52 seconds
Started Mar 10 01:24:28 PM PDT 24
Finished Mar 10 01:26:00 PM PDT 24
Peak memory 233308 kb
Host smart-cad4bd4c-8aa8-423b-96f3-571b4d2fa0bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96703592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_co
rrupt_sig_fatal_chk.96703592
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3619907244
Short name T133
Test name
Test status
Simulation time 4582426301 ps
CPU time 17.25 seconds
Started Mar 10 01:24:25 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 211688 kb
Host smart-088d6254-91cd-4202-9682-ea57e7684ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619907244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3619907244
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2136227330
Short name T12
Test name
Test status
Simulation time 8585811258 ps
CPU time 17.97 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:44 PM PDT 24
Peak memory 210800 kb
Host smart-84a69aa5-bf62-4342-b89b-aa7c20bbc51a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136227330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2136227330
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.46378358
Short name T117
Test name
Test status
Simulation time 180052575 ps
CPU time 9.84 seconds
Started Mar 10 01:24:24 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 213072 kb
Host smart-620d25ad-3d09-428f-bad2-2da218ed404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46378358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.46378358
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.82659738
Short name T234
Test name
Test status
Simulation time 7745113292 ps
CPU time 45.12 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:25:12 PM PDT 24
Peak memory 219068 kb
Host smart-bd610bcd-64ae-403d-a14d-eabe8c7abd8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82659738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.rom_ctrl_stress_all.82659738
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4176930595
Short name T55
Test name
Test status
Simulation time 1095040527 ps
CPU time 10.68 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:37 PM PDT 24
Peak memory 210896 kb
Host smart-364379d4-4a2c-4d97-9676-d97e21de66e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176930595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4176930595
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3657205175
Short name T138
Test name
Test status
Simulation time 73478613054 ps
CPU time 221.11 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:28:07 PM PDT 24
Peak memory 212284 kb
Host smart-d9e9dbf9-ce13-4b1e-9094-435c94535508
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657205175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3657205175
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1755023358
Short name T177
Test name
Test status
Simulation time 1246843537 ps
CPU time 12.29 seconds
Started Mar 10 01:24:25 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 211376 kb
Host smart-2ff72cc2-0dc8-4b30-8e0b-3cab66e934e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755023358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1755023358
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3606196729
Short name T338
Test name
Test status
Simulation time 1808493623 ps
CPU time 7.97 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 210792 kb
Host smart-bab839cc-036d-4433-a4f9-ddd829b0c49f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606196729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3606196729
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1920640097
Short name T71
Test name
Test status
Simulation time 2242419563 ps
CPU time 26.56 seconds
Started Mar 10 01:24:28 PM PDT 24
Finished Mar 10 01:24:55 PM PDT 24
Peak memory 213116 kb
Host smart-e8be47f0-dae5-4a5c-acfd-7054271f7891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920640097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1920640097
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3149759645
Short name T336
Test name
Test status
Simulation time 1739383881 ps
CPU time 16.47 seconds
Started Mar 10 01:24:23 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 211132 kb
Host smart-b1d28717-8879-4937-96e3-4d13994f2619
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149759645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3149759645
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3686129308
Short name T33
Test name
Test status
Simulation time 12892238962 ps
CPU time 13.66 seconds
Started Mar 10 01:24:27 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 210980 kb
Host smart-539ee792-088f-4d30-b642-911f9b5149fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686129308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3686129308
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.925553577
Short name T29
Test name
Test status
Simulation time 2002805493 ps
CPU time 133.08 seconds
Started Mar 10 01:24:27 PM PDT 24
Finished Mar 10 01:26:40 PM PDT 24
Peak memory 232276 kb
Host smart-67503a12-eccb-472d-9b18-d43074501248
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925553577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.925553577
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.189854652
Short name T366
Test name
Test status
Simulation time 2461337562 ps
CPU time 24.44 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:51 PM PDT 24
Peak memory 211472 kb
Host smart-e8409459-e742-4760-8acd-4565e5f3b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189854652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.189854652
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2410616281
Short name T183
Test name
Test status
Simulation time 4729338941 ps
CPU time 11.84 seconds
Started Mar 10 01:24:27 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 210888 kb
Host smart-f19f20fe-0005-4277-b227-a6441d0d1c79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410616281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2410616281
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1988489205
Short name T228
Test name
Test status
Simulation time 13686619056 ps
CPU time 29.57 seconds
Started Mar 10 01:24:25 PM PDT 24
Finished Mar 10 01:24:54 PM PDT 24
Peak memory 219016 kb
Host smart-fd3f89a9-38f9-4fa9-ad44-e54c6f8e6ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988489205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1988489205
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2236890211
Short name T156
Test name
Test status
Simulation time 4041750370 ps
CPU time 14.07 seconds
Started Mar 10 01:24:27 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 211972 kb
Host smart-34b22f03-e993-4d2e-b6a2-41b1cc390340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236890211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2236890211
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.649784010
Short name T358
Test name
Test status
Simulation time 8100835103 ps
CPU time 16.55 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 210936 kb
Host smart-2d734413-4d71-47eb-a618-8ae884f5aefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649784010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.649784010
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.451658706
Short name T341
Test name
Test status
Simulation time 1313091700 ps
CPU time 72.7 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 212204 kb
Host smart-24838188-a67f-4dde-a1f9-61c4e7244c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451658706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.451658706
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1227935527
Short name T304
Test name
Test status
Simulation time 173452878 ps
CPU time 9.49 seconds
Started Mar 10 01:24:27 PM PDT 24
Finished Mar 10 01:24:37 PM PDT 24
Peak memory 211376 kb
Host smart-5389370b-48f9-41a7-9d1e-c87339a57e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227935527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1227935527
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.324638683
Short name T201
Test name
Test status
Simulation time 102000310 ps
CPU time 5.77 seconds
Started Mar 10 01:24:24 PM PDT 24
Finished Mar 10 01:24:30 PM PDT 24
Peak memory 210760 kb
Host smart-7b464a5c-cbff-4aa7-b55e-7a003169fac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324638683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.324638683
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1652847438
Short name T74
Test name
Test status
Simulation time 370464145 ps
CPU time 10.35 seconds
Started Mar 10 01:24:28 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 212756 kb
Host smart-c7c75c89-eef5-4dc3-adef-b561c0c30e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652847438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1652847438
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1900025962
Short name T116
Test name
Test status
Simulation time 1745502887 ps
CPU time 8.53 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 210776 kb
Host smart-d59511bc-7c17-4067-8c8e-7c7d05d370ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900025962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1900025962
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3185593091
Short name T245
Test name
Test status
Simulation time 167779247 ps
CPU time 4.25 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:31 PM PDT 24
Peak memory 210896 kb
Host smart-63541286-d81d-4139-9d91-802cad0ac1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185593091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3185593091
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.589625151
Short name T233
Test name
Test status
Simulation time 61453324781 ps
CPU time 219.05 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:28:05 PM PDT 24
Peak memory 235700 kb
Host smart-ce677f1f-b71b-43c4-a2f1-fec58e7907d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589625151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.589625151
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2774438036
Short name T243
Test name
Test status
Simulation time 7186902335 ps
CPU time 20.96 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 211940 kb
Host smart-00e37af8-cfca-406a-9955-dbdd0d658180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774438036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2774438036
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1620591361
Short name T357
Test name
Test status
Simulation time 138711284 ps
CPU time 6.65 seconds
Started Mar 10 01:24:25 PM PDT 24
Finished Mar 10 01:24:32 PM PDT 24
Peak memory 210796 kb
Host smart-2c91bc53-2119-4de1-bba9-1f0e61bc15de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620591361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1620591361
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.729462455
Short name T131
Test name
Test status
Simulation time 1334966669 ps
CPU time 17.78 seconds
Started Mar 10 01:24:29 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 212652 kb
Host smart-20aed587-66e3-41fd-93bf-eabb84492f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729462455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.729462455
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1885777481
Short name T282
Test name
Test status
Simulation time 860139702 ps
CPU time 13.54 seconds
Started Mar 10 01:24:29 PM PDT 24
Finished Mar 10 01:24:43 PM PDT 24
Peak memory 213584 kb
Host smart-52e5c054-e8a1-4b38-9289-6679222270f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885777481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1885777481
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.975547662
Short name T292
Test name
Test status
Simulation time 9007672212 ps
CPU time 702.17 seconds
Started Mar 10 01:24:33 PM PDT 24
Finished Mar 10 01:36:15 PM PDT 24
Peak memory 227660 kb
Host smart-78dfd28c-c74e-4638-8483-c2ee4b4566e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975547662 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.975547662
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2377546396
Short name T171
Test name
Test status
Simulation time 9152171524 ps
CPU time 15.8 seconds
Started Mar 10 01:24:29 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 211044 kb
Host smart-e9a151ae-a84b-4a5d-a345-1feb8625294f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377546396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2377546396
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1367718976
Short name T125
Test name
Test status
Simulation time 46140795576 ps
CPU time 421.81 seconds
Started Mar 10 01:24:25 PM PDT 24
Finished Mar 10 01:31:27 PM PDT 24
Peak memory 237372 kb
Host smart-3725c012-99b6-46a1-9b7f-1066184994bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367718976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1367718976
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3812726265
Short name T175
Test name
Test status
Simulation time 2241818338 ps
CPU time 23.9 seconds
Started Mar 10 01:24:26 PM PDT 24
Finished Mar 10 01:24:50 PM PDT 24
Peak memory 211500 kb
Host smart-ea378eb1-a9e9-4801-b6d7-d0f5ee12583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812726265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3812726265
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2310307072
Short name T320
Test name
Test status
Simulation time 3280438217 ps
CPU time 10.46 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 210776 kb
Host smart-a11f420b-b0e8-420b-b6b0-4531415355ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310307072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2310307072
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2957599601
Short name T13
Test name
Test status
Simulation time 19381521063 ps
CPU time 31.24 seconds
Started Mar 10 01:24:28 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 213992 kb
Host smart-04d47404-98da-46f8-8482-56d004798ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957599601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2957599601
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.122220842
Short name T212
Test name
Test status
Simulation time 593275285 ps
CPU time 4.18 seconds
Started Mar 10 01:24:32 PM PDT 24
Finished Mar 10 01:24:37 PM PDT 24
Peak memory 210840 kb
Host smart-a7dec523-95d5-422a-a73b-0b5fb094837d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122220842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.122220842
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3130177120
Short name T155
Test name
Test status
Simulation time 7105790717 ps
CPU time 126.69 seconds
Started Mar 10 01:24:32 PM PDT 24
Finished Mar 10 01:26:39 PM PDT 24
Peak memory 228280 kb
Host smart-a54aa021-aa7a-4300-b794-6177c7293ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130177120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3130177120
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1155112374
Short name T356
Test name
Test status
Simulation time 5815527241 ps
CPU time 18.66 seconds
Started Mar 10 01:24:30 PM PDT 24
Finished Mar 10 01:24:49 PM PDT 24
Peak memory 211952 kb
Host smart-568c761a-9d85-4324-94d5-7cb5ddeb73ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155112374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1155112374
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.68548156
Short name T298
Test name
Test status
Simulation time 93455844 ps
CPU time 5.42 seconds
Started Mar 10 01:24:29 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 210740 kb
Host smart-546f6021-b2eb-44e7-abe7-81f2cae110a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68548156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.68548156
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.527830852
Short name T57
Test name
Test status
Simulation time 5683827852 ps
CPU time 31.54 seconds
Started Mar 10 01:24:30 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 212876 kb
Host smart-81431561-52d9-4e36-87b3-a565557dff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527830852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.527830852
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1725477948
Short name T160
Test name
Test status
Simulation time 6361587969 ps
CPU time 22.6 seconds
Started Mar 10 01:24:30 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 214448 kb
Host smart-6ea42c6f-3caf-4993-a483-909d67d44d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725477948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1725477948
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2376004909
Short name T178
Test name
Test status
Simulation time 498205584 ps
CPU time 5.2 seconds
Started Mar 10 01:24:29 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 210940 kb
Host smart-5e2bda2d-59c5-486b-a179-660fc7d549eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376004909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2376004909
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2869264700
Short name T293
Test name
Test status
Simulation time 76063675315 ps
CPU time 179.08 seconds
Started Mar 10 01:24:32 PM PDT 24
Finished Mar 10 01:27:31 PM PDT 24
Peak memory 233500 kb
Host smart-36c97354-09fc-453c-9e2e-c437c9130678
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869264700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2869264700
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3719517659
Short name T307
Test name
Test status
Simulation time 10436214843 ps
CPU time 25.91 seconds
Started Mar 10 01:24:29 PM PDT 24
Finished Mar 10 01:24:55 PM PDT 24
Peak memory 210988 kb
Host smart-2dbef560-2398-4f2c-b75d-d15248b3bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719517659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3719517659
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1535168864
Short name T9
Test name
Test status
Simulation time 686428803 ps
CPU time 8.05 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 210824 kb
Host smart-df14e2c3-9bfb-4976-83c3-151c59b36e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535168864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1535168864
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1889613142
Short name T134
Test name
Test status
Simulation time 5367803036 ps
CPU time 30.15 seconds
Started Mar 10 01:24:32 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 212940 kb
Host smart-df59bf4f-a40d-4c90-92c2-777ac66f7bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889613142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1889613142
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1263482547
Short name T283
Test name
Test status
Simulation time 758943752 ps
CPU time 41.74 seconds
Started Mar 10 01:24:35 PM PDT 24
Finished Mar 10 01:25:18 PM PDT 24
Peak memory 214832 kb
Host smart-0f14a7e3-0604-429a-9bd5-4c7e3f025cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263482547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1263482547
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.576129012
Short name T301
Test name
Test status
Simulation time 98290782740 ps
CPU time 4191.09 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 02:34:22 PM PDT 24
Peak memory 268220 kb
Host smart-f2cc5135-d375-4462-824a-d205ddde563c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576129012 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.576129012
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2614388299
Short name T227
Test name
Test status
Simulation time 416168297 ps
CPU time 7.03 seconds
Started Mar 10 01:23:26 PM PDT 24
Finished Mar 10 01:23:33 PM PDT 24
Peak memory 210964 kb
Host smart-66c3d314-b9ea-4898-9c4b-4e58092ce2e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614388299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2614388299
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.598153104
Short name T272
Test name
Test status
Simulation time 3040819533 ps
CPU time 111 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 232392 kb
Host smart-1fa28aba-88aa-46cb-8050-6811c6279883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598153104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.598153104
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3371137729
Short name T215
Test name
Test status
Simulation time 22345271681 ps
CPU time 29.45 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:57 PM PDT 24
Peak memory 212096 kb
Host smart-5260bf43-3ff9-4463-9cb9-58d9781e4369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371137729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3371137729
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.158411181
Short name T174
Test name
Test status
Simulation time 4620030004 ps
CPU time 17.08 seconds
Started Mar 10 01:23:23 PM PDT 24
Finished Mar 10 01:23:40 PM PDT 24
Peak memory 210744 kb
Host smart-5cd364e5-39e7-436a-8452-2d5c22eb9dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158411181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.158411181
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1850372268
Short name T312
Test name
Test status
Simulation time 1584394160 ps
CPU time 21.65 seconds
Started Mar 10 01:23:24 PM PDT 24
Finished Mar 10 01:23:46 PM PDT 24
Peak memory 213280 kb
Host smart-91529390-b691-4c0a-8dcb-64dd335cc6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850372268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1850372268
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.47954346
Short name T235
Test name
Test status
Simulation time 7974058096 ps
CPU time 17.9 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:45 PM PDT 24
Peak memory 210916 kb
Host smart-87108057-772c-45dd-b3aa-3f9dac9ae08b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47954346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.rom_ctrl_stress_all.47954346
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4189260516
Short name T294
Test name
Test status
Simulation time 3794260910 ps
CPU time 10.6 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:38 PM PDT 24
Peak memory 210800 kb
Host smart-bf1d0257-46a6-4c91-9b34-8c24f5e327f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189260516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4189260516
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4065210478
Short name T262
Test name
Test status
Simulation time 55275779846 ps
CPU time 446.62 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:30:55 PM PDT 24
Peak memory 237468 kb
Host smart-f9b05462-6ba6-4ce6-8bcd-b34a55804442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065210478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4065210478
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2879671017
Short name T60
Test name
Test status
Simulation time 1281673019 ps
CPU time 17.05 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:23:46 PM PDT 24
Peak memory 211432 kb
Host smart-d3f1bb4e-a24d-4f44-ae64-06301919239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879671017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2879671017
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.985059907
Short name T225
Test name
Test status
Simulation time 186042493 ps
CPU time 5.34 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:32 PM PDT 24
Peak memory 210748 kb
Host smart-cd55bcd1-2e45-49dc-b6b9-e974ae43087a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985059907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.985059907
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.694148438
Short name T241
Test name
Test status
Simulation time 3857275317 ps
CPU time 16.17 seconds
Started Mar 10 01:23:26 PM PDT 24
Finished Mar 10 01:23:42 PM PDT 24
Peak memory 212872 kb
Host smart-27a471f5-8d8c-48cf-bebf-ce6d84301193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694148438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.694148438
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3700634081
Short name T147
Test name
Test status
Simulation time 797786742 ps
CPU time 23.48 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:23:53 PM PDT 24
Peak memory 213992 kb
Host smart-1f103529-1f73-4f38-9510-80a0900f723a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700634081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3700634081
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3714675872
Short name T349
Test name
Test status
Simulation time 438785417 ps
CPU time 4.31 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:23:32 PM PDT 24
Peak memory 210876 kb
Host smart-6b6a15e6-e66e-4f76-970d-d208fcecda36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714675872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3714675872
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1921781206
Short name T206
Test name
Test status
Simulation time 150302928616 ps
CPU time 432.31 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:30:41 PM PDT 24
Peak memory 233272 kb
Host smart-a25020dd-c75b-4fb2-9d7c-a41ed841ffca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921781206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1921781206
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2242603631
Short name T154
Test name
Test status
Simulation time 5286227868 ps
CPU time 33.12 seconds
Started Mar 10 01:23:30 PM PDT 24
Finished Mar 10 01:24:03 PM PDT 24
Peak memory 211820 kb
Host smart-2da5512b-55f3-4295-afcc-0561bef61e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242603631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2242603631
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2298859165
Short name T121
Test name
Test status
Simulation time 181993144 ps
CPU time 5.86 seconds
Started Mar 10 01:23:30 PM PDT 24
Finished Mar 10 01:23:36 PM PDT 24
Peak memory 210748 kb
Host smart-50fa7a58-7885-462a-aa42-893b54b7ab0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298859165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2298859165
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3720992368
Short name T318
Test name
Test status
Simulation time 7371953961 ps
CPU time 21.84 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:23:50 PM PDT 24
Peak memory 213208 kb
Host smart-0a964945-5168-401e-8261-cc6bca199cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720992368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3720992368
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3405583533
Short name T276
Test name
Test status
Simulation time 4091387221 ps
CPU time 26.55 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:23:54 PM PDT 24
Peak memory 216000 kb
Host smart-778e6874-2bf7-4175-8eb8-8b5b5e493a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405583533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3405583533
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4260788472
Short name T41
Test name
Test status
Simulation time 50484205429 ps
CPU time 580.5 seconds
Started Mar 10 01:23:31 PM PDT 24
Finished Mar 10 01:33:11 PM PDT 24
Peak memory 227392 kb
Host smart-b600b39e-dd54-4ae7-918b-bcec34c1f5bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260788472 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.4260788472
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.765732244
Short name T232
Test name
Test status
Simulation time 332686332 ps
CPU time 4.37 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:23:33 PM PDT 24
Peak memory 210924 kb
Host smart-0631e1b7-2fa8-49dd-9248-293735ffa999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765732244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.765732244
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2661480542
Short name T148
Test name
Test status
Simulation time 6097845032 ps
CPU time 139.33 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:25:47 PM PDT 24
Peak memory 219408 kb
Host smart-71c2d2d5-0520-410d-a52c-ff2f720f56e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661480542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2661480542
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.262780804
Short name T20
Test name
Test status
Simulation time 177651040 ps
CPU time 9.67 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:23:38 PM PDT 24
Peak memory 211428 kb
Host smart-fed9d94a-3459-494e-a99c-9e78649d3b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262780804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.262780804
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2600521001
Short name T246
Test name
Test status
Simulation time 7420707616 ps
CPU time 16.76 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:44 PM PDT 24
Peak memory 210796 kb
Host smart-db8a76a8-b9ac-4d72-a606-b3e8d2824bc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600521001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2600521001
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2946250664
Short name T73
Test name
Test status
Simulation time 2065380547 ps
CPU time 26.39 seconds
Started Mar 10 01:23:28 PM PDT 24
Finished Mar 10 01:23:54 PM PDT 24
Peak memory 212804 kb
Host smart-38000f2c-a69e-403b-a6e0-48e1ee7c5a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946250664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2946250664
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3819102718
Short name T202
Test name
Test status
Simulation time 17662039640 ps
CPU time 46.57 seconds
Started Mar 10 01:23:29 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 213560 kb
Host smart-87d068c6-0a01-4456-9fae-fc35a0a29cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819102718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3819102718
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1033196511
Short name T11
Test name
Test status
Simulation time 23841941579 ps
CPU time 898.37 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:38:25 PM PDT 24
Peak memory 234848 kb
Host smart-8a2b33ff-e4a5-411a-8e9a-6e17583165d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033196511 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1033196511
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1379041812
Short name T273
Test name
Test status
Simulation time 88937181 ps
CPU time 4.25 seconds
Started Mar 10 01:23:38 PM PDT 24
Finished Mar 10 01:23:42 PM PDT 24
Peak memory 210920 kb
Host smart-b9b90ff4-fcff-4f1f-9c0d-dbf7c8e77e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379041812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1379041812
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1146783711
Short name T39
Test name
Test status
Simulation time 61670762164 ps
CPU time 221 seconds
Started Mar 10 01:23:39 PM PDT 24
Finished Mar 10 01:27:20 PM PDT 24
Peak memory 224532 kb
Host smart-3919bef8-5fab-4abf-89b3-ad45f9834f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146783711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1146783711
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2449155248
Short name T226
Test name
Test status
Simulation time 666929944 ps
CPU time 13.98 seconds
Started Mar 10 01:23:33 PM PDT 24
Finished Mar 10 01:23:47 PM PDT 24
Peak memory 213472 kb
Host smart-1ab8d688-8008-4c6d-8357-c702bf4acc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449155248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2449155248
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4265318801
Short name T340
Test name
Test status
Simulation time 1315818483 ps
CPU time 12.68 seconds
Started Mar 10 01:23:39 PM PDT 24
Finished Mar 10 01:23:52 PM PDT 24
Peak memory 210716 kb
Host smart-b943e5f4-6012-4371-8650-26fe70cea32f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265318801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4265318801
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.294265473
Short name T308
Test name
Test status
Simulation time 13267782959 ps
CPU time 23.73 seconds
Started Mar 10 01:23:27 PM PDT 24
Finished Mar 10 01:23:51 PM PDT 24
Peak memory 213848 kb
Host smart-9bcdbf98-9ab4-457d-9747-5fb474717c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294265473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.294265473
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2332869684
Short name T114
Test name
Test status
Simulation time 7329556599 ps
CPU time 38.56 seconds
Started Mar 10 01:23:33 PM PDT 24
Finished Mar 10 01:24:11 PM PDT 24
Peak memory 215832 kb
Host smart-1d18b7ba-6744-4fb1-ba0d-e746076ef78c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332869684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2332869684
Directory /workspace/9.rom_ctrl_stress_all/latest
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