Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	104278	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1050201

1

T1

14

T4

23

T5

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	291434	1			T1	32		T4	32		T5	64
values[0x0]	401204	1			T3	1		T13	45180		T33	5
values[0x1]	461841	1			T3	2		T32	6		T13	51894

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1106971

1

T1

17

T4

28

T5

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5109	1			T13	503		T15	351		T16	294
valid_sources[0x01]	5008	1			T13	507		T15	363		T16	252
valid_sources[0x02]	4328	1			T10	1		T32	1		T13	449
valid_sources[0x03]	5058	1			T9	1		T13	490		T15	397
valid_sources[0x04]	4987	1			T20	1		T13	514		T15	410
valid_sources[0x05]	4482	1			T20	1		T13	472		T18	2
valid_sources[0x06]	4261	1			T13	545		T136	1		T15	386
valid_sources[0x07]	4402	1			T1	1		T13	506		T15	393
valid_sources[0x08]	4783	1			T13	481		T46	1		T135	2
valid_sources[0x09]	4391	1			T13	470		T15	386		T16	276
valid_sources[0x0a]	4348	1			T5	2		T13	502		T46	1
valid_sources[0x0b]	4510	1			T13	593		T15	370		T16	273
valid_sources[0x0c]	4564	1			T13	499		T135	3		T15	393
valid_sources[0x0d]	4628	1			T13	466		T15	395		T16	271
valid_sources[0x0e]	4546	1			T1	1		T13	558		T68	128
valid_sources[0x0f]	4365	1			T13	518		T33	1		T15	374
valid_sources[0x10]	4629	1			T32	1		T13	517		T15	358
valid_sources[0x11]	4532	1			T13	503		T15	303		T16	228
valid_sources[0x12]	4590	1			T28	1		T13	519		T18	4
valid_sources[0x13]	4913	1			T13	481		T18	6		T118	1
valid_sources[0x14]	4186	1			T13	584		T18	2		T15	339
valid_sources[0x15]	4610	1			T5	1		T13	517		T15	404
valid_sources[0x16]	4534	1			T13	484		T15	373		T16	247
valid_sources[0x17]	4485	1			T20	1		T26	1		T13	505
valid_sources[0x18]	4247	1			T10	1		T13	446		T18	1
valid_sources[0x19]	4322	1			T27	1		T13	488		T33	2
valid_sources[0x1a]	4285	1			T20	1		T13	492		T58	1
valid_sources[0x1b]	4399	1			T13	519		T46	2		T15	372
valid_sources[0x1c]	4793	1			T13	490		T67	1		T15	403
valid_sources[0x1d]	4559	1			T20	1		T13	473		T18	2
valid_sources[0x1e]	4045	1			T1	1		T4	5		T10	1
valid_sources[0x1f]	4939	1			T13	546		T15	348		T16	245
valid_sources[0x20]	4191	1			T20	1		T13	537		T15	399
valid_sources[0x21]	4517	1			T27	2		T13	492		T33	1
valid_sources[0x22]	4579	1			T20	1		T13	521		T67	1
valid_sources[0x23]	4495	1			T26	1		T13	525		T15	318
valid_sources[0x24]	4401	1			T13	463		T15	416		T16	254
valid_sources[0x25]	4269	1			T5	2		T13	492		T15	317
valid_sources[0x26]	4475	1			T10	1		T13	550		T25	1
valid_sources[0x27]	4975	1			T20	1		T28	1		T13	474
valid_sources[0x28]	4329	1			T5	2		T27	1		T13	521
valid_sources[0x29]	4531	1			T5	1		T10	1		T13	554
valid_sources[0x2a]	4399	1			T13	461		T67	1		T15	413
valid_sources[0x2b]	4684	1			T5	2		T13	468		T15	372
valid_sources[0x2c]	4629	1			T28	1		T13	537		T15	431
valid_sources[0x2d]	4311	1			T13	532		T18	5		T15	396
valid_sources[0x2e]	4930	1			T20	2		T13	535		T60	1
valid_sources[0x2f]	4481	1			T27	1		T20	1		T13	508
valid_sources[0x30]	4585	1			T28	1		T13	550		T15	391
valid_sources[0x31]	4759	1			T13	525		T15	420		T16	246
valid_sources[0x32]	4133	1			T4	1		T28	1		T13	512
valid_sources[0x33]	4778	1			T1	2		T13	499		T15	400
valid_sources[0x34]	4257	1			T20	1		T13	487		T33	1
valid_sources[0x35]	4270	1			T13	525		T15	328		T16	260
valid_sources[0x36]	4617	1			T13	519		T15	351		T16	240
valid_sources[0x37]	4489	1			T1	1		T13	479		T15	319
valid_sources[0x38]	4227	1			T5	1		T32	1		T13	538
valid_sources[0x39]	4476	1			T13	489		T118	3		T135	1
valid_sources[0x3a]	4583	1			T5	2		T13	508		T15	371
valid_sources[0x3b]	4462	1			T1	1		T5	2		T13	554
valid_sources[0x3c]	4567	1			T28	1		T13	538		T15	348
valid_sources[0x3d]	4334	1			T5	2		T13	420		T67	1
valid_sources[0x3e]	4319	1			T3	1		T13	508		T15	331
valid_sources[0x3f]	4690	1			T27	1		T13	515		T15	390
valid_sources[0x40]	4932	1			T1	2		T5	1		T20	1
valid_sources[0x41]	4375	1			T20	1		T13	519		T58	2
valid_sources[0x42]	4759	1			T13	493		T15	336		T16	249
valid_sources[0x43]	4180	1			T13	514		T18	1		T137	1
valid_sources[0x44]	4704	1			T13	542		T46	1		T15	331
valid_sources[0x45]	4658	1			T7	1		T13	507		T46	1
valid_sources[0x46]	4299	1			T13	513		T15	318		T16	253
valid_sources[0x47]	4961	1			T5	1		T13	579		T15	361
valid_sources[0x48]	4509	1			T13	525		T15	392		T16	267
valid_sources[0x49]	4998	1			T13	458		T15	386		T16	282
valid_sources[0x4a]	4874	1			T13	508		T15	441		T16	250
valid_sources[0x4b]	4648	1			T27	1		T32	1		T13	493
valid_sources[0x4c]	4420	1			T13	482		T135	1		T15	320
valid_sources[0x4d]	4704	1			T13	572		T118	1		T67	2
valid_sources[0x4e]	4180	1			T13	514		T15	359		T16	217
valid_sources[0x4f]	4484	1			T13	473		T15	431		T16	223
valid_sources[0x50]	4337	1			T1	1		T13	545		T15	396
valid_sources[0x51]	4864	1			T13	513		T15	359		T16	300
valid_sources[0x52]	4360	1			T13	521		T118	1		T135	1
valid_sources[0x53]	4578	1			T10	2		T13	452		T15	375
valid_sources[0x54]	4647	1			T13	503		T60	1		T118	1
valid_sources[0x55]	4942	1			T13	502		T15	412		T16	235
valid_sources[0x56]	4515	1			T13	506		T15	410		T16	261
valid_sources[0x57]	4369	1			T13	504		T18	1		T46	1
valid_sources[0x58]	4640	1			T13	512		T15	365		T16	266
valid_sources[0x59]	4787	1			T13	542		T15	368		T16	283
valid_sources[0x5a]	4337	1			T26	4		T13	506		T67	2
valid_sources[0x5b]	4961	1			T13	441		T15	356		T16	258
valid_sources[0x5c]	5034	1			T13	512		T15	424		T16	238
valid_sources[0x5d]	4744	1			T13	515		T15	320		T16	266
valid_sources[0x5e]	4644	1			T13	502		T15	348		T16	252
valid_sources[0x5f]	4817	1			T4	3		T5	5		T13	566
valid_sources[0x60]	4700	1			T1	1		T13	538		T33	2
valid_sources[0x61]	4293	1			T13	499		T15	360		T16	280
valid_sources[0x62]	4545	1			T1	1		T20	1		T13	502
valid_sources[0x63]	4254	1			T5	1		T13	503		T135	2
valid_sources[0x64]	4536	1			T4	2		T13	470		T15	331
valid_sources[0x65]	4282	1			T4	2		T28	3		T13	452
valid_sources[0x66]	4753	1			T27	1		T13	536		T67	3
valid_sources[0x67]	4112	1			T1	2		T13	418		T118	1
valid_sources[0x68]	4170	1			T13	502		T33	2		T15	421
valid_sources[0x69]	4211	1			T13	472		T15	338		T16	262
valid_sources[0x6a]	4593	1			T13	515		T15	334		T16	261
valid_sources[0x6b]	4803	1			T4	5		T5	1		T10	2
valid_sources[0x6c]	4576	1			T5	1		T13	510		T15	387
valid_sources[0x6d]	4381	1			T13	501		T46	1		T15	368
valid_sources[0x6e]	4703	1			T10	1		T28	1		T13	488
valid_sources[0x6f]	4107	1			T13	502		T15	352		T16	249
valid_sources[0x70]	4392	1			T5	1		T13	540		T118	2
valid_sources[0x71]	4364	1			T13	488		T18	1		T15	355
valid_sources[0x72]	4633	1			T13	552		T118	1		T135	1
valid_sources[0x73]	4698	1			T4	1		T13	519		T18	1
valid_sources[0x74]	4424	1			T26	1		T13	484		T15	417
valid_sources[0x75]	4353	1			T5	1		T26	2		T13	486
valid_sources[0x76]	4183	1			T1	1		T27	2		T13	496
valid_sources[0x77]	4797	1			T1	1		T13	507		T15	357
valid_sources[0x78]	4227	1			T10	1		T13	587		T15	353
valid_sources[0x79]	4794	1			T13	483		T15	420		T16	248
valid_sources[0x7a]	4552	1			T13	549		T15	395		T16	237
valid_sources[0x7b]	4643	1			T13	540		T15	370		T16	257
valid_sources[0x7c]	4424	1			T1	1		T5	2		T13	512
valid_sources[0x7d]	4736	1			T13	484		T15	407		T16	225
valid_sources[0x7e]	4783	1			T13	539		T15	362		T16	255
valid_sources[0x7f]	4184	1			T5	1		T13	443		T15	332
valid_sources[0x80]	4899	1			T13	530		T15	371		T16	268

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

266511

1

T1

14

T4

23

T5

32

values[0x0]

all_enables

biggest_size

392929

1

T13

44330

T33

1

T57

2

values[0x1]

all_enables

biggest_size

390761

1

T32

1

T13

44157

T33

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	242022	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1017759

1

T1

3

T2

14

T4

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	293378	1			T1	58		T2	137		T4	78
values[0x0]	399269	1			T13	46067		T15	33042		T16	23420
values[0x1]	567134	1			T13	65015		T15	46410		T16	33580

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	92648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1167133

1

T1

34

T2

89

T4

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4673	1			T2	1		T13	576		T119	1
valid_sources[0x01]	4347	1			T2	1		T8	1		T13	450
valid_sources[0x02]	4405	1			T13	545		T34	3		T118	2
valid_sources[0x03]	4835	1			T13	672		T34	1		T119	1
valid_sources[0x04]	6049	1			T5	1		T8	2		T13	708
valid_sources[0x05]	4831	1			T8	1		T11	22		T13	591
valid_sources[0x06]	5147	1			T5	2		T13	604		T34	2
valid_sources[0x07]	4698	1			T1	3		T2	1		T13	601
valid_sources[0x08]	4800	1			T2	2		T11	2		T49	35
valid_sources[0x09]	5206	1			T5	3		T13	561		T34	2
valid_sources[0x0a]	5004	1			T5	1		T6	43		T8	2
valid_sources[0x0b]	4791	1			T2	1		T13	491		T138	5
valid_sources[0x0c]	4842	1			T13	509		T34	3		T119	1
valid_sources[0x0d]	4548	1			T11	31		T13	584		T68	2
valid_sources[0x0e]	4406	1			T5	1		T8	1		T13	505
valid_sources[0x0f]	5337	1			T13	532		T34	5		T68	2
valid_sources[0x10]	4524	1			T1	3		T5	1		T8	10
valid_sources[0x11]	4840	1			T8	2		T13	522		T34	3
valid_sources[0x12]	4423	1			T5	1		T8	1		T13	521
valid_sources[0x13]	5521	1			T2	2		T5	2		T8	3
valid_sources[0x14]	5473	1			T2	1		T13	556		T34	2
valid_sources[0x15]	5013	1			T8	1		T13	570		T34	1
valid_sources[0x16]	5131	1			T1	2		T13	509		T68	1
valid_sources[0x17]	4891	1			T4	1		T13	595		T34	2
valid_sources[0x18]	4927	1			T2	2		T5	1		T13	581
valid_sources[0x19]	4622	1			T2	1		T8	5		T13	617
valid_sources[0x1a]	4761	1			T4	3		T26	9		T28	3
valid_sources[0x1b]	5454	1			T13	561		T34	3		T15	387
valid_sources[0x1c]	4511	1			T1	2		T2	1		T13	572
valid_sources[0x1d]	5329	1			T2	1		T8	4		T13	626
valid_sources[0x1e]	4951	1			T5	1		T13	527		T34	1
valid_sources[0x1f]	4825	1			T13	560		T34	2		T68	2
valid_sources[0x20]	4570	1			T13	563		T34	2		T118	1
valid_sources[0x21]	4615	1			T2	1		T4	1		T5	1
valid_sources[0x22]	5111	1			T4	2		T5	3		T13	573
valid_sources[0x23]	4811	1			T2	1		T13	495		T34	2
valid_sources[0x24]	4647	1			T4	2		T5	4		T11	3
valid_sources[0x25]	4447	1			T1	3		T13	519		T18	1
valid_sources[0x26]	5590	1			T2	1		T4	2		T13	581
valid_sources[0x27]	4889	1			T2	1		T13	549		T119	2
valid_sources[0x28]	4973	1			T2	1		T13	504		T119	1
valid_sources[0x29]	5340	1			T5	1		T8	4		T13	531
valid_sources[0x2a]	4537	1			T2	1		T4	1		T13	570
valid_sources[0x2b]	5141	1			T6	34		T13	566		T34	2
valid_sources[0x2c]	4598	1			T4	1		T13	585		T138	2
valid_sources[0x2d]	5837	1			T2	1		T13	528		T34	1
valid_sources[0x2e]	4744	1			T2	1		T5	1		T13	588
valid_sources[0x2f]	4651	1			T13	580		T34	2		T18	2
valid_sources[0x30]	5056	1			T11	9		T13	571		T34	1
valid_sources[0x31]	5770	1			T5	2		T13	583		T34	2
valid_sources[0x32]	5406	1			T2	1		T4	1		T13	582
valid_sources[0x33]	4959	1			T2	3		T4	1		T6	10
valid_sources[0x34]	5071	1			T5	5		T13	580		T18	4
valid_sources[0x35]	4472	1			T13	497		T34	1		T15	325
valid_sources[0x36]	4831	1			T8	1		T13	575		T34	2
valid_sources[0x37]	6012	1			T2	1		T4	2		T13	550
valid_sources[0x38]	4276	1			T13	491		T119	1		T15	374
valid_sources[0x39]	4535	1			T8	4		T13	562		T119	1
valid_sources[0x3a]	4786	1			T1	1		T2	1		T6	21
valid_sources[0x3b]	5864	1			T13	531		T34	1		T119	1
valid_sources[0x3c]	4815	1			T8	2		T13	519		T138	3
valid_sources[0x3d]	5061	1			T5	2		T13	561		T34	1
valid_sources[0x3e]	5548	1			T5	4		T13	554		T34	2
valid_sources[0x3f]	4773	1			T13	531		T34	1		T119	1
valid_sources[0x40]	4554	1			T13	651		T15	406		T16	46
valid_sources[0x41]	4800	1			T2	1		T5	3		T13	524
valid_sources[0x42]	5487	1			T2	1		T13	625		T34	4
valid_sources[0x43]	5630	1			T1	5		T13	651		T34	1
valid_sources[0x44]	4701	1			T2	2		T4	2		T5	2
valid_sources[0x45]	5152	1			T5	1		T13	538		T34	2
valid_sources[0x46]	5152	1			T8	1		T13	567		T34	2
valid_sources[0x47]	4714	1			T13	591		T118	1		T138	3
valid_sources[0x48]	4447	1			T2	1		T13	532		T34	1
valid_sources[0x49]	4930	1			T13	635		T68	1		T15	357
valid_sources[0x4a]	5052	1			T4	3		T13	552		T68	1
valid_sources[0x4b]	5103	1			T2	3		T13	548		T67	1
valid_sources[0x4c]	4765	1			T5	2		T13	433		T138	4
valid_sources[0x4d]	5046	1			T13	487		T34	1		T67	1
valid_sources[0x4e]	4830	1			T4	1		T5	2		T13	508
valid_sources[0x4f]	4799	1			T13	548		T34	1		T138	1
valid_sources[0x50]	4978	1			T2	1		T49	37		T13	582
valid_sources[0x51]	4861	1			T2	1		T5	1		T13	654
valid_sources[0x52]	4524	1			T1	5		T2	1		T8	2
valid_sources[0x53]	4599	1			T2	1		T5	2		T8	3
valid_sources[0x54]	4494	1			T8	3		T13	513		T68	1
valid_sources[0x55]	4603	1			T8	3		T13	547		T34	1
valid_sources[0x56]	4885	1			T1	2		T13	591		T138	13
valid_sources[0x57]	4598	1			T5	1		T13	633		T119	2
valid_sources[0x58]	4653	1			T49	46		T13	532		T34	1
valid_sources[0x59]	5102	1			T4	1		T13	517		T118	1
valid_sources[0x5a]	5906	1			T13	605		T15	398		T16	695
valid_sources[0x5b]	4885	1			T13	649		T34	2		T119	1
valid_sources[0x5c]	4537	1			T4	2		T8	1		T13	526
valid_sources[0x5d]	4807	1			T2	2		T13	508		T34	2
valid_sources[0x5e]	5100	1			T5	1		T13	518		T67	2
valid_sources[0x5f]	4745	1			T5	4		T8	2		T13	563
valid_sources[0x60]	4464	1			T5	1		T13	510		T34	2
valid_sources[0x61]	4863	1			T5	2		T13	615		T34	2
valid_sources[0x62]	4984	1			T8	2		T13	605		T119	1
valid_sources[0x63]	4479	1			T13	474		T34	1		T67	1
valid_sources[0x64]	4647	1			T4	6		T13	486		T34	1
valid_sources[0x65]	5755	1			T8	2		T13	579		T18	1
valid_sources[0x66]	5840	1			T1	1		T2	1		T13	644
valid_sources[0x67]	4916	1			T8	1		T13	490		T15	380
valid_sources[0x68]	4892	1			T1	1		T2	2		T5	4
valid_sources[0x69]	5267	1			T5	2		T13	525		T118	1
valid_sources[0x6a]	4625	1			T2	1		T5	1		T13	592
valid_sources[0x6b]	4392	1			T1	2		T13	562		T15	402
valid_sources[0x6c]	5448	1			T8	1		T13	544		T34	1
valid_sources[0x6d]	5531	1			T5	1		T13	611		T68	1
valid_sources[0x6e]	5220	1			T2	2		T8	1		T13	498
valid_sources[0x6f]	4515	1			T2	3		T5	3		T13	505
valid_sources[0x70]	4645	1			T5	4		T13	541		T138	1
valid_sources[0x71]	5377	1			T13	471		T15	311		T16	703
valid_sources[0x72]	5070	1			T5	1		T6	45		T13	529
valid_sources[0x73]	4751	1			T13	485		T34	1		T118	3
valid_sources[0x74]	4482	1			T5	1		T8	5		T13	592
valid_sources[0x75]	4824	1			T13	646		T34	2		T15	323
valid_sources[0x76]	4356	1			T2	3		T13	499		T34	2
valid_sources[0x77]	4406	1			T13	608		T118	1		T68	1
valid_sources[0x78]	4902	1			T1	3		T2	1		T13	586
valid_sources[0x79]	5957	1			T13	507		T34	2		T18	1
valid_sources[0x7a]	5180	1			T2	2		T13	564		T119	1
valid_sources[0x7b]	4984	1			T2	2		T13	576		T34	1
valid_sources[0x7c]	5381	1			T5	2		T13	486		T138	8
valid_sources[0x7d]	4781	1			T13	579		T34	1		T118	1
valid_sources[0x7e]	4367	1			T13	533		T34	2		T68	1
valid_sources[0x7f]	5700	1			T2	1		T13	550		T67	1
valid_sources[0x80]	4523	1			T13	630		T34	1		T67	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

257521

1

T1

3

T2

14

T4

9

values[0x0]

all_enables

biggest_size

379725

1

T13

43829

T15

31517

T16

22223

values[0x1]

all_enables

biggest_size

380513

1

T13

43996

T15

31905

T16

22186