Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2838472

1

T1

55

T2

123

T4

69

full_word

1220153

1

T1

3

T2

14

T4

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4058335	1			T1	58		T2	137		T4	78
auto[TlIntgErrCmd]	105	1			T61	4		T62	7		T63	2
auto[TlIntgErrData]	93	1			T61	3		T62	8		T63	6
auto[TlIntgErrBoth]	92	1			T61	3		T62	5		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

497848

1

T1

58

T2

137

T4

78

auto[1]

3560777

1

T13

407046

T15

286059

T16

213078

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	215969	1			T1	55		T2	123		T4	69
auto[TlIntgErrNone]	partial	auto[1]	2622241	1			T13	298876		T15	208421		T16	158114
auto[TlIntgErrNone]	full_word	auto[0]	281755	1			T1	3		T2	14		T4	9
auto[TlIntgErrNone]	full_word	auto[1]	938370	1			T13	108170		T15	77638		T16	54964
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T61	3		T62	2		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T61	1		T62	3		T63	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T62	1		T127	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T62	1		T129	1		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1			T62	5		T63	2		T131	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T61	2		T62	2		T63	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T62	1		T124	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T61	1		T124	1		T133	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T61	1		T62	2		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T61	1		T62	3		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T61	1		T127	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T124	2		T125	1		T128	1