Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2506839

1

T1

209200

T4

54

T6

70

full_word

1603665

1

T1

138828

T3

2

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4110234	1			T1	348028		T3	2		T4	62
auto[TlIntgErrCmd]	98	1			T57	4		T58	5		T59	6
auto[TlIntgErrData]	81	1			T57	2		T58	2		T59	8
auto[TlIntgErrBoth]	91	1			T57	4		T58	3		T59	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657339

1

T1

53500

T3

2

T4

62

auto[1]

3453165

1

T1

294528

T11

74777

T12

339951

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	277912	1			T1	20809		T4	54		T6	70
auto[TlIntgErrNone]	partial	auto[1]	2228689	1			T1	188391		T11	47982		T12	219344
auto[TlIntgErrNone]	full_word	auto[0]	379313	1			T1	32691		T3	2		T4	8
auto[TlIntgErrNone]	full_word	auto[1]	1224320	1			T1	106137		T11	26795		T12	120607
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T58	3		T59	3		T115	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T57	3		T58	2		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T122	1		T120	2		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T57	1		T115	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T59	5		T115	1		T119	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T57	2		T58	1		T59	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T115	1		T122	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T58	1		T117	2		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T57	1		T58	1		T115	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T57	3		T58	2		T59	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T59	1		T115	2		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T115	1		T117	1		T124	1