Unified Coverage Report :: Module :: rom_ctrl_counter

Module : rom_ctrl_counter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.64	100.00	98.18		100.00	100.00	75.00	gen_fsm_scramble_enabled.u_checker_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl_counter

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	74	1	1	100.00
ALWAYS	76	3	3	100.00
ALWAYS	84	6	6	100.00
ALWAYS	94	5	5	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	1	1
76	1	1
77	1	1
79	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
89	1	1
			MISSING_ELSE
94	1	1
95	1	1
96	1	1
101	1	1
104	1	1
108	1	1
110	1	1
111	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1

---

Cond Coverage for Module : rom_ctrl_counter

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (addr_q == TopAddr)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 EXPRESSION (data_rdy_i & vld_q & ((~done_d)))
             -----1----   --2--   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (addr_q == TNTAddr)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (go ? addr_d : addr_q)
             -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : rom_ctrl_counter

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	114	2	2	100.00
IF	76	2	2	100.00
IF	84	3	3	100.00
IF	94	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	114	(go) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	84	if ((!rst_ni))
-2-:	87	if (go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl_counter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NonTopCountValid_A	321	321	0	0
TopCountValid_A	321	321	0	0

NonTopCountValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321	321	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TopCountValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	321	321	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0