Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 96.97 93.25 97.88 100.00 99.01 97.89 98.37


Total test records in report: 918
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T562 /workspace/coverage/default/46.rom_ctrl_smoke.3018244148 Mar 17 01:47:34 PM PDT 24 Mar 17 01:48:21 PM PDT 24 51419633024 ps
T563 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3503978963 Mar 17 01:47:02 PM PDT 24 Mar 17 01:47:58 PM PDT 24 11267976423 ps
T564 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4095430059 Mar 17 02:40:24 PM PDT 24 Mar 17 02:40:36 PM PDT 24 1341691638 ps
T565 /workspace/coverage/default/49.rom_ctrl_stress_all.492017356 Mar 17 01:47:41 PM PDT 24 Mar 17 01:49:04 PM PDT 24 5956857603 ps
T566 /workspace/coverage/default/41.rom_ctrl_smoke.4075105920 Mar 17 02:40:41 PM PDT 24 Mar 17 02:41:01 PM PDT 24 349299783 ps
T567 /workspace/coverage/default/9.rom_ctrl_stress_all.3015988498 Mar 17 02:40:02 PM PDT 24 Mar 17 02:42:53 PM PDT 24 15629942227 ps
T568 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2988253292 Mar 17 02:40:55 PM PDT 24 Mar 17 02:41:28 PM PDT 24 3795227836 ps
T569 /workspace/coverage/default/19.rom_ctrl_stress_all.3891561783 Mar 17 01:47:15 PM PDT 24 Mar 17 01:47:54 PM PDT 24 2952605671 ps
T570 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.449797677 Mar 17 01:47:27 PM PDT 24 Mar 17 01:47:51 PM PDT 24 2280842070 ps
T571 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4140239702 Mar 17 01:47:39 PM PDT 24 Mar 17 01:48:05 PM PDT 24 14638577266 ps
T572 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1656907821 Mar 17 02:40:11 PM PDT 24 Mar 17 02:40:33 PM PDT 24 3790290168 ps
T573 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2813287805 Mar 17 01:46:43 PM PDT 24 Mar 17 01:50:26 PM PDT 24 86909410316 ps
T574 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1942133173 Mar 17 02:40:33 PM PDT 24 Mar 17 02:40:53 PM PDT 24 1319016371 ps
T575 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2177202649 Mar 17 01:46:56 PM PDT 24 Mar 17 01:47:07 PM PDT 24 181796822 ps
T576 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.122784733 Mar 17 01:47:27 PM PDT 24 Mar 17 01:47:43 PM PDT 24 5573849096 ps
T577 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2525157950 Mar 17 01:46:53 PM PDT 24 Mar 17 01:54:28 PM PDT 24 112906875924 ps
T578 /workspace/coverage/default/18.rom_ctrl_smoke.1783523096 Mar 17 01:47:15 PM PDT 24 Mar 17 01:48:01 PM PDT 24 8914896512 ps
T579 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1196976522 Mar 17 02:40:09 PM PDT 24 Mar 17 02:40:35 PM PDT 24 24532732109 ps
T580 /workspace/coverage/default/2.rom_ctrl_stress_all.2794109927 Mar 17 02:40:02 PM PDT 24 Mar 17 02:43:35 PM PDT 24 24160142766 ps
T581 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.172334678 Mar 17 01:46:56 PM PDT 24 Mar 17 01:47:22 PM PDT 24 12059693731 ps
T582 /workspace/coverage/default/0.rom_ctrl_stress_all.2183748701 Mar 17 02:39:53 PM PDT 24 Mar 17 02:41:54 PM PDT 24 36675983281 ps
T583 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.801107161 Mar 17 01:47:21 PM PDT 24 Mar 17 01:52:29 PM PDT 24 12086579413 ps
T584 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3307992841 Mar 17 02:41:05 PM PDT 24 Mar 17 02:41:30 PM PDT 24 5101844010 ps
T585 /workspace/coverage/default/26.rom_ctrl_smoke.3416280364 Mar 17 01:47:27 PM PDT 24 Mar 17 01:48:28 PM PDT 24 27276363206 ps
T586 /workspace/coverage/default/36.rom_ctrl_alert_test.83040278 Mar 17 01:47:31 PM PDT 24 Mar 17 01:47:40 PM PDT 24 169207287 ps
T587 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1886138500 Mar 17 02:40:35 PM PDT 24 Mar 17 02:43:57 PM PDT 24 12033004976 ps
T588 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4246393366 Mar 17 02:40:34 PM PDT 24 Mar 17 02:42:50 PM PDT 24 1653952021 ps
T589 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1410044712 Mar 17 01:47:07 PM PDT 24 Mar 17 01:47:48 PM PDT 24 3581525426 ps
T590 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2779990699 Mar 17 01:47:26 PM PDT 24 Mar 17 01:48:15 PM PDT 24 5068491722 ps
T591 /workspace/coverage/default/43.rom_ctrl_stress_all.2250337625 Mar 17 01:47:29 PM PDT 24 Mar 17 01:51:18 PM PDT 24 41071096686 ps
T592 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2203235830 Mar 17 02:41:11 PM PDT 24 Mar 17 02:54:06 PM PDT 24 68914462250 ps
T593 /workspace/coverage/default/37.rom_ctrl_stress_all.2343136129 Mar 17 02:40:35 PM PDT 24 Mar 17 02:41:19 PM PDT 24 1477845513 ps
T594 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.305233011 Mar 17 02:40:47 PM PDT 24 Mar 17 02:50:59 PM PDT 24 53933466459 ps
T595 /workspace/coverage/default/25.rom_ctrl_smoke.3166319130 Mar 17 02:40:23 PM PDT 24 Mar 17 02:41:01 PM PDT 24 3371901725 ps
T596 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2100316837 Mar 17 01:47:35 PM PDT 24 Mar 17 01:48:47 PM PDT 24 8488093146 ps
T597 /workspace/coverage/default/6.rom_ctrl_alert_test.2885050269 Mar 17 01:46:52 PM PDT 24 Mar 17 01:47:06 PM PDT 24 2524778770 ps
T598 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3261047164 Mar 17 02:39:59 PM PDT 24 Mar 17 02:40:16 PM PDT 24 1167739665 ps
T599 /workspace/coverage/default/28.rom_ctrl_alert_test.1379805345 Mar 17 02:40:32 PM PDT 24 Mar 17 02:41:04 PM PDT 24 3889143599 ps
T600 /workspace/coverage/default/35.rom_ctrl_smoke.1788034836 Mar 17 01:47:30 PM PDT 24 Mar 17 01:48:35 PM PDT 24 29664696262 ps
T601 /workspace/coverage/default/19.rom_ctrl_alert_test.98121960 Mar 17 02:40:15 PM PDT 24 Mar 17 02:40:24 PM PDT 24 194592640 ps
T602 /workspace/coverage/default/44.rom_ctrl_smoke.3751991968 Mar 17 02:40:55 PM PDT 24 Mar 17 02:42:00 PM PDT 24 20460160332 ps
T603 /workspace/coverage/default/8.rom_ctrl_smoke.610453105 Mar 17 01:46:53 PM PDT 24 Mar 17 01:47:26 PM PDT 24 1692990244 ps
T42 /workspace/coverage/default/1.rom_ctrl_sec_cm.3266632601 Mar 17 01:46:48 PM PDT 24 Mar 17 01:49:08 PM PDT 24 3933453406 ps
T604 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3182887304 Mar 17 01:47:21 PM PDT 24 Mar 17 01:48:14 PM PDT 24 5575234314 ps
T605 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.679397703 Mar 17 02:40:37 PM PDT 24 Mar 17 02:41:46 PM PDT 24 8794769500 ps
T606 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1655488741 Mar 17 02:40:36 PM PDT 24 Mar 17 02:41:04 PM PDT 24 12744379874 ps
T607 /workspace/coverage/default/31.rom_ctrl_smoke.4178099381 Mar 17 01:47:21 PM PDT 24 Mar 17 01:47:50 PM PDT 24 1048770653 ps
T608 /workspace/coverage/default/0.rom_ctrl_alert_test.1079938141 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:55 PM PDT 24 2743705767 ps
T609 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2996623626 Mar 17 02:41:03 PM PDT 24 Mar 17 02:41:36 PM PDT 24 1974291483 ps
T610 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2014590296 Mar 17 01:47:28 PM PDT 24 Mar 17 01:50:59 PM PDT 24 34432916380 ps
T611 /workspace/coverage/default/17.rom_ctrl_stress_all.1750950040 Mar 17 02:40:13 PM PDT 24 Mar 17 02:40:36 PM PDT 24 365466335 ps
T612 /workspace/coverage/default/36.rom_ctrl_alert_test.3723471030 Mar 17 02:40:37 PM PDT 24 Mar 17 02:41:00 PM PDT 24 2389641990 ps
T43 /workspace/coverage/default/4.rom_ctrl_sec_cm.3818856956 Mar 17 01:46:50 PM PDT 24 Mar 17 01:50:48 PM PDT 24 2013454252 ps
T613 /workspace/coverage/default/22.rom_ctrl_alert_test.2392461287 Mar 17 02:40:24 PM PDT 24 Mar 17 02:40:53 PM PDT 24 12487048537 ps
T614 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.572051961 Mar 17 02:40:18 PM PDT 24 Mar 17 02:40:39 PM PDT 24 3891553337 ps
T615 /workspace/coverage/default/34.rom_ctrl_alert_test.2582558424 Mar 17 01:47:32 PM PDT 24 Mar 17 01:48:02 PM PDT 24 7450968013 ps
T616 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2058010633 Mar 17 01:47:30 PM PDT 24 Mar 17 01:48:40 PM PDT 24 37219370622 ps
T617 /workspace/coverage/default/39.rom_ctrl_stress_all.2266408181 Mar 17 01:47:28 PM PDT 24 Mar 17 01:48:31 PM PDT 24 3050801498 ps
T618 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4134151038 Mar 17 02:40:23 PM PDT 24 Mar 17 02:41:07 PM PDT 24 8039790900 ps
T619 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1405723446 Mar 17 01:46:58 PM PDT 24 Mar 17 01:47:55 PM PDT 24 28458340461 ps
T44 /workspace/coverage/default/2.rom_ctrl_sec_cm.2326218915 Mar 17 01:46:55 PM PDT 24 Mar 17 01:49:12 PM PDT 24 3539554973 ps
T620 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.110458807 Mar 17 01:46:54 PM PDT 24 Mar 17 01:47:14 PM PDT 24 332648737 ps
T621 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1657294576 Mar 17 02:40:07 PM PDT 24 Mar 17 02:46:47 PM PDT 24 59668135687 ps
T622 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.14315246 Mar 17 02:40:54 PM PDT 24 Mar 17 02:41:54 PM PDT 24 13053941606 ps
T623 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.788393416 Mar 17 01:46:53 PM PDT 24 Mar 17 01:54:45 PM PDT 24 245913414205 ps
T624 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2394478456 Mar 17 02:40:18 PM PDT 24 Mar 17 02:40:37 PM PDT 24 332409581 ps
T625 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2346362498 Mar 17 02:39:58 PM PDT 24 Mar 17 02:45:29 PM PDT 24 4640807182 ps
T626 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.847000190 Mar 17 01:47:38 PM PDT 24 Mar 17 01:47:49 PM PDT 24 726879933 ps
T627 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3159674815 Mar 17 02:40:33 PM PDT 24 Mar 17 04:53:13 PM PDT 24 96091353511 ps
T628 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3599924538 Mar 17 01:47:18 PM PDT 24 Mar 17 01:47:28 PM PDT 24 186664507 ps
T629 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1702223320 Mar 17 01:47:17 PM PDT 24 Mar 17 01:48:00 PM PDT 24 15717344370 ps
T630 /workspace/coverage/default/5.rom_ctrl_smoke.768207890 Mar 17 02:39:59 PM PDT 24 Mar 17 02:40:52 PM PDT 24 17789814496 ps
T631 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3792165739 Mar 17 01:47:34 PM PDT 24 Mar 17 01:48:04 PM PDT 24 3295345949 ps
T632 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3777291389 Mar 17 02:40:54 PM PDT 24 Mar 17 02:42:03 PM PDT 24 45531564409 ps
T633 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2792153414 Mar 17 01:47:19 PM PDT 24 Mar 17 01:47:52 PM PDT 24 7941656746 ps
T634 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2300925265 Mar 17 01:47:30 PM PDT 24 Mar 17 01:47:59 PM PDT 24 1163949012 ps
T635 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2524954884 Mar 17 02:40:59 PM PDT 24 Mar 17 02:41:27 PM PDT 24 6342202273 ps
T636 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1379609986 Mar 17 02:40:08 PM PDT 24 Mar 17 02:46:31 PM PDT 24 86059445206 ps
T637 /workspace/coverage/default/6.rom_ctrl_smoke.645092798 Mar 17 02:39:58 PM PDT 24 Mar 17 02:40:48 PM PDT 24 5239443906 ps
T638 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2761339928 Mar 17 01:47:28 PM PDT 24 Mar 17 01:47:45 PM PDT 24 916688574 ps
T639 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4007486203 Mar 17 01:47:15 PM PDT 24 Mar 17 01:47:43 PM PDT 24 1384988158 ps
T640 /workspace/coverage/default/41.rom_ctrl_stress_all.3639066912 Mar 17 01:47:30 PM PDT 24 Mar 17 01:49:04 PM PDT 24 15969290073 ps
T641 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1288290708 Mar 17 02:40:17 PM PDT 24 Mar 17 02:40:45 PM PDT 24 1226913032 ps
T642 /workspace/coverage/default/28.rom_ctrl_smoke.1704570311 Mar 17 02:40:32 PM PDT 24 Mar 17 02:41:10 PM PDT 24 2789587898 ps
T16 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2962508816 Mar 17 01:47:14 PM PDT 24 Mar 17 02:05:43 PM PDT 24 30604594198 ps
T643 /workspace/coverage/default/1.rom_ctrl_alert_test.167413444 Mar 17 02:39:57 PM PDT 24 Mar 17 02:40:06 PM PDT 24 332494120 ps
T644 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3509622978 Mar 17 01:46:51 PM PDT 24 Mar 17 02:23:17 PM PDT 24 57276901717 ps
T645 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1909079435 Mar 17 01:47:14 PM PDT 24 Mar 17 01:47:40 PM PDT 24 3048433440 ps
T646 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.136842461 Mar 17 01:47:32 PM PDT 24 Mar 17 01:48:02 PM PDT 24 11810882251 ps
T647 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2059753241 Mar 17 02:40:59 PM PDT 24 Mar 17 02:53:27 PM PDT 24 65037664695 ps
T648 /workspace/coverage/default/25.rom_ctrl_alert_test.3450350802 Mar 17 01:47:23 PM PDT 24 Mar 17 01:47:41 PM PDT 24 1637669568 ps
T649 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4283440974 Mar 17 01:47:29 PM PDT 24 Mar 17 01:54:09 PM PDT 24 19889589366 ps
T650 /workspace/coverage/default/46.rom_ctrl_stress_all.1276246620 Mar 17 01:47:34 PM PDT 24 Mar 17 01:48:17 PM PDT 24 5701307683 ps
T651 /workspace/coverage/default/33.rom_ctrl_stress_all.160699749 Mar 17 02:40:32 PM PDT 24 Mar 17 02:42:10 PM PDT 24 35971522778 ps
T652 /workspace/coverage/default/11.rom_ctrl_alert_test.752119141 Mar 17 01:47:06 PM PDT 24 Mar 17 01:47:21 PM PDT 24 935525053 ps
T653 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1349888078 Mar 17 01:47:15 PM PDT 24 Mar 17 01:47:38 PM PDT 24 2148829183 ps
T654 /workspace/coverage/default/2.rom_ctrl_smoke.3107157045 Mar 17 02:39:56 PM PDT 24 Mar 17 02:40:40 PM PDT 24 18688323421 ps
T655 /workspace/coverage/default/6.rom_ctrl_alert_test.2179242920 Mar 17 02:40:00 PM PDT 24 Mar 17 02:40:31 PM PDT 24 3533681720 ps
T656 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3252773287 Mar 17 01:47:13 PM PDT 24 Mar 17 01:53:18 PM PDT 24 139399471610 ps
T657 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.799580919 Mar 17 02:40:35 PM PDT 24 Mar 17 02:40:46 PM PDT 24 190106931 ps
T658 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2188752312 Mar 17 02:40:13 PM PDT 24 Mar 17 02:41:20 PM PDT 24 11904884167 ps
T659 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4042563328 Mar 17 02:41:00 PM PDT 24 Mar 17 02:41:26 PM PDT 24 2504792862 ps
T660 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1708427863 Mar 17 01:47:19 PM PDT 24 Mar 17 01:47:30 PM PDT 24 246780670 ps
T661 /workspace/coverage/default/46.rom_ctrl_alert_test.3705327814 Mar 17 02:40:59 PM PDT 24 Mar 17 02:41:07 PM PDT 24 717952575 ps
T662 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4266855072 Mar 17 01:46:53 PM PDT 24 Mar 17 01:53:13 PM PDT 24 31519342857 ps
T663 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3039359797 Mar 17 01:47:35 PM PDT 24 Mar 17 01:48:23 PM PDT 24 5054064307 ps
T664 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2418278898 Mar 17 02:40:15 PM PDT 24 Mar 17 02:41:21 PM PDT 24 10563346456 ps
T665 /workspace/coverage/default/5.rom_ctrl_alert_test.775818977 Mar 17 02:40:01 PM PDT 24 Mar 17 02:40:32 PM PDT 24 3614061759 ps
T666 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4041435223 Mar 17 01:47:16 PM PDT 24 Mar 17 01:47:43 PM PDT 24 4412523133 ps
T667 /workspace/coverage/default/44.rom_ctrl_stress_all.4046104506 Mar 17 02:40:53 PM PDT 24 Mar 17 02:42:31 PM PDT 24 7553494813 ps
T668 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3112807713 Mar 17 01:47:17 PM PDT 24 Mar 17 01:48:25 PM PDT 24 35518952293 ps
T669 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.570167422 Mar 17 01:47:11 PM PDT 24 Mar 17 01:47:22 PM PDT 24 177978009 ps
T670 /workspace/coverage/default/48.rom_ctrl_alert_test.3736121834 Mar 17 01:47:39 PM PDT 24 Mar 17 01:48:09 PM PDT 24 7237690078 ps
T671 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3576114620 Mar 17 02:40:03 PM PDT 24 Mar 17 02:40:57 PM PDT 24 23838821606 ps
T672 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1790576930 Mar 17 01:47:32 PM PDT 24 Mar 17 01:53:17 PM PDT 24 98403124918 ps
T673 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.215095118 Mar 17 01:46:57 PM PDT 24 Mar 17 01:47:37 PM PDT 24 8801313786 ps
T674 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.599967493 Mar 17 02:40:35 PM PDT 24 Mar 17 02:40:46 PM PDT 24 186890795 ps
T675 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1098129694 Mar 17 02:40:40 PM PDT 24 Mar 17 02:46:00 PM PDT 24 4246703256 ps
T676 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3945861087 Mar 17 01:47:28 PM PDT 24 Mar 17 01:52:33 PM PDT 24 28887536259 ps
T677 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1954449238 Mar 17 02:40:56 PM PDT 24 Mar 17 02:52:04 PM PDT 24 87190933358 ps
T678 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1526205881 Mar 17 01:47:01 PM PDT 24 Mar 17 01:47:51 PM PDT 24 24989264950 ps
T114 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1190729426 Mar 17 02:40:40 PM PDT 24 Mar 17 02:50:33 PM PDT 24 15009515353 ps
T679 /workspace/coverage/default/4.rom_ctrl_stress_all.148420439 Mar 17 01:46:47 PM PDT 24 Mar 17 01:47:57 PM PDT 24 26776885631 ps
T680 /workspace/coverage/default/40.rom_ctrl_stress_all.1630590013 Mar 17 02:40:36 PM PDT 24 Mar 17 02:40:52 PM PDT 24 2450244053 ps
T681 /workspace/coverage/default/32.rom_ctrl_stress_all.530333708 Mar 17 01:47:28 PM PDT 24 Mar 17 01:48:13 PM PDT 24 2593763428 ps
T682 /workspace/coverage/default/36.rom_ctrl_smoke.1035671148 Mar 17 01:47:30 PM PDT 24 Mar 17 01:48:50 PM PDT 24 8504648188 ps
T683 /workspace/coverage/default/24.rom_ctrl_alert_test.2060880820 Mar 17 01:47:21 PM PDT 24 Mar 17 01:47:38 PM PDT 24 3686870361 ps
T684 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1771140815 Mar 17 02:40:03 PM PDT 24 Mar 17 02:40:23 PM PDT 24 1646347860 ps
T53 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2782732819 Mar 17 01:46:41 PM PDT 24 Mar 17 01:47:28 PM PDT 24 6919680007 ps
T685 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.36666148 Mar 17 01:46:34 PM PDT 24 Mar 17 01:46:41 PM PDT 24 309306100 ps
T56 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4030918074 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:56 PM PDT 24 2989862014 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1622733056 Mar 17 01:46:33 PM PDT 24 Mar 17 01:46:52 PM PDT 24 1799312988 ps
T686 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.296957029 Mar 17 01:46:34 PM PDT 24 Mar 17 01:46:39 PM PDT 24 101758441 ps
T68 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2446679506 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:56 PM PDT 24 1805851537 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3237202044 Mar 17 01:46:19 PM PDT 24 Mar 17 01:47:22 PM PDT 24 41020685080 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.251339904 Mar 17 03:03:29 PM PDT 24 Mar 17 03:04:44 PM PDT 24 12506275856 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.840915454 Mar 17 03:03:52 PM PDT 24 Mar 17 03:04:09 PM PDT 24 6386845087 ps
T687 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.740541076 Mar 17 03:03:47 PM PDT 24 Mar 17 03:03:58 PM PDT 24 261608397 ps
T688 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1628681182 Mar 17 03:03:38 PM PDT 24 Mar 17 03:04:02 PM PDT 24 10244941848 ps
T689 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3356067977 Mar 17 01:46:32 PM PDT 24 Mar 17 01:46:36 PM PDT 24 85573550 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2782523141 Mar 17 03:03:28 PM PDT 24 Mar 17 03:03:59 PM PDT 24 15583750517 ps
T690 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1227717046 Mar 17 01:46:18 PM PDT 24 Mar 17 01:46:30 PM PDT 24 1312643216 ps
T54 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2873706860 Mar 17 01:46:34 PM PDT 24 Mar 17 01:47:20 PM PDT 24 1797195103 ps
T691 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2681308974 Mar 17 01:46:33 PM PDT 24 Mar 17 01:46:50 PM PDT 24 8017980038 ps
T692 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.848105283 Mar 17 03:03:27 PM PDT 24 Mar 17 03:03:48 PM PDT 24 1669618225 ps
T693 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.803506873 Mar 17 01:46:34 PM PDT 24 Mar 17 01:46:53 PM PDT 24 3881144355 ps
T71 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4160690343 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:55 PM PDT 24 2171618131 ps
T694 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3718370813 Mar 17 03:03:39 PM PDT 24 Mar 17 03:03:57 PM PDT 24 1540942993 ps
T72 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4204484479 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:52 PM PDT 24 1836303386 ps
T73 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3365695975 Mar 17 01:46:18 PM PDT 24 Mar 17 01:47:52 PM PDT 24 22155906339 ps
T695 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3726857235 Mar 17 03:03:46 PM PDT 24 Mar 17 03:04:03 PM PDT 24 5832290993 ps
T696 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1924001721 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:55 PM PDT 24 5854361768 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3617827774 Mar 17 01:46:53 PM PDT 24 Mar 17 01:46:59 PM PDT 24 178466195 ps
T109 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3523468814 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:52 PM PDT 24 2727073297 ps
T105 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3119699993 Mar 17 03:03:46 PM PDT 24 Mar 17 03:04:13 PM PDT 24 2518282830 ps
T697 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1336384152 Mar 17 03:03:41 PM PDT 24 Mar 17 03:04:09 PM PDT 24 3588036172 ps
T698 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3102946291 Mar 17 03:03:27 PM PDT 24 Mar 17 03:03:35 PM PDT 24 689399433 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.913866995 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:48 PM PDT 24 1075906666 ps
T699 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.189393696 Mar 17 01:46:27 PM PDT 24 Mar 17 01:46:35 PM PDT 24 643523935 ps
T55 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3005206521 Mar 17 03:03:29 PM PDT 24 Mar 17 03:06:20 PM PDT 24 17566049856 ps
T107 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.169562638 Mar 17 03:03:46 PM PDT 24 Mar 17 03:04:06 PM PDT 24 4645904799 ps
T108 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2425103095 Mar 17 03:03:51 PM PDT 24 Mar 17 03:04:04 PM PDT 24 614753403 ps
T700 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2238015129 Mar 17 01:46:31 PM PDT 24 Mar 17 01:46:44 PM PDT 24 2849892775 ps
T701 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1792085894 Mar 17 01:46:27 PM PDT 24 Mar 17 01:46:39 PM PDT 24 1222679684 ps
T702 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.884224578 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:38 PM PDT 24 170994248 ps
T703 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3891974375 Mar 17 01:46:33 PM PDT 24 Mar 17 01:46:37 PM PDT 24 554923210 ps
T704 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.999308683 Mar 17 01:46:42 PM PDT 24 Mar 17 01:46:52 PM PDT 24 175141029 ps
T74 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1252474765 Mar 17 01:46:36 PM PDT 24 Mar 17 01:47:57 PM PDT 24 37155503080 ps
T705 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3029946167 Mar 17 01:46:44 PM PDT 24 Mar 17 01:47:01 PM PDT 24 2701299076 ps
T706 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3901225978 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:50 PM PDT 24 2959552788 ps
T75 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3945501248 Mar 17 01:46:40 PM PDT 24 Mar 17 01:47:49 PM PDT 24 33891675839 ps
T707 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1104404679 Mar 17 03:03:54 PM PDT 24 Mar 17 03:04:26 PM PDT 24 8226434318 ps
T120 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.304156524 Mar 17 03:03:38 PM PDT 24 Mar 17 03:06:25 PM PDT 24 2791247500 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3954970487 Mar 17 03:03:37 PM PDT 24 Mar 17 03:04:18 PM PDT 24 60692569687 ps
T708 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.515300759 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:38 PM PDT 24 717470895 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1411356242 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:39 PM PDT 24 331789479 ps
T84 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1127079260 Mar 17 03:03:40 PM PDT 24 Mar 17 03:03:48 PM PDT 24 661746104 ps
T709 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.430842432 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:56 PM PDT 24 1930258233 ps
T115 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1646681431 Mar 17 03:03:44 PM PDT 24 Mar 17 03:06:25 PM PDT 24 2065704616 ps
T710 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1991820061 Mar 17 03:03:46 PM PDT 24 Mar 17 03:04:36 PM PDT 24 27842836129 ps
T711 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4232572056 Mar 17 03:03:44 PM PDT 24 Mar 17 03:04:05 PM PDT 24 11803409125 ps
T712 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2433034621 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:47 PM PDT 24 369978697 ps
T713 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3692533954 Mar 17 01:46:21 PM PDT 24 Mar 17 01:46:33 PM PDT 24 1153128459 ps
T714 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.84816771 Mar 17 03:03:27 PM PDT 24 Mar 17 03:03:54 PM PDT 24 6817079954 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4106010723 Mar 17 03:03:47 PM PDT 24 Mar 17 03:04:24 PM PDT 24 3436258568 ps
T715 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2527803337 Mar 17 01:46:45 PM PDT 24 Mar 17 01:47:49 PM PDT 24 34420166225 ps
T716 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2028533123 Mar 17 03:03:40 PM PDT 24 Mar 17 03:03:52 PM PDT 24 171036082 ps
T717 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.352364076 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:48 PM PDT 24 87946076 ps
T718 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.177590283 Mar 17 01:46:51 PM PDT 24 Mar 17 01:47:53 PM PDT 24 7548224744 ps
T719 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1199609549 Mar 17 03:03:43 PM PDT 24 Mar 17 03:04:19 PM PDT 24 22427653060 ps
T720 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3676003637 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:49 PM PDT 24 3001148684 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3990139412 Mar 17 01:46:21 PM PDT 24 Mar 17 01:46:41 PM PDT 24 7035543694 ps
T721 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1022645797 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:47 PM PDT 24 1080129563 ps
T722 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2058178771 Mar 17 03:03:36 PM PDT 24 Mar 17 03:05:56 PM PDT 24 27659347545 ps
T723 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4238042482 Mar 17 01:46:22 PM PDT 24 Mar 17 01:47:12 PM PDT 24 8555488005 ps
T724 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.860348567 Mar 17 03:03:51 PM PDT 24 Mar 17 03:04:20 PM PDT 24 56266806478 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1227229255 Mar 17 01:46:20 PM PDT 24 Mar 17 01:46:48 PM PDT 24 1396711629 ps
T725 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3067863103 Mar 17 03:03:36 PM PDT 24 Mar 17 03:04:08 PM PDT 24 4221422092 ps
T726 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1924118542 Mar 17 03:03:44 PM PDT 24 Mar 17 03:03:57 PM PDT 24 636848275 ps
T727 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.504528445 Mar 17 03:03:38 PM PDT 24 Mar 17 03:04:00 PM PDT 24 8983528961 ps
T728 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2998312366 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:53 PM PDT 24 2305408745 ps
T729 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1400939795 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:55 PM PDT 24 1880926693 ps
T121 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1673240878 Mar 17 01:46:36 PM PDT 24 Mar 17 01:47:54 PM PDT 24 1959889808 ps
T730 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2183060286 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:38 PM PDT 24 338441755 ps
T731 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2787362718 Mar 17 03:03:36 PM PDT 24 Mar 17 03:03:57 PM PDT 24 2140859762 ps
T116 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.635580028 Mar 17 01:46:29 PM PDT 24 Mar 17 01:47:40 PM PDT 24 4212879812 ps
T732 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2330894339 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:45 PM PDT 24 1571505189 ps
T733 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.31994833 Mar 17 01:46:32 PM PDT 24 Mar 17 01:46:49 PM PDT 24 1596833156 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.60773468 Mar 17 03:03:52 PM PDT 24 Mar 17 03:06:34 PM PDT 24 1346456217 ps
T734 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.987308985 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:45 PM PDT 24 346245688 ps
T118 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3392309052 Mar 17 01:46:37 PM PDT 24 Mar 17 01:47:14 PM PDT 24 170922661 ps
T735 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1522455794 Mar 17 01:46:38 PM PDT 24 Mar 17 01:47:42 PM PDT 24 23791923531 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.91332107 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:55 PM PDT 24 1241936550 ps
T736 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.8174707 Mar 17 03:03:57 PM PDT 24 Mar 17 03:04:07 PM PDT 24 688215243 ps
T737 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.89601485 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:53 PM PDT 24 332660235 ps
T119 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1014787117 Mar 17 01:46:35 PM PDT 24 Mar 17 01:47:53 PM PDT 24 2051911767 ps
T738 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3628052986 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:55 PM PDT 24 1706382395 ps
T739 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1433767236 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:50 PM PDT 24 10787186558 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.141594743 Mar 17 03:03:51 PM PDT 24 Mar 17 03:04:50 PM PDT 24 5973189610 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2054813018 Mar 17 03:03:34 PM PDT 24 Mar 17 03:03:56 PM PDT 24 21912329501 ps
T740 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3523353911 Mar 17 01:46:28 PM PDT 24 Mar 17 01:46:33 PM PDT 24 136571460 ps
T741 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.462132336 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:54 PM PDT 24 6572876419 ps
T742 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4123902100 Mar 17 03:03:28 PM PDT 24 Mar 17 03:03:43 PM PDT 24 954479758 ps
T743 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3148273661 Mar 17 03:03:29 PM PDT 24 Mar 17 03:04:01 PM PDT 24 13517330388 ps
T744 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.963652610 Mar 17 03:03:50 PM PDT 24 Mar 17 03:04:21 PM PDT 24 16323978051 ps
T745 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3214194719 Mar 17 01:46:41 PM PDT 24 Mar 17 01:48:02 PM PDT 24 7473553057 ps
T746 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3394145132 Mar 17 03:03:47 PM PDT 24 Mar 17 03:03:58 PM PDT 24 1964450619 ps
T747 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3392095923 Mar 17 01:46:57 PM PDT 24 Mar 17 01:47:02 PM PDT 24 430642075 ps
T748 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.9605631 Mar 17 03:03:30 PM PDT 24 Mar 17 03:05:49 PM PDT 24 53308190828 ps
T749 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3716736546 Mar 17 01:46:39 PM PDT 24 Mar 17 01:47:00 PM PDT 24 19611413337 ps
T750 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1805097211 Mar 17 01:46:30 PM PDT 24 Mar 17 01:46:43 PM PDT 24 1610316093 ps
T751 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4017938206 Mar 17 03:03:40 PM PDT 24 Mar 17 03:05:16 PM PDT 24 5501283925 ps
T752 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1504431880 Mar 17 03:03:52 PM PDT 24 Mar 17 03:04:17 PM PDT 24 11360670054 ps
T753 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3608036920 Mar 17 03:03:40 PM PDT 24 Mar 17 03:03:49 PM PDT 24 660564228 ps
T754 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3923967088 Mar 17 03:03:51 PM PDT 24 Mar 17 03:04:26 PM PDT 24 8211396385 ps
T755 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2852518682 Mar 17 03:03:29 PM PDT 24 Mar 17 03:04:07 PM PDT 24 34427708171 ps
T90 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3634736167 Mar 17 01:46:46 PM PDT 24 Mar 17 01:47:53 PM PDT 24 27891444262 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3022656132 Mar 17 03:03:31 PM PDT 24 Mar 17 03:06:39 PM PDT 24 83242763151 ps
T756 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3094005006 Mar 17 03:03:37 PM PDT 24 Mar 17 03:04:01 PM PDT 24 2747548374 ps
T122 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1510247427 Mar 17 01:46:44 PM PDT 24 Mar 17 01:48:05 PM PDT 24 2180359667 ps
T757 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2534699816 Mar 17 03:03:46 PM PDT 24 Mar 17 03:04:06 PM PDT 24 2053712159 ps
T758 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3367239095 Mar 17 03:03:35 PM PDT 24 Mar 17 03:05:08 PM PDT 24 2048349621 ps
T759 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1809070316 Mar 17 01:46:32 PM PDT 24 Mar 17 01:46:38 PM PDT 24 369708879 ps
T760 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1159129953 Mar 17 03:03:42 PM PDT 24 Mar 17 03:03:54 PM PDT 24 499795863 ps
T761 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3843506222 Mar 17 01:46:44 PM PDT 24 Mar 17 01:47:02 PM PDT 24 1993027740 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2786547416 Mar 17 03:03:40 PM PDT 24 Mar 17 03:05:46 PM PDT 24 12734287670 ps
T762 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1718473088 Mar 17 03:03:52 PM PDT 24 Mar 17 03:04:12 PM PDT 24 905397940 ps
T100 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2048813737 Mar 17 03:03:50 PM PDT 24 Mar 17 03:05:18 PM PDT 24 8515513865 ps
T763 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1103312910 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:50 PM PDT 24 1524959585 ps
T764 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4130559946 Mar 17 03:03:39 PM PDT 24 Mar 17 03:04:19 PM PDT 24 16538628914 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%