Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3042717

1

T2

97392

T3

59

T6

40

full_word

1959901

1

T1

2

T2

63369

T3

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5001978	1			T1	2		T2	160761		T3	70
auto[TlIntgErrCmd]	199	1			T53	4		T54	2		T55	4
auto[TlIntgErrData]	229	1			T53	4		T54	6		T55	7
auto[TlIntgErrBoth]	212	1			T53	2		T54	2		T55	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

818304

1

T1

2

T2

25519

T3

70

auto[1]

4184314

1

T2

135242

T12

196559

T13

105886

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	352772	1			T2	10630		T3	59		T6	40
auto[TlIntgErrNone]	partial	auto[1]	2689349	1			T2	86762		T12	125210		T13	69028
auto[TlIntgErrNone]	full_word	auto[0]	465233	1			T1	2		T2	14889		T3	11
auto[TlIntgErrNone]	full_word	auto[1]	1494624	1			T2	48480		T12	71349		T13	36858
auto[TlIntgErrCmd]	partial	auto[0]	76	1			T55	2		T120	3		T115	1
auto[TlIntgErrCmd]	partial	auto[1]	109	1			T53	4		T54	1		T55	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T122	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	13	1			T54	1		T120	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	112	1			T53	2		T54	5		T55	4
auto[TlIntgErrData]	partial	auto[1]	105	1			T53	2		T54	1		T55	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T121	1		T116	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T126	1		T127	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	91	1			T53	1		T54	1		T55	3
auto[TlIntgErrBoth]	partial	auto[1]	103	1			T53	1		T54	1		T55	6
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T119	1		T126	2		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T115	1		T128	2		T129	1