Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 100.00 33.33 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 100.00 33.33 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_prim_count_addr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.07 100.00 95.35 100.00 100.00 100.00 u_compare


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
90.00 90.00
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_prim_count_addr

TotalCoveredPercent
Totals 6 5 83.33
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 6 5 83.33
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
90.00 90.00
tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
90.00 90.00
tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 8 7 87.50
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

Toggle Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_prim_count_addr
TotalCoveredPercent
Totals 6 5 83.33
Total Bits 20 18 90.00
Total Bits 0->1 10 9 90.00
Total Bits 1->0 10 9 90.00

Ports 6 5 83.33
Port Bits 20 18 90.00
Port Bits 0->1 10 9 90.00
Port Bits 1->0 10 9 90.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[2:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[2:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o No No No OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%