Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120789	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2611618

1

T1

7

T4

4

T5

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	726473	1			T1	42		T4	61		T5	15
values[0x0]	984173	1			T11	41152		T12	10046		T13	47900
values[0x1]	1021761	1			T11	42566		T12	10214		T13	49918

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2670779

1

T1

28

T4

38

T5

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11722	1			T5	1		T11	424		T12	145
valid_sources[0x01]	9858	1			T11	441		T12	114		T20	3
valid_sources[0x02]	10647	1			T11	435		T12	100		T79	2
valid_sources[0x03]	10467	1			T4	1		T11	454		T12	142
valid_sources[0x04]	11656	1			T11	454		T12	120		T69	9
valid_sources[0x05]	12820	1			T11	411		T12	106		T20	1
valid_sources[0x06]	10028	1			T5	1		T11	435		T12	128
valid_sources[0x07]	10583	1			T5	1		T10	2		T11	477
valid_sources[0x08]	10708	1			T11	413		T12	170		T79	1
valid_sources[0x09]	10398	1			T11	434		T12	87		T113	2
valid_sources[0x0a]	11407	1			T11	438		T12	94		T79	1
valid_sources[0x0b]	10753	1			T10	7		T11	482		T12	116
valid_sources[0x0c]	11068	1			T1	2		T11	452		T12	114
valid_sources[0x0d]	11868	1			T11	438		T12	98		T79	1
valid_sources[0x0e]	9960	1			T4	2		T11	423		T12	107
valid_sources[0x0f]	10686	1			T11	446		T12	140		T117	2
valid_sources[0x10]	10236	1			T11	441		T12	103		T113	2
valid_sources[0x11]	11426	1			T11	447		T12	125		T117	1
valid_sources[0x12]	9851	1			T11	457		T12	135		T79	1
valid_sources[0x13]	10195	1			T11	415		T12	86		T19	4
valid_sources[0x14]	11264	1			T1	1		T11	476		T12	78
valid_sources[0x15]	11563	1			T11	407		T12	112		T113	1
valid_sources[0x16]	10747	1			T1	1		T11	444		T12	102
valid_sources[0x17]	10467	1			T11	419		T12	134		T20	1
valid_sources[0x18]	9926	1			T11	431		T12	114		T69	1
valid_sources[0x19]	10881	1			T11	421		T12	106		T79	2
valid_sources[0x1a]	10315	1			T1	1		T11	428		T12	126
valid_sources[0x1b]	11639	1			T10	7		T17	1		T11	432
valid_sources[0x1c]	12733	1			T11	467		T12	63		T79	1
valid_sources[0x1d]	10595	1			T11	394		T12	103		T80	2
valid_sources[0x1e]	12212	1			T5	1		T11	455		T12	124
valid_sources[0x1f]	11097	1			T11	420		T12	163		T19	7
valid_sources[0x20]	10949	1			T11	416		T12	102		T20	2
valid_sources[0x21]	11616	1			T11	389		T12	139		T19	4
valid_sources[0x22]	10362	1			T11	410		T12	97		T79	3
valid_sources[0x23]	11126	1			T4	1		T11	436		T12	103
valid_sources[0x24]	11193	1			T4	1		T10	8		T11	424
valid_sources[0x25]	9728	1			T1	1		T4	3		T10	5
valid_sources[0x26]	10075	1			T4	2		T11	445		T12	130
valid_sources[0x27]	9956	1			T11	462		T12	86		T113	3
valid_sources[0x28]	10366	1			T11	434		T12	106		T114	3
valid_sources[0x29]	11279	1			T11	460		T12	80		T113	4
valid_sources[0x2a]	9257	1			T1	1		T11	452		T12	110
valid_sources[0x2b]	11427	1			T4	2		T11	414		T12	82
valid_sources[0x2c]	9285	1			T4	1		T10	8		T11	456
valid_sources[0x2d]	10867	1			T11	443		T12	144		T113	1
valid_sources[0x2e]	9738	1			T10	4		T11	451		T12	94
valid_sources[0x2f]	12191	1			T10	1		T11	435		T12	89
valid_sources[0x30]	11063	1			T11	422		T12	120		T43	1
valid_sources[0x31]	9006	1			T11	481		T12	76		T134	1
valid_sources[0x32]	9331	1			T11	444		T12	129		T134	1
valid_sources[0x33]	8875	1			T11	428		T12	96		T57	3
valid_sources[0x34]	11800	1			T11	431		T12	160		T43	1
valid_sources[0x35]	10154	1			T5	2		T11	416		T12	85
valid_sources[0x36]	11697	1			T4	1		T11	453		T12	162
valid_sources[0x37]	9169	1			T11	430		T12	87		T80	1
valid_sources[0x38]	9769	1			T1	1		T11	426		T12	104
valid_sources[0x39]	9349	1			T1	1		T4	1		T11	441
valid_sources[0x3a]	9896	1			T11	460		T12	156		T116	4
valid_sources[0x3b]	8963	1			T11	424		T12	82		T79	2
valid_sources[0x3c]	9436	1			T4	1		T11	427		T12	135
valid_sources[0x3d]	9660	1			T4	1		T11	432		T12	83
valid_sources[0x3e]	11127	1			T11	438		T12	106		T57	11
valid_sources[0x3f]	11052	1			T11	417		T12	100		T113	3
valid_sources[0x40]	11679	1			T11	468		T12	124		T79	1
valid_sources[0x41]	10891	1			T5	2		T11	466		T12	117
valid_sources[0x42]	11159	1			T1	1		T4	1		T11	421
valid_sources[0x43]	8997	1			T17	1		T11	466		T12	152
valid_sources[0x44]	9574	1			T11	406		T12	101		T79	1
valid_sources[0x45]	10845	1			T11	443		T12	81		T113	1
valid_sources[0x46]	10583	1			T4	2		T11	409		T12	118
valid_sources[0x47]	10977	1			T4	1		T11	428		T12	111
valid_sources[0x48]	10119	1			T11	449		T12	168		T79	1
valid_sources[0x49]	11085	1			T11	412		T12	82		T113	2
valid_sources[0x4a]	10185	1			T10	2		T11	435		T12	82
valid_sources[0x4b]	10273	1			T4	1		T11	416		T12	123
valid_sources[0x4c]	12147	1			T11	443		T12	87		T19	9
valid_sources[0x4d]	9687	1			T1	1		T11	457		T12	93
valid_sources[0x4e]	10374	1			T11	414		T12	94		T69	4
valid_sources[0x4f]	10469	1			T11	430		T12	116		T79	3
valid_sources[0x50]	12290	1			T11	466		T12	91		T113	2
valid_sources[0x51]	12671	1			T11	411		T12	83		T69	1
valid_sources[0x52]	13071	1			T4	1		T10	1		T11	501
valid_sources[0x53]	8436	1			T11	449		T12	95		T113	1
valid_sources[0x54]	12948	1			T11	453		T12	103		T113	1
valid_sources[0x55]	10631	1			T10	5		T11	424		T12	160
valid_sources[0x56]	10385	1			T4	2		T11	430		T12	75
valid_sources[0x57]	9366	1			T1	1		T11	445		T12	142
valid_sources[0x58]	10890	1			T11	434		T12	105		T69	3
valid_sources[0x59]	13657	1			T1	1		T11	455		T12	91
valid_sources[0x5a]	12092	1			T4	1		T11	427		T12	93
valid_sources[0x5b]	10288	1			T10	4		T11	409		T12	94
valid_sources[0x5c]	11046	1			T11	455		T12	96		T79	2
valid_sources[0x5d]	11220	1			T11	437		T12	91		T40	6
valid_sources[0x5e]	10967	1			T1	2		T11	444		T12	96
valid_sources[0x5f]	12428	1			T11	425		T12	110		T113	1
valid_sources[0x60]	10551	1			T11	410		T12	156		T79	1
valid_sources[0x61]	10596	1			T11	436		T12	101		T113	3
valid_sources[0x62]	9941	1			T10	2		T11	449		T12	163
valid_sources[0x63]	10555	1			T4	1		T11	437		T12	108
valid_sources[0x64]	10335	1			T11	487		T12	94		T79	1
valid_sources[0x65]	11346	1			T4	1		T11	467		T12	100
valid_sources[0x66]	12288	1			T11	422		T12	114		T79	1
valid_sources[0x67]	9632	1			T4	1		T11	447		T12	91
valid_sources[0x68]	12402	1			T11	395		T12	133		T79	1
valid_sources[0x69]	14771	1			T11	446		T12	117		T79	1
valid_sources[0x6a]	9145	1			T1	2		T11	441		T12	135
valid_sources[0x6b]	10766	1			T11	436		T12	143		T79	4
valid_sources[0x6c]	12966	1			T11	430		T12	78		T79	1
valid_sources[0x6d]	10233	1			T4	2		T11	448		T12	87
valid_sources[0x6e]	9811	1			T11	423		T12	81		T79	2
valid_sources[0x6f]	9525	1			T11	453		T12	115		T113	2
valid_sources[0x70]	10899	1			T11	444		T12	87		T134	2
valid_sources[0x71]	11200	1			T11	468		T12	98		T79	1
valid_sources[0x72]	10453	1			T11	435		T12	107		T19	16
valid_sources[0x73]	9432	1			T1	1		T11	439		T12	105
valid_sources[0x74]	10009	1			T11	396		T12	132		T79	2
valid_sources[0x75]	9564	1			T11	445		T12	121		T79	1
valid_sources[0x76]	10893	1			T11	459		T12	74		T113	1
valid_sources[0x77]	11107	1			T10	1		T11	416		T12	94
valid_sources[0x78]	9004	1			T4	1		T11	421		T12	88
valid_sources[0x79]	10227	1			T11	451		T12	107		T117	1
valid_sources[0x7a]	12213	1			T11	392		T12	109		T80	3
valid_sources[0x7b]	10001	1			T11	438		T12	90		T69	8
valid_sources[0x7c]	10421	1			T11	418		T12	121		T20	1
valid_sources[0x7d]	10576	1			T11	452		T12	165		T79	1
valid_sources[0x7e]	9111	1			T10	9		T11	448		T12	104
valid_sources[0x7f]	10132	1			T10	13		T11	415		T12	111
valid_sources[0x80]	10046	1			T10	23		T11	480		T12	113

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

658545

1

T1

7

T4

4

T5

15

values[0x0]

all_enables

biggest_size

975535

1

T11

40829

T12

9976

T13

47483

values[0x1]

all_enables

biggest_size

977538

1

T11

40577

T12

9828

T13

47801

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	194372	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1971522

1

T1

18

T2

2

T4

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	545604	1			T1	32		T3	1		T4	32
values[0x0]	751196	1			T2	7		T6	3		T11	31773
values[0x1]	869094	1			T2	4		T6	4		T11	36895

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88739	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2077155

1

T1

22

T2

3

T4

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7477	1			T11	341		T12	82		T66	1
valid_sources[0x01]	7864	1			T11	376		T12	87		T84	1
valid_sources[0x02]	9269	1			T11	338		T12	81		T135	1
valid_sources[0x03]	8837	1			T11	411		T12	93		T135	1
valid_sources[0x04]	7938	1			T11	351		T12	89		T27	1
valid_sources[0x05]	9070	1			T11	388		T12	89		T44	32
valid_sources[0x06]	8982	1			T6	1		T11	336		T12	81
valid_sources[0x07]	7236	1			T11	310		T12	86		T64	1
valid_sources[0x08]	8117	1			T11	303		T12	95		T66	1
valid_sources[0x09]	8780	1			T7	3		T11	367		T12	84
valid_sources[0x0a]	7728	1			T11	348		T12	88		T69	2
valid_sources[0x0b]	9337	1			T10	3		T11	372		T12	92
valid_sources[0x0c]	8283	1			T11	412		T12	84		T19	1
valid_sources[0x0d]	8803	1			T11	292		T12	82		T80	1
valid_sources[0x0e]	8350	1			T11	366		T12	78		T136	1
valid_sources[0x0f]	8290	1			T1	32		T11	426		T18	4
valid_sources[0x10]	8794	1			T11	350		T12	89		T20	1
valid_sources[0x11]	7236	1			T4	2		T11	376		T12	96
valid_sources[0x12]	9115	1			T17	5		T11	343		T12	81
valid_sources[0x13]	8157	1			T17	1		T11	404		T12	105
valid_sources[0x14]	9384	1			T11	373		T12	95		T19	1
valid_sources[0x15]	8014	1			T6	1		T7	2		T11	366
valid_sources[0x16]	7853	1			T7	1		T11	429		T12	104
valid_sources[0x17]	10962	1			T11	337		T12	89		T57	1
valid_sources[0x18]	7817	1			T4	1		T11	384		T12	95
valid_sources[0x19]	9456	1			T11	341		T12	76		T80	1
valid_sources[0x1a]	9129	1			T17	1		T11	430		T12	80
valid_sources[0x1b]	8145	1			T10	1		T11	348		T12	75
valid_sources[0x1c]	7514	1			T4	1		T5	1		T11	374
valid_sources[0x1d]	8397	1			T11	366		T12	95		T13	624
valid_sources[0x1e]	7856	1			T11	355		T12	93		T137	1
valid_sources[0x1f]	7851	1			T11	359		T12	96		T138	1
valid_sources[0x20]	8587	1			T11	393		T12	86		T85	1
valid_sources[0x21]	8416	1			T11	378		T12	82		T65	1
valid_sources[0x22]	8031	1			T11	353		T12	98		T13	276
valid_sources[0x23]	7590	1			T11	350		T12	88		T69	1
valid_sources[0x24]	8623	1			T11	332		T12	90		T57	1
valid_sources[0x25]	9803	1			T11	364		T12	77		T80	1
valid_sources[0x26]	7836	1			T11	369		T12	86		T19	1
valid_sources[0x27]	9687	1			T7	1		T11	338		T12	91
valid_sources[0x28]	8208	1			T11	383		T12	97		T69	2
valid_sources[0x29]	8481	1			T11	338		T12	96		T32	1
valid_sources[0x2a]	9646	1			T2	2		T11	379		T12	80
valid_sources[0x2b]	8478	1			T11	360		T12	93		T57	1
valid_sources[0x2c]	9335	1			T11	296		T12	81		T80	2
valid_sources[0x2d]	7972	1			T11	322		T12	86		T80	1
valid_sources[0x2e]	9424	1			T11	331		T12	83		T19	1
valid_sources[0x2f]	8738	1			T11	310		T12	92		T57	2
valid_sources[0x30]	7569	1			T11	296		T12	93		T114	7
valid_sources[0x31]	7939	1			T11	374		T12	103		T139	1
valid_sources[0x32]	8129	1			T11	410		T12	96		T82	1
valid_sources[0x33]	7451	1			T10	9		T11	360		T12	90
valid_sources[0x34]	7415	1			T11	332		T12	84		T82	1
valid_sources[0x35]	8279	1			T11	327		T12	95		T20	1
valid_sources[0x36]	8276	1			T11	346		T12	89		T81	2
valid_sources[0x37]	8869	1			T11	367		T12	84		T19	1
valid_sources[0x38]	8031	1			T11	309		T12	86		T57	1
valid_sources[0x39]	7642	1			T10	3		T11	264		T12	92
valid_sources[0x3a]	9094	1			T11	336		T12	111		T40	1
valid_sources[0x3b]	8293	1			T10	2		T11	413		T12	89
valid_sources[0x3c]	8334	1			T5	1		T11	385		T18	2
valid_sources[0x3d]	7637	1			T11	397		T12	101		T57	1
valid_sources[0x3e]	9998	1			T11	353		T12	99		T69	1
valid_sources[0x3f]	8087	1			T6	1		T11	366		T12	88
valid_sources[0x40]	9362	1			T11	367		T12	105		T32	2
valid_sources[0x41]	8759	1			T7	1		T11	302		T12	94
valid_sources[0x42]	7340	1			T11	353		T12	85		T85	1
valid_sources[0x43]	9233	1			T11	373		T12	100		T40	1
valid_sources[0x44]	9209	1			T11	376		T12	84		T66	1
valid_sources[0x45]	8415	1			T11	336		T12	98		T27	1
valid_sources[0x46]	7652	1			T4	1		T11	330		T12	80
valid_sources[0x47]	8185	1			T17	1		T11	370		T26	1
valid_sources[0x48]	9181	1			T3	1		T11	371		T12	94
valid_sources[0x49]	8538	1			T11	356		T12	80		T19	1
valid_sources[0x4a]	7781	1			T5	1		T7	3		T11	398
valid_sources[0x4b]	8505	1			T11	374		T12	80		T57	1
valid_sources[0x4c]	7305	1			T5	1		T11	290		T12	86
valid_sources[0x4d]	7365	1			T11	355		T12	108		T69	1
valid_sources[0x4e]	7876	1			T10	3		T11	358		T12	98
valid_sources[0x4f]	9207	1			T10	5		T11	370		T12	84
valid_sources[0x50]	8488	1			T11	342		T12	75		T65	1
valid_sources[0x51]	8337	1			T11	361		T12	88		T20	1
valid_sources[0x52]	7839	1			T5	1		T11	374		T12	105
valid_sources[0x53]	8005	1			T5	1		T11	331		T12	94
valid_sources[0x54]	8617	1			T11	372		T18	1		T12	95
valid_sources[0x55]	8106	1			T4	1		T5	1		T11	310
valid_sources[0x56]	7920	1			T6	1		T11	380		T12	96
valid_sources[0x57]	8120	1			T10	2		T11	340		T12	73
valid_sources[0x58]	7378	1			T11	346		T12	97		T20	1
valid_sources[0x59]	8196	1			T11	333		T12	90		T114	9
valid_sources[0x5a]	9553	1			T11	369		T12	105		T40	4
valid_sources[0x5b]	8198	1			T11	370		T12	81		T32	1
valid_sources[0x5c]	8980	1			T11	338		T12	89		T57	1
valid_sources[0x5d]	9521	1			T11	348		T12	84		T69	1
valid_sources[0x5e]	8225	1			T11	359		T12	86		T13	537
valid_sources[0x5f]	8334	1			T5	1		T11	305		T12	114
valid_sources[0x60]	10090	1			T4	1		T11	360		T12	92
valid_sources[0x61]	8529	1			T11	354		T12	96		T65	1
valid_sources[0x62]	8898	1			T7	1		T11	357		T12	100
valid_sources[0x63]	7543	1			T11	370		T12	84		T80	1
valid_sources[0x64]	8209	1			T10	4		T11	342		T12	103
valid_sources[0x65]	9431	1			T11	358		T12	88		T49	14
valid_sources[0x66]	9242	1			T11	401		T18	5		T12	81
valid_sources[0x67]	8400	1			T5	1		T11	405		T18	3
valid_sources[0x68]	9276	1			T11	290		T12	100		T57	1
valid_sources[0x69]	8711	1			T17	3		T11	340		T12	104
valid_sources[0x6a]	8218	1			T11	352		T12	89		T136	1
valid_sources[0x6b]	9706	1			T11	367		T12	105		T40	1
valid_sources[0x6c]	9306	1			T10	3		T11	396		T12	106
valid_sources[0x6d]	8302	1			T11	393		T12	94		T138	1
valid_sources[0x6e]	7550	1			T4	1		T11	345		T12	90
valid_sources[0x6f]	9690	1			T11	383		T12	106		T81	2
valid_sources[0x70]	9690	1			T4	1		T10	1		T11	331
valid_sources[0x71]	7884	1			T11	365		T12	93		T13	110
valid_sources[0x72]	9225	1			T7	1		T11	364		T18	3
valid_sources[0x73]	7392	1			T11	353		T12	82		T57	1
valid_sources[0x74]	8588	1			T11	406		T12	77		T80	1
valid_sources[0x75]	9058	1			T11	396		T12	84		T85	2
valid_sources[0x76]	9194	1			T10	1		T17	2		T11	310
valid_sources[0x77]	8490	1			T2	2		T11	315		T12	91
valid_sources[0x78]	7359	1			T4	2		T11	314		T12	104
valid_sources[0x79]	8684	1			T11	339		T12	81		T65	1
valid_sources[0x7a]	8285	1			T4	2		T11	389		T12	89
valid_sources[0x7b]	8497	1			T11	376		T12	99		T19	1
valid_sources[0x7c]	6991	1			T11	312		T12	75		T114	25
valid_sources[0x7d]	9286	1			T11	356		T12	86		T27	1
valid_sources[0x7e]	8023	1			T11	380		T50	1		T12	91
valid_sources[0x7f]	6501	1			T11	337		T12	74		T40	2
valid_sources[0x80]	8178	1			T17	2		T11	331		T12	102

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

499581

1

T1

18

T4

22

T5

11

values[0x0]

all_enables

biggest_size

735662

1

T2

1

T6

2

T11

31192

values[0x1]

all_enables

biggest_size

736279

1

T2

1

T11

31513

T12

7962