Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4733973

1

T1

35

T4

57

T10

177

full_word

3042952

1

T1

7

T4

4

T5

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7776305	1			T1	42		T4	61		T5	10
auto[TlIntgErrCmd]	199	1			T58	7		T59	5		T60	6
auto[TlIntgErrData]	202	1			T58	9		T59	2		T60	6
auto[TlIntgErrBoth]	219	1			T58	4		T59	3		T60	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1250113

1

T1

42

T4

61

T5

10

auto[1]

6526812

1

T11

278027

T12

66099

T13

308349

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	528447	1			T1	35		T4	57		T10	177
auto[TlIntgErrNone]	partial	auto[1]	4204948	1			T11	180596		T12	42523		T13	196140
auto[TlIntgErrNone]	full_word	auto[0]	721406	1			T1	7		T4	4		T5	10
auto[TlIntgErrNone]	full_word	auto[1]	2321504	1			T11	97431		T12	23576		T13	112209
auto[TlIntgErrCmd]	partial	auto[0]	75	1			T58	3		T59	2		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	111	1			T58	4		T59	3		T60	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T123	1		T126	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T120	1		T127	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	97	1			T58	3		T59	1		T60	1
auto[TlIntgErrData]	partial	auto[1]	92	1			T58	5		T60	5		T119	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T129	2		T128	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T58	1		T59	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	74	1			T58	1		T59	1		T60	3
auto[TlIntgErrBoth]	partial	auto[1]	129	1			T58	2		T59	2		T60	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T123	1		T132	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T58	1		T123	2		T126	1