Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
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Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_kmac_cg 100.00 1 100 1 64 64




Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_kmac_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group Instance rom_ctrl_kmac_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_kmac_done 3 0 3 100.00 100 1 1 0
cp_kmac_ready 4 0 4 100.00 100 1 1 0


Summary for Variable cp_kmac_done

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_kmac_done

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
kmac_first 926 1 T5 14 T8 2 T17 21
same_cycle 16 1 T12 1 T23 1 T24 1
rom_first 2293 1 T1 2 T2 1 T3 2



Summary for Variable cp_kmac_ready

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_kmac_ready

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stall_repeat 160680489 1 T1 137764 T2 68694 T3 97240
stall_long 17003467 1 T1 14321 T2 7174 T3 10923
stall_1 1431984 1 T1 381 T2 175 T3 1073
zero_delay_5 7231590 1 T3 2 T5 143508 T8 16360

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