Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.53	96.97	93.25	97.88	100.00	99.01	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.26	91.56	84.30	99.07		96.39	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
207	1	1
253	1	1
308	1	1
409	8	8
410	8	8
412	8	8
413	8	8
415	8	8
416	8	8
420	1	1
422	1	1
425	1	1
426	1	1
427	1	1
428	1	1
433	1	1
437	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       253
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T17
1	1	Covered	T1,T4,T5

 LINE       413
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Not Covered

 LINE       422
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T17,T18
1	0	Covered	T3,T5,T7

 LINE       433
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T32

 LINE       437
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T17,T18
0	1	0	Covered	T3,T5,T7
1	0	0	Covered	T29,T30,T31

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T9	Yes	T4,T5,T17	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T9	Yes	T4,T5,T9	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T4,T10	Yes	T1,T4,T10	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T7,T17	Yes	T4,T7,T17	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T4,T6,T5	Yes	T2,T4,T6	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T4,T6	Yes	T1,T2,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T4,T5,T7	Yes	T2,T3,T4	OUTPUT
kmac_data_i.error	No	Yes	T3,T8,T9	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T3,T5	Yes	T4,T5,T7	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T4,T5	Yes	T5,T7,T8	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	207	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	207	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	378243231	377899921	0	0
BusRomIndicesMatch_A	378215387	377884196	0	0
FpvSecCmFifoRptrCheck_A	378243231	0	0	0
FpvSecCmFifoWptrCheck_A	378243231	0	0	0
FpvSecCmRegWeOnehotCheck_A	378243231	160	0	0
KeymgrDataODataKnown_A	378243231	112057234	0	0
KeymgrDataODataKnown_AKnownEnable	378243231	377899921	0	0
KeymgrDataOValidKnown_A	378243231	377899921	0	0
KeymgrValidChk_A	378243231	0	0	633
KmacDataODataKnown_A	378243231	265608466	0	0
KmacDataODataKnown_AKnownEnable	378243231	377899921	0	0
KmacDataOValidKnown_A	378243231	377899921	0	0
PwrmgrDataChk_A	378243231	0	0	633
PwrmgrDataOKnown_A	378243231	377899921	0	0
RegsTlOAReadyKnown_A	378243231	377899921	0	0
RegsTlODDataKnown_A	378243231	23225679	0	0
RegsTlODDataKnown_AKnownEnable	378243231	377899921	0	0
RegsTlODValidKnown_A	378243231	377899921	0	0
RomTlOAReadyKnown_A	378243231	377899921	0	0
RomTlODDataKnown_A	378243231	20436505	0	0
RomTlODDataKnown_AKnownEnable	378243231	377899921	0	0
RomTlODValidKnown_A	378243231	377899921	0	0
StabilityChkKmac_A	378243231	265603724	0	0
StabilityChkkeymgr_A	378243231	112054942	0	0
TlAccessChk_A	378243231	265842687	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	378243231	160	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	378243231	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	378243231	992	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	378243231	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378215387	377884196	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	150742	149395	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	160	0	0
T23	199341	0	0	0
T29	88964	20	0	0
T30	0	10	0	0
T31	0	20	0	0
T33	0	10	0	0
T34	0	10	0	0
T35	0	20	0	0
T36	0	20	0	0
T37	0	10	0	0
T38	0	20	0	0
T39	0	20	0	0
T40	33825	0	0	0
T41	329501	0	0	0
T42	205968	0	0	0
T43	18474	0	0	0
T44	50873	0	0	0
T45	105814	0	0	0
T46	115105	0	0	0
T47	16630	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	112057234	0	0
T1	338124	1320	0	0
T2	165434	275	0	0
T3	131834	71	0	0
T4	398661	1625	0	0
T5	151389	5485	0	0
T6	201231	64	0	0
T7	139401	2652	0	0
T8	16641	56	0	0
T9	148348	281	0	0
T10	200343	3470	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	0	0	633

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	265608466	0	0
T1	338124	336488	0	0
T2	165434	164986	0	0
T3	131834	131488	0	0
T4	398661	396762	0	0
T5	151389	143557	0	0
T6	201231	201086	0	0
T7	139401	138862	0	0
T8	16641	16368	0	0
T9	148348	147715	0	0
T10	200343	196399	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	0	0	633

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	23225679	0	0
T1	338124	32	0	0
T2	165434	55	0	0
T3	131834	1	0	0
T4	398661	32	0	0
T5	151389	17	0	0
T6	201231	7	0	0
T7	139401	16	0	0
T8	16641	1	0	0
T9	148348	3	0	0
T10	200343	96	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	20436505	0	0
T1	338124	269	0	0
T2	165434	0	0	0
T3	131834	0	0	0
T4	398661	218	0	0
T5	151389	15	0	0
T6	201231	0	0	0
T7	139401	0	0	0
T8	16641	0	0	0
T9	148348	0	0	0
T10	200343	195	0	0
T11	0	328727	0	0
T12	0	433283	0	0
T17	0	9	0	0
T18	0	8	0	0
T19	0	462	0	0
T20	0	387	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	377899921	0	0
T1	338124	337964	0	0
T2	165434	165337	0	0
T3	131834	131685	0	0
T4	398661	398546	0	0
T5	151389	149624	0	0
T6	201231	201173	0	0
T7	139401	139253	0	0
T8	16641	16485	0	0
T9	148348	148220	0	0
T10	200343	200125	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	265603724	0	0
T1	338124	336486	0	0
T2	165434	164985	0	0
T3	131834	131486	0	0
T4	398661	396760	0	0
T5	151389	143534	0	0
T6	201231	201085	0	0
T7	139401	138860	0	0
T8	16641	16366	0	0
T9	148348	147713	0	0
T10	200343	196396	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	112054942	0	0
T1	338124	1318	0	0
T2	165434	274	0	0
T3	131834	70	0	0
T4	398661	1623	0	0
T5	151389	5471	0	0
T6	201231	63	0	0
T7	139401	2647	0	0
T8	16641	55	0	0
T9	148348	280	0	0
T10	200343	3467	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	265842687	0	0
T1	338124	336644	0	0
T2	165434	165062	0	0
T3	131834	131614	0	0
T4	398661	396921	0	0
T5	151389	144139	0	0
T6	201231	201109	0	0
T7	139401	138988	0	0
T8	16641	16429	0	0
T9	148348	147939	0	0
T10	200343	196655	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	160	0	0
T23	199341	0	0	0
T29	88964	20	0	0
T30	0	10	0	0
T31	0	20	0	0
T33	0	10	0	0
T34	0	10	0	0
T35	0	20	0	0
T36	0	20	0	0
T37	0	10	0	0
T38	0	20	0	0
T39	0	20	0	0
T40	33825	0	0	0
T41	329501	0	0	0
T42	205968	0	0	0
T43	18474	0	0	0
T44	50873	0	0	0
T45	105814	0	0	0
T46	115105	0	0	0
T47	16630	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	992	0	0
T7	139401	5	0	0
T8	16641	0	0	0
T9	148348	0	0	0
T10	200343	0	0	0
T11	555879	0	0	0
T12	123010	0	0	0
T17	208353	10	0	0
T18	956466	5	0	0
T26	388197	0	0	0
T27	0	16	0	0
T28	0	5	0	0
T29	0	20	0	0
T45	0	5	0	0
T46	0	5	0	0
T48	0	5	0	0
T49	0	5	0	0
T50	270340	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378243231	0	0	0