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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.65 96.97 93.25 97.88 100.00 99.01 98.04 98.37


Total test records in report: 923
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T562 /workspace/coverage/default/48.rom_ctrl_stress_all.1814975375 Mar 19 02:49:26 PM PDT 24 Mar 19 02:50:20 PM PDT 24 2632205568 ps
T563 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3732979888 Mar 19 02:49:23 PM PDT 24 Mar 19 02:49:29 PM PDT 24 385551982 ps
T564 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2776784809 Mar 19 02:48:42 PM PDT 24 Mar 19 02:48:56 PM PDT 24 2898443264 ps
T565 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.180015480 Mar 19 03:09:10 PM PDT 24 Mar 19 03:09:19 PM PDT 24 692065750 ps
T566 /workspace/coverage/default/4.rom_ctrl_smoke.215376685 Mar 19 02:48:56 PM PDT 24 Mar 19 02:49:17 PM PDT 24 1984053834 ps
T567 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3577470746 Mar 19 03:09:18 PM PDT 24 Mar 19 03:09:49 PM PDT 24 3502547935 ps
T568 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.894874918 Mar 19 02:48:31 PM PDT 24 Mar 19 02:48:58 PM PDT 24 2961599848 ps
T569 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1607904343 Mar 19 02:49:11 PM PDT 24 Mar 19 02:53:18 PM PDT 24 142305632935 ps
T570 /workspace/coverage/default/42.rom_ctrl_alert_test.745816492 Mar 19 02:49:28 PM PDT 24 Mar 19 02:49:44 PM PDT 24 4185879889 ps
T571 /workspace/coverage/default/23.rom_ctrl_smoke.301224085 Mar 19 02:49:09 PM PDT 24 Mar 19 02:49:41 PM PDT 24 2955261635 ps
T572 /workspace/coverage/default/11.rom_ctrl_smoke.2151201219 Mar 19 02:48:50 PM PDT 24 Mar 19 02:49:26 PM PDT 24 7866131304 ps
T573 /workspace/coverage/default/5.rom_ctrl_alert_test.4210750859 Mar 19 02:48:42 PM PDT 24 Mar 19 02:48:55 PM PDT 24 2659116744 ps
T574 /workspace/coverage/default/16.rom_ctrl_smoke.2597116334 Mar 19 03:08:39 PM PDT 24 Mar 19 03:08:49 PM PDT 24 183014949 ps
T575 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3577162152 Mar 19 02:49:22 PM PDT 24 Mar 19 02:51:03 PM PDT 24 5671153082 ps
T576 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2071101109 Mar 19 03:09:15 PM PDT 24 Mar 19 03:09:41 PM PDT 24 10818583891 ps
T577 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3076823339 Mar 19 03:08:58 PM PDT 24 Mar 19 03:09:09 PM PDT 24 7166891328 ps
T578 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2392648506 Mar 19 02:48:40 PM PDT 24 Mar 19 02:49:14 PM PDT 24 3955073762 ps
T579 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.110454218 Mar 19 03:08:42 PM PDT 24 Mar 19 03:08:50 PM PDT 24 1151537985 ps
T580 /workspace/coverage/default/15.rom_ctrl_smoke.3316945092 Mar 19 03:08:41 PM PDT 24 Mar 19 03:09:20 PM PDT 24 13186812730 ps
T581 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3812606318 Mar 19 03:08:49 PM PDT 24 Mar 19 03:09:15 PM PDT 24 18867188829 ps
T582 /workspace/coverage/default/18.rom_ctrl_smoke.4271665025 Mar 19 03:09:13 PM PDT 24 Mar 19 03:09:35 PM PDT 24 7451742851 ps
T583 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1072316341 Mar 19 03:09:15 PM PDT 24 Mar 19 03:19:07 PM PDT 24 61539908780 ps
T584 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2565567681 Mar 19 03:08:42 PM PDT 24 Mar 19 03:09:01 PM PDT 24 5554428873 ps
T585 /workspace/coverage/default/37.rom_ctrl_smoke.2918608990 Mar 19 02:49:22 PM PDT 24 Mar 19 02:49:49 PM PDT 24 17590243767 ps
T586 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4098264 Mar 19 03:08:34 PM PDT 24 Mar 19 03:08:41 PM PDT 24 184323831 ps
T587 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.451734692 Mar 19 03:09:00 PM PDT 24 Mar 19 03:11:21 PM PDT 24 9040314603 ps
T588 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3083173917 Mar 19 03:08:33 PM PDT 24 Mar 19 03:08:39 PM PDT 24 99999770 ps
T589 /workspace/coverage/default/35.rom_ctrl_alert_test.1738988009 Mar 19 03:08:46 PM PDT 24 Mar 19 03:09:01 PM PDT 24 4287284536 ps
T590 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.708899393 Mar 19 03:08:48 PM PDT 24 Mar 19 03:09:17 PM PDT 24 6885290835 ps
T98 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2465260688 Mar 19 03:09:08 PM PDT 24 Mar 19 03:09:22 PM PDT 24 1594259052 ps
T99 /workspace/coverage/default/37.rom_ctrl_stress_all.23877178 Mar 19 03:09:11 PM PDT 24 Mar 19 03:10:32 PM PDT 24 15563964351 ps
T100 /workspace/coverage/default/29.rom_ctrl_alert_test.651231914 Mar 19 02:49:11 PM PDT 24 Mar 19 02:49:22 PM PDT 24 968071636 ps
T101 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2505614733 Mar 19 02:49:25 PM PDT 24 Mar 19 02:49:37 PM PDT 24 2012138392 ps
T38 /workspace/coverage/default/0.rom_ctrl_sec_cm.158139441 Mar 19 03:08:35 PM PDT 24 Mar 19 03:10:25 PM PDT 24 22546044372 ps
T102 /workspace/coverage/default/42.rom_ctrl_stress_all.2444848196 Mar 19 03:08:56 PM PDT 24 Mar 19 03:09:46 PM PDT 24 8134015882 ps
T103 /workspace/coverage/default/7.rom_ctrl_stress_all.184697782 Mar 19 03:08:50 PM PDT 24 Mar 19 03:09:17 PM PDT 24 4196973502 ps
T104 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2714523948 Mar 19 03:09:06 PM PDT 24 Mar 19 03:09:23 PM PDT 24 1266232850 ps
T105 /workspace/coverage/default/42.rom_ctrl_stress_all.2207016165 Mar 19 02:49:19 PM PDT 24 Mar 19 02:50:16 PM PDT 24 26295375486 ps
T106 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2015671147 Mar 19 02:48:54 PM PDT 24 Mar 19 03:25:02 PM PDT 24 24836060086 ps
T591 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3497786068 Mar 19 02:49:28 PM PDT 24 Mar 19 02:53:09 PM PDT 24 23058598711 ps
T39 /workspace/coverage/default/2.rom_ctrl_sec_cm.2872293150 Mar 19 03:08:37 PM PDT 24 Mar 19 03:10:25 PM PDT 24 12914331091 ps
T592 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4157908085 Mar 19 02:48:54 PM PDT 24 Mar 19 02:49:00 PM PDT 24 93793732 ps
T593 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3360641787 Mar 19 03:09:09 PM PDT 24 Mar 19 03:09:40 PM PDT 24 3526864450 ps
T594 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3590881113 Mar 19 02:48:43 PM PDT 24 Mar 19 02:51:25 PM PDT 24 28794695403 ps
T595 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2657129749 Mar 19 02:48:59 PM PDT 24 Mar 19 03:24:56 PM PDT 24 10691363338 ps
T596 /workspace/coverage/default/4.rom_ctrl_smoke.542237741 Mar 19 03:08:31 PM PDT 24 Mar 19 03:08:50 PM PDT 24 2833135421 ps
T597 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.179791625 Mar 19 03:09:19 PM PDT 24 Mar 19 03:09:38 PM PDT 24 5129054971 ps
T25 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.842960637 Mar 19 02:48:59 PM PDT 24 Mar 19 02:49:33 PM PDT 24 4746259679 ps
T598 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3349161236 Mar 19 03:09:03 PM PDT 24 Mar 19 03:09:35 PM PDT 24 7205623645 ps
T599 /workspace/coverage/default/7.rom_ctrl_alert_test.3272981035 Mar 19 02:48:45 PM PDT 24 Mar 19 02:48:54 PM PDT 24 3007086493 ps
T600 /workspace/coverage/default/6.rom_ctrl_stress_all.1146425830 Mar 19 02:48:47 PM PDT 24 Mar 19 02:49:26 PM PDT 24 2042041915 ps
T601 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3963445497 Mar 19 03:08:45 PM PDT 24 Mar 19 03:08:57 PM PDT 24 1082590589 ps
T602 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2503598538 Mar 19 03:08:56 PM PDT 24 Mar 19 03:09:11 PM PDT 24 3300351403 ps
T603 /workspace/coverage/default/13.rom_ctrl_smoke.682903189 Mar 19 02:49:02 PM PDT 24 Mar 19 02:49:17 PM PDT 24 2118356970 ps
T604 /workspace/coverage/default/20.rom_ctrl_alert_test.1338729957 Mar 19 03:09:06 PM PDT 24 Mar 19 03:09:10 PM PDT 24 87073072 ps
T605 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1169060143 Mar 19 03:08:45 PM PDT 24 Mar 19 03:08:58 PM PDT 24 1261985394 ps
T606 /workspace/coverage/default/12.rom_ctrl_smoke.1333048145 Mar 19 03:08:41 PM PDT 24 Mar 19 03:08:59 PM PDT 24 15515790249 ps
T607 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2464526412 Mar 19 03:09:08 PM PDT 24 Mar 19 04:51:15 PM PDT 24 725715258219 ps
T608 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.396486221 Mar 19 03:09:06 PM PDT 24 Mar 19 03:09:14 PM PDT 24 2015444383 ps
T609 /workspace/coverage/default/19.rom_ctrl_alert_test.2049290968 Mar 19 02:49:00 PM PDT 24 Mar 19 02:49:09 PM PDT 24 5805148082 ps
T610 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4171894486 Mar 19 03:09:03 PM PDT 24 Mar 19 03:09:30 PM PDT 24 2960758580 ps
T611 /workspace/coverage/default/38.rom_ctrl_stress_all.410785796 Mar 19 03:09:06 PM PDT 24 Mar 19 03:10:11 PM PDT 24 10748964979 ps
T612 /workspace/coverage/default/1.rom_ctrl_alert_test.82230781 Mar 19 02:48:43 PM PDT 24 Mar 19 02:48:48 PM PDT 24 85554409 ps
T613 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1119124555 Mar 19 03:08:53 PM PDT 24 Mar 19 03:09:02 PM PDT 24 334707635 ps
T614 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.973354074 Mar 19 02:49:23 PM PDT 24 Mar 19 02:51:22 PM PDT 24 36534465424 ps
T615 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4187212995 Mar 19 03:08:57 PM PDT 24 Mar 19 03:09:03 PM PDT 24 1334138484 ps
T616 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4093859785 Mar 19 02:48:45 PM PDT 24 Mar 19 02:52:53 PM PDT 24 26092099104 ps
T617 /workspace/coverage/default/17.rom_ctrl_smoke.1994659267 Mar 19 03:09:11 PM PDT 24 Mar 19 03:09:29 PM PDT 24 1985144946 ps
T618 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3910274514 Mar 19 02:49:10 PM PDT 24 Mar 19 02:49:33 PM PDT 24 3936989303 ps
T619 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.540869985 Mar 19 02:49:12 PM PDT 24 Mar 19 02:53:21 PM PDT 24 18846344475 ps
T620 /workspace/coverage/default/7.rom_ctrl_stress_all.3828313313 Mar 19 02:48:56 PM PDT 24 Mar 19 02:49:56 PM PDT 24 4534380682 ps
T621 /workspace/coverage/default/45.rom_ctrl_stress_all.948052984 Mar 19 03:09:15 PM PDT 24 Mar 19 03:10:32 PM PDT 24 8514411424 ps
T622 /workspace/coverage/default/7.rom_ctrl_smoke.2253995022 Mar 19 02:48:55 PM PDT 24 Mar 19 02:49:22 PM PDT 24 5021586036 ps
T623 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1999389296 Mar 19 02:49:19 PM PDT 24 Mar 19 03:03:08 PM PDT 24 20895652053 ps
T624 /workspace/coverage/default/44.rom_ctrl_alert_test.55165445 Mar 19 03:09:13 PM PDT 24 Mar 19 03:09:26 PM PDT 24 5863042135 ps
T625 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.953990445 Mar 19 02:49:29 PM PDT 24 Mar 19 02:49:43 PM PDT 24 1604378711 ps
T626 /workspace/coverage/default/37.rom_ctrl_alert_test.1067248674 Mar 19 03:09:06 PM PDT 24 Mar 19 03:09:11 PM PDT 24 89073805 ps
T627 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3126576750 Mar 19 03:09:10 PM PDT 24 Mar 19 03:25:29 PM PDT 24 11579913758 ps
T628 /workspace/coverage/default/9.rom_ctrl_alert_test.2302192677 Mar 19 02:48:52 PM PDT 24 Mar 19 02:49:03 PM PDT 24 4662182262 ps
T629 /workspace/coverage/default/14.rom_ctrl_alert_test.3890694808 Mar 19 03:08:40 PM PDT 24 Mar 19 03:08:45 PM PDT 24 347673982 ps
T630 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1825117193 Mar 19 03:09:15 PM PDT 24 Mar 19 03:09:28 PM PDT 24 7694555551 ps
T631 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1802136636 Mar 19 03:09:11 PM PDT 24 Mar 19 03:09:31 PM PDT 24 1683393884 ps
T632 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1827612152 Mar 19 03:09:01 PM PDT 24 Mar 19 03:13:59 PM PDT 24 25679329034 ps
T633 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3080017914 Mar 19 03:09:10 PM PDT 24 Mar 19 03:11:45 PM PDT 24 18643475029 ps
T634 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3175892624 Mar 19 03:08:44 PM PDT 24 Mar 19 03:09:00 PM PDT 24 7165052017 ps
T635 /workspace/coverage/default/37.rom_ctrl_alert_test.3039863242 Mar 19 02:49:23 PM PDT 24 Mar 19 02:49:34 PM PDT 24 1140566363 ps
T636 /workspace/coverage/default/31.rom_ctrl_stress_all.2439195285 Mar 19 02:49:12 PM PDT 24 Mar 19 02:49:36 PM PDT 24 2520094345 ps
T637 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1838107206 Mar 19 02:48:59 PM PDT 24 Mar 19 02:52:44 PM PDT 24 22983598725 ps
T638 /workspace/coverage/default/26.rom_ctrl_stress_all.1648662258 Mar 19 03:08:53 PM PDT 24 Mar 19 03:09:18 PM PDT 24 5686778875 ps
T639 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4196948072 Mar 19 03:08:44 PM PDT 24 Mar 19 03:08:51 PM PDT 24 224145613 ps
T640 /workspace/coverage/default/21.rom_ctrl_alert_test.3724038888 Mar 19 02:49:10 PM PDT 24 Mar 19 02:49:14 PM PDT 24 89127690 ps
T641 /workspace/coverage/default/38.rom_ctrl_smoke.3553524944 Mar 19 03:09:10 PM PDT 24 Mar 19 03:09:30 PM PDT 24 1663716417 ps
T642 /workspace/coverage/default/30.rom_ctrl_alert_test.1285941290 Mar 19 03:09:01 PM PDT 24 Mar 19 03:09:16 PM PDT 24 1930331751 ps
T643 /workspace/coverage/default/1.rom_ctrl_stress_all.1223314516 Mar 19 02:48:51 PM PDT 24 Mar 19 02:50:55 PM PDT 24 14410915741 ps
T644 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3776375295 Mar 19 02:49:19 PM PDT 24 Mar 19 02:49:33 PM PDT 24 5944714182 ps
T645 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2423474382 Mar 19 03:08:36 PM PDT 24 Mar 19 03:09:09 PM PDT 24 47812468116 ps
T646 /workspace/coverage/default/24.rom_ctrl_alert_test.1034479967 Mar 19 03:08:46 PM PDT 24 Mar 19 03:08:59 PM PDT 24 2728586375 ps
T647 /workspace/coverage/default/23.rom_ctrl_alert_test.3388301620 Mar 19 02:49:11 PM PDT 24 Mar 19 02:49:25 PM PDT 24 3086883815 ps
T648 /workspace/coverage/default/34.rom_ctrl_alert_test.1142648402 Mar 19 02:49:18 PM PDT 24 Mar 19 02:49:33 PM PDT 24 5640557111 ps
T649 /workspace/coverage/default/14.rom_ctrl_smoke.1619442416 Mar 19 03:08:40 PM PDT 24 Mar 19 03:08:55 PM PDT 24 1580489214 ps
T650 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.522963479 Mar 19 02:49:00 PM PDT 24 Mar 19 02:49:08 PM PDT 24 1516567764 ps
T651 /workspace/coverage/default/39.rom_ctrl_alert_test.607559523 Mar 19 03:09:13 PM PDT 24 Mar 19 03:09:24 PM PDT 24 2167992319 ps
T652 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2460956526 Mar 19 02:49:18 PM PDT 24 Mar 19 02:49:28 PM PDT 24 175813113 ps
T653 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1715705559 Mar 19 02:48:57 PM PDT 24 Mar 19 02:49:19 PM PDT 24 8224487519 ps
T654 /workspace/coverage/default/3.rom_ctrl_alert_test.479668483 Mar 19 02:48:43 PM PDT 24 Mar 19 02:48:57 PM PDT 24 1756221681 ps
T655 /workspace/coverage/default/43.rom_ctrl_alert_test.3236949714 Mar 19 03:09:01 PM PDT 24 Mar 19 03:09:11 PM PDT 24 823538143 ps
T656 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1051759151 Mar 19 03:08:25 PM PDT 24 Mar 19 03:08:38 PM PDT 24 1052784146 ps
T657 /workspace/coverage/default/2.rom_ctrl_alert_test.1479443484 Mar 19 02:48:42 PM PDT 24 Mar 19 02:48:59 PM PDT 24 4262750525 ps
T658 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.455196065 Mar 19 03:08:38 PM PDT 24 Mar 19 03:16:02 PM PDT 24 188502690200 ps
T659 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1023798679 Mar 19 02:49:16 PM PDT 24 Mar 19 02:49:21 PM PDT 24 97226337 ps
T660 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3457961673 Mar 19 02:49:11 PM PDT 24 Mar 19 02:49:26 PM PDT 24 2219905862 ps
T661 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3121294216 Mar 19 02:49:21 PM PDT 24 Mar 19 02:49:38 PM PDT 24 2168884237 ps
T662 /workspace/coverage/default/17.rom_ctrl_stress_all.3490339658 Mar 19 03:08:49 PM PDT 24 Mar 19 03:09:19 PM PDT 24 8612074094 ps
T663 /workspace/coverage/default/28.rom_ctrl_stress_all.1920145175 Mar 19 02:49:18 PM PDT 24 Mar 19 02:50:00 PM PDT 24 3349883050 ps
T664 /workspace/coverage/default/38.rom_ctrl_stress_all.2959503033 Mar 19 02:49:22 PM PDT 24 Mar 19 02:50:04 PM PDT 24 14875234503 ps
T665 /workspace/coverage/default/30.rom_ctrl_alert_test.3090196587 Mar 19 02:49:14 PM PDT 24 Mar 19 02:49:23 PM PDT 24 3241515356 ps
T666 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3809133478 Mar 19 03:08:35 PM PDT 24 Mar 19 03:13:22 PM PDT 24 37543511510 ps
T667 /workspace/coverage/default/33.rom_ctrl_smoke.996266942 Mar 19 02:49:21 PM PDT 24 Mar 19 02:49:32 PM PDT 24 177106775 ps
T668 /workspace/coverage/default/7.rom_ctrl_smoke.3682472967 Mar 19 03:08:41 PM PDT 24 Mar 19 03:09:13 PM PDT 24 11184695426 ps
T669 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2137825822 Mar 19 03:09:04 PM PDT 24 Mar 19 03:09:21 PM PDT 24 8095952776 ps
T670 /workspace/coverage/default/39.rom_ctrl_stress_all.2826408562 Mar 19 03:09:11 PM PDT 24 Mar 19 03:09:31 PM PDT 24 3873694299 ps
T671 /workspace/coverage/default/46.rom_ctrl_alert_test.408566292 Mar 19 02:49:29 PM PDT 24 Mar 19 02:49:44 PM PDT 24 7297185193 ps
T672 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1140181743 Mar 19 02:48:57 PM PDT 24 Mar 19 02:50:17 PM PDT 24 4605562752 ps
T673 /workspace/coverage/default/20.rom_ctrl_smoke.1686715558 Mar 19 02:49:00 PM PDT 24 Mar 19 02:49:29 PM PDT 24 16913195955 ps
T674 /workspace/coverage/default/40.rom_ctrl_smoke.1773026898 Mar 19 03:09:08 PM PDT 24 Mar 19 03:09:38 PM PDT 24 12295381017 ps
T675 /workspace/coverage/default/28.rom_ctrl_smoke.3179306046 Mar 19 03:09:01 PM PDT 24 Mar 19 03:09:11 PM PDT 24 186668606 ps
T676 /workspace/coverage/default/19.rom_ctrl_smoke.1592053920 Mar 19 03:08:49 PM PDT 24 Mar 19 03:08:59 PM PDT 24 940496888 ps
T677 /workspace/coverage/default/35.rom_ctrl_stress_all.4069810739 Mar 19 03:08:41 PM PDT 24 Mar 19 03:08:58 PM PDT 24 597933929 ps
T678 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3531564651 Mar 19 03:08:42 PM PDT 24 Mar 19 03:12:13 PM PDT 24 98243778984 ps
T679 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3516876760 Mar 19 02:49:19 PM PDT 24 Mar 19 02:49:25 PM PDT 24 371762810 ps
T680 /workspace/coverage/default/10.rom_ctrl_smoke.129568444 Mar 19 02:48:51 PM PDT 24 Mar 19 02:49:02 PM PDT 24 182961794 ps
T681 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2984056484 Mar 19 03:08:53 PM PDT 24 Mar 19 03:15:42 PM PDT 24 47591577500 ps
T682 /workspace/coverage/default/9.rom_ctrl_stress_all.1064202949 Mar 19 02:48:50 PM PDT 24 Mar 19 02:49:22 PM PDT 24 3496443147 ps
T61 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1001129308 Mar 19 02:54:38 PM PDT 24 Mar 19 02:55:00 PM PDT 24 2139607203 ps
T62 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2342960230 Mar 19 02:44:31 PM PDT 24 Mar 19 02:45:19 PM PDT 24 1675171652 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2118112772 Mar 19 02:44:15 PM PDT 24 Mar 19 02:44:31 PM PDT 24 999679080 ps
T683 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.681272918 Mar 19 02:44:19 PM PDT 24 Mar 19 02:44:27 PM PDT 24 459927319 ps
T107 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2240681835 Mar 19 02:44:13 PM PDT 24 Mar 19 02:44:41 PM PDT 24 2541517413 ps
T684 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3825349211 Mar 19 02:44:51 PM PDT 24 Mar 19 02:45:09 PM PDT 24 4752085709 ps
T685 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1852547014 Mar 19 02:44:40 PM PDT 24 Mar 19 02:45:01 PM PDT 24 1736001195 ps
T686 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.127176366 Mar 19 02:54:47 PM PDT 24 Mar 19 02:55:07 PM PDT 24 16376689933 ps
T70 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1480101353 Mar 19 02:54:54 PM PDT 24 Mar 19 02:55:21 PM PDT 24 12000663135 ps
T687 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.457807142 Mar 19 02:44:20 PM PDT 24 Mar 19 02:44:33 PM PDT 24 2725297907 ps
T58 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3963766990 Mar 19 02:54:54 PM PDT 24 Mar 19 02:57:26 PM PDT 24 1202096375 ps
T688 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2805839900 Mar 19 02:54:34 PM PDT 24 Mar 19 02:55:06 PM PDT 24 21218093101 ps
T689 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3901945524 Mar 19 02:44:12 PM PDT 24 Mar 19 02:44:45 PM PDT 24 14631533957 ps
T71 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.88520242 Mar 19 02:44:38 PM PDT 24 Mar 19 02:47:52 PM PDT 24 98405948212 ps
T690 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3421625337 Mar 19 02:44:44 PM PDT 24 Mar 19 02:45:03 PM PDT 24 7181963652 ps
T59 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1115341367 Mar 19 02:54:38 PM PDT 24 Mar 19 02:56:02 PM PDT 24 287844092 ps
T691 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2531109545 Mar 19 02:44:13 PM PDT 24 Mar 19 02:44:25 PM PDT 24 174391834 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1936893448 Mar 19 02:44:31 PM PDT 24 Mar 19 02:44:40 PM PDT 24 360302966 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2727275356 Mar 19 02:44:12 PM PDT 24 Mar 19 02:46:56 PM PDT 24 37188722664 ps
T692 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1836064464 Mar 19 02:44:35 PM PDT 24 Mar 19 02:45:05 PM PDT 24 3523390823 ps
T109 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.469146161 Mar 19 02:44:21 PM PDT 24 Mar 19 02:45:13 PM PDT 24 8314260321 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2091723351 Mar 19 02:54:31 PM PDT 24 Mar 19 02:57:20 PM PDT 24 2412522386 ps
T693 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1132267263 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:41 PM PDT 24 613089220 ps
T694 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1724252605 Mar 19 02:44:30 PM PDT 24 Mar 19 02:44:55 PM PDT 24 2599624851 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3052149023 Mar 19 02:44:20 PM PDT 24 Mar 19 02:44:51 PM PDT 24 4872662392 ps
T695 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.576144709 Mar 19 02:54:45 PM PDT 24 Mar 19 02:54:58 PM PDT 24 601130461 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2151991390 Mar 19 02:54:50 PM PDT 24 Mar 19 02:55:12 PM PDT 24 2227922199 ps
T119 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4177080147 Mar 19 02:54:40 PM PDT 24 Mar 19 02:57:31 PM PDT 24 12734331956 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3099632304 Mar 19 02:44:13 PM PDT 24 Mar 19 02:46:14 PM PDT 24 59150597732 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.453343934 Mar 19 02:54:26 PM PDT 24 Mar 19 02:54:40 PM PDT 24 434204329 ps
T696 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4084350435 Mar 19 02:44:31 PM PDT 24 Mar 19 02:44:54 PM PDT 24 4973479554 ps
T697 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3426307829 Mar 19 02:54:32 PM PDT 24 Mar 19 02:55:04 PM PDT 24 27318040090 ps
T123 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2289449830 Mar 19 02:44:40 PM PDT 24 Mar 19 02:47:36 PM PDT 24 4065580187 ps
T698 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2195948739 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:47 PM PDT 24 10523205852 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.446309342 Mar 19 02:44:25 PM PDT 24 Mar 19 02:44:45 PM PDT 24 1081839609 ps
T77 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1647225290 Mar 19 02:44:51 PM PDT 24 Mar 19 02:45:12 PM PDT 24 1922167847 ps
T699 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1279852705 Mar 19 02:54:46 PM PDT 24 Mar 19 02:54:57 PM PDT 24 174667842 ps
T126 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1545408939 Mar 19 02:44:30 PM PDT 24 Mar 19 02:47:11 PM PDT 24 1064892600 ps
T700 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3248104267 Mar 19 02:44:30 PM PDT 24 Mar 19 02:44:42 PM PDT 24 428750177 ps
T701 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1921112 Mar 19 02:54:26 PM PDT 24 Mar 19 02:54:59 PM PDT 24 14898794718 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3396826643 Mar 19 02:54:38 PM PDT 24 Mar 19 02:55:00 PM PDT 24 1706750030 ps
T702 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1557962318 Mar 19 02:54:39 PM PDT 24 Mar 19 02:55:14 PM PDT 24 4277195739 ps
T703 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1774672311 Mar 19 02:54:37 PM PDT 24 Mar 19 02:55:09 PM PDT 24 10276336896 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2102321546 Mar 19 02:44:20 PM PDT 24 Mar 19 02:44:49 PM PDT 24 14166877374 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.624866118 Mar 19 02:44:38 PM PDT 24 Mar 19 02:44:52 PM PDT 24 1713334989 ps
T704 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4045988781 Mar 19 02:54:39 PM PDT 24 Mar 19 02:55:04 PM PDT 24 25477663466 ps
T131 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2427286318 Mar 19 02:44:38 PM PDT 24 Mar 19 02:46:19 PM PDT 24 14603188346 ps
T705 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.997774958 Mar 19 02:44:38 PM PDT 24 Mar 19 02:44:58 PM PDT 24 2160011416 ps
T706 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3969030026 Mar 19 02:54:38 PM PDT 24 Mar 19 02:54:46 PM PDT 24 689421901 ps
T707 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4126756452 Mar 19 02:44:14 PM PDT 24 Mar 19 02:44:29 PM PDT 24 959714415 ps
T124 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2102314141 Mar 19 02:44:44 PM PDT 24 Mar 19 02:47:36 PM PDT 24 13584219355 ps
T86 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.409432148 Mar 19 02:54:34 PM PDT 24 Mar 19 02:56:54 PM PDT 24 17277077651 ps
T708 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.579198085 Mar 19 02:54:46 PM PDT 24 Mar 19 02:54:59 PM PDT 24 735425211 ps
T709 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2391601915 Mar 19 02:54:30 PM PDT 24 Mar 19 02:54:52 PM PDT 24 4412414810 ps
T710 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2737222813 Mar 19 02:54:30 PM PDT 24 Mar 19 02:56:20 PM PDT 24 12970721740 ps
T711 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1202308500 Mar 19 02:54:37 PM PDT 24 Mar 19 02:54:46 PM PDT 24 704930070 ps
T712 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2837816885 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:59 PM PDT 24 11383622322 ps
T713 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.553236111 Mar 19 02:54:31 PM PDT 24 Mar 19 02:54:57 PM PDT 24 3028175678 ps
T714 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2549056363 Mar 19 02:54:32 PM PDT 24 Mar 19 02:54:54 PM PDT 24 2228295202 ps
T715 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.901118821 Mar 19 02:54:47 PM PDT 24 Mar 19 02:56:28 PM PDT 24 6667792448 ps
T716 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1183076686 Mar 19 02:44:40 PM PDT 24 Mar 19 02:47:22 PM PDT 24 6516710301 ps
T717 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4278612715 Mar 19 02:54:52 PM PDT 24 Mar 19 02:55:04 PM PDT 24 345430238 ps
T718 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.12945528 Mar 19 02:44:30 PM PDT 24 Mar 19 02:45:09 PM PDT 24 688632136 ps
T719 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3481663941 Mar 19 02:54:50 PM PDT 24 Mar 19 02:55:03 PM PDT 24 360674528 ps
T720 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2912659425 Mar 19 02:54:45 PM PDT 24 Mar 19 02:55:22 PM PDT 24 6190576268 ps
T721 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3089331830 Mar 19 02:44:51 PM PDT 24 Mar 19 02:45:05 PM PDT 24 1711504394 ps
T722 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2402570213 Mar 19 02:44:19 PM PDT 24 Mar 19 02:44:46 PM PDT 24 3204642848 ps
T723 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.900567843 Mar 19 02:54:46 PM PDT 24 Mar 19 02:55:10 PM PDT 24 5282473602 ps
T724 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.491367779 Mar 19 02:44:13 PM PDT 24 Mar 19 02:44:38 PM PDT 24 10868025193 ps
T725 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2243686797 Mar 19 02:54:48 PM PDT 24 Mar 19 02:55:12 PM PDT 24 2386803436 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2338220553 Mar 19 02:54:45 PM PDT 24 Mar 19 02:56:26 PM PDT 24 21008619436 ps
T726 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.943702082 Mar 19 02:54:24 PM PDT 24 Mar 19 02:54:54 PM PDT 24 13790176022 ps
T727 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1283937290 Mar 19 02:44:15 PM PDT 24 Mar 19 02:44:41 PM PDT 24 10902662429 ps
T728 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2997314527 Mar 19 02:54:27 PM PDT 24 Mar 19 02:55:41 PM PDT 24 11924102736 ps
T729 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2351313543 Mar 19 02:44:13 PM PDT 24 Mar 19 02:44:41 PM PDT 24 3226433848 ps
T730 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1406999216 Mar 19 02:44:25 PM PDT 24 Mar 19 02:44:45 PM PDT 24 1859800374 ps
T731 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.559572181 Mar 19 02:44:40 PM PDT 24 Mar 19 02:46:21 PM PDT 24 49092677729 ps
T88 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2907982756 Mar 19 02:44:32 PM PDT 24 Mar 19 02:46:33 PM PDT 24 41132528134 ps
T732 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3605252825 Mar 19 02:54:51 PM PDT 24 Mar 19 02:55:13 PM PDT 24 9240935271 ps
T120 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1093501506 Mar 19 02:44:13 PM PDT 24 Mar 19 02:47:09 PM PDT 24 9074209564 ps
T733 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.953326648 Mar 19 02:54:24 PM PDT 24 Mar 19 02:55:03 PM PDT 24 6871104199 ps
T734 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2924962001 Mar 19 02:44:13 PM PDT 24 Mar 19 02:45:12 PM PDT 24 2990575350 ps
T735 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1366151641 Mar 19 02:44:22 PM PDT 24 Mar 19 02:44:36 PM PDT 24 849457838 ps
T736 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3423630505 Mar 19 02:54:39 PM PDT 24 Mar 19 02:54:52 PM PDT 24 969947185 ps
T737 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3109078445 Mar 19 02:44:40 PM PDT 24 Mar 19 02:45:13 PM PDT 24 16786256713 ps
T738 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4257585697 Mar 19 02:44:14 PM PDT 24 Mar 19 02:44:26 PM PDT 24 496101534 ps
T121 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3587697525 Mar 19 02:44:40 PM PDT 24 Mar 19 02:46:02 PM PDT 24 3765154743 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1237164655 Mar 19 02:44:30 PM PDT 24 Mar 19 02:47:19 PM PDT 24 2669633937 ps
T739 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3290196382 Mar 19 02:44:15 PM PDT 24 Mar 19 02:44:38 PM PDT 24 7525778567 ps
T740 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1847698346 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:54 PM PDT 24 1387343245 ps
T132 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3218979244 Mar 19 02:54:48 PM PDT 24 Mar 19 02:56:18 PM PDT 24 1475290294 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3179467929 Mar 19 02:44:33 PM PDT 24 Mar 19 02:46:08 PM PDT 24 22077230646 ps
T741 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.398017576 Mar 19 02:54:38 PM PDT 24 Mar 19 02:55:12 PM PDT 24 4115155490 ps
T742 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3066882758 Mar 19 02:44:29 PM PDT 24 Mar 19 02:45:05 PM PDT 24 35120599405 ps
T743 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1977491059 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:42 PM PDT 24 1375022627 ps
T744 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2452547004 Mar 19 02:44:13 PM PDT 24 Mar 19 02:45:42 PM PDT 24 519638316 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.879021618 Mar 19 02:54:24 PM PDT 24 Mar 19 02:54:33 PM PDT 24 687856188 ps
T745 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4213473892 Mar 19 02:54:35 PM PDT 24 Mar 19 02:54:48 PM PDT 24 339253160 ps
T746 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.461316425 Mar 19 02:44:22 PM PDT 24 Mar 19 02:46:11 PM PDT 24 8074711791 ps
T747 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2653720781 Mar 19 02:44:19 PM PDT 24 Mar 19 02:44:41 PM PDT 24 8273165847 ps
T118 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2150337767 Mar 19 02:54:38 PM PDT 24 Mar 19 02:55:36 PM PDT 24 3647433247 ps
T748 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1182049659 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:58 PM PDT 24 7501045168 ps
T749 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1888801216 Mar 19 02:54:31 PM PDT 24 Mar 19 02:54:48 PM PDT 24 1741962354 ps
T750 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2704105226 Mar 19 02:44:33 PM PDT 24 Mar 19 02:45:03 PM PDT 24 4634491322 ps
T751 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.927961613 Mar 19 02:44:40 PM PDT 24 Mar 19 02:44:48 PM PDT 24 338374738 ps
T125 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.965673353 Mar 19 02:54:27 PM PDT 24 Mar 19 02:55:53 PM PDT 24 1939004683 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3134453368 Mar 19 02:54:27 PM PDT 24 Mar 19 02:54:51 PM PDT 24 10811224088 ps
T752 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3928627638 Mar 19 02:54:33 PM PDT 24 Mar 19 02:54:47 PM PDT 24 6833421572 ps
T133 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.225300799 Mar 19 02:44:12 PM PDT 24 Mar 19 02:47:02 PM PDT 24 3024507076 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3526112057 Mar 19 02:44:41 PM PDT 24 Mar 19 02:45:38 PM PDT 24 3335163871 ps
T753 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1951363380 Mar 19 02:54:37 PM PDT 24 Mar 19 02:55:07 PM PDT 24 12640944529 ps
T754 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3524934770 Mar 19 02:54:27 PM PDT 24 Mar 19 02:54:42 PM PDT 24 3283126267 ps
T755 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.413450089 Mar 19 02:54:51 PM PDT 24 Mar 19 02:55:15 PM PDT 24 5021419457 ps
T756 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3161049601 Mar 19 02:44:32 PM PDT 24 Mar 19 02:44:54 PM PDT 24 11139061260 ps
T757 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2939248155 Mar 19 02:54:29 PM PDT 24 Mar 19 02:56:06 PM PDT 24 14028147137 ps
T758 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.625154300 Mar 19 02:54:46 PM PDT 24 Mar 19 02:55:11 PM PDT 24 10161703496 ps
T759 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3556680558 Mar 19 02:44:41 PM PDT 24 Mar 19 02:44:51 PM PDT 24 180743977 ps
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