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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.65 96.97 93.25 97.88 100.00 99.01 98.04 98.37


Total test records in report: 923
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T760 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1695921457 Mar 19 02:44:37 PM PDT 24 Mar 19 02:46:46 PM PDT 24 16751418865 ps
T761 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2064710952 Mar 19 02:44:41 PM PDT 24 Mar 19 02:45:16 PM PDT 24 15230923708 ps
T762 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.562765320 Mar 19 02:44:50 PM PDT 24 Mar 19 02:45:09 PM PDT 24 1421045251 ps
T763 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.808328583 Mar 19 02:44:40 PM PDT 24 Mar 19 02:45:05 PM PDT 24 19244608172 ps
T764 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1199044493 Mar 19 02:44:35 PM PDT 24 Mar 19 02:44:44 PM PDT 24 183301665 ps
T94 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3894645467 Mar 19 02:44:44 PM PDT 24 Mar 19 02:44:52 PM PDT 24 612838540 ps
T765 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2300265864 Mar 19 02:44:32 PM PDT 24 Mar 19 02:44:58 PM PDT 24 34103549215 ps
T766 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3757846729 Mar 19 02:44:44 PM PDT 24 Mar 19 02:45:58 PM PDT 24 23302907431 ps
T95 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.221713491 Mar 19 02:54:54 PM PDT 24 Mar 19 02:56:58 PM PDT 24 23091283351 ps
T767 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3940117598 Mar 19 02:54:47 PM PDT 24 Mar 19 02:57:20 PM PDT 24 32110119034 ps
T768 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4049621266 Mar 19 02:54:45 PM PDT 24 Mar 19 02:55:15 PM PDT 24 12602051657 ps
T769 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.998088762 Mar 19 02:54:51 PM PDT 24 Mar 19 02:55:18 PM PDT 24 2212035357 ps
T770 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2473046825 Mar 19 02:54:50 PM PDT 24 Mar 19 02:57:44 PM PDT 24 14434004019 ps
T771 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4090707169 Mar 19 02:54:22 PM PDT 24 Mar 19 02:54:33 PM PDT 24 174045725 ps
T772 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2669255973 Mar 19 02:44:14 PM PDT 24 Mar 19 02:44:36 PM PDT 24 9484692105 ps
T96 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1519728490 Mar 19 02:54:39 PM PDT 24 Mar 19 02:54:52 PM PDT 24 770213899 ps
T773 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1555044803 Mar 19 02:54:28 PM PDT 24 Mar 19 02:54:37 PM PDT 24 1270300295 ps
T774 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3124268570 Mar 19 02:54:27 PM PDT 24 Mar 19 02:54:45 PM PDT 24 1323449989 ps
T775 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3237801785 Mar 19 02:44:35 PM PDT 24 Mar 19 02:47:20 PM PDT 24 4858044575 ps
T776 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.909221562 Mar 19 02:54:24 PM PDT 24 Mar 19 02:54:43 PM PDT 24 1086495551 ps
T777 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2643886281 Mar 19 02:54:50 PM PDT 24 Mar 19 02:55:24 PM PDT 24 19769763675 ps
T778 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4135881421 Mar 19 02:54:26 PM PDT 24 Mar 19 02:54:59 PM PDT 24 3826696074 ps
T779 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1557165391 Mar 19 02:44:50 PM PDT 24 Mar 19 02:45:22 PM PDT 24 12581286629 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2426180589 Mar 19 02:44:35 PM PDT 24 Mar 19 02:45:31 PM PDT 24 6053003307 ps
T780 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3522410620 Mar 19 02:44:40 PM PDT 24 Mar 19 02:45:02 PM PDT 24 5903015882 ps
T781 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.241749956 Mar 19 02:44:51 PM PDT 24 Mar 19 02:45:22 PM PDT 24 17407736517 ps
T782 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1249876409 Mar 19 02:44:31 PM PDT 24 Mar 19 02:45:27 PM PDT 24 3850510403 ps
T783 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2201085243 Mar 19 02:44:38 PM PDT 24 Mar 19 02:45:10 PM PDT 24 21331278134 ps
T784 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.570897199 Mar 19 02:54:54 PM PDT 24 Mar 19 02:55:18 PM PDT 24 3694397844 ps
T785 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3586973685 Mar 19 02:44:25 PM PDT 24 Mar 19 02:44:35 PM PDT 24 993114605 ps
T786 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2652016381 Mar 19 02:44:38 PM PDT 24 Mar 19 02:45:03 PM PDT 24 10506272759 ps
T787 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.915341255 Mar 19 02:54:53 PM PDT 24 Mar 19 02:55:23 PM PDT 24 5564000060 ps
T788 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.433523877 Mar 19 02:44:40 PM PDT 24 Mar 19 02:44:48 PM PDT 24 170758417 ps
T789 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2122951256 Mar 19 02:54:25 PM PDT 24 Mar 19 02:56:36 PM PDT 24 167561268698 ps
T127 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1032090708 Mar 19 02:44:22 PM PDT 24 Mar 19 02:47:01 PM PDT 24 1078619898 ps
T790 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.225134137 Mar 19 02:44:19 PM PDT 24 Mar 19 02:44:39 PM PDT 24 2182775015 ps
T791 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2580114062 Mar 19 02:54:35 PM PDT 24 Mar 19 02:55:07 PM PDT 24 16187721460 ps
T792 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2697737759 Mar 19 02:54:38 PM PDT 24 Mar 19 02:54:57 PM PDT 24 6136170992 ps
T91 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4043166018 Mar 19 02:54:40 PM PDT 24 Mar 19 02:54:59 PM PDT 24 1889695349 ps
T793 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2228880166 Mar 19 02:44:31 PM PDT 24 Mar 19 02:46:12 PM PDT 24 3982691670 ps
T794 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.540234750 Mar 19 02:54:33 PM PDT 24 Mar 19 02:54:51 PM PDT 24 7057856575 ps
T795 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1232117633 Mar 19 02:44:30 PM PDT 24 Mar 19 02:44:53 PM PDT 24 8817959909 ps
T796 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.587772098 Mar 19 02:44:32 PM PDT 24 Mar 19 02:47:16 PM PDT 24 4312286461 ps
T797 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2610663541 Mar 19 02:44:38 PM PDT 24 Mar 19 02:44:58 PM PDT 24 1909936050 ps
T798 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.714417938 Mar 19 02:54:38 PM PDT 24 Mar 19 02:55:06 PM PDT 24 8355311013 ps
T799 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.954812714 Mar 19 02:54:46 PM PDT 24 Mar 19 02:55:15 PM PDT 24 10954430959 ps
T800 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.721548122 Mar 19 02:44:32 PM PDT 24 Mar 19 02:44:44 PM PDT 24 696397658 ps
T801 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.287375079 Mar 19 02:54:51 PM PDT 24 Mar 19 02:56:37 PM PDT 24 8519445195 ps
T129 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3244429365 Mar 19 02:54:38 PM PDT 24 Mar 19 02:56:00 PM PDT 24 867818214 ps
T802 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1758953023 Mar 19 02:44:33 PM PDT 24 Mar 19 02:45:04 PM PDT 24 8020364549 ps
T803 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2135515357 Mar 19 02:44:14 PM PDT 24 Mar 19 02:44:39 PM PDT 24 10671117728 ps
T804 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2147120163 Mar 19 02:44:41 PM PDT 24 Mar 19 02:45:11 PM PDT 24 7142629214 ps
T805 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1234640868 Mar 19 02:54:46 PM PDT 24 Mar 19 02:56:26 PM PDT 24 13485506895 ps
T806 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.36926224 Mar 19 02:54:42 PM PDT 24 Mar 19 02:56:28 PM PDT 24 8771802420 ps
T807 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2097037195 Mar 19 02:44:32 PM PDT 24 Mar 19 02:44:40 PM PDT 24 345555249 ps
T808 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.649434098 Mar 19 02:54:54 PM PDT 24 Mar 19 02:55:22 PM PDT 24 23533276921 ps
T128 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1822524404 Mar 19 02:54:34 PM PDT 24 Mar 19 02:57:25 PM PDT 24 14797476982 ps
T809 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3158420878 Mar 19 02:44:40 PM PDT 24 Mar 19 02:44:55 PM PDT 24 1004760195 ps
T810 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.826715216 Mar 19 02:54:47 PM PDT 24 Mar 19 02:55:13 PM PDT 24 21566005514 ps
T811 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2616564159 Mar 19 02:44:13 PM PDT 24 Mar 19 02:44:21 PM PDT 24 178091579 ps
T812 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1304382447 Mar 19 02:44:35 PM PDT 24 Mar 19 02:44:47 PM PDT 24 345804402 ps
T813 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1335538242 Mar 19 02:54:47 PM PDT 24 Mar 19 02:54:59 PM PDT 24 1547396535 ps
T814 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.876817139 Mar 19 02:54:35 PM PDT 24 Mar 19 02:57:09 PM PDT 24 847317667 ps
T815 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4146863155 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:46 PM PDT 24 176801499 ps
T816 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.140123927 Mar 19 02:54:51 PM PDT 24 Mar 19 02:55:20 PM PDT 24 12361864063 ps
T817 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4074176438 Mar 19 02:44:44 PM PDT 24 Mar 19 02:44:56 PM PDT 24 404686918 ps
T818 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3105433319 Mar 19 02:44:54 PM PDT 24 Mar 19 02:45:12 PM PDT 24 9855990802 ps
T819 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4045731075 Mar 19 02:54:34 PM PDT 24 Mar 19 02:57:26 PM PDT 24 6588672143 ps
T820 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1642614731 Mar 19 02:54:50 PM PDT 24 Mar 19 02:57:40 PM PDT 24 2744173304 ps
T821 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1271507637 Mar 19 02:44:41 PM PDT 24 Mar 19 02:45:09 PM PDT 24 2471195753 ps
T822 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2035020726 Mar 19 02:44:13 PM PDT 24 Mar 19 02:44:34 PM PDT 24 26779599497 ps
T823 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3779724947 Mar 19 02:54:44 PM PDT 24 Mar 19 02:55:06 PM PDT 24 2040584211 ps
T824 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.220617503 Mar 19 02:54:45 PM PDT 24 Mar 19 02:56:07 PM PDT 24 943432881 ps
T825 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3510712801 Mar 19 02:44:36 PM PDT 24 Mar 19 02:44:45 PM PDT 24 202790784 ps
T826 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2956885737 Mar 19 02:54:34 PM PDT 24 Mar 19 02:54:43 PM PDT 24 172748954 ps
T827 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1110567159 Mar 19 02:54:25 PM PDT 24 Mar 19 02:54:52 PM PDT 24 6614664524 ps
T828 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1823575850 Mar 19 02:54:40 PM PDT 24 Mar 19 02:55:01 PM PDT 24 2128484964 ps
T829 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2259407928 Mar 19 02:54:25 PM PDT 24 Mar 19 02:55:57 PM PDT 24 8625126598 ps
T830 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.260044204 Mar 19 02:44:22 PM PDT 24 Mar 19 02:44:34 PM PDT 24 171054145 ps
T831 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.641128490 Mar 19 02:44:38 PM PDT 24 Mar 19 02:44:50 PM PDT 24 438978885 ps
T832 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1665097706 Mar 19 02:54:44 PM PDT 24 Mar 19 02:54:52 PM PDT 24 2743788388 ps
T833 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2519850939 Mar 19 02:44:39 PM PDT 24 Mar 19 02:45:08 PM PDT 24 3130975832 ps
T834 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1180805492 Mar 19 02:54:28 PM PDT 24 Mar 19 02:54:57 PM PDT 24 6341462676 ps
T835 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.143735891 Mar 19 02:44:50 PM PDT 24 Mar 19 02:45:04 PM PDT 24 331761784 ps
T836 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.453251082 Mar 19 02:44:31 PM PDT 24 Mar 19 02:44:42 PM PDT 24 2449807629 ps
T837 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3700619350 Mar 19 02:44:35 PM PDT 24 Mar 19 02:46:49 PM PDT 24 33410732150 ps
T838 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.369311250 Mar 19 02:44:26 PM PDT 24 Mar 19 02:45:00 PM PDT 24 9138494943 ps
T839 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2949649107 Mar 19 02:44:16 PM PDT 24 Mar 19 02:44:46 PM PDT 24 3703657070 ps
T840 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2574528020 Mar 19 02:54:45 PM PDT 24 Mar 19 02:57:59 PM PDT 24 96286083296 ps
T841 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2590087673 Mar 19 02:44:20 PM PDT 24 Mar 19 02:45:57 PM PDT 24 3017494363 ps
T842 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.617240064 Mar 19 02:54:50 PM PDT 24 Mar 19 02:55:19 PM PDT 24 2969872533 ps
T843 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.336423300 Mar 19 02:54:54 PM PDT 24 Mar 19 02:56:23 PM PDT 24 32978752029 ps
T844 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1949672007 Mar 19 02:44:38 PM PDT 24 Mar 19 02:45:08 PM PDT 24 3811321739 ps
T845 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2874778450 Mar 19 02:44:13 PM PDT 24 Mar 19 02:44:50 PM PDT 24 41554637983 ps
T846 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1798176590 Mar 19 02:44:32 PM PDT 24 Mar 19 02:45:56 PM PDT 24 1244164141 ps
T847 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.370650171 Mar 19 02:54:54 PM PDT 24 Mar 19 02:55:19 PM PDT 24 3256455033 ps
T848 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2803998383 Mar 19 02:44:14 PM PDT 24 Mar 19 02:44:28 PM PDT 24 3957207951 ps
T849 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.624388023 Mar 19 02:44:37 PM PDT 24 Mar 19 02:45:34 PM PDT 24 5744997417 ps
T850 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2941608388 Mar 19 02:54:25 PM PDT 24 Mar 19 02:54:55 PM PDT 24 5185188087 ps
T851 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1819638426 Mar 19 02:54:42 PM PDT 24 Mar 19 02:55:04 PM PDT 24 4805371604 ps
T852 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.812879317 Mar 19 02:44:33 PM PDT 24 Mar 19 02:44:56 PM PDT 24 3070451981 ps
T853 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1454091751 Mar 19 02:54:31 PM PDT 24 Mar 19 02:54:40 PM PDT 24 688563360 ps
T854 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3134577480 Mar 19 02:54:35 PM PDT 24 Mar 19 02:54:50 PM PDT 24 354709122 ps
T855 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1216809561 Mar 19 02:44:22 PM PDT 24 Mar 19 02:44:30 PM PDT 24 688733424 ps
T856 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.889448624 Mar 19 02:44:31 PM PDT 24 Mar 19 02:44:56 PM PDT 24 12022116022 ps
T857 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1179443702 Mar 19 02:54:29 PM PDT 24 Mar 19 02:55:00 PM PDT 24 7752893714 ps
T858 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2714781759 Mar 19 02:44:18 PM PDT 24 Mar 19 02:44:45 PM PDT 24 6605161627 ps
T859 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3898777769 Mar 19 02:54:31 PM PDT 24 Mar 19 02:54:42 PM PDT 24 1373044817 ps
T860 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1325203256 Mar 19 02:44:39 PM PDT 24 Mar 19 02:46:34 PM PDT 24 53962460765 ps
T861 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3180811008 Mar 19 02:54:35 PM PDT 24 Mar 19 02:54:46 PM PDT 24 3284838862 ps
T862 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3024344757 Mar 19 02:54:38 PM PDT 24 Mar 19 02:55:11 PM PDT 24 16462965439 ps
T863 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3308589869 Mar 19 02:54:54 PM PDT 24 Mar 19 02:55:14 PM PDT 24 2048039186 ps
T864 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2844621061 Mar 19 02:44:51 PM PDT 24 Mar 19 02:46:21 PM PDT 24 1670274612 ps
T865 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1943556870 Mar 19 02:54:35 PM PDT 24 Mar 19 02:55:07 PM PDT 24 21540198393 ps
T866 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1720901087 Mar 19 02:54:51 PM PDT 24 Mar 19 02:55:06 PM PDT 24 1564951503 ps
T867 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2228863212 Mar 19 02:54:29 PM PDT 24 Mar 19 02:54:59 PM PDT 24 4066877736 ps
T868 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3158579689 Mar 19 02:44:49 PM PDT 24 Mar 19 02:46:13 PM PDT 24 28431820526 ps
T869 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1876733150 Mar 19 02:44:31 PM PDT 24 Mar 19 02:44:42 PM PDT 24 422356299 ps
T870 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.441183652 Mar 19 02:44:42 PM PDT 24 Mar 19 02:46:18 PM PDT 24 10743273025 ps
T871 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3799277415 Mar 19 02:54:37 PM PDT 24 Mar 19 02:55:08 PM PDT 24 13049126885 ps
T872 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3830557193 Mar 19 02:44:22 PM PDT 24 Mar 19 02:44:32 PM PDT 24 186813369 ps
T873 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3680334155 Mar 19 02:54:54 PM PDT 24 Mar 19 02:55:15 PM PDT 24 4467257557 ps
T874 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1410081807 Mar 19 02:54:34 PM PDT 24 Mar 19 02:54:46 PM PDT 24 825841796 ps
T875 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1062926870 Mar 19 02:44:39 PM PDT 24 Mar 19 02:45:12 PM PDT 24 16767005228 ps
T876 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3365916732 Mar 19 02:54:37 PM PDT 24 Mar 19 02:55:06 PM PDT 24 7180924378 ps
T877 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.236662097 Mar 19 02:44:34 PM PDT 24 Mar 19 02:44:47 PM PDT 24 2352617602 ps
T878 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2740525765 Mar 19 02:54:30 PM PDT 24 Mar 19 02:54:38 PM PDT 24 689669173 ps
T879 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.527319344 Mar 19 02:54:40 PM PDT 24 Mar 19 02:54:58 PM PDT 24 5638404613 ps
T880 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1393103984 Mar 19 02:44:54 PM PDT 24 Mar 19 02:47:32 PM PDT 24 1031534880 ps
T881 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.412873686 Mar 19 02:44:39 PM PDT 24 Mar 19 02:45:11 PM PDT 24 7854226704 ps
T882 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3142260873 Mar 19 02:44:21 PM PDT 24 Mar 19 02:44:55 PM PDT 24 3961975279 ps
T883 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3884978032 Mar 19 02:44:17 PM PDT 24 Mar 19 02:44:43 PM PDT 24 4940418556 ps
T884 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.580483455 Mar 19 02:44:14 PM PDT 24 Mar 19 02:44:22 PM PDT 24 688544780 ps
T885 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2454202838 Mar 19 02:44:31 PM PDT 24 Mar 19 02:44:40 PM PDT 24 171082136 ps
T130 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2835274377 Mar 19 02:54:51 PM PDT 24 Mar 19 02:57:39 PM PDT 24 2293783636 ps
T886 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2073892016 Mar 19 02:54:37 PM PDT 24 Mar 19 02:54:58 PM PDT 24 2292194375 ps
T887 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1515261123 Mar 19 02:44:39 PM PDT 24 Mar 19 02:45:09 PM PDT 24 3330075018 ps
T888 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4130121588 Mar 19 02:54:39 PM PDT 24 Mar 19 02:54:58 PM PDT 24 1735342297 ps
T889 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1759391557 Mar 19 02:54:41 PM PDT 24 Mar 19 02:57:55 PM PDT 24 25583321755 ps
T890 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2217054996 Mar 19 02:54:38 PM PDT 24 Mar 19 02:57:24 PM PDT 24 2448140233 ps
T891 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2529405719 Mar 19 02:44:44 PM PDT 24 Mar 19 02:45:07 PM PDT 24 11284921909 ps
T892 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2257727728 Mar 19 02:54:24 PM PDT 24 Mar 19 02:54:44 PM PDT 24 2173052195 ps
T893 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.790191905 Mar 19 02:54:48 PM PDT 24 Mar 19 02:55:26 PM PDT 24 900978694 ps
T894 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3806793747 Mar 19 02:54:51 PM PDT 24 Mar 19 02:55:07 PM PDT 24 4595729992 ps
T895 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2919002986 Mar 19 02:54:37 PM PDT 24 Mar 19 02:55:05 PM PDT 24 6739064541 ps
T896 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3905739842 Mar 19 02:54:26 PM PDT 24 Mar 19 02:54:53 PM PDT 24 52675817874 ps
T897 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3314358238 Mar 19 02:54:46 PM PDT 24 Mar 19 02:55:00 PM PDT 24 3286405262 ps
T898 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.333626921 Mar 19 02:54:38 PM PDT 24 Mar 19 02:54:50 PM PDT 24 167633620 ps
T899 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4143026445 Mar 19 02:44:39 PM PDT 24 Mar 19 02:46:38 PM PDT 24 57307680110 ps
T900 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2872273156 Mar 19 02:54:25 PM PDT 24 Mar 19 02:54:52 PM PDT 24 2854043616 ps
T901 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.832265252 Mar 19 02:54:35 PM PDT 24 Mar 19 02:54:55 PM PDT 24 2142010727 ps
T902 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.718221863 Mar 19 02:54:28 PM PDT 24 Mar 19 02:54:45 PM PDT 24 3600077956 ps
T903 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2760212428 Mar 19 02:54:46 PM PDT 24 Mar 19 02:57:27 PM PDT 24 55721694054 ps
T904 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.391647793 Mar 19 02:54:49 PM PDT 24 Mar 19 02:55:10 PM PDT 24 4490307023 ps
T905 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2589226283 Mar 19 02:54:24 PM PDT 24 Mar 19 02:54:33 PM PDT 24 170760816 ps
T906 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.66102714 Mar 19 02:54:38 PM PDT 24 Mar 19 02:56:18 PM PDT 24 11224278230 ps
T907 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.216895155 Mar 19 02:44:40 PM PDT 24 Mar 19 02:45:04 PM PDT 24 1942739757 ps
T908 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3948598674 Mar 19 02:54:39 PM PDT 24 Mar 19 02:54:49 PM PDT 24 1036524653 ps
T909 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4040548352 Mar 19 02:54:44 PM PDT 24 Mar 19 02:54:53 PM PDT 24 2350682017 ps
T910 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.662471434 Mar 19 02:54:33 PM PDT 24 Mar 19 02:55:03 PM PDT 24 3731954095 ps
T911 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2395317053 Mar 19 02:54:40 PM PDT 24 Mar 19 02:55:18 PM PDT 24 2860631557 ps
T912 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3717411593 Mar 19 02:54:52 PM PDT 24 Mar 19 02:55:01 PM PDT 24 374415123 ps
T913 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.142113209 Mar 19 02:44:22 PM PDT 24 Mar 19 02:44:44 PM PDT 24 2719110334 ps
T914 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3877426792 Mar 19 02:54:39 PM PDT 24 Mar 19 02:55:04 PM PDT 24 10823712481 ps
T915 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1485088406 Mar 19 02:54:25 PM PDT 24 Mar 19 02:54:55 PM PDT 24 4582603911 ps
T916 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1987674431 Mar 19 02:44:29 PM PDT 24 Mar 19 02:45:08 PM PDT 24 17980840562 ps
T917 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1866754444 Mar 19 02:44:20 PM PDT 24 Mar 19 02:44:43 PM PDT 24 2651923750 ps
T918 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.974314042 Mar 19 02:44:32 PM PDT 24 Mar 19 02:44:40 PM PDT 24 214099921 ps
T919 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3167650629 Mar 19 02:54:55 PM PDT 24 Mar 19 02:55:31 PM PDT 24 720299126 ps
T920 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3747203797 Mar 19 02:54:40 PM PDT 24 Mar 19 02:57:32 PM PDT 24 4174355065 ps
T921 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2020485657 Mar 19 02:54:46 PM PDT 24 Mar 19 02:55:12 PM PDT 24 3314380876 ps
T922 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2752192422 Mar 19 02:54:38 PM PDT 24 Mar 19 02:54:47 PM PDT 24 972342346 ps
T923 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.322258999 Mar 19 02:44:19 PM PDT 24 Mar 19 02:44:33 PM PDT 24 3739923312 ps

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2024508880
Short name T5
Test name
Test status
Simulation time 6308010816 ps
CPU time 83.96 seconds
Started Mar 19 03:09:12 PM PDT 24
Finished Mar 19 03:10:37 PM PDT 24
Peak memory 236552 kb
Host smart-b52dd2cb-bd33-49e5-812d-180e6ec22ce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024508880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2024508880
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3705820477
Short name T11
Test name
Test status
Simulation time 61085571786 ps
CPU time 5793.73 seconds
Started Mar 19 03:09:04 PM PDT 24
Finished Mar 19 04:45:39 PM PDT 24
Peak memory 235612 kb
Host smart-ce135b03-9003-417b-bed5-3b206c3798f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705820477 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3705820477
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1500876277
Short name T48
Test name
Test status
Simulation time 137329166470 ps
CPU time 273.66 seconds
Started Mar 19 02:48:58 PM PDT 24
Finished Mar 19 02:53:32 PM PDT 24
Peak memory 232584 kb
Host smart-9e11d307-19a4-40a0-b605-e9fb9d9fa7a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500876277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1500876277
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1086725777
Short name T12
Test name
Test status
Simulation time 82007369437 ps
CPU time 2327.45 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:47:58 PM PDT 24
Peak memory 228528 kb
Host smart-f39a2994-7a6c-40e3-b4a4-95a096ac2f76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086725777 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1086725777
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3322486013
Short name T137
Test name
Test status
Simulation time 2493348889 ps
CPU time 157.1 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:11:14 PM PDT 24
Peak memory 233496 kb
Host smart-98f07a3f-d172-460c-9245-1d327d56ec59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322486013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3322486013
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2289449830
Short name T123
Test name
Test status
Simulation time 4065580187 ps
CPU time 175.97 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:47:36 PM PDT 24
Peak memory 213592 kb
Host smart-edffb266-97d6-4e0c-91d4-ef0808687203
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289449830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2289449830
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.876560481
Short name T29
Test name
Test status
Simulation time 889666459 ps
CPU time 104.42 seconds
Started Mar 19 02:48:41 PM PDT 24
Finished Mar 19 02:50:25 PM PDT 24
Peak memory 236556 kb
Host smart-2cf67c98-37a5-42c7-b742-ad4a8211ca92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876560481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.876560481
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.88520242
Short name T71
Test name
Test status
Simulation time 98405948212 ps
CPU time 193.11 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 215068 kb
Host smart-fd00abc8-e100-41b7-a2db-000575dbec22
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88520242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pas
sthru_mem_tl_intg_err.88520242
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1093501506
Short name T120
Test name
Test status
Simulation time 9074209564 ps
CPU time 175.99 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:47:09 PM PDT 24
Peak memory 213940 kb
Host smart-dc58bef8-8e3b-4f03-a5a4-a64c04f83c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093501506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1093501506
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.477089574
Short name T32
Test name
Test status
Simulation time 532398283 ps
CPU time 5.78 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:08:50 PM PDT 24
Peak memory 210864 kb
Host smart-5c650dc5-4e64-4c27-8e05-94e4ca915e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477089574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.477089574
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1927137302
Short name T16
Test name
Test status
Simulation time 92449573348 ps
CPU time 1822.73 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:38:52 PM PDT 24
Peak memory 235604 kb
Host smart-dd38811e-4734-4e9f-921c-d11d7c5d8a0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927137302 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1927137302
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3244429365
Short name T129
Test name
Test status
Simulation time 867818214 ps
CPU time 81.57 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 212956 kb
Host smart-1467380c-483a-4bf3-a390-b0de919f6786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244429365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3244429365
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.221713491
Short name T95
Test name
Test status
Simulation time 23091283351 ps
CPU time 123.29 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:56:58 PM PDT 24
Peak memory 215408 kb
Host smart-1ab91a98-f238-499e-9416-5a2bef35c759
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221713491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.221713491
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1951591194
Short name T80
Test name
Test status
Simulation time 2700353447 ps
CPU time 18.11 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 219076 kb
Host smart-600fadea-c077-40e1-b19d-db09744d6f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951591194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1951591194
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3900746399
Short name T56
Test name
Test status
Simulation time 51008456437 ps
CPU time 25.79 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:09:07 PM PDT 24
Peak memory 211808 kb
Host smart-8691f948-0983-4bcc-94e6-733d2c14883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900746399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3900746399
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2649120255
Short name T197
Test name
Test status
Simulation time 177058414 ps
CPU time 9.36 seconds
Started Mar 19 02:48:51 PM PDT 24
Finished Mar 19 02:49:00 PM PDT 24
Peak memory 211404 kb
Host smart-b5a31461-3269-41ed-a336-d966c5b62f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649120255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2649120255
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.842960637
Short name T25
Test name
Test status
Simulation time 4746259679 ps
CPU time 33.66 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:49:33 PM PDT 24
Peak memory 211728 kb
Host smart-b3a829ba-05a0-43a8-8bb5-628ffb633b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842960637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.842960637
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2727275356
Short name T72
Test name
Test status
Simulation time 37188722664 ps
CPU time 164.17 seconds
Started Mar 19 02:44:12 PM PDT 24
Finished Mar 19 02:46:56 PM PDT 24
Peak memory 215008 kb
Host smart-e27a2292-44fb-4d02-b81f-eb4ab56f75c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727275356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2727275356
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2465260688
Short name T98
Test name
Test status
Simulation time 1594259052 ps
CPU time 14.07 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:22 PM PDT 24
Peak memory 210836 kb
Host smart-7465e86f-ee2b-49d5-b4e2-9f9859ef47aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465260688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2465260688
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2212387159
Short name T556
Test name
Test status
Simulation time 199906504574 ps
CPU time 1901.36 seconds
Started Mar 19 02:49:17 PM PDT 24
Finished Mar 19 03:20:59 PM PDT 24
Peak memory 235580 kb
Host smart-6f12fe99-3995-47dc-b866-7f1bbaca4180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212387159 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2212387159
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2102321546
Short name T78
Test name
Test status
Simulation time 14166877374 ps
CPU time 29.38 seconds
Started Mar 19 02:44:20 PM PDT 24
Finished Mar 19 02:44:49 PM PDT 24
Peak memory 211784 kb
Host smart-acfe1258-85db-4168-b8bc-4833fe3b2e51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102321546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2102321546
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3134453368
Short name T92
Test name
Test status
Simulation time 10811224088 ps
CPU time 22.61 seconds
Started Mar 19 02:54:27 PM PDT 24
Finished Mar 19 02:54:51 PM PDT 24
Peak memory 211896 kb
Host smart-973a8241-2cce-4a0b-becf-d8ac280cfe33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134453368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3134453368
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2035020726
Short name T822
Test name
Test status
Simulation time 26779599497 ps
CPU time 20.59 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:34 PM PDT 24
Peak memory 211552 kb
Host smart-5dae27dc-ad5c-4e0c-b155-89769a5c08d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035020726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2035020726
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.832265252
Short name T901
Test name
Test status
Simulation time 2142010727 ps
CPU time 20.59 seconds
Started Mar 19 02:54:35 PM PDT 24
Finished Mar 19 02:54:55 PM PDT 24
Peak memory 210960 kb
Host smart-e077352c-64b4-406a-9ba1-5f7171b28f41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832265252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.832265252
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1110567159
Short name T827
Test name
Test status
Simulation time 6614664524 ps
CPU time 25.56 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 212000 kb
Host smart-7b390f28-b384-463b-a779-b618baccf773
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110567159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1110567159
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3290196382
Short name T739
Test name
Test status
Simulation time 7525778567 ps
CPU time 23.03 seconds
Started Mar 19 02:44:15 PM PDT 24
Finished Mar 19 02:44:38 PM PDT 24
Peak memory 211840 kb
Host smart-563d7250-07e7-4afa-8869-7df25df162f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290196382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3290196382
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2135515357
Short name T803
Test name
Test status
Simulation time 10671117728 ps
CPU time 24.96 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:39 PM PDT 24
Peak memory 217220 kb
Host smart-1123edb3-7c8f-4b93-9c6e-e36f0896358c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135515357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2135515357
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4135881421
Short name T778
Test name
Test status
Simulation time 3826696074 ps
CPU time 30.4 seconds
Started Mar 19 02:54:26 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 217920 kb
Host smart-7038ee8e-8287-4c50-a904-2972ca06c051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135881421 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4135881421
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1866754444
Short name T917
Test name
Test status
Simulation time 2651923750 ps
CPU time 22.8 seconds
Started Mar 19 02:44:20 PM PDT 24
Finished Mar 19 02:44:43 PM PDT 24
Peak memory 211808 kb
Host smart-d3e11aa7-7cf0-450a-b982-5a4d22a64579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866754444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1866754444
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.879021618
Short name T90
Test name
Test status
Simulation time 687856188 ps
CPU time 8.16 seconds
Started Mar 19 02:54:24 PM PDT 24
Finished Mar 19 02:54:33 PM PDT 24
Peak memory 210920 kb
Host smart-b8662fa1-91ae-483d-ba4f-e3621a3171b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879021618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.879021618
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2714781759
Short name T858
Test name
Test status
Simulation time 6605161627 ps
CPU time 27.16 seconds
Started Mar 19 02:44:18 PM PDT 24
Finished Mar 19 02:44:45 PM PDT 24
Peak memory 210860 kb
Host smart-fb4a8d06-458d-4d84-8f2d-f1e63dd66b42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714781759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2714781759
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3905739842
Short name T896
Test name
Test status
Simulation time 52675817874 ps
CPU time 24.76 seconds
Started Mar 19 02:54:26 PM PDT 24
Finished Mar 19 02:54:53 PM PDT 24
Peak memory 210888 kb
Host smart-5fd05e98-0a0b-416e-a286-d75f5a81c91b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905739842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3905739842
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2589226283
Short name T905
Test name
Test status
Simulation time 170760816 ps
CPU time 8.14 seconds
Started Mar 19 02:54:24 PM PDT 24
Finished Mar 19 02:54:33 PM PDT 24
Peak memory 210808 kb
Host smart-486252c1-5e0d-4bae-9187-2e290e0365d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589226283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2589226283
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.681272918
Short name T683
Test name
Test status
Simulation time 459927319 ps
CPU time 7.94 seconds
Started Mar 19 02:44:19 PM PDT 24
Finished Mar 19 02:44:27 PM PDT 24
Peak memory 210776 kb
Host smart-f8f27695-3968-45b9-a3a3-f3f892a823dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681272918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
681272918
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.953326648
Short name T733
Test name
Test status
Simulation time 6871104199 ps
CPU time 38.18 seconds
Started Mar 19 02:54:24 PM PDT 24
Finished Mar 19 02:55:03 PM PDT 24
Peak memory 213776 kb
Host smart-08b8e581-dd7f-4b5c-981a-0652da90f29a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953326648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.953326648
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2803998383
Short name T848
Test name
Test status
Simulation time 3957207951 ps
CPU time 14.88 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:28 PM PDT 24
Peak memory 211024 kb
Host smart-9729f6de-43cc-461d-801a-bf29b4d12710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803998383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2803998383
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3524934770
Short name T754
Test name
Test status
Simulation time 3283126267 ps
CPU time 13.85 seconds
Started Mar 19 02:54:27 PM PDT 24
Finished Mar 19 02:54:42 PM PDT 24
Peak memory 210284 kb
Host smart-0370a6dd-ddd0-4f7a-b28b-3c29dfecbcb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524934770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3524934770
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2531109545
Short name T691
Test name
Test status
Simulation time 174391834 ps
CPU time 11.79 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:25 PM PDT 24
Peak memory 216076 kb
Host smart-1a889860-e2f1-468d-a2d5-f701c148655b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531109545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2531109545
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.718221863
Short name T902
Test name
Test status
Simulation time 3600077956 ps
CPU time 16.66 seconds
Started Mar 19 02:54:28 PM PDT 24
Finished Mar 19 02:54:45 PM PDT 24
Peak memory 217224 kb
Host smart-12022619-2137-46b7-8a01-910a0e7734b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718221863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.718221863
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2939248155
Short name T757
Test name
Test status
Simulation time 14028147137 ps
CPU time 97.08 seconds
Started Mar 19 02:54:29 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 213520 kb
Host smart-20ee2752-916b-4b2a-9aaf-ecf407536efe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939248155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2939248155
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1555044803
Short name T773
Test name
Test status
Simulation time 1270300295 ps
CPU time 8.4 seconds
Started Mar 19 02:54:28 PM PDT 24
Finished Mar 19 02:54:37 PM PDT 24
Peak memory 210936 kb
Host smart-1349babc-10d2-4a13-87ff-117e9487bd93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555044803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1555044803
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.580483455
Short name T884
Test name
Test status
Simulation time 688544780 ps
CPU time 8.12 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:22 PM PDT 24
Peak memory 210872 kb
Host smart-18f5d5e0-99be-4b5b-a42b-3e78252b3477
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580483455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.580483455
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1283937290
Short name T727
Test name
Test status
Simulation time 10902662429 ps
CPU time 25.46 seconds
Started Mar 19 02:44:15 PM PDT 24
Finished Mar 19 02:44:41 PM PDT 24
Peak memory 211912 kb
Host smart-577c6111-035a-49b6-8707-dd21aa855084
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283937290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1283937290
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3124268570
Short name T774
Test name
Test status
Simulation time 1323449989 ps
CPU time 16.73 seconds
Started Mar 19 02:54:27 PM PDT 24
Finished Mar 19 02:54:45 PM PDT 24
Peak memory 211052 kb
Host smart-16a82b7e-3bf1-4e4e-9d61-1873e40dd3b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124268570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3124268570
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2118112772
Short name T63
Test name
Test status
Simulation time 999679080 ps
CPU time 15.55 seconds
Started Mar 19 02:44:15 PM PDT 24
Finished Mar 19 02:44:31 PM PDT 24
Peak memory 211780 kb
Host smart-1a360c27-370b-4ce2-8516-6f957776f9a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118112772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2118112772
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3134577480
Short name T854
Test name
Test status
Simulation time 354709122 ps
CPU time 15.61 seconds
Started Mar 19 02:54:35 PM PDT 24
Finished Mar 19 02:54:50 PM PDT 24
Peak memory 211572 kb
Host smart-fce399ec-21dc-4e5e-a05c-89f5aca52022
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134577480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3134577480
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.322258999
Short name T923
Test name
Test status
Simulation time 3739923312 ps
CPU time 13.93 seconds
Started Mar 19 02:44:19 PM PDT 24
Finished Mar 19 02:44:33 PM PDT 24
Peak memory 216432 kb
Host smart-16c58949-2c28-45cd-bfd6-7be87b8987d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322258999 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.322258999
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4090707169
Short name T771
Test name
Test status
Simulation time 174045725 ps
CPU time 8.44 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:33 PM PDT 24
Peak memory 214004 kb
Host smart-7884bdcd-d8c6-481f-82a2-13d9ad2dc592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090707169 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4090707169
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1179443702
Short name T857
Test name
Test status
Simulation time 7752893714 ps
CPU time 30.36 seconds
Started Mar 19 02:54:29 PM PDT 24
Finished Mar 19 02:55:00 PM PDT 24
Peak memory 212116 kb
Host smart-a8cf851b-7601-46fd-ab2e-1ac3e96e6afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179443702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1179443702
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2949649107
Short name T839
Test name
Test status
Simulation time 3703657070 ps
CPU time 29.56 seconds
Started Mar 19 02:44:16 PM PDT 24
Finished Mar 19 02:44:46 PM PDT 24
Peak memory 211436 kb
Host smart-6c905805-a564-4f82-b2e8-d1bd39ad672e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949649107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2949649107
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2616564159
Short name T811
Test name
Test status
Simulation time 178091579 ps
CPU time 8.19 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:21 PM PDT 24
Peak memory 210784 kb
Host smart-7a861ea1-5cf5-4b94-b86e-12b05aff703a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616564159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2616564159
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2872273156
Short name T900
Test name
Test status
Simulation time 2854043616 ps
CPU time 24.93 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 210892 kb
Host smart-332af435-95de-4ec7-ba22-903f4af3a89b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872273156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2872273156
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2740525765
Short name T878
Test name
Test status
Simulation time 689669173 ps
CPU time 8.07 seconds
Started Mar 19 02:54:30 PM PDT 24
Finished Mar 19 02:54:38 PM PDT 24
Peak memory 210848 kb
Host smart-4992bf8d-f5cf-4c8d-910c-2cb0a9a321ce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740525765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2740525765
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4257585697
Short name T738
Test name
Test status
Simulation time 496101534 ps
CPU time 11.89 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:26 PM PDT 24
Peak memory 210800 kb
Host smart-23cd55dd-05a0-4a0c-88bd-56c837a919f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257585697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4257585697
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2997314527
Short name T728
Test name
Test status
Simulation time 11924102736 ps
CPU time 72.41 seconds
Started Mar 19 02:54:27 PM PDT 24
Finished Mar 19 02:55:41 PM PDT 24
Peak memory 214080 kb
Host smart-a1c174a7-b0d5-4a1d-b6e4-c64dd5edcce3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997314527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2997314527
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3099632304
Short name T75
Test name
Test status
Simulation time 59150597732 ps
CPU time 121.61 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:46:14 PM PDT 24
Peak memory 219128 kb
Host smart-430754a1-187e-4d03-a7f7-3baec5d7429c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099632304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3099632304
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1180805492
Short name T834
Test name
Test status
Simulation time 6341462676 ps
CPU time 28.95 seconds
Started Mar 19 02:54:28 PM PDT 24
Finished Mar 19 02:54:57 PM PDT 24
Peak memory 212492 kb
Host smart-2c116a2b-4de4-4cf1-a22d-a618f37a49ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180805492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1180805492
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4126756452
Short name T707
Test name
Test status
Simulation time 959714415 ps
CPU time 14.61 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:29 PM PDT 24
Peak memory 210880 kb
Host smart-865e5b4a-177d-4450-aead-caf28afb55a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126756452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4126756452
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2257727728
Short name T892
Test name
Test status
Simulation time 2173052195 ps
CPU time 18.99 seconds
Started Mar 19 02:54:24 PM PDT 24
Finished Mar 19 02:54:44 PM PDT 24
Peak memory 216952 kb
Host smart-bdde898f-0c75-4dba-8033-ba06219f81f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257727728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2257727728
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3884978032
Short name T883
Test name
Test status
Simulation time 4940418556 ps
CPU time 26.48 seconds
Started Mar 19 02:44:17 PM PDT 24
Finished Mar 19 02:44:43 PM PDT 24
Peak memory 217664 kb
Host smart-0b155dd7-7e0e-4766-a410-4f296188517a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884978032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3884978032
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2091723351
Short name T60
Test name
Test status
Simulation time 2412522386 ps
CPU time 168.81 seconds
Started Mar 19 02:54:31 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 213744 kb
Host smart-a050c686-2e33-495d-bc28-6a62720ebb87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091723351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2091723351
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2452547004
Short name T744
Test name
Test status
Simulation time 519638316 ps
CPU time 88.98 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:45:42 PM PDT 24
Peak memory 213036 kb
Host smart-09fedbaa-eec1-40f5-8f66-82f269c8213d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452547004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2452547004
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1836064464
Short name T692
Test name
Test status
Simulation time 3523390823 ps
CPU time 29.55 seconds
Started Mar 19 02:44:35 PM PDT 24
Finished Mar 19 02:45:05 PM PDT 24
Peak memory 215160 kb
Host smart-ff569ed5-1901-4ba8-8031-7b440d4b8ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836064464 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1836064464
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.714417938
Short name T798
Test name
Test status
Simulation time 8355311013 ps
CPU time 28.67 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 216520 kb
Host smart-548921d9-7e19-4a0f-ad42-d69f99048600
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714417938 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.714417938
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1519728490
Short name T96
Test name
Test status
Simulation time 770213899 ps
CPU time 13.31 seconds
Started Mar 19 02:54:39 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 210888 kb
Host smart-eea29892-b846-4893-ab04-35415765a131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519728490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1519728490
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1758953023
Short name T802
Test name
Test status
Simulation time 8020364549 ps
CPU time 31.22 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:45:04 PM PDT 24
Peak memory 211620 kb
Host smart-40b4c3b2-1e6d-4578-a756-3d15a9fb448b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758953023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1758953023
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2395317053
Short name T911
Test name
Test status
Simulation time 2860631557 ps
CPU time 37.54 seconds
Started Mar 19 02:54:40 PM PDT 24
Finished Mar 19 02:55:18 PM PDT 24
Peak memory 214048 kb
Host smart-988fc21a-9a15-4543-9477-3f9dda24cc92
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395317053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2395317053
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2426180589
Short name T97
Test name
Test status
Simulation time 6053003307 ps
CPU time 55.9 seconds
Started Mar 19 02:44:35 PM PDT 24
Finished Mar 19 02:45:31 PM PDT 24
Peak memory 215048 kb
Host smart-2d980123-8baf-44de-9a19-34398e12aeb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426180589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2426180589
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1977491059
Short name T743
Test name
Test status
Simulation time 1375022627 ps
CPU time 8.59 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:42 PM PDT 24
Peak memory 211004 kb
Host smart-39c04deb-62f0-48a9-b660-4f896c483505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977491059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1977491059
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.527319344
Short name T879
Test name
Test status
Simulation time 5638404613 ps
CPU time 18.7 seconds
Started Mar 19 02:54:40 PM PDT 24
Finished Mar 19 02:54:58 PM PDT 24
Peak memory 212388 kb
Host smart-746ee242-cd78-4010-9d0d-1c5c32fca043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527319344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.527319344
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1847698346
Short name T740
Test name
Test status
Simulation time 1387343245 ps
CPU time 20.82 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 217184 kb
Host smart-014e9e6e-af9d-4734-88a7-e13305986fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847698346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1847698346
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3024344757
Short name T862
Test name
Test status
Simulation time 16462965439 ps
CPU time 33.22 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 216328 kb
Host smart-4635044d-39f6-446b-8803-760c67e9471f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024344757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3024344757
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1545408939
Short name T126
Test name
Test status
Simulation time 1064892600 ps
CPU time 160.96 seconds
Started Mar 19 02:44:30 PM PDT 24
Finished Mar 19 02:47:11 PM PDT 24
Peak memory 213708 kb
Host smart-2869c379-3cb6-4675-b616-f4e8453ac561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545408939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1545408939
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1515261123
Short name T887
Test name
Test status
Simulation time 3330075018 ps
CPU time 30.04 seconds
Started Mar 19 02:44:39 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 217396 kb
Host smart-7b17cf39-0fd7-4d1e-ac4f-de1d8e3c5126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515261123 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1515261123
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.576144709
Short name T695
Test name
Test status
Simulation time 601130461 ps
CPU time 12.78 seconds
Started Mar 19 02:54:45 PM PDT 24
Finished Mar 19 02:54:58 PM PDT 24
Peak memory 214196 kb
Host smart-0a696135-d491-4201-9a68-b7c522cc6087
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576144709 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.576144709
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3894645467
Short name T94
Test name
Test status
Simulation time 612838540 ps
CPU time 8.08 seconds
Started Mar 19 02:44:44 PM PDT 24
Finished Mar 19 02:44:52 PM PDT 24
Peak memory 210868 kb
Host smart-04011b3b-de0a-4b2a-a373-2296a39508e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894645467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3894645467
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.391647793
Short name T904
Test name
Test status
Simulation time 4490307023 ps
CPU time 21.62 seconds
Started Mar 19 02:54:49 PM PDT 24
Finished Mar 19 02:55:10 PM PDT 24
Peak memory 212020 kb
Host smart-5320f4dd-5e2e-4114-a820-9aad64617aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391647793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.391647793
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1249876409
Short name T782
Test name
Test status
Simulation time 3850510403 ps
CPU time 55.86 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 214228 kb
Host smart-98ca49d4-cfe7-469c-addb-03a453c6ce7d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249876409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1249876409
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.790191905
Short name T893
Test name
Test status
Simulation time 900978694 ps
CPU time 38.12 seconds
Started Mar 19 02:54:48 PM PDT 24
Finished Mar 19 02:55:26 PM PDT 24
Peak memory 213000 kb
Host smart-4d298045-e7d4-4db4-b00d-e0a04c82ffaa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790191905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.790191905
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1949672007
Short name T844
Test name
Test status
Simulation time 3811321739 ps
CPU time 29.54 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:45:08 PM PDT 24
Peak memory 211868 kb
Host smart-982f612a-f3d7-4cd3-b125-0649b61dee0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949672007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1949672007
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4049621266
Short name T768
Test name
Test status
Simulation time 12602051657 ps
CPU time 29.41 seconds
Started Mar 19 02:54:45 PM PDT 24
Finished Mar 19 02:55:15 PM PDT 24
Peak memory 212424 kb
Host smart-200425e3-e078-4bc7-b315-37a1516c8145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049621266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4049621266
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2704105226
Short name T750
Test name
Test status
Simulation time 4634491322 ps
CPU time 30.15 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:45:03 PM PDT 24
Peak memory 217868 kb
Host smart-7636fee6-8776-4814-873b-01ce78bd6496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704105226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2704105226
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.915341255
Short name T787
Test name
Test status
Simulation time 5564000060 ps
CPU time 29.46 seconds
Started Mar 19 02:54:53 PM PDT 24
Finished Mar 19 02:55:23 PM PDT 24
Peak memory 217408 kb
Host smart-7c3412a6-eadd-4a6d-8bc4-91d78f345f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915341255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.915341255
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2102314141
Short name T124
Test name
Test status
Simulation time 13584219355 ps
CPU time 172.04 seconds
Started Mar 19 02:44:44 PM PDT 24
Finished Mar 19 02:47:36 PM PDT 24
Peak memory 213996 kb
Host smart-de03602b-363c-4b2a-9832-672029fac4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102314141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2102314141
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3963766990
Short name T58
Test name
Test status
Simulation time 1202096375 ps
CPU time 151.83 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 213668 kb
Host smart-a9725416-87bf-4b8e-a1da-69f7a3fed169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963766990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3963766990
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2243686797
Short name T725
Test name
Test status
Simulation time 2386803436 ps
CPU time 24.18 seconds
Started Mar 19 02:54:48 PM PDT 24
Finished Mar 19 02:55:12 PM PDT 24
Peak memory 218212 kb
Host smart-16826e94-47ff-4c91-bce1-64b0440d8d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243686797 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2243686797
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2529405719
Short name T891
Test name
Test status
Simulation time 11284921909 ps
CPU time 23.6 seconds
Started Mar 19 02:44:44 PM PDT 24
Finished Mar 19 02:45:07 PM PDT 24
Peak memory 214812 kb
Host smart-b3e29c78-1c12-4458-aa24-fdf20eb6229e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529405719 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2529405719
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2201085243
Short name T783
Test name
Test status
Simulation time 21331278134 ps
CPU time 31.12 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 211728 kb
Host smart-e5228bbe-66c4-434d-af6c-e9652b33bd4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201085243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2201085243
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3308589869
Short name T863
Test name
Test status
Simulation time 2048039186 ps
CPU time 20.46 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:55:14 PM PDT 24
Peak memory 211032 kb
Host smart-8d330b0b-3094-4c00-a3b8-2b617ce0d43d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308589869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3308589869
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1325203256
Short name T860
Test name
Test status
Simulation time 53962460765 ps
CPU time 114.25 seconds
Started Mar 19 02:44:39 PM PDT 24
Finished Mar 19 02:46:34 PM PDT 24
Peak memory 214048 kb
Host smart-dbc78343-6f24-4ea2-8a2d-5cd9d26a16f7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325203256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1325203256
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2574528020
Short name T840
Test name
Test status
Simulation time 96286083296 ps
CPU time 193.47 seconds
Started Mar 19 02:54:45 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 215084 kb
Host smart-0fb94712-f6bf-4c9a-9df5-1f0564722ba2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574528020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2574528020
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.617240064
Short name T842
Test name
Test status
Simulation time 2969872533 ps
CPU time 29.33 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 212256 kb
Host smart-75cb36a2-eb6b-4804-923e-88bcdbfd2b4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617240064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.617240064
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.624866118
Short name T112
Test name
Test status
Simulation time 1713334989 ps
CPU time 13.84 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:44:52 PM PDT 24
Peak memory 210900 kb
Host smart-39e4d9e8-e303-42c8-9b33-95705ab965d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624866118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.624866118
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.127176366
Short name T686
Test name
Test status
Simulation time 16376689933 ps
CPU time 19.93 seconds
Started Mar 19 02:54:47 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 218284 kb
Host smart-be5b053b-9e27-481b-ab17-27fb38ce0568
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127176366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.127176366
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3522410620
Short name T780
Test name
Test status
Simulation time 5903015882 ps
CPU time 21.6 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:45:02 PM PDT 24
Peak memory 218276 kb
Host smart-2104a7b8-5bac-4420-bca2-0c43c4324ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522410620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3522410620
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3218979244
Short name T132
Test name
Test status
Simulation time 1475290294 ps
CPU time 90.3 seconds
Started Mar 19 02:54:48 PM PDT 24
Finished Mar 19 02:56:18 PM PDT 24
Peak memory 213384 kb
Host smart-85e9da8d-8946-4c97-abff-4c1b84b05892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218979244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3218979244
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.441183652
Short name T870
Test name
Test status
Simulation time 10743273025 ps
CPU time 95.6 seconds
Started Mar 19 02:44:42 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 213408 kb
Host smart-e323b6f3-6d2f-468f-a601-436d5ef39fb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441183652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.441183652
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.625154300
Short name T758
Test name
Test status
Simulation time 10161703496 ps
CPU time 25.11 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 215792 kb
Host smart-26f5060c-8dcc-46af-9032-ee8890a76409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625154300 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.625154300
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.997774958
Short name T705
Test name
Test status
Simulation time 2160011416 ps
CPU time 19.33 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 216616 kb
Host smart-c382a190-ac78-404c-ae4c-3d406e8ba54d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997774958 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.997774958
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2610663541
Short name T797
Test name
Test status
Simulation time 1909936050 ps
CPU time 20.07 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 211300 kb
Host smart-18a43fa8-b379-417d-876d-3999c43f7a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610663541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2610663541
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3314358238
Short name T897
Test name
Test status
Simulation time 3286405262 ps
CPU time 13.46 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:55:00 PM PDT 24
Peak memory 210960 kb
Host smart-dd1c1aa0-5188-4b4f-8298-a3c2406a98b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314358238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3314358238
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2912659425
Short name T720
Test name
Test status
Simulation time 6190576268 ps
CPU time 37.81 seconds
Started Mar 19 02:54:45 PM PDT 24
Finished Mar 19 02:55:22 PM PDT 24
Peak memory 214064 kb
Host smart-314b27c7-bd25-44b7-8f41-8c4ebeacb35d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912659425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2912659425
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1062926870
Short name T875
Test name
Test status
Simulation time 16767005228 ps
CPU time 32.53 seconds
Started Mar 19 02:44:39 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 212336 kb
Host smart-59d4b187-1fb7-4bd4-aea7-c768432e3d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062926870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1062926870
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.370650171
Short name T847
Test name
Test status
Simulation time 3256455033 ps
CPU time 24.86 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 212052 kb
Host smart-28168e08-de41-48d1-871e-5cfecc069a68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370650171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.370650171
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1279852705
Short name T699
Test name
Test status
Simulation time 174667842 ps
CPU time 11.62 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:54:57 PM PDT 24
Peak memory 217008 kb
Host smart-ca3c0097-1496-445b-bcad-5cf0583fc3bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279852705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1279852705
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.216895155
Short name T907
Test name
Test status
Simulation time 1942739757 ps
CPU time 22.94 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:45:04 PM PDT 24
Peak memory 218232 kb
Host smart-9ab7a185-e99b-4e66-ba9e-6059e7da54c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216895155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.216895155
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2473046825
Short name T770
Test name
Test status
Simulation time 14434004019 ps
CPU time 173.06 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:57:44 PM PDT 24
Peak memory 213960 kb
Host smart-45c81e35-6f8b-4afd-ab8a-b4aa44fad0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473046825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2473046825
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.559572181
Short name T731
Test name
Test status
Simulation time 49092677729 ps
CPU time 101.24 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 213580 kb
Host smart-16674a3d-2943-4811-8116-0cd941db597f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559572181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.559572181
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2519850939
Short name T833
Test name
Test status
Simulation time 3130975832 ps
CPU time 28.41 seconds
Started Mar 19 02:44:39 PM PDT 24
Finished Mar 19 02:45:08 PM PDT 24
Peak memory 216636 kb
Host smart-fb66a808-74f8-49ec-82dd-4b08565cd8fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519850939 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2519850939
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3605252825
Short name T732
Test name
Test status
Simulation time 9240935271 ps
CPU time 22.41 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:55:13 PM PDT 24
Peak memory 216496 kb
Host smart-f03ed9a7-ca3d-4576-9fdf-ffded420c10c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605252825 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3605252825
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.433523877
Short name T788
Test name
Test status
Simulation time 170758417 ps
CPU time 8.3 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:44:48 PM PDT 24
Peak memory 210896 kb
Host smart-25d76cf3-c237-4e0e-96a0-961044f4f8cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433523877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.433523877
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.826715216
Short name T810
Test name
Test status
Simulation time 21566005514 ps
CPU time 25.48 seconds
Started Mar 19 02:54:47 PM PDT 24
Finished Mar 19 02:55:13 PM PDT 24
Peak memory 211688 kb
Host smart-a8dfa2eb-8746-4a0d-99b0-2c6f26fe15a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826715216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.826715216
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3167650629
Short name T919
Test name
Test status
Simulation time 720299126 ps
CPU time 36.59 seconds
Started Mar 19 02:54:55 PM PDT 24
Finished Mar 19 02:55:31 PM PDT 24
Peak memory 212988 kb
Host smart-2f392ccf-b7cf-4134-b931-595d4b7af874
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167650629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3167650629
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3757846729
Short name T766
Test name
Test status
Simulation time 23302907431 ps
CPU time 73.47 seconds
Started Mar 19 02:44:44 PM PDT 24
Finished Mar 19 02:45:58 PM PDT 24
Peak memory 212880 kb
Host smart-d0e29f47-8f1b-438b-96ab-e07e55d27d38
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757846729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3757846729
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3158420878
Short name T809
Test name
Test status
Simulation time 1004760195 ps
CPU time 14.83 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 210908 kb
Host smart-7b861182-fe25-4777-bfcb-2d627385bec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158420878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3158420878
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.570897199
Short name T784
Test name
Test status
Simulation time 3694397844 ps
CPU time 23.44 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:55:18 PM PDT 24
Peak memory 211780 kb
Host smart-1479aa73-dbba-4127-92b6-6def744e01c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570897199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.570897199
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2064710952
Short name T761
Test name
Test status
Simulation time 15230923708 ps
CPU time 34.52 seconds
Started Mar 19 02:44:41 PM PDT 24
Finished Mar 19 02:45:16 PM PDT 24
Peak memory 217520 kb
Host smart-6c5e9f01-771b-463f-b504-1e74a272c9af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064710952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2064710952
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3680334155
Short name T873
Test name
Test status
Simulation time 4467257557 ps
CPU time 20.02 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:55:15 PM PDT 24
Peak memory 218688 kb
Host smart-6579fa65-07b5-46f1-b9ae-c16aa8a39b28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680334155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3680334155
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2835274377
Short name T130
Test name
Test status
Simulation time 2293783636 ps
CPU time 167.72 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:57:39 PM PDT 24
Peak memory 213712 kb
Host smart-c0a12099-8512-4f11-9e03-87246ddc1de7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835274377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2835274377
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3587697525
Short name T121
Test name
Test status
Simulation time 3765154743 ps
CPU time 81.31 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 212416 kb
Host smart-f38596ce-bc21-486c-8d16-c238d087d183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587697525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3587697525
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3421625337
Short name T690
Test name
Test status
Simulation time 7181963652 ps
CPU time 18.89 seconds
Started Mar 19 02:44:44 PM PDT 24
Finished Mar 19 02:45:03 PM PDT 24
Peak memory 216792 kb
Host smart-d6300ad3-03d9-4ea3-8db4-a60ce6679b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421625337 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3421625337
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.900567843
Short name T723
Test name
Test status
Simulation time 5282473602 ps
CPU time 23.9 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:55:10 PM PDT 24
Peak memory 218256 kb
Host smart-943b8734-21cb-4887-8d9c-cc918d97a4e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900567843 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.900567843
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2020485657
Short name T921
Test name
Test status
Simulation time 3314380876 ps
CPU time 26.17 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:55:12 PM PDT 24
Peak memory 210928 kb
Host smart-29ac4898-d565-41e3-b139-6598f1fde7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020485657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2020485657
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.927961613
Short name T751
Test name
Test status
Simulation time 338374738 ps
CPU time 8.09 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:44:48 PM PDT 24
Peak memory 210888 kb
Host smart-462c5344-dd8c-4786-8e23-e453c154643a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927961613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.927961613
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2760212428
Short name T903
Test name
Test status
Simulation time 55721694054 ps
CPU time 161.39 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 215064 kb
Host smart-88ffb104-c757-4e17-91d4-a5ef7b526528
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760212428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2760212428
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.624388023
Short name T849
Test name
Test status
Simulation time 5744997417 ps
CPU time 56.07 seconds
Started Mar 19 02:44:37 PM PDT 24
Finished Mar 19 02:45:34 PM PDT 24
Peak memory 214336 kb
Host smart-a8676099-b348-4f4f-9380-7fc9089c2420
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624388023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.624388023
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1665097706
Short name T832
Test name
Test status
Simulation time 2743788388 ps
CPU time 8.2 seconds
Started Mar 19 02:54:44 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 211072 kb
Host smart-c0faf3da-9440-49c0-9925-8db4a6f0b93b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665097706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1665097706
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.641128490
Short name T831
Test name
Test status
Simulation time 438978885 ps
CPU time 11.52 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:44:50 PM PDT 24
Peak memory 211056 kb
Host smart-7edbf7a8-ee03-44e7-beba-eb47b0176fe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641128490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.641128490
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4074176438
Short name T817
Test name
Test status
Simulation time 404686918 ps
CPU time 11.43 seconds
Started Mar 19 02:44:44 PM PDT 24
Finished Mar 19 02:44:56 PM PDT 24
Peak memory 217080 kb
Host smart-bda60adb-fb62-4055-9d53-2b8a97a0cff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074176438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4074176438
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4278612715
Short name T717
Test name
Test status
Simulation time 345430238 ps
CPU time 11.8 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 216988 kb
Host smart-9075cc1e-4288-4e83-8ef4-fe27c1314458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278612715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4278612715
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2427286318
Short name T131
Test name
Test status
Simulation time 14603188346 ps
CPU time 100.32 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:46:19 PM PDT 24
Peak memory 213628 kb
Host smart-017a426a-b3e9-4250-90db-f5ae55a3e631
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427286318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2427286318
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.901118821
Short name T715
Test name
Test status
Simulation time 6667792448 ps
CPU time 101.22 seconds
Started Mar 19 02:54:47 PM PDT 24
Finished Mar 19 02:56:28 PM PDT 24
Peak memory 213260 kb
Host smart-850ec528-f448-43d1-8ca0-97dd8236d99d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901118821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.901118821
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1335538242
Short name T813
Test name
Test status
Simulation time 1547396535 ps
CPU time 11.68 seconds
Started Mar 19 02:54:47 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 216024 kb
Host smart-93f864bc-2068-4d52-85e2-6a00d6a0d4fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335538242 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1335538242
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3556680558
Short name T759
Test name
Test status
Simulation time 180743977 ps
CPU time 9.98 seconds
Started Mar 19 02:44:41 PM PDT 24
Finished Mar 19 02:44:51 PM PDT 24
Peak memory 217448 kb
Host smart-1e4303c7-0312-43f6-af44-07994dc7f3a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556680558 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3556680558
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.140123927
Short name T816
Test name
Test status
Simulation time 12361864063 ps
CPU time 29.25 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:55:20 PM PDT 24
Peak memory 211980 kb
Host smart-2a065b3d-6cb2-426b-a522-60ddd7794749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140123927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.140123927
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2147120163
Short name T804
Test name
Test status
Simulation time 7142629214 ps
CPU time 29.36 seconds
Started Mar 19 02:44:41 PM PDT 24
Finished Mar 19 02:45:11 PM PDT 24
Peak memory 211892 kb
Host smart-35384cdf-f458-4a14-9665-265532c6bd65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147120163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2147120163
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4143026445
Short name T899
Test name
Test status
Simulation time 57307680110 ps
CPU time 118.83 seconds
Started Mar 19 02:44:39 PM PDT 24
Finished Mar 19 02:46:38 PM PDT 24
Peak memory 213008 kb
Host smart-0e49e403-05f8-4c2e-b62e-776c5d6fc21d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143026445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4143026445
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4040548352
Short name T909
Test name
Test status
Simulation time 2350682017 ps
CPU time 8.46 seconds
Started Mar 19 02:54:44 PM PDT 24
Finished Mar 19 02:54:53 PM PDT 24
Peak memory 211020 kb
Host smart-fcbe7b70-4847-4116-99c3-11c183c58432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040548352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4040548352
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.412873686
Short name T881
Test name
Test status
Simulation time 7854226704 ps
CPU time 32.17 seconds
Started Mar 19 02:44:39 PM PDT 24
Finished Mar 19 02:45:11 PM PDT 24
Peak memory 212236 kb
Host smart-7aaa2a1b-efe2-4704-8925-7f465abb1dc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412873686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.412873686
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1271507637
Short name T821
Test name
Test status
Simulation time 2471195753 ps
CPU time 28.2 seconds
Started Mar 19 02:44:41 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 218332 kb
Host smart-2abff028-66df-4dcd-ac04-3ec03be58e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271507637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1271507637
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2643886281
Short name T777
Test name
Test status
Simulation time 19769763675 ps
CPU time 34.4 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:55:24 PM PDT 24
Peak memory 217396 kb
Host smart-55a5ca01-e5f6-4c90-a269-eb88b92b0f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643886281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2643886281
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1234640868
Short name T805
Test name
Test status
Simulation time 13485506895 ps
CPU time 99.48 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 213544 kb
Host smart-91c4b07c-b461-425f-8edf-4ef3f1d27433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234640868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1234640868
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3109078445
Short name T737
Test name
Test status
Simulation time 16786256713 ps
CPU time 32.52 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:45:13 PM PDT 24
Peak memory 214876 kb
Host smart-7b6231a3-92c0-41a0-9a12-c556ddfbfa22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109078445 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3109078445
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3779724947
Short name T823
Test name
Test status
Simulation time 2040584211 ps
CPU time 21.23 seconds
Started Mar 19 02:54:44 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 215328 kb
Host smart-66717f06-11d1-4219-ad78-008495cd7461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779724947 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3779724947
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1480101353
Short name T70
Test name
Test status
Simulation time 12000663135 ps
CPU time 26 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:55:21 PM PDT 24
Peak memory 212164 kb
Host smart-e56ed50f-e348-47e0-b363-50ee644258d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480101353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1480101353
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2652016381
Short name T786
Test name
Test status
Simulation time 10506272759 ps
CPU time 24.45 seconds
Started Mar 19 02:44:38 PM PDT 24
Finished Mar 19 02:45:03 PM PDT 24
Peak memory 212008 kb
Host smart-16148cb4-863f-48da-929a-c23b9b2bbb8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652016381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2652016381
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1695921457
Short name T760
Test name
Test status
Simulation time 16751418865 ps
CPU time 128.85 seconds
Started Mar 19 02:44:37 PM PDT 24
Finished Mar 19 02:46:46 PM PDT 24
Peak memory 214216 kb
Host smart-57339aad-c0cb-4412-a6b9-590b87b4b58d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695921457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1695921457
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3940117598
Short name T767
Test name
Test status
Simulation time 32110119034 ps
CPU time 152.48 seconds
Started Mar 19 02:54:47 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 215080 kb
Host smart-a9c64e3c-a95f-4f14-a271-8398922fa447
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940117598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3940117598
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.579198085
Short name T708
Test name
Test status
Simulation time 735425211 ps
CPU time 12.28 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 212260 kb
Host smart-9e4b10ce-da89-4c24-8122-4032f430a4f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579198085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.579198085
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.808328583
Short name T763
Test name
Test status
Simulation time 19244608172 ps
CPU time 24.32 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:45:05 PM PDT 24
Peak memory 212088 kb
Host smart-1c3c703e-ba84-4eb9-aec7-83bc2d463dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808328583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.808328583
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1852547014
Short name T685
Test name
Test status
Simulation time 1736001195 ps
CPU time 20.66 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:45:01 PM PDT 24
Peak memory 217944 kb
Host smart-8c1dc8d6-9cac-428b-81a1-ba15a039f1c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852547014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1852547014
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3481663941
Short name T719
Test name
Test status
Simulation time 360674528 ps
CPU time 12.99 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:55:03 PM PDT 24
Peak memory 217132 kb
Host smart-56e8a1b2-d94b-4576-9b2e-65a7e03050b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481663941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3481663941
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1183076686
Short name T716
Test name
Test status
Simulation time 6516710301 ps
CPU time 161.35 seconds
Started Mar 19 02:44:40 PM PDT 24
Finished Mar 19 02:47:22 PM PDT 24
Peak memory 212952 kb
Host smart-844e5190-522a-46ca-ab19-70145867f934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183076686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1183076686
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.220617503
Short name T824
Test name
Test status
Simulation time 943432881 ps
CPU time 81.15 seconds
Started Mar 19 02:54:45 PM PDT 24
Finished Mar 19 02:56:07 PM PDT 24
Peak memory 213424 kb
Host smart-3ffa907c-fe4d-4e7a-8e34-4d73af80e4bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220617503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.220617503
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3717411593
Short name T912
Test name
Test status
Simulation time 374415123 ps
CPU time 8.89 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:55:01 PM PDT 24
Peak memory 216244 kb
Host smart-c4a176e5-269e-466a-964d-61712d07ab28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717411593 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3717411593
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.562765320
Short name T762
Test name
Test status
Simulation time 1421045251 ps
CPU time 18.12 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 217756 kb
Host smart-9bb91bec-207c-4d8c-872c-9b80117ee751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562765320 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.562765320
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3105433319
Short name T818
Test name
Test status
Simulation time 9855990802 ps
CPU time 17.93 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 211660 kb
Host smart-c57e5ace-20fc-4bbd-ba86-d0f011b4da3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105433319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3105433319
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.649434098
Short name T808
Test name
Test status
Simulation time 23533276921 ps
CPU time 28 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:55:22 PM PDT 24
Peak memory 211740 kb
Host smart-d126bd9b-d9e0-488a-b1ea-9154d3b823d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649434098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.649434098
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2338220553
Short name T87
Test name
Test status
Simulation time 21008619436 ps
CPU time 100.81 seconds
Started Mar 19 02:54:45 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 213988 kb
Host smart-05a0e168-89d5-456c-a0d9-b9819ed53e0c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338220553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2338220553
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3526112057
Short name T93
Test name
Test status
Simulation time 3335163871 ps
CPU time 55.73 seconds
Started Mar 19 02:44:41 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 215100 kb
Host smart-322bd324-fdb0-42f5-9faf-f5ffbe4a698c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526112057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3526112057
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.241749956
Short name T781
Test name
Test status
Simulation time 17407736517 ps
CPU time 30.49 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 212092 kb
Host smart-feac5720-924f-4388-a9d2-adb3052b0183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241749956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.241749956
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3806793747
Short name T894
Test name
Test status
Simulation time 4595729992 ps
CPU time 15.97 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 212316 kb
Host smart-9bfc8b85-f635-4b93-b0bd-8df5269e79df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806793747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3806793747
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1557165391
Short name T779
Test name
Test status
Simulation time 12581286629 ps
CPU time 31.06 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 218376 kb
Host smart-46df9a6c-cec3-42d1-a929-115dead92cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557165391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1557165391
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.954812714
Short name T799
Test name
Test status
Simulation time 10954430959 ps
CPU time 28.64 seconds
Started Mar 19 02:54:46 PM PDT 24
Finished Mar 19 02:55:15 PM PDT 24
Peak memory 218448 kb
Host smart-c6177093-7ceb-4547-9b08-54b8b18de8f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954812714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.954812714
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1642614731
Short name T820
Test name
Test status
Simulation time 2744173304 ps
CPU time 170.32 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 213684 kb
Host smart-b09040da-5cd1-4af0-a7f7-f0a011f8c3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642614731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1642614731
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2844621061
Short name T864
Test name
Test status
Simulation time 1670274612 ps
CPU time 89.48 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 213240 kb
Host smart-3bbef5c7-7c84-4cbd-84fe-39cec7f5b53b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844621061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2844621061
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1720901087
Short name T866
Test name
Test status
Simulation time 1564951503 ps
CPU time 15.2 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 217260 kb
Host smart-60c6375c-1b29-4e6c-abb3-9636b364101b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720901087 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1720901087
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3825349211
Short name T684
Test name
Test status
Simulation time 4752085709 ps
CPU time 17.43 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 216640 kb
Host smart-2eda68ce-38df-477e-bd82-ca8196a42382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825349211 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3825349211
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1647225290
Short name T77
Test name
Test status
Simulation time 1922167847 ps
CPU time 19.88 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 211016 kb
Host smart-20738e33-10d1-47fd-ad3f-1f97b2fd960b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647225290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1647225290
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2151991390
Short name T74
Test name
Test status
Simulation time 2227922199 ps
CPU time 21.06 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:55:12 PM PDT 24
Peak memory 211612 kb
Host smart-a8d69240-157b-48bd-a783-667080c4c4cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151991390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2151991390
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3158579689
Short name T868
Test name
Test status
Simulation time 28431820526 ps
CPU time 83.45 seconds
Started Mar 19 02:44:49 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 215076 kb
Host smart-194f8ed0-7024-462e-9aed-401abc273630
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158579689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3158579689
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.336423300
Short name T843
Test name
Test status
Simulation time 32978752029 ps
CPU time 88.66 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 210992 kb
Host smart-0c4f3bb7-b479-4dde-9875-8e62f81d14f4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336423300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.336423300
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3089331830
Short name T721
Test name
Test status
Simulation time 1711504394 ps
CPU time 13.91 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:45:05 PM PDT 24
Peak memory 210936 kb
Host smart-fb652448-8a24-4bb8-9a1c-d4943e85e275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089331830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3089331830
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.413450089
Short name T755
Test name
Test status
Simulation time 5021419457 ps
CPU time 23.55 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:55:15 PM PDT 24
Peak memory 212244 kb
Host smart-f24b7fac-1b51-4033-8d1e-efcb36efe5a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413450089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.413450089
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.143735891
Short name T835
Test name
Test status
Simulation time 331761784 ps
CPU time 13.6 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:45:04 PM PDT 24
Peak memory 217076 kb
Host smart-3569e652-384f-4f2f-a7c2-895738fe1bc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143735891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.143735891
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.998088762
Short name T769
Test name
Test status
Simulation time 2212035357 ps
CPU time 26.41 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:55:18 PM PDT 24
Peak memory 218028 kb
Host smart-0192cfc3-1498-4f41-87ea-7fad82f1ca5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998088762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.998088762
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1393103984
Short name T880
Test name
Test status
Simulation time 1031534880 ps
CPU time 157.9 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 213648 kb
Host smart-3690a994-cbc1-4934-8f35-439aab5fa04a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393103984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1393103984
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.287375079
Short name T801
Test name
Test status
Simulation time 8519445195 ps
CPU time 105.82 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 213700 kb
Host smart-758cfaa2-c813-4b32-933a-5fe062a9d932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287375079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.287375079
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2402570213
Short name T722
Test name
Test status
Simulation time 3204642848 ps
CPU time 26.79 seconds
Started Mar 19 02:44:19 PM PDT 24
Finished Mar 19 02:44:46 PM PDT 24
Peak memory 211304 kb
Host smart-b7e6bac8-5e21-4187-8536-1fa460210eda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402570213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2402570213
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.453343934
Short name T76
Test name
Test status
Simulation time 434204329 ps
CPU time 11.2 seconds
Started Mar 19 02:54:26 PM PDT 24
Finished Mar 19 02:54:40 PM PDT 24
Peak memory 210916 kb
Host smart-01079614-8ff5-4f18-8a3e-fc5ed2a8ad40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453343934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.453343934
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2228863212
Short name T867
Test name
Test status
Simulation time 4066877736 ps
CPU time 29.47 seconds
Started Mar 19 02:54:29 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 211056 kb
Host smart-173481cd-5f55-4302-a9f8-40c2cea2d340
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228863212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2228863212
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2351313543
Short name T729
Test name
Test status
Simulation time 3226433848 ps
CPU time 27.94 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:41 PM PDT 24
Peak memory 210896 kb
Host smart-11aa9e28-bfaa-4cd0-b71e-6fdb83930e7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351313543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2351313543
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2874778450
Short name T845
Test name
Test status
Simulation time 41554637983 ps
CPU time 36.88 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:50 PM PDT 24
Peak memory 211816 kb
Host smart-dc177d96-fc83-4f9f-b7a2-2f0ce4a08057
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874778450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2874778450
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.909221562
Short name T776
Test name
Test status
Simulation time 1086495551 ps
CPU time 18.31 seconds
Started Mar 19 02:54:24 PM PDT 24
Finished Mar 19 02:54:43 PM PDT 24
Peak memory 211192 kb
Host smart-10b5ed39-d3d2-43c1-a43a-a06d1ed1aff5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909221562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.909221562
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1888801216
Short name T749
Test name
Test status
Simulation time 1741962354 ps
CPU time 17.61 seconds
Started Mar 19 02:54:31 PM PDT 24
Finished Mar 19 02:54:48 PM PDT 24
Peak memory 213568 kb
Host smart-4640402c-57e0-42b2-8037-5b54ff8c2013
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888801216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1888801216
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.225134137
Short name T790
Test name
Test status
Simulation time 2182775015 ps
CPU time 19.13 seconds
Started Mar 19 02:44:19 PM PDT 24
Finished Mar 19 02:44:39 PM PDT 24
Peak memory 216376 kb
Host smart-15e9453d-b677-4a28-9fc8-4bb5590f9225
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225134137 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.225134137
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1921112
Short name T701
Test name
Test status
Simulation time 14898794718 ps
CPU time 30.13 seconds
Started Mar 19 02:54:26 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 211864 kb
Host smart-ab694526-d75d-420e-8dcc-edfe91797c38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1921112
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2669255973
Short name T772
Test name
Test status
Simulation time 9484692105 ps
CPU time 22.29 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:36 PM PDT 24
Peak memory 212136 kb
Host smart-e1534119-d9f7-47a5-a9f0-b1d1ab0dda7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669255973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2669255973
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.491367779
Short name T724
Test name
Test status
Simulation time 10868025193 ps
CPU time 25.06 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:38 PM PDT 24
Peak memory 210844 kb
Host smart-9773165f-e704-4cc5-86bf-656df28b23bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491367779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.491367779
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.943702082
Short name T726
Test name
Test status
Simulation time 13790176022 ps
CPU time 29.22 seconds
Started Mar 19 02:54:24 PM PDT 24
Finished Mar 19 02:54:54 PM PDT 24
Peak memory 210900 kb
Host smart-4dbb2561-049c-4dd9-935e-206c5d544b38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943702082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.943702082
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1485088406
Short name T915
Test name
Test status
Simulation time 4582603911 ps
CPU time 28.46 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:55 PM PDT 24
Peak memory 210900 kb
Host smart-aa804cb4-81b7-4380-8a46-c096f4928cce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485088406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1485088406
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2653720781
Short name T747
Test name
Test status
Simulation time 8273165847 ps
CPU time 22.68 seconds
Started Mar 19 02:44:19 PM PDT 24
Finished Mar 19 02:44:41 PM PDT 24
Peak memory 210864 kb
Host smart-59caa4c1-45ac-4367-871c-42a33e72d4e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653720781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2653720781
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2259407928
Short name T829
Test name
Test status
Simulation time 8625126598 ps
CPU time 90.35 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:55:57 PM PDT 24
Peak memory 214420 kb
Host smart-3a542f40-3a69-4cbf-96cd-53043a1eeade
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259407928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2259407928
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2924962001
Short name T734
Test name
Test status
Simulation time 2990575350 ps
CPU time 58.85 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 213024 kb
Host smart-28a78254-a079-4169-a3d9-998ee1eb6e31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924962001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2924962001
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2240681835
Short name T107
Test name
Test status
Simulation time 2541517413 ps
CPU time 26.96 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:41 PM PDT 24
Peak memory 212084 kb
Host smart-3d113ab1-b0d8-4f23-b0f9-98e99b373dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240681835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2240681835
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2391601915
Short name T709
Test name
Test status
Simulation time 4412414810 ps
CPU time 21.99 seconds
Started Mar 19 02:54:30 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 211940 kb
Host smart-c0613bcf-e0d4-41b2-9ddb-a3280a7a7517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391601915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2391601915
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2941608388
Short name T850
Test name
Test status
Simulation time 5185188087 ps
CPU time 27.39 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:55 PM PDT 24
Peak memory 217308 kb
Host smart-9788b8fb-053d-4be0-ac1f-09fb77b22aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941608388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2941608388
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3901945524
Short name T689
Test name
Test status
Simulation time 14631533957 ps
CPU time 32.72 seconds
Started Mar 19 02:44:12 PM PDT 24
Finished Mar 19 02:44:45 PM PDT 24
Peak memory 217508 kb
Host smart-5baa4739-198e-422d-aa6d-bd932b2bfe80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901945524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3901945524
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.225300799
Short name T133
Test name
Test status
Simulation time 3024507076 ps
CPU time 169.32 seconds
Started Mar 19 02:44:12 PM PDT 24
Finished Mar 19 02:47:02 PM PDT 24
Peak memory 212492 kb
Host smart-cd125894-2033-4e38-847a-c2d12cb59fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225300799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.225300799
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.965673353
Short name T125
Test name
Test status
Simulation time 1939004683 ps
CPU time 84.29 seconds
Started Mar 19 02:54:27 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 212780 kb
Host smart-843a099a-f9a8-47d3-9d3e-84c24046d72e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965673353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.965673353
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1216809561
Short name T855
Test name
Test status
Simulation time 688733424 ps
CPU time 8.28 seconds
Started Mar 19 02:44:22 PM PDT 24
Finished Mar 19 02:44:30 PM PDT 24
Peak memory 210900 kb
Host smart-0638d5af-0f8c-4e5b-968d-1da67c1b4b9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216809561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1216809561
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.553236111
Short name T713
Test name
Test status
Simulation time 3028175678 ps
CPU time 25.48 seconds
Started Mar 19 02:54:31 PM PDT 24
Finished Mar 19 02:54:57 PM PDT 24
Peak memory 211124 kb
Host smart-9254c6f6-6316-43c1-8349-a49497b2b7cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553236111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.553236111
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3180811008
Short name T861
Test name
Test status
Simulation time 3284838862 ps
CPU time 11.71 seconds
Started Mar 19 02:54:35 PM PDT 24
Finished Mar 19 02:54:46 PM PDT 24
Peak memory 211016 kb
Host smart-e3c4b0a7-dbfe-448f-b531-41e1267d927c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180811008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3180811008
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.457807142
Short name T687
Test name
Test status
Simulation time 2725297907 ps
CPU time 13.15 seconds
Started Mar 19 02:44:20 PM PDT 24
Finished Mar 19 02:44:33 PM PDT 24
Peak memory 210908 kb
Host smart-59b01238-6dcf-4986-aba6-0cd3de088916
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457807142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.457807142
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3426307829
Short name T697
Test name
Test status
Simulation time 27318040090 ps
CPU time 31.87 seconds
Started Mar 19 02:54:32 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 211772 kb
Host smart-c7f5ab9a-ccd7-4ab3-8468-9bf00db5effd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426307829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3426307829
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.369311250
Short name T838
Test name
Test status
Simulation time 9138494943 ps
CPU time 34.82 seconds
Started Mar 19 02:44:26 PM PDT 24
Finished Mar 19 02:45:00 PM PDT 24
Peak memory 211636 kb
Host smart-358e7fff-a385-4324-a1b9-5ab9fb3bd327
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369311250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.369311250
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2580114062
Short name T791
Test name
Test status
Simulation time 16187721460 ps
CPU time 31.3 seconds
Started Mar 19 02:54:35 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 216592 kb
Host smart-7b4c2cbe-cc6a-4d9e-9f87-c4d9312e1b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580114062 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2580114062
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3830557193
Short name T872
Test name
Test status
Simulation time 186813369 ps
CPU time 9.26 seconds
Started Mar 19 02:44:22 PM PDT 24
Finished Mar 19 02:44:32 PM PDT 24
Peak memory 215484 kb
Host smart-23a10ce4-6271-4fdd-9863-7c8426056002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830557193 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3830557193
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3052149023
Short name T73
Test name
Test status
Simulation time 4872662392 ps
CPU time 31.72 seconds
Started Mar 19 02:44:20 PM PDT 24
Finished Mar 19 02:44:51 PM PDT 24
Peak memory 211900 kb
Host smart-c9b6729e-1b25-4d22-9e8f-a82f320b98d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052149023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3052149023
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.662471434
Short name T910
Test name
Test status
Simulation time 3731954095 ps
CPU time 30.25 seconds
Started Mar 19 02:54:33 PM PDT 24
Finished Mar 19 02:55:03 PM PDT 24
Peak memory 211392 kb
Host smart-4f7dc8d7-6f62-4026-af2c-1860bfb866d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662471434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.662471434
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.142113209
Short name T913
Test name
Test status
Simulation time 2719110334 ps
CPU time 21.49 seconds
Started Mar 19 02:44:22 PM PDT 24
Finished Mar 19 02:44:44 PM PDT 24
Peak memory 210892 kb
Host smart-32ca5a2d-50d1-45aa-a3a4-7bd61cd0ee3f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142113209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.142113209
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2956885737
Short name T826
Test name
Test status
Simulation time 172748954 ps
CPU time 8.1 seconds
Started Mar 19 02:54:34 PM PDT 24
Finished Mar 19 02:54:43 PM PDT 24
Peak memory 210852 kb
Host smart-fbfcfa1e-b91d-44d7-bdbc-1859e7c430c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956885737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2956885737
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1406999216
Short name T730
Test name
Test status
Simulation time 1859800374 ps
CPU time 19.66 seconds
Started Mar 19 02:44:25 PM PDT 24
Finished Mar 19 02:44:45 PM PDT 24
Peak memory 210700 kb
Host smart-f964ef5f-d1a7-4516-a0ea-0f76da786bb4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406999216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1406999216
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2073892016
Short name T886
Test name
Test status
Simulation time 2292194375 ps
CPU time 21.08 seconds
Started Mar 19 02:54:37 PM PDT 24
Finished Mar 19 02:54:58 PM PDT 24
Peak memory 210872 kb
Host smart-44eb29ea-15f7-4b85-b16d-f01a8ebe236f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073892016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2073892016
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2122951256
Short name T789
Test name
Test status
Simulation time 167561268698 ps
CPU time 129.79 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 214084 kb
Host smart-12fbfc20-92e7-4532-9ec8-7f8c2c6fc76f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122951256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2122951256
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.461316425
Short name T746
Test name
Test status
Simulation time 8074711791 ps
CPU time 108.64 seconds
Started Mar 19 02:44:22 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 215208 kb
Host smart-a2304096-ebba-4d47-9ff7-c2dcfec88ee2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461316425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.461316425
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.446309342
Short name T110
Test name
Test status
Simulation time 1081839609 ps
CPU time 19.39 seconds
Started Mar 19 02:44:25 PM PDT 24
Finished Mar 19 02:44:45 PM PDT 24
Peak memory 211696 kb
Host smart-8784a894-b7ff-441f-862b-f21c6ed886bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446309342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.446309342
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.540234750
Short name T794
Test name
Test status
Simulation time 7057856575 ps
CPU time 18.25 seconds
Started Mar 19 02:54:33 PM PDT 24
Finished Mar 19 02:54:51 PM PDT 24
Peak memory 211028 kb
Host smart-29dd7c26-ab2d-476d-9a41-3a6a3463ba31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540234750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.540234750
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3142260873
Short name T882
Test name
Test status
Simulation time 3961975279 ps
CPU time 34.16 seconds
Started Mar 19 02:44:21 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 217764 kb
Host smart-7685c027-a048-4ed3-a9e5-de353b169bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142260873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3142260873
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4213473892
Short name T745
Test name
Test status
Simulation time 339253160 ps
CPU time 12.74 seconds
Started Mar 19 02:54:35 PM PDT 24
Finished Mar 19 02:54:48 PM PDT 24
Peak memory 217280 kb
Host smart-19c53487-b5bb-4287-bee8-67ee42b779fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213473892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4213473892
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1822524404
Short name T128
Test name
Test status
Simulation time 14797476982 ps
CPU time 171.51 seconds
Started Mar 19 02:54:34 PM PDT 24
Finished Mar 19 02:57:25 PM PDT 24
Peak memory 213696 kb
Host smart-a5e47408-15a4-4db2-b852-e9b78fb2d39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822524404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1822524404
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2590087673
Short name T841
Test name
Test status
Simulation time 3017494363 ps
CPU time 96.98 seconds
Started Mar 19 02:44:20 PM PDT 24
Finished Mar 19 02:45:57 PM PDT 24
Peak memory 213284 kb
Host smart-feb6dbc5-8f0b-4cb7-a0bb-9dc1677d8cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590087673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2590087673
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1876733150
Short name T869
Test name
Test status
Simulation time 422356299 ps
CPU time 10.61 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:44:42 PM PDT 24
Peak memory 210960 kb
Host smart-c700da44-5216-4317-8b08-d4ada47044ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876733150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1876733150
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3898777769
Short name T859
Test name
Test status
Simulation time 1373044817 ps
CPU time 10.59 seconds
Started Mar 19 02:54:31 PM PDT 24
Finished Mar 19 02:54:42 PM PDT 24
Peak memory 210896 kb
Host smart-3e6778dc-79cc-42cd-b68b-cb1a2ca929da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898777769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3898777769
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1724252605
Short name T694
Test name
Test status
Simulation time 2599624851 ps
CPU time 23.77 seconds
Started Mar 19 02:44:30 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 211436 kb
Host smart-ce864730-d5a2-4686-ac2a-33764c26d87d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724252605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1724252605
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2752192422
Short name T922
Test name
Test status
Simulation time 972342346 ps
CPU time 8.82 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:54:47 PM PDT 24
Peak memory 210904 kb
Host smart-af9755a6-c782-4b39-b6f0-1332416bcf80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752192422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2752192422
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1943556870
Short name T865
Test name
Test status
Simulation time 21540198393 ps
CPU time 31.54 seconds
Started Mar 19 02:54:35 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 211984 kb
Host smart-bb0ee672-f527-4e9d-9f78-e985f3e43180
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943556870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1943556870
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2837816885
Short name T712
Test name
Test status
Simulation time 11383622322 ps
CPU time 25.67 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:59 PM PDT 24
Peak memory 211844 kb
Host smart-8d1780c8-c1b1-4596-9903-54f57670f360
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837816885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2837816885
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1199044493
Short name T764
Test name
Test status
Simulation time 183301665 ps
CPU time 8.75 seconds
Started Mar 19 02:44:35 PM PDT 24
Finished Mar 19 02:44:44 PM PDT 24
Peak memory 214900 kb
Host smart-59daefe1-f354-4fd6-a1e8-3af6f4deccf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199044493 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1199044493
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1454091751
Short name T853
Test name
Test status
Simulation time 688563360 ps
CPU time 8.56 seconds
Started Mar 19 02:54:31 PM PDT 24
Finished Mar 19 02:54:40 PM PDT 24
Peak memory 215436 kb
Host smart-4be61528-3ba9-4121-953d-be4b8533f8f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454091751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1454091751
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2195948739
Short name T698
Test name
Test status
Simulation time 10523205852 ps
CPU time 13.63 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:47 PM PDT 24
Peak memory 210932 kb
Host smart-0444f6f9-908a-4105-801a-56d263145e88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195948739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2195948739
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3928627638
Short name T752
Test name
Test status
Simulation time 6833421572 ps
CPU time 14.1 seconds
Started Mar 19 02:54:33 PM PDT 24
Finished Mar 19 02:54:47 PM PDT 24
Peak memory 212044 kb
Host smart-8f205f09-5f7a-4dca-b107-a777d954fb09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928627638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3928627638
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2805839900
Short name T688
Test name
Test status
Simulation time 21218093101 ps
CPU time 31.4 seconds
Started Mar 19 02:54:34 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 210916 kb
Host smart-7a27ee2d-b32a-4846-b99d-6c35b16b2455
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805839900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2805839900
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3586973685
Short name T785
Test name
Test status
Simulation time 993114605 ps
CPU time 9.95 seconds
Started Mar 19 02:44:25 PM PDT 24
Finished Mar 19 02:44:35 PM PDT 24
Peak memory 210516 kb
Host smart-87ed80e1-daef-4817-a3dc-686644fa2fb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586973685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3586973685
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1366151641
Short name T735
Test name
Test status
Simulation time 849457838 ps
CPU time 14.01 seconds
Started Mar 19 02:44:22 PM PDT 24
Finished Mar 19 02:44:36 PM PDT 24
Peak memory 210836 kb
Host smart-8c06d788-3895-4009-a41b-fe1fc29d4ae2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366151641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1366151641
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2549056363
Short name T714
Test name
Test status
Simulation time 2228295202 ps
CPU time 21.46 seconds
Started Mar 19 02:54:32 PM PDT 24
Finished Mar 19 02:54:54 PM PDT 24
Peak memory 210888 kb
Host smart-11fb265c-abc0-4156-bfff-958782d44986
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549056363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2549056363
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2737222813
Short name T710
Test name
Test status
Simulation time 12970721740 ps
CPU time 109.21 seconds
Started Mar 19 02:54:30 PM PDT 24
Finished Mar 19 02:56:20 PM PDT 24
Peak memory 214092 kb
Host smart-ed68b5b5-f753-4860-b648-a817cd25526a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737222813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2737222813
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.469146161
Short name T109
Test name
Test status
Simulation time 8314260321 ps
CPU time 51.94 seconds
Started Mar 19 02:44:21 PM PDT 24
Finished Mar 19 02:45:13 PM PDT 24
Peak memory 215068 kb
Host smart-4759094a-7746-4244-bb4a-d2e9b9a04c1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469146161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.469146161
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1001129308
Short name T61
Test name
Test status
Simulation time 2139607203 ps
CPU time 21.78 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:55:00 PM PDT 24
Peak memory 212088 kb
Host smart-5c02d6c2-ab51-479c-9729-eea693dc26a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001129308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1001129308
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3066882758
Short name T742
Test name
Test status
Simulation time 35120599405 ps
CPU time 35.33 seconds
Started Mar 19 02:44:29 PM PDT 24
Finished Mar 19 02:45:05 PM PDT 24
Peak memory 212576 kb
Host smart-ed9da30a-a10e-4bc9-954f-f8ab7d95e9be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066882758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3066882758
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1410081807
Short name T874
Test name
Test status
Simulation time 825841796 ps
CPU time 11.01 seconds
Started Mar 19 02:54:34 PM PDT 24
Finished Mar 19 02:54:46 PM PDT 24
Peak memory 217140 kb
Host smart-763c2639-2cd8-4003-9abe-7ca30199e1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410081807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1410081807
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.260044204
Short name T830
Test name
Test status
Simulation time 171054145 ps
CPU time 12.3 seconds
Started Mar 19 02:44:22 PM PDT 24
Finished Mar 19 02:44:34 PM PDT 24
Peak memory 217024 kb
Host smart-109db4b9-d08a-42ae-ad2f-5366467bf497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260044204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.260044204
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1032090708
Short name T127
Test name
Test status
Simulation time 1078619898 ps
CPU time 159.04 seconds
Started Mar 19 02:44:22 PM PDT 24
Finished Mar 19 02:47:01 PM PDT 24
Peak memory 214688 kb
Host smart-567bc3ca-811c-4464-ba08-0487e3a06e85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032090708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1032090708
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4045731075
Short name T819
Test name
Test status
Simulation time 6588672143 ps
CPU time 172.28 seconds
Started Mar 19 02:54:34 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 214012 kb
Host smart-e096b52c-251a-4170-98d5-e06574b1f67b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045731075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4045731075
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1819638426
Short name T851
Test name
Test status
Simulation time 4805371604 ps
CPU time 22.01 seconds
Started Mar 19 02:54:42 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 217164 kb
Host smart-926d0c2a-81c0-4717-89df-37623f4f8904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819638426 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1819638426
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.453251082
Short name T836
Test name
Test status
Simulation time 2449807629 ps
CPU time 11.1 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:44:42 PM PDT 24
Peak memory 215896 kb
Host smart-cc8042ae-d6dc-49e0-9799-56d2426e41ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453251082 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.453251082
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2697737759
Short name T792
Test name
Test status
Simulation time 6136170992 ps
CPU time 18.81 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:54:57 PM PDT 24
Peak memory 212264 kb
Host smart-9efe5c3a-7f25-4294-9fc7-0646012ca838
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697737759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2697737759
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3248104267
Short name T700
Test name
Test status
Simulation time 428750177 ps
CPU time 11.18 seconds
Started Mar 19 02:44:30 PM PDT 24
Finished Mar 19 02:44:42 PM PDT 24
Peak memory 210932 kb
Host smart-cef94938-2948-46f8-a113-65b65fa9bf35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248104267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3248104267
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3700619350
Short name T837
Test name
Test status
Simulation time 33410732150 ps
CPU time 133.81 seconds
Started Mar 19 02:44:35 PM PDT 24
Finished Mar 19 02:46:49 PM PDT 24
Peak memory 214016 kb
Host smart-aaac35c0-b48c-4197-aa60-bbc78029b8ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700619350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3700619350
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.409432148
Short name T86
Test name
Test status
Simulation time 17277077651 ps
CPU time 139.33 seconds
Started Mar 19 02:54:34 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 214072 kb
Host smart-39e3ed10-9b62-496f-abfd-f2ac40e0209b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409432148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.409432148
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3161049601
Short name T756
Test name
Test status
Simulation time 11139061260 ps
CPU time 21.91 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 212376 kb
Host smart-d44ad16e-e74d-45a1-8189-5cf62a35bd23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161049601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3161049601
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3948598674
Short name T908
Test name
Test status
Simulation time 1036524653 ps
CPU time 10.05 seconds
Started Mar 19 02:54:39 PM PDT 24
Finished Mar 19 02:54:49 PM PDT 24
Peak memory 211060 kb
Host smart-b545e8c2-793f-44b7-9dc0-b51653ba09ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948598674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3948598674
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1987674431
Short name T916
Test name
Test status
Simulation time 17980840562 ps
CPU time 38.72 seconds
Started Mar 19 02:44:29 PM PDT 24
Finished Mar 19 02:45:08 PM PDT 24
Peak memory 218356 kb
Host smart-dc20dea4-3c7a-4f63-88bc-0ee21f8c180f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987674431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1987674431
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4045988781
Short name T704
Test name
Test status
Simulation time 25477663466 ps
CPU time 25.17 seconds
Started Mar 19 02:54:39 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 218464 kb
Host smart-52a38f29-488a-4d79-8be5-398befe72252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045988781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4045988781
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1237164655
Short name T122
Test name
Test status
Simulation time 2669633937 ps
CPU time 169.01 seconds
Started Mar 19 02:44:30 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 214656 kb
Host smart-89a0d7a7-06a6-4c10-aca0-b43f9e8fda57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237164655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1237164655
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4177080147
Short name T119
Test name
Test status
Simulation time 12734331956 ps
CPU time 170.73 seconds
Started Mar 19 02:54:40 PM PDT 24
Finished Mar 19 02:57:31 PM PDT 24
Peak memory 213920 kb
Host smart-3bca0184-9938-4058-a75d-25b2e9148107
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177080147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4177080147
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1557962318
Short name T702
Test name
Test status
Simulation time 4277195739 ps
CPU time 34.92 seconds
Started Mar 19 02:54:39 PM PDT 24
Finished Mar 19 02:55:14 PM PDT 24
Peak memory 217600 kb
Host smart-cbf4fc47-65f0-4ab2-a191-8516267871dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557962318 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1557962318
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2300265864
Short name T765
Test name
Test status
Simulation time 34103549215 ps
CPU time 25.83 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 219004 kb
Host smart-94345202-b9dd-4d27-b340-849e2fda7be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300265864 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2300265864
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2454202838
Short name T885
Test name
Test status
Simulation time 171082136 ps
CPU time 8.45 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:44:40 PM PDT 24
Peak memory 210832 kb
Host smart-ecc4d2e6-b5af-4cc8-867e-8646c1e5c0fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454202838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2454202838
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3969030026
Short name T706
Test name
Test status
Simulation time 689421901 ps
CPU time 8.07 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:54:46 PM PDT 24
Peak memory 210936 kb
Host smart-50b63884-b93f-450f-bb9a-4f9addd8c8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969030026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3969030026
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2150337767
Short name T118
Test name
Test status
Simulation time 3647433247 ps
CPU time 57.51 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:55:36 PM PDT 24
Peak memory 214040 kb
Host smart-2a381e2f-38a7-4081-9452-6a0aa7d7b834
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150337767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2150337767
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3179467929
Short name T89
Test name
Test status
Simulation time 22077230646 ps
CPU time 94.23 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:46:08 PM PDT 24
Peak memory 215224 kb
Host smart-5d1ad246-1663-435e-a5f0-20ae4297482f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179467929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3179467929
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1823575850
Short name T828
Test name
Test status
Simulation time 2128484964 ps
CPU time 21.66 seconds
Started Mar 19 02:54:40 PM PDT 24
Finished Mar 19 02:55:01 PM PDT 24
Peak memory 211796 kb
Host smart-b2645ab3-48f3-47c5-9a52-9c361615d5bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823575850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1823575850
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.721548122
Short name T800
Test name
Test status
Simulation time 696397658 ps
CPU time 12.12 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:44:44 PM PDT 24
Peak memory 211944 kb
Host smart-1ab65874-9f92-4502-a877-e2131326e11d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721548122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.721548122
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1304382447
Short name T812
Test name
Test status
Simulation time 345804402 ps
CPU time 11.5 seconds
Started Mar 19 02:44:35 PM PDT 24
Finished Mar 19 02:44:47 PM PDT 24
Peak memory 216928 kb
Host smart-9217f88b-5880-4d7b-b162-122d03a96c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304382447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1304382447
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1951363380
Short name T753
Test name
Test status
Simulation time 12640944529 ps
CPU time 29.8 seconds
Started Mar 19 02:54:37 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 217620 kb
Host smart-fcdcbfc1-61bf-474d-ab32-f1c250ac193a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951363380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1951363380
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2217054996
Short name T890
Test name
Test status
Simulation time 2448140233 ps
CPU time 165.79 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 213604 kb
Host smart-54269d02-cca3-4d03-b3b5-f0ec1c727fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217054996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2217054996
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.587772098
Short name T796
Test name
Test status
Simulation time 4312286461 ps
CPU time 163.35 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:47:16 PM PDT 24
Peak memory 213840 kb
Host smart-061e9429-2b36-4a16-908b-2161b712d850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587772098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.587772098
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1202308500
Short name T711
Test name
Test status
Simulation time 704930070 ps
CPU time 8.62 seconds
Started Mar 19 02:54:37 PM PDT 24
Finished Mar 19 02:54:46 PM PDT 24
Peak memory 213804 kb
Host smart-3e1c9576-25cf-4db6-af02-cf3d142f0429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202308500 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1202308500
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3510712801
Short name T825
Test name
Test status
Simulation time 202790784 ps
CPU time 8.76 seconds
Started Mar 19 02:44:36 PM PDT 24
Finished Mar 19 02:44:45 PM PDT 24
Peak memory 215704 kb
Host smart-0a2bd9f4-e7ee-4460-98a8-a25312297648
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510712801 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3510712801
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1132267263
Short name T693
Test name
Test status
Simulation time 613089220 ps
CPU time 8.04 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:41 PM PDT 24
Peak memory 210840 kb
Host smart-880cf3f2-c4ff-4366-8acd-8cddb32b5806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132267263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1132267263
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4043166018
Short name T91
Test name
Test status
Simulation time 1889695349 ps
CPU time 19.59 seconds
Started Mar 19 02:54:40 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 211220 kb
Host smart-68b7d288-3963-4de9-9a3f-b53056705b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043166018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4043166018
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.12945528
Short name T718
Test name
Test status
Simulation time 688632136 ps
CPU time 38.23 seconds
Started Mar 19 02:44:30 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 212932 kb
Host smart-613e83fb-b2c5-4799-9217-92f245db7be0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12945528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pass
thru_mem_tl_intg_err.12945528
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1759391557
Short name T889
Test name
Test status
Simulation time 25583321755 ps
CPU time 193.29 seconds
Started Mar 19 02:54:41 PM PDT 24
Finished Mar 19 02:57:55 PM PDT 24
Peak memory 215060 kb
Host smart-6f326044-1233-493d-a422-bd2871d0c95e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759391557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1759391557
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3877426792
Short name T914
Test name
Test status
Simulation time 10823712481 ps
CPU time 25.53 seconds
Started Mar 19 02:54:39 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 210948 kb
Host smart-a32a5626-ee82-44ef-99d3-aa4fe9a270c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877426792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3877426792
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.974314042
Short name T918
Test name
Test status
Simulation time 214099921 ps
CPU time 8.48 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:44:40 PM PDT 24
Peak memory 210936 kb
Host smart-815af677-9044-4310-8fec-dc5a806efe1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974314042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.974314042
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1182049659
Short name T748
Test name
Test status
Simulation time 7501045168 ps
CPU time 24.63 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 218520 kb
Host smart-25db62ad-7247-4b44-a829-4fde73addc04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182049659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1182049659
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3799277415
Short name T871
Test name
Test status
Simulation time 13049126885 ps
CPU time 30.56 seconds
Started Mar 19 02:54:37 PM PDT 24
Finished Mar 19 02:55:08 PM PDT 24
Peak memory 217756 kb
Host smart-6acfce44-a06e-4bda-becd-54661c7bee31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799277415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3799277415
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2228880166
Short name T793
Test name
Test status
Simulation time 3982691670 ps
CPU time 101.11 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 214200 kb
Host smart-0f7448a4-71cd-4b98-8337-e92ffc4750d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228880166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2228880166
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3747203797
Short name T920
Test name
Test status
Simulation time 4174355065 ps
CPU time 172.4 seconds
Started Mar 19 02:54:40 PM PDT 24
Finished Mar 19 02:57:32 PM PDT 24
Peak memory 214560 kb
Host smart-15b96a10-c908-4fe8-b5d3-2b158f93971f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747203797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3747203797
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2919002986
Short name T895
Test name
Test status
Simulation time 6739064541 ps
CPU time 27.98 seconds
Started Mar 19 02:54:37 PM PDT 24
Finished Mar 19 02:55:05 PM PDT 24
Peak memory 218336 kb
Host smart-5ca6fad6-b839-4a96-b0ec-80313307b970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919002986 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2919002986
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.889448624
Short name T856
Test name
Test status
Simulation time 12022116022 ps
CPU time 25.34 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:44:56 PM PDT 24
Peak memory 215396 kb
Host smart-b4708548-4515-41fd-b6b2-a1a686f38cfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889448624 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.889448624
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2097037195
Short name T807
Test name
Test status
Simulation time 345555249 ps
CPU time 8.11 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:44:40 PM PDT 24
Peak memory 210888 kb
Host smart-a6b88242-d081-4195-84cc-b5d23e501104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097037195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2097037195
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4130121588
Short name T888
Test name
Test status
Simulation time 1735342297 ps
CPU time 18.59 seconds
Started Mar 19 02:54:39 PM PDT 24
Finished Mar 19 02:54:58 PM PDT 24
Peak memory 211592 kb
Host smart-cd286875-262c-4eee-ba55-d492c6e64fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130121588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4130121588
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2342960230
Short name T62
Test name
Test status
Simulation time 1675171652 ps
CPU time 47.98 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:45:19 PM PDT 24
Peak memory 212824 kb
Host smart-57e97ecb-9412-42d1-a399-b268082f2cb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342960230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2342960230
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.36926224
Short name T806
Test name
Test status
Simulation time 8771802420 ps
CPU time 105.81 seconds
Started Mar 19 02:54:42 PM PDT 24
Finished Mar 19 02:56:28 PM PDT 24
Peak memory 215516 kb
Host smart-8cda9a21-c293-4b98-92de-b0504fb38f0f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36926224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pass
thru_mem_tl_intg_err.36926224
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3396826643
Short name T111
Test name
Test status
Simulation time 1706750030 ps
CPU time 21.67 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:55:00 PM PDT 24
Peak memory 212128 kb
Host smart-90b37733-96ed-4dc4-a4e3-eb6524f3be5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396826643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3396826643
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4146863155
Short name T815
Test name
Test status
Simulation time 176801499 ps
CPU time 12.4 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:46 PM PDT 24
Peak memory 212264 kb
Host smart-a618fa43-2f68-4fdd-9c63-670303ebfc9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146863155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4146863155
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.333626921
Short name T898
Test name
Test status
Simulation time 167633620 ps
CPU time 12.15 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:54:50 PM PDT 24
Peak memory 216064 kb
Host smart-90db6eac-b661-4e8e-8089-81bf7b69dc7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333626921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.333626921
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.812879317
Short name T852
Test name
Test status
Simulation time 3070451981 ps
CPU time 22.9 seconds
Started Mar 19 02:44:33 PM PDT 24
Finished Mar 19 02:44:56 PM PDT 24
Peak memory 217264 kb
Host smart-64a3cce5-213a-4e2f-ac14-119cef614d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812879317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.812879317
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1798176590
Short name T846
Test name
Test status
Simulation time 1244164141 ps
CPU time 83.9 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:45:56 PM PDT 24
Peak memory 214040 kb
Host smart-92c7e051-4d13-4d23-9895-640aacb52fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798176590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1798176590
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.876817139
Short name T814
Test name
Test status
Simulation time 847317667 ps
CPU time 153.83 seconds
Started Mar 19 02:54:35 PM PDT 24
Finished Mar 19 02:57:09 PM PDT 24
Peak memory 213628 kb
Host smart-cf4b96bc-7aae-4096-b130-3bf7da25e11e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876817139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.876817139
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1232117633
Short name T795
Test name
Test status
Simulation time 8817959909 ps
CPU time 21.84 seconds
Started Mar 19 02:44:30 PM PDT 24
Finished Mar 19 02:44:53 PM PDT 24
Peak memory 217112 kb
Host smart-28897197-498e-468d-a211-c7f6eb4fb5e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232117633 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1232117633
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.398017576
Short name T741
Test name
Test status
Simulation time 4115155490 ps
CPU time 34.02 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:55:12 PM PDT 24
Peak memory 217052 kb
Host smart-baca2d7f-1efb-4786-8301-6fea87420905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398017576 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.398017576
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1774672311
Short name T703
Test name
Test status
Simulation time 10276336896 ps
CPU time 32.05 seconds
Started Mar 19 02:54:37 PM PDT 24
Finished Mar 19 02:55:09 PM PDT 24
Peak memory 212164 kb
Host smart-602e152c-ba24-4c4a-b0a3-526f4dcbccf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774672311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1774672311
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4084350435
Short name T696
Test name
Test status
Simulation time 4973479554 ps
CPU time 22.86 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 211680 kb
Host smart-8cb9701c-a3f9-487f-8db7-9fc17f75ba62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084350435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4084350435
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2907982756
Short name T88
Test name
Test status
Simulation time 41132528134 ps
CPU time 121.28 seconds
Started Mar 19 02:44:32 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 215132 kb
Host smart-ddd2e020-cfaa-4490-992e-4f523dd8c6e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907982756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2907982756
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.66102714
Short name T906
Test name
Test status
Simulation time 11224278230 ps
CPU time 99.39 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:56:18 PM PDT 24
Peak memory 214056 kb
Host smart-68a22426-e8a3-453b-ad36-f5d93aaece9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66102714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pass
thru_mem_tl_intg_err.66102714
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1936893448
Short name T108
Test name
Test status
Simulation time 360302966 ps
CPU time 8.37 seconds
Started Mar 19 02:44:31 PM PDT 24
Finished Mar 19 02:44:40 PM PDT 24
Peak memory 210924 kb
Host smart-b3a2c921-ba46-490c-9d04-761e374226c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936893448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1936893448
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3365916732
Short name T876
Test name
Test status
Simulation time 7180924378 ps
CPU time 29.18 seconds
Started Mar 19 02:54:37 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 212224 kb
Host smart-9aef19b6-9ec4-46ce-8d3c-520b40a60bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365916732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3365916732
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.236662097
Short name T877
Test name
Test status
Simulation time 2352617602 ps
CPU time 12.47 seconds
Started Mar 19 02:44:34 PM PDT 24
Finished Mar 19 02:44:47 PM PDT 24
Peak memory 217060 kb
Host smart-c00490f2-5e45-49f8-8801-e00ab3a7bdde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236662097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.236662097
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3423630505
Short name T736
Test name
Test status
Simulation time 969947185 ps
CPU time 12.95 seconds
Started Mar 19 02:54:39 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 217120 kb
Host smart-029ae6d0-baee-474d-adad-0e2c0aa405e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423630505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3423630505
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1115341367
Short name T59
Test name
Test status
Simulation time 287844092 ps
CPU time 84.14 seconds
Started Mar 19 02:54:38 PM PDT 24
Finished Mar 19 02:56:02 PM PDT 24
Peak memory 213432 kb
Host smart-54576b25-6099-41bf-a269-a36c95268c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115341367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1115341367
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3237801785
Short name T775
Test name
Test status
Simulation time 4858044575 ps
CPU time 164.46 seconds
Started Mar 19 02:44:35 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 213752 kb
Host smart-8f317145-7761-4c46-b050-2b85d2ea5f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237801785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3237801785
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3073187772
Short name T246
Test name
Test status
Simulation time 1339586649 ps
CPU time 8.74 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:48 PM PDT 24
Peak memory 210892 kb
Host smart-797d2cd4-0b77-4fa2-a91e-cb6825acb242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073187772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3073187772
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3424349028
Short name T221
Test name
Test status
Simulation time 4988034374 ps
CPU time 11.16 seconds
Started Mar 19 02:48:34 PM PDT 24
Finished Mar 19 02:48:45 PM PDT 24
Peak memory 210948 kb
Host smart-60b6f63b-89c7-48cf-ad15-c4dca01b503e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424349028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3424349028
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.30792992
Short name T450
Test name
Test status
Simulation time 14337953656 ps
CPU time 136.17 seconds
Started Mar 19 02:48:49 PM PDT 24
Finished Mar 19 02:51:05 PM PDT 24
Peak memory 224320 kb
Host smart-1ec67b9b-f708-4585-8b25-e6738bbae5fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30792992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_cor
rupt_sig_fatal_chk.30792992
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2423474382
Short name T645
Test name
Test status
Simulation time 47812468116 ps
CPU time 32.74 seconds
Started Mar 19 03:08:36 PM PDT 24
Finished Mar 19 03:09:09 PM PDT 24
Peak memory 211880 kb
Host smart-473fe755-7dce-4753-9874-07f5a40aaae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423474382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2423474382
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.894874918
Short name T568
Test name
Test status
Simulation time 2961599848 ps
CPU time 26.74 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:58 PM PDT 24
Peak memory 211764 kb
Host smart-101cd661-d890-4725-99bf-fa9cc2de9b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894874918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.894874918
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2863059367
Short name T115
Test name
Test status
Simulation time 2013411820 ps
CPU time 16.87 seconds
Started Mar 19 02:48:33 PM PDT 24
Finished Mar 19 02:48:50 PM PDT 24
Peak memory 210832 kb
Host smart-606ff1af-3445-413a-a7ce-7824184156a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863059367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2863059367
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4098264
Short name T586
Test name
Test status
Simulation time 184323831 ps
CPU time 5.62 seconds
Started Mar 19 03:08:34 PM PDT 24
Finished Mar 19 03:08:41 PM PDT 24
Peak memory 210804 kb
Host smart-d4c31063-766f-4bbd-af5c-31d7b0528243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4098264
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.158139441
Short name T38
Test name
Test status
Simulation time 22546044372 ps
CPU time 109.65 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:10:25 PM PDT 24
Peak memory 230656 kb
Host smart-646b7750-f6c6-4eb0-a873-b12408b466ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158139441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.158139441
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1859140469
Short name T33
Test name
Test status
Simulation time 3064158004 ps
CPU time 61.06 seconds
Started Mar 19 02:48:37 PM PDT 24
Finished Mar 19 02:49:38 PM PDT 24
Peak memory 233144 kb
Host smart-401b8f45-253b-44db-b085-614683aa0205
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859140469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1859140469
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1464902577
Short name T117
Test name
Test status
Simulation time 453806112 ps
CPU time 10.18 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:42 PM PDT 24
Peak memory 218984 kb
Host smart-fb834f3d-28a8-4dd3-af77-832407d76b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464902577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1464902577
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4269293008
Short name T355
Test name
Test status
Simulation time 35442025650 ps
CPU time 30.84 seconds
Started Mar 19 03:08:38 PM PDT 24
Finished Mar 19 03:09:09 PM PDT 24
Peak memory 219080 kb
Host smart-bf669b35-74ad-4c84-9f22-4bb8d815f0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269293008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4269293008
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1485212503
Short name T228
Test name
Test status
Simulation time 742587826 ps
CPU time 11.58 seconds
Started Mar 19 02:48:38 PM PDT 24
Finished Mar 19 02:48:49 PM PDT 24
Peak memory 213736 kb
Host smart-af233ee0-08fc-4ce8-ab8a-7f2962ece2ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485212503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1485212503
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2407375621
Short name T513
Test name
Test status
Simulation time 3620028528 ps
CPU time 23 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:47 PM PDT 24
Peak memory 219016 kb
Host smart-77b9239b-10e3-4b46-83cb-13a29e347651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407375621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2407375621
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3950100886
Short name T67
Test name
Test status
Simulation time 2109053908 ps
CPU time 16.02 seconds
Started Mar 19 03:08:32 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 210888 kb
Host smart-a6cd94b1-c703-4ebd-9318-dddab618e3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950100886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3950100886
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.82230781
Short name T612
Test name
Test status
Simulation time 85554409 ps
CPU time 4.41 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:48:48 PM PDT 24
Peak memory 210884 kb
Host smart-32df33d7-8d50-4c05-af4b-90bee127cc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82230781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.82230781
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1121126852
Short name T354
Test name
Test status
Simulation time 70231994071 ps
CPU time 318.78 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:13:42 PM PDT 24
Peak memory 229280 kb
Host smart-8aee7051-3f70-437d-bb73-ea6f82647a21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121126852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1121126852
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1369661451
Short name T400
Test name
Test status
Simulation time 16124038562 ps
CPU time 199.13 seconds
Started Mar 19 02:48:44 PM PDT 24
Finished Mar 19 02:52:03 PM PDT 24
Peak memory 228360 kb
Host smart-664ac387-9552-4135-b0f6-9d4cd0fd1cc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369661451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1369661451
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2392648506
Short name T578
Test name
Test status
Simulation time 3955073762 ps
CPU time 33.68 seconds
Started Mar 19 02:48:40 PM PDT 24
Finished Mar 19 02:49:14 PM PDT 24
Peak memory 211524 kb
Host smart-a8521866-0127-49df-bd3d-68ef953d6609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392648506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2392648506
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3668104542
Short name T251
Test name
Test status
Simulation time 4257158283 ps
CPU time 35.09 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:09:06 PM PDT 24
Peak memory 211524 kb
Host smart-2c806609-7a0f-464a-9ec2-65d67efb30ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668104542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3668104542
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1051759151
Short name T656
Test name
Test status
Simulation time 1052784146 ps
CPU time 12.29 seconds
Started Mar 19 03:08:25 PM PDT 24
Finished Mar 19 03:08:38 PM PDT 24
Peak memory 210844 kb
Host smart-96090896-d0e8-419e-a352-803ff6fa1397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051759151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1051759151
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1616424740
Short name T206
Test name
Test status
Simulation time 1335855731 ps
CPU time 13.59 seconds
Started Mar 19 02:48:32 PM PDT 24
Finished Mar 19 02:48:45 PM PDT 24
Peak memory 210812 kb
Host smart-103a8624-5f2f-47d0-818e-691a7833b30c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616424740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1616424740
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3504021750
Short name T37
Test name
Test status
Simulation time 2075517422 ps
CPU time 61.88 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:09:37 PM PDT 24
Peak memory 236232 kb
Host smart-04fa6963-e1d3-4e2e-9974-41a9cc8faae3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504021750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3504021750
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2527671880
Short name T84
Test name
Test status
Simulation time 1072848293 ps
CPU time 10.22 seconds
Started Mar 19 02:48:31 PM PDT 24
Finished Mar 19 02:48:41 PM PDT 24
Peak memory 219016 kb
Host smart-7a859f66-460b-4676-92fc-e3c6fc38a39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527671880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2527671880
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4226727462
Short name T4
Test name
Test status
Simulation time 4067956501 ps
CPU time 43.88 seconds
Started Mar 19 03:08:28 PM PDT 24
Finished Mar 19 03:09:14 PM PDT 24
Peak memory 213060 kb
Host smart-d3fdb980-5d04-4be4-87de-629751b982a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226727462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4226727462
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1223314516
Short name T643
Test name
Test status
Simulation time 14410915741 ps
CPU time 124.71 seconds
Started Mar 19 02:48:51 PM PDT 24
Finished Mar 19 02:50:55 PM PDT 24
Peak memory 219060 kb
Host smart-c80b6286-b762-4c7a-811c-dd0aa0452a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223314516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1223314516
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2828519284
Short name T505
Test name
Test status
Simulation time 596368954 ps
CPU time 33.26 seconds
Started Mar 19 03:08:30 PM PDT 24
Finished Mar 19 03:09:05 PM PDT 24
Peak memory 219080 kb
Host smart-32712ea8-17cf-454f-99ef-430816233338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828519284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2828519284
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2015671147
Short name T106
Test name
Test status
Simulation time 24836060086 ps
CPU time 2167.7 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 03:25:02 PM PDT 24
Peak memory 227396 kb
Host smart-c3d7b8fd-fe9c-4db7-9320-b2f96f4e5f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015671147 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2015671147
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1108917352
Short name T208
Test name
Test status
Simulation time 1476163817 ps
CPU time 12.91 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:52 PM PDT 24
Peak memory 210884 kb
Host smart-9ea2709f-cdce-43ba-a720-c5f81025708d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108917352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1108917352
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3260996441
Short name T431
Test name
Test status
Simulation time 4952856306 ps
CPU time 11.68 seconds
Started Mar 19 02:48:56 PM PDT 24
Finished Mar 19 02:49:08 PM PDT 24
Peak memory 210916 kb
Host smart-9c9b74ca-ae49-46e2-ae8d-cd68231caf3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260996441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3260996441
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4007829801
Short name T201
Test name
Test status
Simulation time 88123591545 ps
CPU time 210.57 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:12:23 PM PDT 24
Peak memory 230532 kb
Host smart-e50458aa-7610-4657-9fdf-3fc30fd3f12f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007829801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4007829801
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.590748987
Short name T284
Test name
Test status
Simulation time 6837024981 ps
CPU time 81.52 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:50:19 PM PDT 24
Peak memory 230684 kb
Host smart-ee752a69-2383-40ae-95f1-ae386230a50a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590748987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.590748987
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2880096726
Short name T217
Test name
Test status
Simulation time 16424425326 ps
CPU time 15.66 seconds
Started Mar 19 02:49:03 PM PDT 24
Finished Mar 19 02:49:20 PM PDT 24
Peak memory 211980 kb
Host smart-a02ee974-674e-4491-bf30-f7ac8b7308b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880096726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2880096726
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1086655993
Short name T510
Test name
Test status
Simulation time 193102709 ps
CPU time 5.45 seconds
Started Mar 19 02:49:04 PM PDT 24
Finished Mar 19 02:49:10 PM PDT 24
Peak memory 210824 kb
Host smart-fc684e00-89fc-4733-b699-d41b6d791cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086655993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1086655993
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.347755940
Short name T202
Test name
Test status
Simulation time 2309689642 ps
CPU time 12.3 seconds
Started Mar 19 03:09:04 PM PDT 24
Finished Mar 19 03:09:16 PM PDT 24
Peak memory 210932 kb
Host smart-20061c43-7b44-45ab-adb9-32bef155b6d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347755940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.347755940
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.129568444
Short name T680
Test name
Test status
Simulation time 182961794 ps
CPU time 10.3 seconds
Started Mar 19 02:48:51 PM PDT 24
Finished Mar 19 02:49:02 PM PDT 24
Peak memory 218988 kb
Host smart-968f61a5-da44-4fa1-ab82-40929e8e797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129568444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.129568444
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1605347081
Short name T275
Test name
Test status
Simulation time 727286024 ps
CPU time 10.31 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 213736 kb
Host smart-e32a41a3-0b77-4b42-bf70-cb61fa80c65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605347081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1605347081
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1768176188
Short name T168
Test name
Test status
Simulation time 44131996856 ps
CPU time 52.17 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:09:35 PM PDT 24
Peak memory 219040 kb
Host smart-66551c77-2af8-4df6-b91f-e879c51d758d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768176188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1768176188
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3774026951
Short name T43
Test name
Test status
Simulation time 803289870 ps
CPU time 11.67 seconds
Started Mar 19 02:49:00 PM PDT 24
Finished Mar 19 02:49:13 PM PDT 24
Peak memory 214456 kb
Host smart-def62806-6a8d-473d-9f27-04144e1cf96d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774026951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3774026951
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3335837596
Short name T493
Test name
Test status
Simulation time 3848225695 ps
CPU time 15.85 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:24 PM PDT 24
Peak memory 210936 kb
Host smart-89a6cea5-e4a4-416b-9ebc-f0a43092bba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335837596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3335837596
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2764504106
Short name T138
Test name
Test status
Simulation time 28294668793 ps
CPU time 264.09 seconds
Started Mar 19 02:49:00 PM PDT 24
Finished Mar 19 02:53:24 PM PDT 24
Peak memory 236836 kb
Host smart-baf911b9-68dd-43d3-8f3c-7a3d053c766e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764504106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2764504106
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3904031776
Short name T144
Test name
Test status
Simulation time 2995643059 ps
CPU time 18.63 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:09:01 PM PDT 24
Peak memory 212356 kb
Host smart-95874174-3208-4c95-81a7-4f710c69eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904031776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3904031776
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4187212995
Short name T615
Test name
Test status
Simulation time 1334138484 ps
CPU time 5.66 seconds
Started Mar 19 03:08:57 PM PDT 24
Finished Mar 19 03:09:03 PM PDT 24
Peak memory 210848 kb
Host smart-b31374cd-f750-4d1e-a2fe-7a355b57ba15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4187212995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4187212995
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4233054206
Short name T23
Test name
Test status
Simulation time 2076564154 ps
CPU time 16.83 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 210836 kb
Host smart-e59bd112-774a-49d0-a90f-e17e1bae034d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233054206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4233054206
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2151201219
Short name T572
Test name
Test status
Simulation time 7866131304 ps
CPU time 36 seconds
Started Mar 19 02:48:50 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 213252 kb
Host smart-729867a5-7184-4544-8dc6-7838115d901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151201219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2151201219
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3853066975
Short name T299
Test name
Test status
Simulation time 2502447782 ps
CPU time 28.28 seconds
Started Mar 19 03:08:47 PM PDT 24
Finished Mar 19 03:09:16 PM PDT 24
Peak memory 219064 kb
Host smart-9218edfd-b2f4-4157-8977-073c2d412c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853066975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3853066975
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.561234795
Short name T249
Test name
Test status
Simulation time 10823426496 ps
CPU time 26.75 seconds
Started Mar 19 02:49:04 PM PDT 24
Finished Mar 19 02:49:31 PM PDT 24
Peak memory 214244 kb
Host smart-237a72c5-89f3-443f-92fc-ef7ec2d3c6dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561234795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.561234795
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.655655922
Short name T474
Test name
Test status
Simulation time 5036321249 ps
CPU time 55.04 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:09:34 PM PDT 24
Peak memory 219072 kb
Host smart-e1fc7c31-e4c9-42eb-a33f-7db84446a397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655655922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.655655922
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2220072416
Short name T65
Test name
Test status
Simulation time 6732601842 ps
CPU time 10.27 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:08:53 PM PDT 24
Peak memory 210976 kb
Host smart-d708be8a-ef19-4c83-8177-d7e4bae18f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220072416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2220072416
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2334358372
Short name T444
Test name
Test status
Simulation time 2175624705 ps
CPU time 16.69 seconds
Started Mar 19 02:49:03 PM PDT 24
Finished Mar 19 02:49:21 PM PDT 24
Peak memory 210960 kb
Host smart-8d8e44e2-359f-4aa6-97ea-e0dedbfa858c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334358372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2334358372
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1374565787
Short name T233
Test name
Test status
Simulation time 23666054936 ps
CPU time 263.54 seconds
Started Mar 19 02:48:53 PM PDT 24
Finished Mar 19 02:53:17 PM PDT 24
Peak memory 228552 kb
Host smart-d2397150-d5fb-461c-a937-7080e524fce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374565787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1374565787
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2240399810
Short name T224
Test name
Test status
Simulation time 51697290446 ps
CPU time 274.65 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:13:14 PM PDT 24
Peak memory 228272 kb
Host smart-78637bf4-7912-48e5-9279-5c8abae92f85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240399810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2240399810
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3026873649
Short name T461
Test name
Test status
Simulation time 3636568049 ps
CPU time 31.01 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:09:16 PM PDT 24
Peak memory 211564 kb
Host smart-569f1710-d2bb-4033-bdbc-7b723dbe95f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026873649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3026873649
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.994512134
Short name T250
Test name
Test status
Simulation time 17217247132 ps
CPU time 27.63 seconds
Started Mar 19 02:49:10 PM PDT 24
Finished Mar 19 02:49:39 PM PDT 24
Peak memory 211736 kb
Host smart-b68cf492-ab0c-4f27-afa4-db509a4df06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994512134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.994512134
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.359286935
Short name T393
Test name
Test status
Simulation time 394010986 ps
CPU time 5.26 seconds
Started Mar 19 03:08:40 PM PDT 24
Finished Mar 19 03:08:46 PM PDT 24
Peak memory 210852 kb
Host smart-545518de-0a4d-4e10-9a77-26964c6c5812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359286935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.359286935
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.936712205
Short name T356
Test name
Test status
Simulation time 2049359147 ps
CPU time 16.88 seconds
Started Mar 19 02:49:02 PM PDT 24
Finished Mar 19 02:49:20 PM PDT 24
Peak memory 210800 kb
Host smart-5144e25f-58d4-4beb-9369-f3073e4ecd43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936712205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.936712205
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1333048145
Short name T606
Test name
Test status
Simulation time 15515790249 ps
CPU time 17.91 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 219064 kb
Host smart-404f6c99-5a80-4834-afe9-a6edad624542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333048145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1333048145
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.230917857
Short name T219
Test name
Test status
Simulation time 190452727 ps
CPU time 10.26 seconds
Started Mar 19 02:49:07 PM PDT 24
Finished Mar 19 02:49:18 PM PDT 24
Peak memory 219024 kb
Host smart-5ba2b6d5-96d5-4a67-8f5b-7e82f65a497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230917857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.230917857
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2893686941
Short name T540
Test name
Test status
Simulation time 7495828183 ps
CPU time 37.71 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 213488 kb
Host smart-4c0e52aa-9f60-433a-9993-fd2bc488ee75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893686941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2893686941
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.88610070
Short name T332
Test name
Test status
Simulation time 8158364441 ps
CPU time 27.67 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:24 PM PDT 24
Peak memory 216120 kb
Host smart-7242a73f-7efd-47a8-b441-ee1411a3d8c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88610070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.rom_ctrl_stress_all.88610070
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1490937113
Short name T463
Test name
Test status
Simulation time 260093192 ps
CPU time 5.06 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:08:46 PM PDT 24
Peak memory 210864 kb
Host smart-3901944a-d220-4742-85ce-11690c3c3349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490937113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1490937113
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2830161621
Short name T552
Test name
Test status
Simulation time 22620388434 ps
CPU time 15.57 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:12 PM PDT 24
Peak memory 210916 kb
Host smart-c8bbe636-beed-4a8d-abfa-b9f33ed90d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830161621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2830161621
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2534005287
Short name T203
Test name
Test status
Simulation time 57537945726 ps
CPU time 230.71 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:53:02 PM PDT 24
Peak memory 213432 kb
Host smart-21f9454f-e238-4cd6-8b56-d9254ce0d666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534005287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2534005287
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3192105889
Short name T190
Test name
Test status
Simulation time 11912404669 ps
CPU time 122.35 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:10:44 PM PDT 24
Peak memory 228292 kb
Host smart-8ab4f0ad-b05c-49c6-88c5-1218920ec930
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192105889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3192105889
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3120207244
Short name T551
Test name
Test status
Simulation time 1797560027 ps
CPU time 19.98 seconds
Started Mar 19 02:48:52 PM PDT 24
Finished Mar 19 02:49:12 PM PDT 24
Peak memory 211516 kb
Host smart-08ba881b-239c-47ff-a6cf-d6bf0214797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120207244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3120207244
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4250672003
Short name T459
Test name
Test status
Simulation time 2860327632 ps
CPU time 27.82 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 211456 kb
Host smart-acfca18c-ffd0-4df7-9f46-e2b1418d5ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250672003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4250672003
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1157748553
Short name T527
Test name
Test status
Simulation time 608057700 ps
CPU time 9.14 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:49:09 PM PDT 24
Peak memory 210816 kb
Host smart-d8e408a8-ba99-4d79-b98b-0d77d842658e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157748553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1157748553
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4036787072
Short name T259
Test name
Test status
Simulation time 547166642 ps
CPU time 8.78 seconds
Started Mar 19 03:08:49 PM PDT 24
Finished Mar 19 03:08:58 PM PDT 24
Peak memory 210832 kb
Host smart-4dd6ded8-ecf0-46ca-8e7d-14312dc6e069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036787072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4036787072
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2932370034
Short name T323
Test name
Test status
Simulation time 2911754962 ps
CPU time 30.67 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 219080 kb
Host smart-0053d62f-25b3-4f95-ba78-225c6311f831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932370034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2932370034
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.682903189
Short name T603
Test name
Test status
Simulation time 2118356970 ps
CPU time 13.54 seconds
Started Mar 19 02:49:02 PM PDT 24
Finished Mar 19 02:49:17 PM PDT 24
Peak memory 213276 kb
Host smart-7b980d02-9697-4b7b-9107-1ff6731cae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682903189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.682903189
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3534234822
Short name T69
Test name
Test status
Simulation time 20394072096 ps
CPU time 24.61 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:49:18 PM PDT 24
Peak memory 219068 kb
Host smart-2546b0f3-9a7f-421e-9b44-242611266d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534234822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3534234822
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.937146586
Short name T351
Test name
Test status
Simulation time 20511231300 ps
CPU time 56.04 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 217104 kb
Host smart-75957a4b-2a6d-43a2-a8b1-eab879570aff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937146586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.937146586
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3368260140
Short name T55
Test name
Test status
Simulation time 75684952574 ps
CPU time 714.03 seconds
Started Mar 19 03:08:36 PM PDT 24
Finished Mar 19 03:20:30 PM PDT 24
Peak memory 227788 kb
Host smart-dcb7bed4-a74c-4ef6-abcf-c822b4e13cda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368260140 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3368260140
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4258211757
Short name T524
Test name
Test status
Simulation time 164096647522 ps
CPU time 3162.33 seconds
Started Mar 19 02:48:49 PM PDT 24
Finished Mar 19 03:41:31 PM PDT 24
Peak memory 244596 kb
Host smart-eeab4f9d-f279-41b6-9f8c-2957b682084e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258211757 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.4258211757
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2019874190
Short name T6
Test name
Test status
Simulation time 8049293756 ps
CPU time 16.28 seconds
Started Mar 19 02:48:53 PM PDT 24
Finished Mar 19 02:49:09 PM PDT 24
Peak memory 210960 kb
Host smart-22d5e113-8670-462e-be61-b5945d45305d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019874190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2019874190
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3890694808
Short name T629
Test name
Test status
Simulation time 347673982 ps
CPU time 4.15 seconds
Started Mar 19 03:08:40 PM PDT 24
Finished Mar 19 03:08:45 PM PDT 24
Peak memory 210916 kb
Host smart-1d0bb1fb-21ca-4555-be1c-3d3acc9b6bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890694808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3890694808
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3517130632
Short name T17
Test name
Test status
Simulation time 3720581464 ps
CPU time 122.63 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:10:56 PM PDT 24
Peak memory 229536 kb
Host smart-8f7d6856-92ce-4c89-9c84-eabb7c3fc6ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517130632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3517130632
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4083815174
Short name T18
Test name
Test status
Simulation time 73574344561 ps
CPU time 175.48 seconds
Started Mar 19 02:48:51 PM PDT 24
Finished Mar 19 02:51:47 PM PDT 24
Peak memory 233516 kb
Host smart-67f7f23d-3708-4f81-9e81-ba51181d7136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083815174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4083815174
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1434159475
Short name T291
Test name
Test status
Simulation time 23474029630 ps
CPU time 32.31 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 211932 kb
Host smart-89d0ee0c-a975-4af1-81bc-b8fd915e1f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434159475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1434159475
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2292154178
Short name T267
Test name
Test status
Simulation time 168530228 ps
CPU time 9.31 seconds
Started Mar 19 03:08:57 PM PDT 24
Finished Mar 19 03:09:07 PM PDT 24
Peak memory 211524 kb
Host smart-22b54ab2-c44d-4961-86bc-7176ace10f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292154178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2292154178
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3304292586
Short name T309
Test name
Test status
Simulation time 4136113611 ps
CPU time 12.66 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 210892 kb
Host smart-8b48229b-be0f-442e-a9cd-9793ee249837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304292586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3304292586
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4160839438
Short name T532
Test name
Test status
Simulation time 8864297091 ps
CPU time 18.35 seconds
Started Mar 19 02:48:52 PM PDT 24
Finished Mar 19 02:49:11 PM PDT 24
Peak memory 210928 kb
Host smart-5adeccab-7e1a-4159-9715-a3a1613d7ddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160839438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4160839438
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1619442416
Short name T649
Test name
Test status
Simulation time 1580489214 ps
CPU time 15.22 seconds
Started Mar 19 03:08:40 PM PDT 24
Finished Mar 19 03:08:55 PM PDT 24
Peak memory 213112 kb
Host smart-731e420e-2b42-4c97-b223-61edb137e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619442416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1619442416
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3437429583
Short name T57
Test name
Test status
Simulation time 365791568 ps
CPU time 10.19 seconds
Started Mar 19 02:48:52 PM PDT 24
Finished Mar 19 02:49:02 PM PDT 24
Peak memory 219016 kb
Host smart-9152476e-0477-4278-9312-026fd83f5fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437429583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3437429583
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1872406001
Short name T165
Test name
Test status
Simulation time 4437639835 ps
CPU time 24.48 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:09:13 PM PDT 24
Peak memory 219056 kb
Host smart-3e0b0a3c-c309-47ed-8ece-b468598ecae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872406001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1872406001
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.416303714
Short name T10
Test name
Test status
Simulation time 4088617621 ps
CPU time 30.47 seconds
Started Mar 19 02:48:53 PM PDT 24
Finished Mar 19 02:49:24 PM PDT 24
Peak memory 219084 kb
Host smart-0e676425-91b0-4276-b9b1-d2b509d8f6e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416303714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.416303714
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2082061776
Short name T262
Test name
Test status
Simulation time 5825267694 ps
CPU time 13.01 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 210940 kb
Host smart-76bde09e-630f-4058-9dbf-9a0d10ab4cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082061776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2082061776
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3434783041
Short name T181
Test name
Test status
Simulation time 1166743514 ps
CPU time 10.87 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:09 PM PDT 24
Peak memory 210860 kb
Host smart-c272dbb5-7431-4f6b-a643-54b6c6ab77c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434783041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3434783041
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3278490299
Short name T502
Test name
Test status
Simulation time 1855732120 ps
CPU time 113.81 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:50:51 PM PDT 24
Peak memory 237532 kb
Host smart-3afdb2d2-75cf-4e7d-a398-206eb782bd89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278490299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3278490299
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.842406175
Short name T244
Test name
Test status
Simulation time 20840453848 ps
CPU time 191.82 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:11:56 PM PDT 24
Peak memory 218368 kb
Host smart-b97cc4a7-e31a-486d-ae3f-444b2a518220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842406175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.842406175
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1282400284
Short name T421
Test name
Test status
Simulation time 16966873923 ps
CPU time 33.13 seconds
Started Mar 19 02:49:03 PM PDT 24
Finished Mar 19 02:49:37 PM PDT 24
Peak memory 219136 kb
Host smart-cc8b0cb0-aa74-438b-911e-eb7dd5350e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282400284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1282400284
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.192139793
Short name T432
Test name
Test status
Simulation time 2845393703 ps
CPU time 26.47 seconds
Started Mar 19 03:08:58 PM PDT 24
Finished Mar 19 03:09:25 PM PDT 24
Peak memory 211588 kb
Host smart-c9e16694-3815-4f4f-a12d-6828d7c70510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192139793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.192139793
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3175892624
Short name T634
Test name
Test status
Simulation time 7165052017 ps
CPU time 15.19 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:09:00 PM PDT 24
Peak memory 210880 kb
Host smart-dec2c126-9b39-416b-af97-c8902238bf58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175892624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3175892624
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3308251175
Short name T222
Test name
Test status
Simulation time 160566382 ps
CPU time 5.71 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:49:05 PM PDT 24
Peak memory 210860 kb
Host smart-e2c6792e-692b-4cc8-8ce7-066fd4035d13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308251175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3308251175
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2335541503
Short name T365
Test name
Test status
Simulation time 721611365 ps
CPU time 10.25 seconds
Started Mar 19 02:49:01 PM PDT 24
Finished Mar 19 02:49:11 PM PDT 24
Peak memory 212888 kb
Host smart-c016d462-5bd4-4220-957c-25274bce8f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335541503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2335541503
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3316945092
Short name T580
Test name
Test status
Simulation time 13186812730 ps
CPU time 38.46 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 214040 kb
Host smart-ce5ad386-4180-40c0-ac59-2146193b09a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316945092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3316945092
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2656820407
Short name T258
Test name
Test status
Simulation time 587372679 ps
CPU time 10.88 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:08:55 PM PDT 24
Peak memory 210768 kb
Host smart-763d40b5-885c-4173-b29c-1261da280711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656820407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2656820407
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3837240779
Short name T499
Test name
Test status
Simulation time 8047318595 ps
CPU time 17.51 seconds
Started Mar 19 02:48:52 PM PDT 24
Finished Mar 19 02:49:10 PM PDT 24
Peak memory 211888 kb
Host smart-0d51b670-816f-404f-8caa-8765aac0e34d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837240779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3837240779
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1154154758
Short name T342
Test name
Test status
Simulation time 334192383 ps
CPU time 4.35 seconds
Started Mar 19 02:49:00 PM PDT 24
Finished Mar 19 02:49:04 PM PDT 24
Peak memory 210900 kb
Host smart-1b215a91-124e-4ae9-95d6-a9ee1f2eaed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154154758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1154154758
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2232094096
Short name T64
Test name
Test status
Simulation time 171730262 ps
CPU time 4.22 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:08:48 PM PDT 24
Peak memory 210904 kb
Host smart-8c55f41d-ae9d-4559-b8cc-35452b43a1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232094096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2232094096
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1140181743
Short name T672
Test name
Test status
Simulation time 4605562752 ps
CPU time 79.84 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:50:17 PM PDT 24
Peak memory 228912 kb
Host smart-45c754f1-f48c-412f-a5aa-14c196cd6578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140181743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1140181743
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3465900266
Short name T504
Test name
Test status
Simulation time 92911481469 ps
CPU time 455.81 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:16:29 PM PDT 24
Peak memory 237556 kb
Host smart-ee4c847d-62f2-4a65-8aa2-953a3f5fff37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465900266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3465900266
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2596489740
Short name T347
Test name
Test status
Simulation time 2037272240 ps
CPU time 20.61 seconds
Started Mar 19 02:49:06 PM PDT 24
Finished Mar 19 02:49:27 PM PDT 24
Peak memory 210820 kb
Host smart-472cdcae-a5ad-471d-adf3-4df6f7d31ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596489740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2596489740
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4175587010
Short name T26
Test name
Test status
Simulation time 14930921886 ps
CPU time 33.39 seconds
Started Mar 19 03:08:46 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 211832 kb
Host smart-fe60c1b3-21b8-4f1b-9357-a272ff5e7535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175587010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4175587010
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2253159008
Short name T185
Test name
Test status
Simulation time 448873391 ps
CPU time 5.7 seconds
Started Mar 19 03:08:52 PM PDT 24
Finished Mar 19 03:08:58 PM PDT 24
Peak memory 210856 kb
Host smart-4468ae54-4d71-461c-ae8d-8c255bb16b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253159008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2253159008
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2853588920
Short name T389
Test name
Test status
Simulation time 1948637257 ps
CPU time 10.93 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:20 PM PDT 24
Peak memory 210832 kb
Host smart-80865b8e-d923-42b4-bd2d-4400dcf2e432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853588920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2853588920
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1906155265
Short name T136
Test name
Test status
Simulation time 12736748360 ps
CPU time 26.96 seconds
Started Mar 19 02:48:58 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 214272 kb
Host smart-ef191ead-c357-47ac-bbad-c4e6beb9704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906155265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1906155265
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2597116334
Short name T574
Test name
Test status
Simulation time 183014949 ps
CPU time 10.44 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 213264 kb
Host smart-9caceaad-3f13-4b08-a154-2dad4c10ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597116334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2597116334
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2043873543
Short name T435
Test name
Test status
Simulation time 7926654270 ps
CPU time 37.37 seconds
Started Mar 19 03:08:38 PM PDT 24
Finished Mar 19 03:09:15 PM PDT 24
Peak memory 213660 kb
Host smart-647e0831-e981-415e-9ced-fa4ba270be25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043873543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2043873543
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4158946072
Short name T177
Test name
Test status
Simulation time 4393706485 ps
CPU time 39.43 seconds
Started Mar 19 02:49:00 PM PDT 24
Finished Mar 19 02:49:40 PM PDT 24
Peak memory 219060 kb
Host smart-cac3e55c-e908-492e-bcfe-eef36f74f8f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158946072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4158946072
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.108208671
Short name T243
Test name
Test status
Simulation time 996853194 ps
CPU time 10.59 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:49:10 PM PDT 24
Peak memory 210880 kb
Host smart-f5cf3396-f7d7-492e-9152-0edf694f0d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108208671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.108208671
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3334814666
Short name T212
Test name
Test status
Simulation time 2740686417 ps
CPU time 12.92 seconds
Started Mar 19 03:08:55 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 210924 kb
Host smart-e117ec9c-f235-45dc-bdc2-c0c091765fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334814666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3334814666
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3052147250
Short name T289
Test name
Test status
Simulation time 14157712201 ps
CPU time 197.32 seconds
Started Mar 19 03:08:38 PM PDT 24
Finished Mar 19 03:11:55 PM PDT 24
Peak memory 232812 kb
Host smart-cf0d52d8-a29f-41e0-aa55-777d38325c2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052147250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3052147250
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.466573989
Short name T472
Test name
Test status
Simulation time 82579381862 ps
CPU time 187.68 seconds
Started Mar 19 02:49:06 PM PDT 24
Finished Mar 19 02:52:14 PM PDT 24
Peak memory 228384 kb
Host smart-41543795-1178-48e3-a903-e0efdef7bb96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466573989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.466573989
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.708899393
Short name T590
Test name
Test status
Simulation time 6885290835 ps
CPU time 28.96 seconds
Started Mar 19 03:08:48 PM PDT 24
Finished Mar 19 03:09:17 PM PDT 24
Peak memory 211764 kb
Host smart-c116d7bc-d0f0-445d-ac01-7d9e3404f489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708899393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.708899393
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1855407538
Short name T378
Test name
Test status
Simulation time 171931721 ps
CPU time 5.73 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:15 PM PDT 24
Peak memory 210840 kb
Host smart-7d653529-c9cd-49dc-afc4-418a3ee7d7e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855407538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1855407538
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.767173041
Short name T336
Test name
Test status
Simulation time 99475304 ps
CPU time 5.9 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:45 PM PDT 24
Peak memory 210836 kb
Host smart-5d8f21e7-a33b-44f4-94e6-e8ce6d8261d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767173041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.767173041
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1994659267
Short name T617
Test name
Test status
Simulation time 1985144946 ps
CPU time 17.18 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:09:29 PM PDT 24
Peak memory 212984 kb
Host smart-5d3c1482-fbe1-4a3c-8f24-85a94a7b975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994659267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1994659267
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.257968982
Short name T339
Test name
Test status
Simulation time 929585368 ps
CPU time 17.87 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:30 PM PDT 24
Peak memory 212804 kb
Host smart-d6863b3b-7e38-47d6-819a-2194cfc0d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257968982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.257968982
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3490339658
Short name T662
Test name
Test status
Simulation time 8612074094 ps
CPU time 30.09 seconds
Started Mar 19 03:08:49 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 213656 kb
Host smart-1a6e17ea-ccb3-42a6-83b1-2d464415c6e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490339658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3490339658
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3873309637
Short name T518
Test name
Test status
Simulation time 1013431276 ps
CPU time 25.73 seconds
Started Mar 19 02:49:05 PM PDT 24
Finished Mar 19 02:49:31 PM PDT 24
Peak memory 219000 kb
Host smart-312eac72-ec58-4b22-9cb4-f4e6ac9cf4a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873309637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3873309637
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2481118336
Short name T302
Test name
Test status
Simulation time 89061699 ps
CPU time 4.32 seconds
Started Mar 19 02:49:14 PM PDT 24
Finished Mar 19 02:49:18 PM PDT 24
Peak memory 210888 kb
Host smart-50b1f7b0-0a72-4445-a231-3b4881f47f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481118336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2481118336
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3595040000
Short name T390
Test name
Test status
Simulation time 1769272842 ps
CPU time 14.55 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:09:28 PM PDT 24
Peak memory 210864 kb
Host smart-d59f38ff-7083-4fe5-81cb-6cdf4123b260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595040000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3595040000
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1838107206
Short name T637
Test name
Test status
Simulation time 22983598725 ps
CPU time 225.13 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:52:44 PM PDT 24
Peak memory 233528 kb
Host smart-829d4139-c7c2-4991-aab2-b5981a2632f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838107206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1838107206
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.743289702
Short name T154
Test name
Test status
Simulation time 54038471828 ps
CPU time 119.44 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:10:43 PM PDT 24
Peak memory 229288 kb
Host smart-3b2df24e-d954-4a58-aad0-4eed27e6ab71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743289702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.743289702
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.180015480
Short name T565
Test name
Test status
Simulation time 692065750 ps
CPU time 9.44 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 211592 kb
Host smart-985bf6ce-6dd3-4624-b59b-10ee47e7a94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180015480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.180015480
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3185673461
Short name T422
Test name
Test status
Simulation time 3222847319 ps
CPU time 28.56 seconds
Started Mar 19 02:49:02 PM PDT 24
Finished Mar 19 02:49:31 PM PDT 24
Peak memory 211588 kb
Host smart-841fdb4d-8107-4bf7-b918-1445ef9b659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185673461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3185673461
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1849299161
Short name T375
Test name
Test status
Simulation time 4346189766 ps
CPU time 11.69 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:09:03 PM PDT 24
Peak memory 210888 kb
Host smart-1a50de27-8a7e-45c6-a8a2-a7bd7820f439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849299161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1849299161
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1864528924
Short name T213
Test name
Test status
Simulation time 8571707117 ps
CPU time 16.84 seconds
Started Mar 19 02:48:58 PM PDT 24
Finished Mar 19 02:49:15 PM PDT 24
Peak memory 210880 kb
Host smart-c19bd76f-1d31-4918-a71d-36a313e19fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864528924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1864528924
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1524644028
Short name T523
Test name
Test status
Simulation time 3079691549 ps
CPU time 30.08 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:42 PM PDT 24
Peak memory 212788 kb
Host smart-0af9319a-7532-4fdb-91d8-68ff6c9903fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524644028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1524644028
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4271665025
Short name T582
Test name
Test status
Simulation time 7451742851 ps
CPU time 20.61 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:09:35 PM PDT 24
Peak memory 219016 kb
Host smart-6d9fb8e7-cbe5-44d9-9153-410fae5ef5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271665025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4271665025
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2313001610
Short name T20
Test name
Test status
Simulation time 1074007714 ps
CPU time 22.7 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:09:15 PM PDT 24
Peak memory 219012 kb
Host smart-2dd770cb-4fb9-4f79-829d-174df79fb6eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313001610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2313001610
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3074733458
Short name T191
Test name
Test status
Simulation time 13702907836 ps
CPU time 82.96 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:50:43 PM PDT 24
Peak memory 219052 kb
Host smart-12202b48-b912-439f-ba52-815d5b801c9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074733458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3074733458
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1702941672
Short name T520
Test name
Test status
Simulation time 3918569558 ps
CPU time 10.65 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:09:05 PM PDT 24
Peak memory 210916 kb
Host smart-ed79a2e6-e98a-4762-923c-58912834c900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702941672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1702941672
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2049290968
Short name T609
Test name
Test status
Simulation time 5805148082 ps
CPU time 8.96 seconds
Started Mar 19 02:49:00 PM PDT 24
Finished Mar 19 02:49:09 PM PDT 24
Peak memory 210944 kb
Host smart-c57f564d-f019-4565-85e1-d78a0638817b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049290968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2049290968
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2695955557
Short name T273
Test name
Test status
Simulation time 9817301684 ps
CPU time 124.16 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:10:55 PM PDT 24
Peak memory 220328 kb
Host smart-2c763b76-f3d4-4fcc-b851-83d16d07d6b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695955557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2695955557
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4101739967
Short name T451
Test name
Test status
Simulation time 1843719698 ps
CPU time 9.42 seconds
Started Mar 19 03:09:20 PM PDT 24
Finished Mar 19 03:09:30 PM PDT 24
Peak memory 211828 kb
Host smart-48452822-8f09-418d-b187-7cd13f8d2eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101739967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4101739967
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.7825036
Short name T290
Test name
Test status
Simulation time 24576491421 ps
CPU time 29.48 seconds
Started Mar 19 02:49:15 PM PDT 24
Finished Mar 19 02:49:45 PM PDT 24
Peak memory 212340 kb
Host smart-4ca4eb55-c9cb-4013-876e-abcd3183a91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7825036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.7825036
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2411651886
Short name T542
Test name
Test status
Simulation time 3440710930 ps
CPU time 15.22 seconds
Started Mar 19 02:49:06 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 210896 kb
Host smart-7a85c257-c882-4817-861d-2760b2827681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411651886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2411651886
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4196948072
Short name T639
Test name
Test status
Simulation time 224145613 ps
CPU time 6.94 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:08:51 PM PDT 24
Peak memory 210844 kb
Host smart-31097058-c399-4b56-a6a1-293e83e480b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196948072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4196948072
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1592053920
Short name T676
Test name
Test status
Simulation time 940496888 ps
CPU time 9.8 seconds
Started Mar 19 03:08:49 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 219012 kb
Host smart-606a89b7-ed9c-48c0-9571-bbecc89a939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592053920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1592053920
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1243427903
Short name T227
Test name
Test status
Simulation time 695156694 ps
CPU time 34.54 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:44 PM PDT 24
Peak memory 218860 kb
Host smart-382a219e-3a55-4999-9144-142f1b3cf2c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243427903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1243427903
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3137773278
Short name T226
Test name
Test status
Simulation time 1285562321 ps
CPU time 14.26 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:08:57 PM PDT 24
Peak memory 210852 kb
Host smart-24664f5e-b49b-4ab5-9d92-e274b62a4d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137773278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3137773278
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1479443484
Short name T657
Test name
Test status
Simulation time 4262750525 ps
CPU time 17.04 seconds
Started Mar 19 02:48:42 PM PDT 24
Finished Mar 19 02:48:59 PM PDT 24
Peak memory 210976 kb
Host smart-14308d04-723a-48cb-8f0a-0e1f3f1fdd18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479443484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1479443484
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3096237903
Short name T406
Test name
Test status
Simulation time 89978568 ps
CPU time 4.26 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:08:36 PM PDT 24
Peak memory 210888 kb
Host smart-8c0193b2-5646-4b08-a03b-31fc91610382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096237903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3096237903
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4093859785
Short name T616
Test name
Test status
Simulation time 26092099104 ps
CPU time 247.95 seconds
Started Mar 19 02:48:45 PM PDT 24
Finished Mar 19 02:52:53 PM PDT 24
Peak memory 225316 kb
Host smart-f16ccf87-7bfe-44de-bd37-ba82113c6a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093859785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4093859785
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.455196065
Short name T658
Test name
Test status
Simulation time 188502690200 ps
CPU time 444.52 seconds
Started Mar 19 03:08:38 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 230540 kb
Host smart-7cb16d73-826c-48c8-a524-9127b9ed5608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455196065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.455196065
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.266450843
Short name T141
Test name
Test status
Simulation time 17173603134 ps
CPU time 33.33 seconds
Started Mar 19 02:48:47 PM PDT 24
Finished Mar 19 02:49:20 PM PDT 24
Peak memory 212720 kb
Host smart-ed298ef7-c2c1-4b36-81ea-f618e4abd34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266450843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.266450843
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3391222957
Short name T22
Test name
Test status
Simulation time 175361170 ps
CPU time 9.4 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:08:45 PM PDT 24
Peak memory 211360 kb
Host smart-a004d938-0bf0-4c74-851c-e59e992eabde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391222957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3391222957
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1934995122
Short name T166
Test name
Test status
Simulation time 95021512 ps
CPU time 5.37 seconds
Started Mar 19 02:48:44 PM PDT 24
Finished Mar 19 02:48:50 PM PDT 24
Peak memory 210852 kb
Host smart-20b45ba3-cf1e-4f50-afa4-d90154d35a45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934995122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1934995122
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4240942447
Short name T229
Test name
Test status
Simulation time 2148949914 ps
CPU time 17.31 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:08:53 PM PDT 24
Peak memory 210896 kb
Host smart-4167c8ed-44ec-4ea1-82be-e7afc89be97d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240942447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4240942447
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2038855417
Short name T35
Test name
Test status
Simulation time 856962089 ps
CPU time 101.33 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:50:38 PM PDT 24
Peak memory 230844 kb
Host smart-39072736-7403-425e-859c-5be6f5a385a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038855417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2038855417
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2872293150
Short name T39
Test name
Test status
Simulation time 12914331091 ps
CPU time 107.82 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:10:25 PM PDT 24
Peak memory 233956 kb
Host smart-c380585e-50cd-46a9-8826-5ef646834b81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872293150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2872293150
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1516872201
Short name T479
Test name
Test status
Simulation time 753716314 ps
CPU time 10.1 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 219004 kb
Host smart-3cc2aa3a-15e3-4f16-ae77-5f7d5202bf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516872201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1516872201
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1556273937
Short name T82
Test name
Test status
Simulation time 1497243643 ps
CPU time 10.53 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:48:53 PM PDT 24
Peak memory 213096 kb
Host smart-6a4bbeba-ed7e-4746-84b8-51c7ce0fa2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556273937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1556273937
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1877709113
Short name T454
Test name
Test status
Simulation time 4308477198 ps
CPU time 49.37 seconds
Started Mar 19 03:08:21 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 213228 kb
Host smart-f58e0fac-8777-42d9-ae93-841a4de43c38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877709113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1877709113
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1878024173
Short name T539
Test name
Test status
Simulation time 27071803090 ps
CPU time 50.66 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:49:46 PM PDT 24
Peak memory 219088 kb
Host smart-63fda60e-0c63-410a-9f19-edc174a6fdc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878024173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1878024173
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1727565471
Short name T51
Test name
Test status
Simulation time 30320791278 ps
CPU time 10237.3 seconds
Started Mar 19 02:48:53 PM PDT 24
Finished Mar 19 05:39:32 PM PDT 24
Peak memory 235556 kb
Host smart-85f0e7ec-ba4f-4196-87c2-3ef157097f6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727565471 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1727565471
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1278742213
Short name T445
Test name
Test status
Simulation time 8015904648 ps
CPU time 14.4 seconds
Started Mar 19 02:49:06 PM PDT 24
Finished Mar 19 02:49:21 PM PDT 24
Peak memory 210916 kb
Host smart-e3ca316a-0a7b-471b-b21b-67ced8ea75f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278742213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1278742213
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1338729957
Short name T604
Test name
Test status
Simulation time 87073072 ps
CPU time 4.31 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:10 PM PDT 24
Peak memory 210892 kb
Host smart-110ce24e-c1da-4094-8001-43e2cfd13921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338729957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1338729957
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2352614021
Short name T425
Test name
Test status
Simulation time 56339349563 ps
CPU time 195.56 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:11:58 PM PDT 24
Peak memory 236520 kb
Host smart-c089a5f3-1643-4eb1-91b2-5574c2100b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352614021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2352614021
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.455898005
Short name T467
Test name
Test status
Simulation time 35307020768 ps
CPU time 187.53 seconds
Started Mar 19 02:49:04 PM PDT 24
Finished Mar 19 02:52:12 PM PDT 24
Peak memory 229716 kb
Host smart-e2125a01-2ad7-402e-ad42-b5814e1c3344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455898005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.455898005
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1146762234
Short name T396
Test name
Test status
Simulation time 665396467 ps
CPU time 9.51 seconds
Started Mar 19 03:08:56 PM PDT 24
Finished Mar 19 03:09:06 PM PDT 24
Peak memory 211500 kb
Host smart-d12dfd0c-9ffe-42b2-ac4e-2c3d96ac78ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146762234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1146762234
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.632683126
Short name T261
Test name
Test status
Simulation time 2654078688 ps
CPU time 14.81 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:13 PM PDT 24
Peak memory 211676 kb
Host smart-b4bcae85-a5e3-4fb5-9699-288be18ba730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632683126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.632683126
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2036720478
Short name T282
Test name
Test status
Simulation time 3358031043 ps
CPU time 10.31 seconds
Started Mar 19 03:08:52 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 210920 kb
Host smart-6ce16990-2f25-43a6-bdaa-87db1e85d075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036720478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2036720478
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3526631123
Short name T507
Test name
Test status
Simulation time 2052251050 ps
CPU time 17.13 seconds
Started Mar 19 02:48:58 PM PDT 24
Finished Mar 19 02:49:15 PM PDT 24
Peak memory 210824 kb
Host smart-08b8d310-dfbd-434d-881a-8f79d55244a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526631123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3526631123
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1686715558
Short name T673
Test name
Test status
Simulation time 16913195955 ps
CPU time 28.93 seconds
Started Mar 19 02:49:00 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 219092 kb
Host smart-7366005a-6e8b-4893-b1a6-5236df62fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686715558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1686715558
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3906799996
Short name T288
Test name
Test status
Simulation time 3863454869 ps
CPU time 35.4 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 212940 kb
Host smart-4c7eff71-fab1-4636-a271-5e21ad1ee6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906799996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3906799996
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1216666077
Short name T417
Test name
Test status
Simulation time 350407048 ps
CPU time 6.47 seconds
Started Mar 19 03:08:47 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 210752 kb
Host smart-e4f4fc6c-e0f4-4337-b93a-060797b9de3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216666077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1216666077
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2498821186
Short name T337
Test name
Test status
Simulation time 4969230286 ps
CPU time 56.53 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:53 PM PDT 24
Peak memory 219100 kb
Host smart-222ea9a5-6852-4f9e-a22d-27cf53d3d470
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498821186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2498821186
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1646318467
Short name T254
Test name
Test status
Simulation time 8604355994 ps
CPU time 15.18 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:09:15 PM PDT 24
Peak memory 210900 kb
Host smart-02c125f3-45fe-4843-9a97-66be8b050105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646318467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1646318467
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3724038888
Short name T640
Test name
Test status
Simulation time 89127690 ps
CPU time 4.36 seconds
Started Mar 19 02:49:10 PM PDT 24
Finished Mar 19 02:49:14 PM PDT 24
Peak memory 210888 kb
Host smart-a75c9165-7f09-4004-8ac6-ab8fe33146a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724038888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3724038888
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3127128601
Short name T170
Test name
Test status
Simulation time 8187766935 ps
CPU time 122.83 seconds
Started Mar 19 03:08:52 PM PDT 24
Finished Mar 19 03:10:55 PM PDT 24
Peak memory 219324 kb
Host smart-4fd62ed5-1d63-43c0-9a6c-75326b809b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127128601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3127128601
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3764686677
Short name T407
Test name
Test status
Simulation time 102247571880 ps
CPU time 426.51 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 230452 kb
Host smart-bacf5089-0230-48dd-b1f5-27513cf02b05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764686677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3764686677
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2364407241
Short name T334
Test name
Test status
Simulation time 615732818 ps
CPU time 9.69 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:09:09 PM PDT 24
Peak memory 211544 kb
Host smart-441059eb-9ae7-4f42-af1f-a42d45ca5c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364407241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2364407241
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3333363784
Short name T276
Test name
Test status
Simulation time 16403374450 ps
CPU time 32.3 seconds
Started Mar 19 02:49:17 PM PDT 24
Finished Mar 19 02:49:49 PM PDT 24
Peak memory 212172 kb
Host smart-d6e4e160-955e-48b4-89f3-5bd3a96e4cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333363784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3333363784
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2714997566
Short name T242
Test name
Test status
Simulation time 393936201 ps
CPU time 5.63 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 210832 kb
Host smart-c508b0bd-d591-4a49-b31d-69ea1d94df8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714997566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2714997566
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.522963479
Short name T650
Test name
Test status
Simulation time 1516567764 ps
CPU time 7.78 seconds
Started Mar 19 02:49:00 PM PDT 24
Finished Mar 19 02:49:08 PM PDT 24
Peak memory 210836 kb
Host smart-cffb703e-794a-4a23-9f14-e5e86237af3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522963479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.522963479
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3615875235
Short name T313
Test name
Test status
Simulation time 5875346627 ps
CPU time 18.97 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:09:12 PM PDT 24
Peak memory 219064 kb
Host smart-c380a150-f202-4b40-8971-dbfb90300b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615875235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3615875235
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.751978820
Short name T187
Test name
Test status
Simulation time 5381399018 ps
CPU time 24.66 seconds
Started Mar 19 02:49:16 PM PDT 24
Finished Mar 19 02:49:41 PM PDT 24
Peak memory 219072 kb
Host smart-dca6824f-cdc0-4596-9669-8dd1913ddbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751978820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.751978820
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2698773264
Short name T327
Test name
Test status
Simulation time 534169906 ps
CPU time 22.19 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 215908 kb
Host smart-d0eba95c-da0a-41ac-9a47-0d5ecb2dba0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698773264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2698773264
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.901788508
Short name T155
Test name
Test status
Simulation time 6390022881 ps
CPU time 32.17 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:09:23 PM PDT 24
Peak memory 218924 kb
Host smart-57c2ca42-badd-4ebc-a8a1-d35d6aea7636
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901788508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.901788508
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4013501043
Short name T436
Test name
Test status
Simulation time 46835679933 ps
CPU time 439.37 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:16:02 PM PDT 24
Peak memory 232332 kb
Host smart-83b6261c-a473-499f-ad80-f0124f617db7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013501043 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4013501043
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1948287942
Short name T371
Test name
Test status
Simulation time 88274142 ps
CPU time 4.22 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:08:50 PM PDT 24
Peak memory 210824 kb
Host smart-e07ee3ba-ed0f-4d06-90ce-86d1e2cfac7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948287942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1948287942
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3110616062
Short name T416
Test name
Test status
Simulation time 995600645 ps
CPU time 6.08 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 210868 kb
Host smart-e3d53bc1-8fa8-4589-978b-2ff122105b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110616062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3110616062
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.451734692
Short name T587
Test name
Test status
Simulation time 9040314603 ps
CPU time 141.07 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:11:21 PM PDT 24
Peak memory 228276 kb
Host smart-1c307979-50e9-417d-befe-873ea86fe6cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451734692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.451734692
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.906312536
Short name T486
Test name
Test status
Simulation time 22542511315 ps
CPU time 248.35 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:53:05 PM PDT 24
Peak memory 234524 kb
Host smart-716fa7c8-c433-40cd-a441-d2b476cba765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906312536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.906312536
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1715705559
Short name T653
Test name
Test status
Simulation time 8224487519 ps
CPU time 21.96 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:19 PM PDT 24
Peak memory 211664 kb
Host smart-698da246-6ec3-4c11-adcf-f26cdf95d5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715705559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1715705559
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3395260545
Short name T142
Test name
Test status
Simulation time 340721940 ps
CPU time 9.51 seconds
Started Mar 19 03:08:58 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 211684 kb
Host smart-02358256-f295-4743-9a73-c833dc53e906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395260545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3395260545
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3518340079
Short name T167
Test name
Test status
Simulation time 6817606110 ps
CPU time 14.99 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 210928 kb
Host smart-1e986c6e-97f6-4e46-8d9d-82eafeebc2d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518340079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3518340079
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.801863589
Short name T149
Test name
Test status
Simulation time 1139812694 ps
CPU time 11.99 seconds
Started Mar 19 02:49:02 PM PDT 24
Finished Mar 19 02:49:15 PM PDT 24
Peak memory 210824 kb
Host smart-551732a0-1070-4fbf-9128-525583c458b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801863589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.801863589
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2162288457
Short name T19
Test name
Test status
Simulation time 4671791231 ps
CPU time 17.82 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 213780 kb
Host smart-5299a449-66bc-4c24-856f-e391be66c2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162288457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2162288457
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.654821707
Short name T314
Test name
Test status
Simulation time 3498326470 ps
CPU time 17.51 seconds
Started Mar 19 02:48:58 PM PDT 24
Finished Mar 19 02:49:16 PM PDT 24
Peak memory 219048 kb
Host smart-05f5f5bf-9545-40ea-9b11-5c1fbf2f0ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654821707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.654821707
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1887397686
Short name T308
Test name
Test status
Simulation time 18124325583 ps
CPU time 53.37 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:50:02 PM PDT 24
Peak memory 219068 kb
Host smart-e234c84d-3b49-4814-8542-61a4a9acaedb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887397686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1887397686
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3259618663
Short name T218
Test name
Test status
Simulation time 797690962 ps
CPU time 9.07 seconds
Started Mar 19 03:08:47 PM PDT 24
Finished Mar 19 03:08:56 PM PDT 24
Peak memory 211536 kb
Host smart-f968d52d-196e-4da5-b4eb-ca50ccca4f27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259618663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3259618663
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2657129749
Short name T595
Test name
Test status
Simulation time 10691363338 ps
CPU time 2156.25 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 03:24:56 PM PDT 24
Peak memory 221968 kb
Host smart-f7dc3b57-1fa3-424e-b2fd-112e48f94eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657129749 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2657129749
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1386958197
Short name T374
Test name
Test status
Simulation time 296626844 ps
CPU time 6.4 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:45 PM PDT 24
Peak memory 210904 kb
Host smart-29490c6f-d0b0-4e8d-aecb-2ccf8066ffa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386958197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1386958197
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3388301620
Short name T647
Test name
Test status
Simulation time 3086883815 ps
CPU time 13.86 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 210916 kb
Host smart-fffec43c-3160-4212-ae0d-e358421c99cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388301620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3388301620
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1972893460
Short name T428
Test name
Test status
Simulation time 48579444408 ps
CPU time 162.13 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:11:36 PM PDT 24
Peak memory 212128 kb
Host smart-65920b98-7f17-4ab2-951d-8e7d7c415d54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972893460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1972893460
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.316862436
Short name T24
Test name
Test status
Simulation time 27087837346 ps
CPU time 302.68 seconds
Started Mar 19 02:49:16 PM PDT 24
Finished Mar 19 02:54:19 PM PDT 24
Peak memory 233588 kb
Host smart-50e1e7b4-f6a1-4b37-a0aa-d1abe3308a59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316862436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.316862436
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3813450925
Short name T456
Test name
Test status
Simulation time 2342529975 ps
CPU time 24.47 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:09:07 PM PDT 24
Peak memory 211544 kb
Host smart-c9113ba7-a52f-4735-83d6-fe70987ff66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813450925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3813450925
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4090900074
Short name T469
Test name
Test status
Simulation time 406534227 ps
CPU time 9.46 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:49:32 PM PDT 24
Peak memory 211504 kb
Host smart-62fdf82f-e8f0-4023-a801-32169bbd77a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090900074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4090900074
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1574000341
Short name T333
Test name
Test status
Simulation time 605019424 ps
CPU time 5.37 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:09:06 PM PDT 24
Peak memory 210840 kb
Host smart-6dae532c-ed77-4a1b-a34a-d4ce13d363db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574000341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1574000341
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4143676955
Short name T304
Test name
Test status
Simulation time 1480301701 ps
CPU time 14.14 seconds
Started Mar 19 02:49:14 PM PDT 24
Finished Mar 19 02:49:28 PM PDT 24
Peak memory 210868 kb
Host smart-dd99e471-c9c4-475d-b57b-74521d75fd6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143676955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4143676955
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2391496816
Short name T498
Test name
Test status
Simulation time 2534349882 ps
CPU time 29.92 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:09:24 PM PDT 24
Peak memory 212680 kb
Host smart-873ace2c-289a-4854-b553-a358cd9e1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391496816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2391496816
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.301224085
Short name T571
Test name
Test status
Simulation time 2955261635 ps
CPU time 31.59 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:41 PM PDT 24
Peak memory 219056 kb
Host smart-6d7b62b5-1758-4d27-839a-dadb62513f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301224085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.301224085
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2939470009
Short name T476
Test name
Test status
Simulation time 5805425488 ps
CPU time 60.92 seconds
Started Mar 19 03:08:48 PM PDT 24
Finished Mar 19 03:09:49 PM PDT 24
Peak memory 217936 kb
Host smart-4338b3fe-91b9-4b2e-9dc5-994746c10dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939470009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2939470009
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3447691555
Short name T446
Test name
Test status
Simulation time 40324389914 ps
CPU time 32.97 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:45 PM PDT 24
Peak memory 216792 kb
Host smart-b1149149-53b0-4227-bf54-dd133d344813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447691555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3447691555
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1034479967
Short name T646
Test name
Test status
Simulation time 2728586375 ps
CPU time 12.9 seconds
Started Mar 19 03:08:46 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 210980 kb
Host smart-2f0667de-884e-48b8-8f13-0d4b429e70fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034479967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1034479967
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1289336307
Short name T449
Test name
Test status
Simulation time 1974957520 ps
CPU time 7.64 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:49:30 PM PDT 24
Peak memory 210876 kb
Host smart-da94013a-56fc-4f10-aa76-df809a9ab61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289336307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1289336307
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3577162152
Short name T575
Test name
Test status
Simulation time 5671153082 ps
CPU time 100.99 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:51:03 PM PDT 24
Peak memory 229560 kb
Host smart-30b1e29b-16ba-4036-8776-85c5b057e6d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577162152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3577162152
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.722622610
Short name T359
Test name
Test status
Simulation time 1854172676 ps
CPU time 74.25 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:09:57 PM PDT 24
Peak memory 211744 kb
Host smart-b9d06c53-d5de-4e16-845c-35c4326c0904
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722622610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.722622610
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3156390394
Short name T426
Test name
Test status
Simulation time 340587592 ps
CPU time 9.62 seconds
Started Mar 19 02:49:16 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 211472 kb
Host smart-d7906346-cf9b-4e06-a11b-75adc626161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156390394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3156390394
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3215355401
Short name T550
Test name
Test status
Simulation time 1270782419 ps
CPU time 17.88 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 211516 kb
Host smart-55c42bfd-9454-4437-8dcb-13020f9efc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215355401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3215355401
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1023798679
Short name T659
Test name
Test status
Simulation time 97226337 ps
CPU time 5.42 seconds
Started Mar 19 02:49:16 PM PDT 24
Finished Mar 19 02:49:21 PM PDT 24
Peak memory 210824 kb
Host smart-f934ae5b-cbd7-4b3e-bf7a-b2ea7812e0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023798679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1023798679
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3455366317
Short name T363
Test name
Test status
Simulation time 129924292 ps
CPU time 5.61 seconds
Started Mar 19 03:08:55 PM PDT 24
Finished Mar 19 03:09:01 PM PDT 24
Peak memory 210840 kb
Host smart-fbc52a21-1cfe-47ba-a76c-7f945a6441a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455366317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3455366317
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2850044927
Short name T44
Test name
Test status
Simulation time 2119797256 ps
CPU time 13.83 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 219016 kb
Host smart-062c623c-7dd7-4e36-af6d-10372a6a2f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850044927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2850044927
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2969356339
Short name T164
Test name
Test status
Simulation time 183793827 ps
CPU time 10.4 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:23 PM PDT 24
Peak memory 212760 kb
Host smart-57a3eb04-5c51-4a27-90bd-4f161cf4fa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969356339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2969356339
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1849900889
Short name T248
Test name
Test status
Simulation time 13864551221 ps
CPU time 46.54 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 219104 kb
Host smart-b84f453a-d0d6-4dd0-9920-d9d0872397dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849900889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1849900889
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3935928898
Short name T531
Test name
Test status
Simulation time 12053421049 ps
CPU time 89.31 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:50:48 PM PDT 24
Peak memory 219088 kb
Host smart-7bc3ec38-3443-403d-8655-6268bec588b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935928898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3935928898
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1055910661
Short name T528
Test name
Test status
Simulation time 214421988 ps
CPU time 5.94 seconds
Started Mar 19 03:08:50 PM PDT 24
Finished Mar 19 03:08:56 PM PDT 24
Peak memory 210868 kb
Host smart-17632f3d-0b5e-47cf-942e-999d0a08740e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055910661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1055910661
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4137362973
Short name T439
Test name
Test status
Simulation time 1898725654 ps
CPU time 11.92 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:21 PM PDT 24
Peak memory 210884 kb
Host smart-f51d8749-6c24-4429-a79a-67db4ba2419e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137362973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4137362973
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3436778375
Short name T506
Test name
Test status
Simulation time 42538219239 ps
CPU time 185.49 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:52:15 PM PDT 24
Peak memory 230596 kb
Host smart-69e305ae-9edf-4e3b-a283-a6337b62e63e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436778375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3436778375
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3504699390
Short name T151
Test name
Test status
Simulation time 45842303689 ps
CPU time 415.94 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:15:38 PM PDT 24
Peak memory 236804 kb
Host smart-8d67ad06-8d9a-438b-a3d8-ee3722afba39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504699390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3504699390
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1119124555
Short name T613
Test name
Test status
Simulation time 334707635 ps
CPU time 9.31 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:09:02 PM PDT 24
Peak memory 211652 kb
Host smart-916297b8-b0c6-4ea8-849e-3dab27524578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119124555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1119124555
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.322142146
Short name T252
Test name
Test status
Simulation time 3977428037 ps
CPU time 33.67 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:53 PM PDT 24
Peak memory 211444 kb
Host smart-6e8c2c34-db90-42d4-b18c-48c0ecd4f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322142146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.322142146
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1770694193
Short name T398
Test name
Test status
Simulation time 4473170752 ps
CPU time 11.92 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:21 PM PDT 24
Peak memory 210900 kb
Host smart-bb98b078-f3e3-4534-a18e-1ea791c5e54a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770694193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1770694193
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2297900185
Short name T240
Test name
Test status
Simulation time 100337872 ps
CPU time 5.66 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 210836 kb
Host smart-d9569f7f-3acf-4958-b16d-b7616a6314e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297900185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2297900185
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2803433254
Short name T465
Test name
Test status
Simulation time 15075721764 ps
CPU time 31.67 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:43 PM PDT 24
Peak memory 219064 kb
Host smart-d5f6ed3b-b12b-4667-ab2c-8bcefdc534a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803433254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2803433254
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2975273461
Short name T353
Test name
Test status
Simulation time 8382100312 ps
CPU time 38.93 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:09:49 PM PDT 24
Peak memory 213888 kb
Host smart-72cd4507-512e-40a3-9768-602508b3d998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975273461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2975273461
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4232073117
Short name T135
Test name
Test status
Simulation time 3122996651 ps
CPU time 30.25 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:09:30 PM PDT 24
Peak memory 214512 kb
Host smart-4dae0e9c-e6e2-4baa-88de-cee9f9fcd14b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232073117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4232073117
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.830527082
Short name T383
Test name
Test status
Simulation time 7950963596 ps
CPU time 47.54 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:57 PM PDT 24
Peak memory 217152 kb
Host smart-11d96f1c-ea71-4f79-a89e-12be2c58f6ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830527082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.830527082
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3524941138
Short name T53
Test name
Test status
Simulation time 64335094199 ps
CPU time 3897.55 seconds
Started Mar 19 03:08:49 PM PDT 24
Finished Mar 19 04:13:48 PM PDT 24
Peak memory 230008 kb
Host smart-93b5c3d6-55ee-49ff-b8a8-e21f828f68d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524941138 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3524941138
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1985553337
Short name T146
Test name
Test status
Simulation time 2874295238 ps
CPU time 12.83 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 210888 kb
Host smart-6d32b7be-d7ed-4afb-9d7b-956759b88590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985553337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1985553337
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.922413477
Short name T264
Test name
Test status
Simulation time 16003374516 ps
CPU time 15.57 seconds
Started Mar 19 03:09:05 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 210940 kb
Host smart-f2ba8b06-faad-425a-a81c-aa5cbcf46f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922413477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.922413477
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1800297994
Short name T235
Test name
Test status
Simulation time 58848179556 ps
CPU time 196.13 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 02:52:30 PM PDT 24
Peak memory 240948 kb
Host smart-f669f878-b3dc-4ba5-9d58-ade42c5cc1b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800297994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1800297994
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1827612152
Short name T632
Test name
Test status
Simulation time 25679329034 ps
CPU time 298.12 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:13:59 PM PDT 24
Peak memory 237496 kb
Host smart-b7445b3e-44fe-4b81-b396-77054aa13fad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827612152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1827612152
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2448663445
Short name T163
Test name
Test status
Simulation time 2370997761 ps
CPU time 9.34 seconds
Started Mar 19 02:49:07 PM PDT 24
Finished Mar 19 02:49:17 PM PDT 24
Peak memory 211456 kb
Host smart-36457c18-53b8-4c23-a8cc-c5709333459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448663445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2448663445
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3812606318
Short name T581
Test name
Test status
Simulation time 18867188829 ps
CPU time 25.69 seconds
Started Mar 19 03:08:49 PM PDT 24
Finished Mar 19 03:09:15 PM PDT 24
Peak memory 212020 kb
Host smart-02b1c333-45cb-440c-bbab-2f3c7e490d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812606318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3812606318
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1594812689
Short name T485
Test name
Test status
Simulation time 307417425 ps
CPU time 7.46 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:19 PM PDT 24
Peak memory 210828 kb
Host smart-465d9e80-3341-4b74-a5e4-d454362e805b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594812689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1594812689
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2088936096
Short name T561
Test name
Test status
Simulation time 627365541 ps
CPU time 9.19 seconds
Started Mar 19 03:08:50 PM PDT 24
Finished Mar 19 03:09:00 PM PDT 24
Peak memory 210808 kb
Host smart-b2e312bd-6c09-4246-88ed-91085b7568af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088936096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2088936096
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3248367697
Short name T537
Test name
Test status
Simulation time 674216084 ps
CPU time 10.53 seconds
Started Mar 19 03:09:05 PM PDT 24
Finished Mar 19 03:09:16 PM PDT 24
Peak memory 213252 kb
Host smart-e93dd245-af45-4a06-80df-c71de6f1c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248367697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3248367697
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3920612770
Short name T538
Test name
Test status
Simulation time 12309029959 ps
CPU time 34.73 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:44 PM PDT 24
Peak memory 213724 kb
Host smart-57c21bb4-035a-407c-9fef-0bb39f44e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920612770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3920612770
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1648662258
Short name T638
Test name
Test status
Simulation time 5686778875 ps
CPU time 24.33 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:09:18 PM PDT 24
Peak memory 216144 kb
Host smart-7a51cca5-e5b0-484e-9d83-4939984d39ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648662258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1648662258
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2319823343
Short name T331
Test name
Test status
Simulation time 5157637672 ps
CPU time 52.58 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:50:00 PM PDT 24
Peak memory 216044 kb
Host smart-fa46134d-b0bf-4a17-aec7-705db08ec3d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319823343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2319823343
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3644554683
Short name T321
Test name
Test status
Simulation time 345680407 ps
CPU time 6.53 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:16 PM PDT 24
Peak memory 210904 kb
Host smart-0dffd4aa-19cf-4c39-9549-ef2d64b59205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644554683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3644554683
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.488299607
Short name T343
Test name
Test status
Simulation time 395288290 ps
CPU time 4.29 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:09:05 PM PDT 24
Peak memory 210876 kb
Host smart-84dbe656-069c-4bfc-903e-9124f9eaf862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488299607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.488299607
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1153472431
Short name T255
Test name
Test status
Simulation time 51120402665 ps
CPU time 133.01 seconds
Started Mar 19 03:08:56 PM PDT 24
Finished Mar 19 03:11:10 PM PDT 24
Peak memory 228224 kb
Host smart-6665b002-af2f-4c03-8acb-4f573ebd188f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153472431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1153472431
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2504445253
Short name T381
Test name
Test status
Simulation time 22949376974 ps
CPU time 189.26 seconds
Started Mar 19 02:49:07 PM PDT 24
Finished Mar 19 02:52:17 PM PDT 24
Peak memory 219348 kb
Host smart-e20c82bf-2a25-49de-a97d-b905ccdffb8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504445253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2504445253
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2560382287
Short name T395
Test name
Test status
Simulation time 2615885853 ps
CPU time 24.53 seconds
Started Mar 19 03:08:57 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 211492 kb
Host smart-ef1ed24b-c015-4ea5-b2a0-a2448f15a711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560382287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2560382287
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3254256066
Short name T325
Test name
Test status
Simulation time 10154269384 ps
CPU time 25.16 seconds
Started Mar 19 02:49:17 PM PDT 24
Finished Mar 19 02:49:42 PM PDT 24
Peak memory 211876 kb
Host smart-4cc32173-8d79-4a08-8ea4-278f06a2e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254256066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3254256066
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1470317725
Short name T241
Test name
Test status
Simulation time 101722851 ps
CPU time 6.08 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:14 PM PDT 24
Peak memory 210848 kb
Host smart-cc62e57b-0718-4ea0-8c20-c96aa128631a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470317725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1470317725
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4006100338
Short name T329
Test name
Test status
Simulation time 2026218875 ps
CPU time 8.96 seconds
Started Mar 19 03:08:55 PM PDT 24
Finished Mar 19 03:09:04 PM PDT 24
Peak memory 210852 kb
Host smart-ff69768e-4a27-4bf5-a3b9-fd47dd473d37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006100338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4006100338
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2688774027
Short name T215
Test name
Test status
Simulation time 726803069 ps
CPU time 10.12 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 218940 kb
Host smart-5d6a2b6f-cf5f-4c46-a3f7-75490338fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688774027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2688774027
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3758563681
Short name T481
Test name
Test status
Simulation time 38522420144 ps
CPU time 32.05 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:42 PM PDT 24
Peak memory 219092 kb
Host smart-ec3143af-7cb4-439b-af21-7a6ef7a695c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758563681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3758563681
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1841543625
Short name T186
Test name
Test status
Simulation time 857725195 ps
CPU time 26.96 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:45 PM PDT 24
Peak memory 213800 kb
Host smart-750c25bb-94a6-4571-b9d5-68f6b8c6a1b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841543625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1841543625
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3817148690
Short name T335
Test name
Test status
Simulation time 927039407 ps
CPU time 25.52 seconds
Started Mar 19 03:08:50 PM PDT 24
Finished Mar 19 03:09:15 PM PDT 24
Peak memory 214944 kb
Host smart-2c3d3504-537b-4f9e-bce8-297c9e6ffa63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817148690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3817148690
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4278864420
Short name T68
Test name
Test status
Simulation time 417322840 ps
CPU time 4.42 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:28 PM PDT 24
Peak memory 210860 kb
Host smart-ec8cf8f2-cf00-4d5d-9dfb-5b769b4779c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278864420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4278864420
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4284831147
Short name T464
Test name
Test status
Simulation time 2035483154 ps
CPU time 10.91 seconds
Started Mar 19 03:08:57 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 210756 kb
Host smart-51f97018-49ee-403b-8494-8cb7cd862f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284831147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4284831147
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1873104982
Short name T442
Test name
Test status
Simulation time 8791322074 ps
CPU time 159.59 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:11:46 PM PDT 24
Peak memory 218304 kb
Host smart-f3805f4b-f7b4-44ce-9e93-0b724a6d5589
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873104982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1873104982
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3522780360
Short name T196
Test name
Test status
Simulation time 31315440257 ps
CPU time 321.35 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:54:44 PM PDT 24
Peak memory 212632 kb
Host smart-9c2be5de-9554-49ec-915b-fabbc70f295f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522780360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3522780360
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2127168057
Short name T470
Test name
Test status
Simulation time 28325030373 ps
CPU time 28.4 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:41 PM PDT 24
Peak memory 211724 kb
Host smart-e9795781-b14f-438c-8cb1-0caa74caf92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127168057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2127168057
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.740090988
Short name T50
Test name
Test status
Simulation time 10813645743 ps
CPU time 26.6 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 211640 kb
Host smart-f613b0e8-2909-441f-864b-df87618669e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740090988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.740090988
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1082853238
Short name T434
Test name
Test status
Simulation time 192323220 ps
CPU time 5.36 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 210696 kb
Host smart-98794dbd-e8df-4d17-85b8-678c1782fe7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082853238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1082853238
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1632489906
Short name T536
Test name
Test status
Simulation time 1293898091 ps
CPU time 9.97 seconds
Started Mar 19 03:09:12 PM PDT 24
Finished Mar 19 03:09:23 PM PDT 24
Peak memory 210856 kb
Host smart-507ee740-00cf-485e-8bea-fd15319ffd83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632489906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1632489906
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1357610530
Short name T415
Test name
Test status
Simulation time 5124775067 ps
CPU time 17.93 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:36 PM PDT 24
Peak memory 219068 kb
Host smart-43e52695-b0f6-4590-a918-0f16c72cc405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357610530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1357610530
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3179306046
Short name T675
Test name
Test status
Simulation time 186668606 ps
CPU time 9.99 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 212376 kb
Host smart-bb9e4741-b523-4ae3-9a95-cbfc1f509bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179306046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3179306046
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1920145175
Short name T663
Test name
Test status
Simulation time 3349883050 ps
CPU time 40.61 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:50:00 PM PDT 24
Peak memory 215740 kb
Host smart-68fb443b-d26a-4b5d-b94f-5251c9eced52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920145175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1920145175
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2974343989
Short name T391
Test name
Test status
Simulation time 31645496651 ps
CPU time 74.27 seconds
Started Mar 19 03:08:59 PM PDT 24
Finished Mar 19 03:10:13 PM PDT 24
Peak memory 219088 kb
Host smart-5356e938-a1ed-4d03-92f0-4bdc179fc03a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974343989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2974343989
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1773787605
Short name T460
Test name
Test status
Simulation time 115448248525 ps
CPU time 1031.11 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:26:12 PM PDT 24
Peak memory 235604 kb
Host smart-ca420f13-efc4-4721-bbb2-ad789db4062f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773787605 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1773787605
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3127987359
Short name T452
Test name
Test status
Simulation time 19663202142 ps
CPU time 673.56 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 03:00:23 PM PDT 24
Peak memory 234912 kb
Host smart-18955508-d26d-4ad1-ac36-f3e831c701bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127987359 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3127987359
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1770821609
Short name T292
Test name
Test status
Simulation time 1796423067 ps
CPU time 14.56 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:09:14 PM PDT 24
Peak memory 210884 kb
Host smart-4fe306de-8b47-405e-9181-4a5e306793dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770821609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1770821609
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.651231914
Short name T100
Test name
Test status
Simulation time 968071636 ps
CPU time 9.97 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 210820 kb
Host smart-5db230e8-8e0f-428c-b1e9-ae2f135aafa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651231914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.651231914
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1039726685
Short name T508
Test name
Test status
Simulation time 1676149091 ps
CPU time 99.5 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:10:30 PM PDT 24
Peak memory 230512 kb
Host smart-ad718b48-ab91-4a7b-a36e-b9f7a63657c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039726685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1039726685
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3695220015
Short name T28
Test name
Test status
Simulation time 3646846914 ps
CPU time 101.83 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:50:50 PM PDT 24
Peak memory 232496 kb
Host smart-e02e5133-a553-494a-8331-80e054781714
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695220015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3695220015
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3349161236
Short name T598
Test name
Test status
Simulation time 7205623645 ps
CPU time 31.44 seconds
Started Mar 19 03:09:03 PM PDT 24
Finished Mar 19 03:09:35 PM PDT 24
Peak memory 211824 kb
Host smart-3a59b1d5-4d4c-4b7d-ae89-212e5afdc39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349161236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3349161236
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3910274514
Short name T618
Test name
Test status
Simulation time 3936989303 ps
CPU time 22.73 seconds
Started Mar 19 02:49:10 PM PDT 24
Finished Mar 19 02:49:33 PM PDT 24
Peak memory 211464 kb
Host smart-aa7ae24d-2cb0-4c26-b5a4-362cc693bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910274514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3910274514
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1807816950
Short name T358
Test name
Test status
Simulation time 3803365282 ps
CPU time 11.12 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 210548 kb
Host smart-97cec290-d0a7-4567-b1ea-6b422adac2d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807816950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1807816950
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3471987556
Short name T437
Test name
Test status
Simulation time 4851379314 ps
CPU time 14.13 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 02:49:28 PM PDT 24
Peak memory 210932 kb
Host smart-d10ef734-b592-423e-8cf1-0d884abbec61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471987556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3471987556
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.411746895
Short name T194
Test name
Test status
Simulation time 3542769314 ps
CPU time 34.41 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:44 PM PDT 24
Peak memory 213200 kb
Host smart-1aa1c267-13bb-42a6-8f20-dd62d4b32dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411746895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.411746895
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.4209870394
Short name T438
Test name
Test status
Simulation time 265880292 ps
CPU time 12.01 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:09:03 PM PDT 24
Peak memory 212892 kb
Host smart-4f906742-7e93-430b-9f69-936048df5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209870394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.4209870394
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3308723554
Short name T350
Test name
Test status
Simulation time 3110509617 ps
CPU time 20.18 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:43 PM PDT 24
Peak memory 215868 kb
Host smart-d5daa376-26eb-4599-b8b3-bd51ad04819f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308723554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3308723554
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3424081929
Short name T380
Test name
Test status
Simulation time 8743617188 ps
CPU time 71.63 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:09:54 PM PDT 24
Peak memory 215868 kb
Host smart-f95b5363-7ac1-4d86-bc9d-07531da022a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424081929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3424081929
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.700855716
Short name T471
Test name
Test status
Simulation time 59387137366 ps
CPU time 2249.87 seconds
Started Mar 19 03:08:56 PM PDT 24
Finished Mar 19 03:46:27 PM PDT 24
Peak memory 235588 kb
Host smart-e337e548-90d4-4b3c-8fc7-ae850777c973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700855716 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.700855716
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.479668483
Short name T654
Test name
Test status
Simulation time 1756221681 ps
CPU time 14.42 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:48:57 PM PDT 24
Peak memory 210916 kb
Host smart-ca188d4f-e21f-419b-9031-614f06017a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479668483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.479668483
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.848299457
Short name T293
Test name
Test status
Simulation time 174865260 ps
CPU time 4.16 seconds
Started Mar 19 03:08:34 PM PDT 24
Finished Mar 19 03:08:39 PM PDT 24
Peak memory 210864 kb
Host smart-04a73160-60b3-48fa-a6ca-fa7e01929a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848299457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.848299457
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2294276252
Short name T272
Test name
Test status
Simulation time 48557962814 ps
CPU time 418.56 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:55:42 PM PDT 24
Peak memory 230488 kb
Host smart-618f5231-b39d-48dc-a07d-bcec203bed00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294276252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2294276252
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4240243811
Short name T207
Test name
Test status
Simulation time 180599215057 ps
CPU time 431.59 seconds
Started Mar 19 03:08:31 PM PDT 24
Finished Mar 19 03:15:43 PM PDT 24
Peak memory 234000 kb
Host smart-dcf9759e-3490-4b31-8fbc-7f521d85195e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240243811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4240243811
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1024066312
Short name T418
Test name
Test status
Simulation time 2648785320 ps
CPU time 24.06 seconds
Started Mar 19 03:08:32 PM PDT 24
Finished Mar 19 03:08:57 PM PDT 24
Peak memory 211796 kb
Host smart-585e6934-dbdd-4443-9587-9b3006137e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024066312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1024066312
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3137381812
Short name T176
Test name
Test status
Simulation time 16369897773 ps
CPU time 26.92 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:49:10 PM PDT 24
Peak memory 211968 kb
Host smart-2c17ba75-b5e2-4185-b00b-8fee02ce573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137381812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3137381812
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3083173917
Short name T588
Test name
Test status
Simulation time 99999770 ps
CPU time 5.38 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:39 PM PDT 24
Peak memory 210840 kb
Host smart-2e801ede-795e-4a03-8dc0-ea1cd8bd638d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083173917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3083173917
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4228275486
Short name T209
Test name
Test status
Simulation time 23792557866 ps
CPU time 18.55 seconds
Started Mar 19 02:48:49 PM PDT 24
Finished Mar 19 02:49:08 PM PDT 24
Peak memory 210920 kb
Host smart-98099ff3-72da-4548-94e1-272424d2aaa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228275486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4228275486
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1437952372
Short name T36
Test name
Test status
Simulation time 413585902 ps
CPU time 105.14 seconds
Started Mar 19 02:48:59 PM PDT 24
Finished Mar 19 02:50:44 PM PDT 24
Peak memory 230468 kb
Host smart-2510ba02-b1aa-4212-9033-fe5b5d3e06d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437952372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1437952372
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3427880514
Short name T31
Test name
Test status
Simulation time 943795765 ps
CPU time 100.19 seconds
Started Mar 19 03:08:36 PM PDT 24
Finished Mar 19 03:10:16 PM PDT 24
Peak memory 228408 kb
Host smart-cfd2cfd6-e93e-4023-9a81-80149347dac7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427880514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3427880514
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.245351042
Short name T419
Test name
Test status
Simulation time 755970907 ps
CPU time 14.67 seconds
Started Mar 19 03:08:34 PM PDT 24
Finished Mar 19 03:08:50 PM PDT 24
Peak memory 212440 kb
Host smart-ae2e7670-b2e2-407d-8fa6-97c89146cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245351042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.245351042
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3256928569
Short name T211
Test name
Test status
Simulation time 1741836981 ps
CPU time 21.43 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:49:04 PM PDT 24
Peak memory 212476 kb
Host smart-094cffb5-42bb-4863-8b17-b4efddae674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256928569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3256928569
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1008700426
Short name T114
Test name
Test status
Simulation time 38877193615 ps
CPU time 81.62 seconds
Started Mar 19 03:08:34 PM PDT 24
Finished Mar 19 03:09:57 PM PDT 24
Peak memory 219084 kb
Host smart-ccc2cd7c-c026-45e0-9c3d-83b4ac924478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008700426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1008700426
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2573875702
Short name T266
Test name
Test status
Simulation time 1227394136 ps
CPU time 18.88 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:49:14 PM PDT 24
Peak memory 215004 kb
Host smart-105735b6-d84e-45eb-8aa9-adb3f5b98f70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573875702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2573875702
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1285941290
Short name T642
Test name
Test status
Simulation time 1930331751 ps
CPU time 15.01 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:09:16 PM PDT 24
Peak memory 210892 kb
Host smart-141a9846-f2f3-4c55-ac17-847f64a4e655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285941290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1285941290
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3090196587
Short name T665
Test name
Test status
Simulation time 3241515356 ps
CPU time 9.1 seconds
Started Mar 19 02:49:14 PM PDT 24
Finished Mar 19 02:49:23 PM PDT 24
Peak memory 210980 kb
Host smart-0a060f16-e1d5-4ec2-94cd-5f2425f3510e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090196587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3090196587
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3592480931
Short name T362
Test name
Test status
Simulation time 3911924536 ps
CPU time 62.4 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:10:18 PM PDT 24
Peak memory 212192 kb
Host smart-077591a3-74b9-402d-8f2e-2c393b6271c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592480931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3592480931
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.540869985
Short name T619
Test name
Test status
Simulation time 18846344475 ps
CPU time 248.81 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:53:21 PM PDT 24
Peak memory 220236 kb
Host smart-8791ed5a-4f40-48ef-832d-467677cff824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540869985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.540869985
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1214183469
Short name T256
Test name
Test status
Simulation time 347357580 ps
CPU time 9.71 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:09:25 PM PDT 24
Peak memory 211484 kb
Host smart-cfa7765d-37a6-4367-8ae6-685dd42b73c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214183469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1214183469
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2331403918
Short name T455
Test name
Test status
Simulation time 3362129197 ps
CPU time 27.31 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:46 PM PDT 24
Peak memory 212196 kb
Host smart-77bc22b3-c03c-43d7-98ab-20b1089c3c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331403918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2331403918
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.110454218
Short name T579
Test name
Test status
Simulation time 1151537985 ps
CPU time 7.79 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:08:50 PM PDT 24
Peak memory 210804 kb
Host smart-ded04d2f-a312-4367-85c8-bf97962c4f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110454218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.110454218
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.28363682
Short name T364
Test name
Test status
Simulation time 1249420523 ps
CPU time 12.75 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 210776 kb
Host smart-ba7ee50b-9a39-4cff-a99d-23771d8efa87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28363682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.28363682
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1650802608
Short name T1
Test name
Test status
Simulation time 14088667436 ps
CPU time 30.86 seconds
Started Mar 19 03:08:50 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 219064 kb
Host smart-88a09717-c736-46e7-9878-4fd834383872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650802608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1650802608
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.203586362
Short name T263
Test name
Test status
Simulation time 13703559367 ps
CPU time 33.84 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:46 PM PDT 24
Peak memory 219068 kb
Host smart-25798b6b-a07d-4dd8-9e64-a7c062fd2c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203586362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.203586362
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1835233630
Short name T348
Test name
Test status
Simulation time 23689965171 ps
CPU time 51.36 seconds
Started Mar 19 03:09:05 PM PDT 24
Finished Mar 19 03:09:56 PM PDT 24
Peak memory 219040 kb
Host smart-7097db19-4f86-41ab-9ae4-c3a64ba67766
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835233630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1835233630
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2972035835
Short name T367
Test name
Test status
Simulation time 16535203125 ps
CPU time 16.16 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 210920 kb
Host smart-dcf6d99d-8296-480a-b7f6-5dd72b7fa35d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972035835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2972035835
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.189606
Short name T554
Test name
Test status
Simulation time 347976132 ps
CPU time 4.31 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:23 PM PDT 24
Peak memory 210868 kb
Host smart-ba5b209e-7b2c-4b23-9ecd-2abf8e37a788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.189606
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3581951443
Short name T410
Test name
Test status
Simulation time 88372724 ps
CPU time 4.31 seconds
Started Mar 19 03:09:14 PM PDT 24
Finished Mar 19 03:09:18 PM PDT 24
Peak memory 210876 kb
Host smart-72d66d8b-10dd-443b-96ee-efc0a70b4b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581951443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3581951443
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1607904343
Short name T569
Test name
Test status
Simulation time 142305632935 ps
CPU time 246.59 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:53:18 PM PDT 24
Peak memory 236916 kb
Host smart-f30621ec-0565-4edb-944a-5690e44a604c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607904343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1607904343
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.360428494
Short name T269
Test name
Test status
Simulation time 86704135057 ps
CPU time 295.69 seconds
Started Mar 19 03:08:56 PM PDT 24
Finished Mar 19 03:13:52 PM PDT 24
Peak memory 230452 kb
Host smart-7125e57b-1311-48e5-a49a-1505f4edf099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360428494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.360428494
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2736239629
Short name T318
Test name
Test status
Simulation time 2289380552 ps
CPU time 21.64 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:34 PM PDT 24
Peak memory 212172 kb
Host smart-c18470b4-0c25-4757-a4c4-274aa55f4f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736239629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2736239629
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3652125482
Short name T509
Test name
Test status
Simulation time 168963173 ps
CPU time 9.27 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 211732 kb
Host smart-f006ccae-c53f-435d-bb11-4af6d317a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652125482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3652125482
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3667742052
Short name T543
Test name
Test status
Simulation time 1551512800 ps
CPU time 7.99 seconds
Started Mar 19 03:08:57 PM PDT 24
Finished Mar 19 03:09:05 PM PDT 24
Peak memory 210784 kb
Host smart-fc426955-1ad4-4b55-9c4e-75a86adee3f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667742052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3667742052
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4131476674
Short name T305
Test name
Test status
Simulation time 1646247777 ps
CPU time 15.14 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:27 PM PDT 24
Peak memory 210828 kb
Host smart-5b525e26-e931-4651-92f5-55a81612f1a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131476674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4131476674
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2173675788
Short name T558
Test name
Test status
Simulation time 3169774471 ps
CPU time 27.68 seconds
Started Mar 19 03:08:58 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 213148 kb
Host smart-b3023e29-af11-4145-8241-239ed2bf1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173675788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2173675788
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2339096171
Short name T205
Test name
Test status
Simulation time 47824282233 ps
CPU time 26.86 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:38 PM PDT 24
Peak memory 219084 kb
Host smart-f6ec809c-fcd5-4bb2-b316-b45252042f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339096171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2339096171
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1028949944
Short name T83
Test name
Test status
Simulation time 31886989971 ps
CPU time 81.18 seconds
Started Mar 19 03:08:49 PM PDT 24
Finished Mar 19 03:10:10 PM PDT 24
Peak memory 219084 kb
Host smart-ad3a7749-7158-4dfb-8e2e-24011641fbb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028949944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1028949944
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2439195285
Short name T636
Test name
Test status
Simulation time 2520094345 ps
CPU time 23.16 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:36 PM PDT 24
Peak memory 214988 kb
Host smart-c18197ed-6505-4bec-be5e-2fabe79cba55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439195285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2439195285
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2939090850
Short name T368
Test name
Test status
Simulation time 1957157780 ps
CPU time 10.28 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 210876 kb
Host smart-148cfb87-e89c-4792-87ec-a0224b9aaea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939090850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2939090850
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.800173041
Short name T247
Test name
Test status
Simulation time 1746430630 ps
CPU time 13.98 seconds
Started Mar 19 02:49:09 PM PDT 24
Finished Mar 19 02:49:24 PM PDT 24
Peak memory 210880 kb
Host smart-d1a3be16-ffb4-4b1a-afb9-2f298697de89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800173041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.800173041
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2841898799
Short name T200
Test name
Test status
Simulation time 4330951657 ps
CPU time 73 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 02:50:26 PM PDT 24
Peak memory 232456 kb
Host smart-1c5ccfa2-d77f-46dc-99e5-e10a42e7c603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841898799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2841898799
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4029794845
Short name T427
Test name
Test status
Simulation time 6187910096 ps
CPU time 168.8 seconds
Started Mar 19 03:08:52 PM PDT 24
Finished Mar 19 03:11:41 PM PDT 24
Peak memory 236756 kb
Host smart-8a30a88a-b9cc-4d77-8fae-a6fa36c80e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029794845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4029794845
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2630588291
Short name T477
Test name
Test status
Simulation time 168458674 ps
CPU time 9.19 seconds
Started Mar 19 02:49:16 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 211544 kb
Host smart-9c6fbb58-9e7c-4861-b957-52359912b19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630588291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2630588291
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4171894486
Short name T610
Test name
Test status
Simulation time 2960758580 ps
CPU time 26.59 seconds
Started Mar 19 03:09:03 PM PDT 24
Finished Mar 19 03:09:30 PM PDT 24
Peak memory 211556 kb
Host smart-5d6e519b-1eae-41a1-83be-a6d27900c92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171894486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4171894486
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2350757194
Short name T490
Test name
Test status
Simulation time 6604151528 ps
CPU time 15.94 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:27 PM PDT 24
Peak memory 210904 kb
Host smart-210fbfae-507e-4454-8de5-c075e490abca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350757194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2350757194
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3076823339
Short name T577
Test name
Test status
Simulation time 7166891328 ps
CPU time 10.49 seconds
Started Mar 19 03:08:58 PM PDT 24
Finished Mar 19 03:09:09 PM PDT 24
Peak memory 210896 kb
Host smart-64876b16-f7f0-40e1-a43e-64cbb76f732a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076823339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3076823339
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.208501713
Short name T549
Test name
Test status
Simulation time 10612394135 ps
CPU time 30.22 seconds
Started Mar 19 02:49:14 PM PDT 24
Finished Mar 19 02:49:44 PM PDT 24
Peak memory 219064 kb
Host smart-25464967-b0c4-41e8-837e-990ebad6ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208501713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.208501713
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3395944282
Short name T156
Test name
Test status
Simulation time 3404521472 ps
CPU time 29.94 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:38 PM PDT 24
Peak memory 219072 kb
Host smart-f7912dbb-7187-4de0-8c1f-eccb56a8e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395944282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3395944282
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1977229155
Short name T424
Test name
Test status
Simulation time 20718862853 ps
CPU time 21.62 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 02:49:35 PM PDT 24
Peak memory 219084 kb
Host smart-141120a6-926f-48af-9846-7de9ad945622
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977229155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1977229155
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3412283736
Short name T277
Test name
Test status
Simulation time 6166527218 ps
CPU time 15.36 seconds
Started Mar 19 03:08:57 PM PDT 24
Finished Mar 19 03:09:13 PM PDT 24
Peak memory 211956 kb
Host smart-fbfaa036-ecaf-430d-bcb7-d655c9aa865c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412283736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3412283736
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2444103455
Short name T52
Test name
Test status
Simulation time 100121982278 ps
CPU time 9905.66 seconds
Started Mar 19 02:49:13 PM PDT 24
Finished Mar 19 05:34:20 PM PDT 24
Peak memory 229644 kb
Host smart-23876010-da60-4176-ae93-f75208e70fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444103455 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2444103455
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2323712252
Short name T496
Test name
Test status
Simulation time 6082975955 ps
CPU time 9.28 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 210948 kb
Host smart-450da4bc-050c-4775-9ae3-78b848bd7d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323712252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2323712252
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4265720563
Short name T340
Test name
Test status
Simulation time 36219315087 ps
CPU time 15.31 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:09:17 PM PDT 24
Peak memory 210960 kb
Host smart-eec3bd32-9743-4915-ae4f-0af84ff7f77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265720563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4265720563
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2904684996
Short name T271
Test name
Test status
Simulation time 1557338273 ps
CPU time 101.68 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:51:02 PM PDT 24
Peak memory 229348 kb
Host smart-5529974f-74fb-49c3-903f-572ecb08329e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904684996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2904684996
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3451137576
Short name T150
Test name
Test status
Simulation time 133987315350 ps
CPU time 203.65 seconds
Started Mar 19 03:08:57 PM PDT 24
Finished Mar 19 03:12:21 PM PDT 24
Peak memory 225896 kb
Host smart-48cbf69a-4a9c-4a76-b7ae-842055b0e2a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451137576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3451137576
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2549599428
Short name T268
Test name
Test status
Simulation time 17166978078 ps
CPU time 35.38 seconds
Started Mar 19 02:49:16 PM PDT 24
Finished Mar 19 02:49:51 PM PDT 24
Peak memory 211744 kb
Host smart-fec03221-eb08-49d7-8da0-bb1759e519ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549599428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2549599428
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3577470746
Short name T567
Test name
Test status
Simulation time 3502547935 ps
CPU time 30.58 seconds
Started Mar 19 03:09:18 PM PDT 24
Finished Mar 19 03:09:49 PM PDT 24
Peak memory 211580 kb
Host smart-3554a2dd-41fd-4969-924b-e33b7dfe67e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577470746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3577470746
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2503598538
Short name T602
Test name
Test status
Simulation time 3300351403 ps
CPU time 14.93 seconds
Started Mar 19 03:08:56 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 210904 kb
Host smart-e8abb472-612f-4898-b23c-4d4c8f75033b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503598538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2503598538
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3516876760
Short name T679
Test name
Test status
Simulation time 371762810 ps
CPU time 5.17 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 210840 kb
Host smart-f13f23dd-e7e0-4cdc-9b62-2c36e0d43257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516876760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3516876760
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1807937597
Short name T274
Test name
Test status
Simulation time 1742017869 ps
CPU time 15.23 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:09:09 PM PDT 24
Peak memory 219012 kb
Host smart-345252f1-3d5f-4332-84c7-070fd667d891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807937597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1807937597
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.996266942
Short name T667
Test name
Test status
Simulation time 177106775 ps
CPU time 9.96 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:49:32 PM PDT 24
Peak memory 212440 kb
Host smart-e44c083f-2832-4649-a649-2b77124834f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996266942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.996266942
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2084285746
Short name T545
Test name
Test status
Simulation time 2128511183 ps
CPU time 22.49 seconds
Started Mar 19 02:49:12 PM PDT 24
Finished Mar 19 02:49:34 PM PDT 24
Peak memory 219024 kb
Host smart-b21eb460-8346-46ef-8edc-f1aa63ef76eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084285746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2084285746
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.98610210
Short name T140
Test name
Test status
Simulation time 2168522117 ps
CPU time 23.33 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:29 PM PDT 24
Peak memory 210804 kb
Host smart-caf287e9-6bbd-4477-be78-8701dfb2b566
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98610210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.rom_ctrl_stress_all.98610210
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1142648402
Short name T648
Test name
Test status
Simulation time 5640557111 ps
CPU time 12.77 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:33 PM PDT 24
Peak memory 210924 kb
Host smart-b88cbd29-cb6c-45b0-8aa3-0086c89b554a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142648402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1142648402
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.515852176
Short name T223
Test name
Test status
Simulation time 171994764 ps
CPU time 4.3 seconds
Started Mar 19 03:08:46 PM PDT 24
Finished Mar 19 03:08:51 PM PDT 24
Peak memory 210908 kb
Host smart-a418e96c-a559-49b0-b56f-c59d39af8e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515852176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.515852176
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1923234122
Short name T195
Test name
Test status
Simulation time 37389147019 ps
CPU time 184.62 seconds
Started Mar 19 03:08:50 PM PDT 24
Finished Mar 19 03:11:54 PM PDT 24
Peak memory 241116 kb
Host smart-79b9785b-3f9c-402e-864b-dd7cc30d86f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923234122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1923234122
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2651772856
Short name T210
Test name
Test status
Simulation time 4284889814 ps
CPU time 78 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:50:40 PM PDT 24
Peak memory 228176 kb
Host smart-7861e4e0-e3da-4bd1-9b6a-1e429efff3c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651772856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2651772856
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.541897107
Short name T174
Test name
Test status
Simulation time 16396667030 ps
CPU time 21.25 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:49:43 PM PDT 24
Peak memory 211948 kb
Host smart-a65cd873-787c-4f9e-8d6a-98940f39ba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541897107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.541897107
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.733290
Short name T214
Test name
Test status
Simulation time 1801036771 ps
CPU time 20.53 seconds
Started Mar 19 03:08:56 PM PDT 24
Finished Mar 19 03:09:17 PM PDT 24
Peak memory 211428 kb
Host smart-9b5b1e8e-2c5e-435f-b482-046fdb1d6ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.733290
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3776375295
Short name T644
Test name
Test status
Simulation time 5944714182 ps
CPU time 13.1 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:33 PM PDT 24
Peak memory 210908 kb
Host smart-7fc4ab73-ad46-4910-9146-66240e89c44c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776375295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3776375295
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.444767935
Short name T346
Test name
Test status
Simulation time 4332966103 ps
CPU time 10.99 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 210912 kb
Host smart-0a3e31c7-bdb7-4bf7-8d5d-3606dd9774bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444767935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.444767935
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.222063074
Short name T320
Test name
Test status
Simulation time 1050044080 ps
CPU time 9.98 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:08:52 PM PDT 24
Peak memory 212568 kb
Host smart-c8bb19f7-8a73-40d0-b6ef-25d2ddd23de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222063074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.222063074
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3793948139
Short name T301
Test name
Test status
Simulation time 15167455665 ps
CPU time 37.46 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:58 PM PDT 24
Peak memory 219080 kb
Host smart-3d9093d7-ba09-4eff-bb47-f0c806a57a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793948139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3793948139
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.197522499
Short name T497
Test name
Test status
Simulation time 14622289913 ps
CPU time 40.42 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:48 PM PDT 24
Peak memory 219072 kb
Host smart-9d4a2932-0c0e-46fc-aace-8b082dc6c075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197522499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.197522499
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.954006877
Short name T516
Test name
Test status
Simulation time 10838021646 ps
CPU time 88.73 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:10:23 PM PDT 24
Peak memory 219068 kb
Host smart-0680b507-3121-4e53-854a-9b5aa613e556
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954006877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.954006877
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3677454253
Short name T495
Test name
Test status
Simulation time 120914900779 ps
CPU time 4507.91 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 04:04:31 PM PDT 24
Peak memory 251980 kb
Host smart-0b0c3123-4224-4b7d-a725-b65df7002975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677454253 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3677454253
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1005948521
Short name T183
Test name
Test status
Simulation time 2462559832 ps
CPU time 8.24 seconds
Started Mar 19 02:49:17 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 210936 kb
Host smart-5b26a10f-401b-40c2-b43a-6728632e29ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005948521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1005948521
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1738988009
Short name T589
Test name
Test status
Simulation time 4287284536 ps
CPU time 14.54 seconds
Started Mar 19 03:08:46 PM PDT 24
Finished Mar 19 03:09:01 PM PDT 24
Peak memory 211032 kb
Host smart-1bb688c4-d0d0-43f5-8cb4-6422dc6b8ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738988009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1738988009
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1858106729
Short name T27
Test name
Test status
Simulation time 60712134354 ps
CPU time 244.03 seconds
Started Mar 19 03:08:46 PM PDT 24
Finished Mar 19 03:12:51 PM PDT 24
Peak memory 224784 kb
Host smart-3e811ada-ad66-48ba-ad01-36a0307483f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858106729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1858106729
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3201681799
Short name T328
Test name
Test status
Simulation time 40129929565 ps
CPU time 249.1 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:53:32 PM PDT 24
Peak memory 238568 kb
Host smart-86fc3939-cb7c-421c-95b3-ce8c1a49bb39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201681799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3201681799
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1047144414
Short name T423
Test name
Test status
Simulation time 3417369673 ps
CPU time 30.32 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:42 PM PDT 24
Peak memory 211472 kb
Host smart-e4f83d16-78f5-4887-b044-0b7c5368032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047144414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1047144414
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.691732877
Short name T468
Test name
Test status
Simulation time 10991427807 ps
CPU time 22.67 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:29 PM PDT 24
Peak memory 211928 kb
Host smart-0630afcb-e525-47ff-b5cc-dd8599d13a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691732877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.691732877
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3457961673
Short name T660
Test name
Test status
Simulation time 2219905862 ps
CPU time 14.19 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 210920 kb
Host smart-67e4136a-09a8-45b5-a5d2-a0ddba8c3dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457961673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3457961673
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3998486438
Short name T188
Test name
Test status
Simulation time 7436646286 ps
CPU time 15.91 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:09:04 PM PDT 24
Peak memory 210920 kb
Host smart-2ecad561-e586-40ce-b9f9-c96a2bd83900
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998486438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3998486438
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1838829675
Short name T143
Test name
Test status
Simulation time 29569321566 ps
CPU time 28.22 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:09:12 PM PDT 24
Peak memory 215352 kb
Host smart-db1649a2-2db1-44ee-a731-34f7df95e756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838829675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1838829675
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4281850047
Short name T253
Test name
Test status
Simulation time 2655698812 ps
CPU time 24.64 seconds
Started Mar 19 02:49:10 PM PDT 24
Finished Mar 19 02:49:35 PM PDT 24
Peak memory 213092 kb
Host smart-a4aca2e9-2d09-4603-b197-039bf08f684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281850047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4281850047
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4069810739
Short name T677
Test name
Test status
Simulation time 597933929 ps
CPU time 16.52 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:08:58 PM PDT 24
Peak memory 219004 kb
Host smart-73107d29-8c95-4e12-a2ee-f12d0b2bb302
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069810739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4069810739
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.652364277
Short name T85
Test name
Test status
Simulation time 1204069384 ps
CPU time 15.51 seconds
Started Mar 19 02:49:08 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 211352 kb
Host smart-51881631-cba1-469c-8eb1-7087894b849c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652364277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.652364277
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1622550333
Short name T283
Test name
Test status
Simulation time 3772477424 ps
CPU time 15.14 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:09:16 PM PDT 24
Peak memory 210956 kb
Host smart-93eb7df0-f86e-4802-b406-3dbdf2aa3cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622550333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1622550333
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3691829752
Short name T152
Test name
Test status
Simulation time 6741168538 ps
CPU time 14.06 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:33 PM PDT 24
Peak memory 210968 kb
Host smart-e7fd3f5d-a296-496d-88ee-af58e2520b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691829752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3691829752
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3531564651
Short name T678
Test name
Test status
Simulation time 98243778984 ps
CPU time 210.78 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:12:13 PM PDT 24
Peak memory 237632 kb
Host smart-d505a174-e546-46f8-ae84-a90926325e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531564651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3531564651
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.973354074
Short name T614
Test name
Test status
Simulation time 36534465424 ps
CPU time 118 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:51:22 PM PDT 24
Peak memory 228452 kb
Host smart-587df7d4-66cb-442d-a1e5-d86e454322a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973354074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.973354074
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2071101109
Short name T576
Test name
Test status
Simulation time 10818583891 ps
CPU time 26.14 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:09:41 PM PDT 24
Peak memory 210972 kb
Host smart-e95316e5-0f74-437e-ad2a-0e4d0a0d0d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071101109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2071101109
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4167046417
Short name T3
Test name
Test status
Simulation time 4882800519 ps
CPU time 18.13 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:49:45 PM PDT 24
Peak memory 211416 kb
Host smart-a182694e-321b-4e66-bfab-1e4ff1f58bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167046417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4167046417
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1169060143
Short name T605
Test name
Test status
Simulation time 1261985394 ps
CPU time 12.98 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:08:58 PM PDT 24
Peak memory 210912 kb
Host smart-46bd70ef-8d5f-489b-8fe5-375689008f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169060143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1169060143
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.983173415
Short name T546
Test name
Test status
Simulation time 1091422668 ps
CPU time 11.55 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:49:35 PM PDT 24
Peak memory 210840 kb
Host smart-893441e2-dd83-4a87-8a31-ce8ba1227f87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983173415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.983173415
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.798289947
Short name T521
Test name
Test status
Simulation time 8520464177 ps
CPU time 34.54 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:09:18 PM PDT 24
Peak memory 213644 kb
Host smart-be6d6c44-9043-41ec-82e4-2404e4416447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798289947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.798289947
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.879975443
Short name T40
Test name
Test status
Simulation time 3382734869 ps
CPU time 12.76 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:49:34 PM PDT 24
Peak memory 213436 kb
Host smart-e896f7dd-0124-47b0-907f-09aae8203b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879975443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.879975443
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4212973522
Short name T457
Test name
Test status
Simulation time 6223475538 ps
CPU time 54.8 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:09:40 PM PDT 24
Peak memory 215640 kb
Host smart-f6b87c20-f2ba-4999-84c3-3edce401d460
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212973522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4212973522
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.767627012
Short name T484
Test name
Test status
Simulation time 7846366251 ps
CPU time 71.79 seconds
Started Mar 19 02:49:11 PM PDT 24
Finished Mar 19 02:50:23 PM PDT 24
Peak memory 216676 kb
Host smart-391fa016-7b06-4f95-8137-24fdabcddd70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767627012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.767627012
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1067248674
Short name T626
Test name
Test status
Simulation time 89073805 ps
CPU time 4.24 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 210884 kb
Host smart-d5ebc1df-1a17-44a8-965d-b7dfd8a94d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067248674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1067248674
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3039863242
Short name T635
Test name
Test status
Simulation time 1140566363 ps
CPU time 10.72 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:34 PM PDT 24
Peak memory 210912 kb
Host smart-883b6051-9fb0-4fa6-931f-815b5f69f2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039863242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3039863242
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2464075771
Short name T45
Test name
Test status
Simulation time 11022766213 ps
CPU time 145.46 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:51:48 PM PDT 24
Peak memory 227836 kb
Host smart-b5755069-022c-4690-9751-111add016c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464075771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2464075771
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.530392788
Short name T49
Test name
Test status
Simulation time 22234992255 ps
CPU time 138.72 seconds
Started Mar 19 03:09:22 PM PDT 24
Finished Mar 19 03:11:41 PM PDT 24
Peak memory 212104 kb
Host smart-a116e6d4-b6ee-42da-ac78-4767fc8fc15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530392788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.530392788
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2836054452
Short name T238
Test name
Test status
Simulation time 2565248110 ps
CPU time 24.32 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:49:47 PM PDT 24
Peak memory 211308 kb
Host smart-2d2cb529-e3dc-481a-b740-347e6c7cd231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836054452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2836054452
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.343863653
Short name T370
Test name
Test status
Simulation time 6156031412 ps
CPU time 18.83 seconds
Started Mar 19 03:09:04 PM PDT 24
Finished Mar 19 03:09:23 PM PDT 24
Peak memory 212240 kb
Host smart-7d082ef8-7c85-4773-8e5e-80d0932fc0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343863653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.343863653
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2269232906
Short name T239
Test name
Test status
Simulation time 6025226550 ps
CPU time 13.91 seconds
Started Mar 19 03:09:04 PM PDT 24
Finished Mar 19 03:09:18 PM PDT 24
Peak memory 210868 kb
Host smart-5230ed11-3bdd-4d50-85ca-38d3706e2021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269232906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2269232906
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3942764139
Short name T443
Test name
Test status
Simulation time 2686375624 ps
CPU time 9.68 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 210904 kb
Host smart-ab720577-b2e7-4a16-8788-d78562fb211f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942764139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3942764139
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2275713238
Short name T245
Test name
Test status
Simulation time 3946747602 ps
CPU time 32.93 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:42 PM PDT 24
Peak memory 219088 kb
Host smart-09ccf8f0-6d32-4eb4-90f0-8ce265e1bcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275713238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2275713238
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2918608990
Short name T585
Test name
Test status
Simulation time 17590243767 ps
CPU time 26.07 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:49:49 PM PDT 24
Peak memory 219084 kb
Host smart-f3035d38-228e-47cf-8c79-74126a2c2e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918608990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2918608990
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.23877178
Short name T99
Test name
Test status
Simulation time 15563964351 ps
CPU time 81.3 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:10:32 PM PDT 24
Peak memory 219092 kb
Host smart-322f5af8-aa9e-4887-bfb7-e532b99e548b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23877178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.rom_ctrl_stress_all.23877178
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3268363194
Short name T373
Test name
Test status
Simulation time 4539861047 ps
CPU time 34.75 seconds
Started Mar 19 02:49:15 PM PDT 24
Finished Mar 19 02:49:50 PM PDT 24
Peak memory 219104 kb
Host smart-ed33967a-1b71-4840-bafd-06a52606d9d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268363194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3268363194
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2464526412
Short name T607
Test name
Test status
Simulation time 725715258219 ps
CPU time 6126.63 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 04:51:15 PM PDT 24
Peak memory 256080 kb
Host smart-bb556795-7ff5-4342-893d-cc429ad65787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464526412 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2464526412
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.570117763
Short name T15
Test name
Test status
Simulation time 77048663257 ps
CPU time 900.94 seconds
Started Mar 19 02:49:17 PM PDT 24
Finished Mar 19 03:04:18 PM PDT 24
Peak memory 227420 kb
Host smart-5c4a4b63-713d-49ba-8d73-b31d85cfab11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570117763 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.570117763
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1664258803
Short name T147
Test name
Test status
Simulation time 88083647 ps
CPU time 4.29 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:27 PM PDT 24
Peak memory 210876 kb
Host smart-b777c1c5-36ab-4561-ba64-7e2a2d2168ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664258803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1664258803
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1961979349
Short name T491
Test name
Test status
Simulation time 10043755837 ps
CPU time 14.19 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 210900 kb
Host smart-0bc2996c-cc1d-4d70-a2c9-e6b09c32fcb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961979349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1961979349
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1347979599
Short name T345
Test name
Test status
Simulation time 169389845431 ps
CPU time 440.56 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 233680 kb
Host smart-a318598a-377e-4bf6-8f55-fb21c47c37fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347979599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1347979599
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3501857157
Short name T310
Test name
Test status
Simulation time 17773152929 ps
CPU time 156.95 seconds
Started Mar 19 03:08:58 PM PDT 24
Finished Mar 19 03:11:35 PM PDT 24
Peak memory 219360 kb
Host smart-12a85abb-10b8-4ae2-952c-1ee574b65ccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501857157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3501857157
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1886319364
Short name T324
Test name
Test status
Simulation time 8478323684 ps
CPU time 24.35 seconds
Started Mar 19 03:09:07 PM PDT 24
Finished Mar 19 03:09:32 PM PDT 24
Peak memory 210972 kb
Host smart-951dc5d7-ae90-4309-bfcb-47f0e19f3afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886319364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1886319364
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2228358725
Short name T41
Test name
Test status
Simulation time 6590064300 ps
CPU time 30.18 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:49:52 PM PDT 24
Peak memory 211764 kb
Host smart-630b3680-d669-42e4-b294-acad4d6fb6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228358725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2228358725
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1723137506
Short name T297
Test name
Test status
Simulation time 1146894326 ps
CPU time 5.64 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 210848 kb
Host smart-7bace9ed-74f1-40b6-b45d-21cd8c578978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723137506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1723137506
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2137825822
Short name T669
Test name
Test status
Simulation time 8095952776 ps
CPU time 16.85 seconds
Started Mar 19 03:09:04 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 210892 kb
Host smart-0e202118-4c8f-429e-864f-55eb817bfcd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137825822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2137825822
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2682163866
Short name T399
Test name
Test status
Simulation time 13604877611 ps
CPU time 21.68 seconds
Started Mar 19 02:49:24 PM PDT 24
Finished Mar 19 02:49:45 PM PDT 24
Peak memory 219068 kb
Host smart-342fe019-32cc-4777-ba5e-f0f938e9446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682163866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2682163866
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3553524944
Short name T641
Test name
Test status
Simulation time 1663716417 ps
CPU time 20.1 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:09:30 PM PDT 24
Peak memory 212664 kb
Host smart-b4c78617-8d02-48f9-a402-6e6b59266771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553524944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3553524944
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2959503033
Short name T664
Test name
Test status
Simulation time 14875234503 ps
CPU time 41.1 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:50:04 PM PDT 24
Peak memory 219064 kb
Host smart-4009884e-9c69-48a4-bd97-5462fdef30f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959503033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2959503033
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.410785796
Short name T611
Test name
Test status
Simulation time 10748964979 ps
CPU time 64.83 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:10:11 PM PDT 24
Peak memory 219096 kb
Host smart-f9ddb7fa-15bd-4442-81f1-25e7c323a34f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410785796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.410785796
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3162939098
Short name T54
Test name
Test status
Simulation time 49234827077 ps
CPU time 6007.13 seconds
Started Mar 19 03:09:12 PM PDT 24
Finished Mar 19 04:49:21 PM PDT 24
Peak memory 235600 kb
Host smart-507354d6-ac2d-4cc5-b4fe-a5262bbe6a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162939098 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3162939098
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1665182184
Short name T172
Test name
Test status
Simulation time 19185297522 ps
CPU time 14.18 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:34 PM PDT 24
Peak memory 210960 kb
Host smart-f2e7f49e-d63c-4ff2-bf96-a08b22074acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665182184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1665182184
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.607559523
Short name T651
Test name
Test status
Simulation time 2167992319 ps
CPU time 11.06 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:09:24 PM PDT 24
Peak memory 210952 kb
Host smart-23c725ad-a7fe-4d9f-8525-b6b613f1074f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607559523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.607559523
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1515016295
Short name T544
Test name
Test status
Simulation time 24549400771 ps
CPU time 291.21 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:13:53 PM PDT 24
Peak memory 228128 kb
Host smart-d3dd3eff-0696-4006-b0bd-c0f82414ff98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515016295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1515016295
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2560887593
Short name T511
Test name
Test status
Simulation time 36111694054 ps
CPU time 205.55 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:52:54 PM PDT 24
Peak memory 219356 kb
Host smart-0e8b0eab-5fca-4913-b8d7-a1cf633eb2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560887593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2560887593
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.179791625
Short name T597
Test name
Test status
Simulation time 5129054971 ps
CPU time 17.9 seconds
Started Mar 19 03:09:19 PM PDT 24
Finished Mar 19 03:09:38 PM PDT 24
Peak memory 211796 kb
Host smart-d97e1099-84b0-48d5-a373-fa9d9ee0bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179791625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.179791625
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2150762893
Short name T47
Test name
Test status
Simulation time 615926864 ps
CPU time 9.24 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:49:32 PM PDT 24
Peak memory 211572 kb
Host smart-4847b9d8-55fb-44a7-8f31-5efb8de4f8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150762893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2150762893
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4252678314
Short name T330
Test name
Test status
Simulation time 5341428150 ps
CPU time 12.84 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:09:07 PM PDT 24
Peak memory 210932 kb
Host smart-b2432a61-3344-4238-bcf9-b04013e9c315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252678314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4252678314
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.487984694
Short name T148
Test name
Test status
Simulation time 11749457089 ps
CPU time 9.56 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:49:32 PM PDT 24
Peak memory 210932 kb
Host smart-fe77e0da-39d9-478a-924a-e7e5b4786182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487984694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.487984694
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1486368193
Short name T280
Test name
Test status
Simulation time 3907003280 ps
CPU time 37.86 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:47 PM PDT 24
Peak memory 213416 kb
Host smart-f1aa833d-0bb2-4ca3-bdaa-1a9723afe6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486368193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1486368193
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2115269838
Short name T234
Test name
Test status
Simulation time 15449885173 ps
CPU time 33.25 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:49:56 PM PDT 24
Peak memory 213488 kb
Host smart-764d0fef-03d7-47d6-9285-06e77cf1e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115269838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2115269838
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2826408562
Short name T670
Test name
Test status
Simulation time 3873694299 ps
CPU time 19.46 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 219064 kb
Host smart-b83005e5-4143-4405-afd9-ed00374f1e9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826408562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2826408562
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2845677303
Short name T414
Test name
Test status
Simulation time 33133499165 ps
CPU time 80.64 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:50:44 PM PDT 24
Peak memory 216756 kb
Host smart-44713bed-21bb-4287-915c-4d829883b7b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845677303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2845677303
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2103034697
Short name T341
Test name
Test status
Simulation time 168644798 ps
CPU time 5.44 seconds
Started Mar 19 02:48:42 PM PDT 24
Finished Mar 19 02:48:48 PM PDT 24
Peak memory 210892 kb
Host smart-2a523810-66b5-4b55-8fea-ed8945b2dd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103034697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2103034697
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4136673142
Short name T184
Test name
Test status
Simulation time 2303005658 ps
CPU time 14.07 seconds
Started Mar 19 03:08:40 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 210976 kb
Host smart-ae787374-bac8-4534-bc02-57802a95cefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136673142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4136673142
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2868411596
Short name T204
Test name
Test status
Simulation time 64813113404 ps
CPU time 205.47 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:12:04 PM PDT 24
Peak memory 228332 kb
Host smart-137c4068-253e-4feb-8639-d9c5898f4e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868411596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2868411596
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3590881113
Short name T594
Test name
Test status
Simulation time 28794695403 ps
CPU time 162.02 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:51:25 PM PDT 24
Peak memory 228524 kb
Host smart-9705b3f2-e161-44f7-801e-5e2bb39de7f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590881113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3590881113
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.154744144
Short name T401
Test name
Test status
Simulation time 694013921 ps
CPU time 9.23 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:49:04 PM PDT 24
Peak memory 212012 kb
Host smart-1f82f662-c785-4b68-92bd-c052bb4e234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154744144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.154744144
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2196578686
Short name T453
Test name
Test status
Simulation time 8046125961 ps
CPU time 33.25 seconds
Started Mar 19 03:08:34 PM PDT 24
Finished Mar 19 03:09:08 PM PDT 24
Peak memory 212120 kb
Host smart-aaa9b7f9-1078-4d7e-99ce-2a7b9ff45e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196578686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2196578686
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.202898085
Short name T192
Test name
Test status
Simulation time 1783632458 ps
CPU time 15.69 seconds
Started Mar 19 03:08:34 PM PDT 24
Finished Mar 19 03:08:51 PM PDT 24
Peak memory 210808 kb
Host smart-65c22cb8-8922-48cf-88bc-946498cce4eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202898085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.202898085
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3428275405
Short name T216
Test name
Test status
Simulation time 101235337 ps
CPU time 5.59 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:48:48 PM PDT 24
Peak memory 210844 kb
Host smart-e4a38424-36ec-4902-8c7f-64534e3defb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428275405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3428275405
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3696918093
Short name T34
Test name
Test status
Simulation time 609705458 ps
CPU time 53.44 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:50 PM PDT 24
Peak memory 229572 kb
Host smart-b51d4727-9df3-4e1c-b449-6cdc49e084a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696918093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3696918093
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3989117684
Short name T30
Test name
Test status
Simulation time 4019073269 ps
CPU time 62.55 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:09:40 PM PDT 24
Peak memory 236244 kb
Host smart-f897c02b-8941-40d2-99fd-85dc7f12150a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989117684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3989117684
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.215376685
Short name T566
Test name
Test status
Simulation time 1984053834 ps
CPU time 21.81 seconds
Started Mar 19 02:48:56 PM PDT 24
Finished Mar 19 02:49:17 PM PDT 24
Peak memory 213056 kb
Host smart-bb7052db-2ef7-400b-9b40-f6b11e8d8b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215376685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.215376685
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.542237741
Short name T596
Test name
Test status
Simulation time 2833135421 ps
CPU time 18.36 seconds
Started Mar 19 03:08:31 PM PDT 24
Finished Mar 19 03:08:50 PM PDT 24
Peak memory 213204 kb
Host smart-7d19d7b6-e7dd-40ba-9d43-89191527c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542237741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.542237741
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1119961321
Short name T392
Test name
Test status
Simulation time 304668165 ps
CPU time 17.01 seconds
Started Mar 19 03:08:36 PM PDT 24
Finished Mar 19 03:08:53 PM PDT 24
Peak memory 213056 kb
Host smart-3d917c6f-cf8f-4486-b53e-e6f7c491c4f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119961321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1119961321
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2663874284
Short name T232
Test name
Test status
Simulation time 30133624341 ps
CPU time 64.25 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:49:47 PM PDT 24
Peak memory 219072 kb
Host smart-28b65300-52be-4c43-b138-b92c5b25a2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663874284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2663874284
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1491935843
Short name T515
Test name
Test status
Simulation time 2245115523 ps
CPU time 10.74 seconds
Started Mar 19 02:49:16 PM PDT 24
Finished Mar 19 02:49:27 PM PDT 24
Peak memory 210948 kb
Host smart-db10c0a1-36d3-48cc-bb6f-03878e363df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491935843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1491935843
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.179371986
Short name T557
Test name
Test status
Simulation time 18698093502 ps
CPU time 10.4 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:19 PM PDT 24
Peak memory 210940 kb
Host smart-98fc3801-6a87-4a02-890f-d0621c0a6a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179371986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.179371986
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1382249717
Short name T145
Test name
Test status
Simulation time 8733761161 ps
CPU time 89.49 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:50:57 PM PDT 24
Peak memory 228376 kb
Host smart-5956ab1c-f895-4ea6-96d7-b99c3ae6ade4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382249717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1382249717
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1802136636
Short name T631
Test name
Test status
Simulation time 1683393884 ps
CPU time 19.88 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 211500 kb
Host smart-5817355c-c39a-474b-abe0-7bf650fc3e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802136636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1802136636
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.695358884
Short name T9
Test name
Test status
Simulation time 1529343263 ps
CPU time 19.13 seconds
Started Mar 19 02:49:24 PM PDT 24
Finished Mar 19 02:49:43 PM PDT 24
Peak memory 211508 kb
Host smart-00bd1fc3-a605-4452-a8c0-17edb954cb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695358884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.695358884
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3732979888
Short name T563
Test name
Test status
Simulation time 385551982 ps
CPU time 5.45 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 210852 kb
Host smart-b086f8d0-bb70-438c-b7b8-0ebb2b1f3590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732979888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3732979888
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.540109244
Short name T388
Test name
Test status
Simulation time 423576005 ps
CPU time 5.57 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:09:15 PM PDT 24
Peak memory 210856 kb
Host smart-ecb0c04a-7c4b-4378-984d-e8678fad4f14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540109244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.540109244
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1773026898
Short name T674
Test name
Test status
Simulation time 12295381017 ps
CPU time 29.14 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:38 PM PDT 24
Peak memory 213928 kb
Host smart-1021d71e-6f18-4948-8854-77ac5635fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773026898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1773026898
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3372936977
Short name T179
Test name
Test status
Simulation time 30261833166 ps
CPU time 43.64 seconds
Started Mar 19 02:49:24 PM PDT 24
Finished Mar 19 02:50:08 PM PDT 24
Peak memory 219076 kb
Host smart-07cefc66-03f9-44a6-a506-c139cc4d4d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372936977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3372936977
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1993313951
Short name T199
Test name
Test status
Simulation time 10455342798 ps
CPU time 50.79 seconds
Started Mar 19 03:08:54 PM PDT 24
Finished Mar 19 03:09:45 PM PDT 24
Peak memory 219096 kb
Host smart-c01975b6-afbf-44e2-99fb-8bdf7227d430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993313951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1993313951
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.539901569
Short name T411
Test name
Test status
Simulation time 5287885334 ps
CPU time 58.11 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:50:21 PM PDT 24
Peak memory 215684 kb
Host smart-1b011777-00a4-4ecd-99ac-aafc233c1b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539901569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.539901569
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.42936284
Short name T382
Test name
Test status
Simulation time 124112005625 ps
CPU time 4976.61 seconds
Started Mar 19 03:09:07 PM PDT 24
Finished Mar 19 04:32:04 PM PDT 24
Peak memory 251952 kb
Host smart-5438e7d4-d1d2-44f3-a0a5-9697c1cfe423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936284 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.42936284
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1237979447
Short name T139
Test name
Test status
Simulation time 991146064 ps
CPU time 10.4 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:34 PM PDT 24
Peak memory 210896 kb
Host smart-d6f0b220-7294-4fdb-8f52-a6f4ed86cbd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237979447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1237979447
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3610579174
Short name T487
Test name
Test status
Simulation time 334306503 ps
CPU time 4.25 seconds
Started Mar 19 03:08:55 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 210916 kb
Host smart-3dc733e1-42dc-4ff6-8a96-7d9e64f5a290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610579174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3610579174
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3171163193
Short name T408
Test name
Test status
Simulation time 39114755592 ps
CPU time 135.91 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:11:26 PM PDT 24
Peak memory 219404 kb
Host smart-c6a820fa-4ade-435f-b929-daed9fa56f96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171163193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3171163193
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4105257613
Short name T157
Test name
Test status
Simulation time 142989380705 ps
CPU time 357.57 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:55:18 PM PDT 24
Peak memory 232988 kb
Host smart-417c12c8-dc28-4585-8979-992b1a18d2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105257613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4105257613
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1630059024
Short name T369
Test name
Test status
Simulation time 16731016148 ps
CPU time 33.5 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:52 PM PDT 24
Peak memory 212004 kb
Host smart-a2a1f8e7-66d0-4758-814d-a1aa2d7a1b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630059024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1630059024
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2125154520
Short name T494
Test name
Test status
Simulation time 694795388 ps
CPU time 9.37 seconds
Started Mar 19 03:09:03 PM PDT 24
Finished Mar 19 03:09:12 PM PDT 24
Peak memory 211676 kb
Host smart-4c09be19-eec1-4e12-aa31-0dc546445201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125154520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2125154520
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3121294216
Short name T661
Test name
Test status
Simulation time 2168884237 ps
CPU time 15.57 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:49:38 PM PDT 24
Peak memory 210928 kb
Host smart-c2981c0f-f26b-4b2a-84c6-0264b4fcba25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3121294216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3121294216
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.396486221
Short name T608
Test name
Test status
Simulation time 2015444383 ps
CPU time 8.42 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:14 PM PDT 24
Peak memory 210856 kb
Host smart-2ace50bf-9c3b-4598-a636-a1486314c137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396486221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.396486221
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.244509791
Short name T559
Test name
Test status
Simulation time 11682630253 ps
CPU time 17.12 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:49:39 PM PDT 24
Peak memory 213904 kb
Host smart-63e4df20-6eec-4783-94a1-534c4b0d82be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244509791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.244509791
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4230658521
Short name T480
Test name
Test status
Simulation time 2252943206 ps
CPU time 15.15 seconds
Started Mar 19 03:09:16 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 213016 kb
Host smart-9a9d6737-0d66-442b-bcf0-0ef7fea76ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230658521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4230658521
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3214231107
Short name T360
Test name
Test status
Simulation time 336884356 ps
CPU time 16.28 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:09:25 PM PDT 24
Peak memory 219012 kb
Host smart-1cde54e1-7d96-4728-9d28-1ece767313a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214231107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3214231107
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4289889753
Short name T338
Test name
Test status
Simulation time 1245308644 ps
CPU time 31.25 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:51 PM PDT 24
Peak memory 214784 kb
Host smart-9bfd6126-d002-47f3-8b81-50108640da27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289889753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4289889753
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.715108226
Short name T180
Test name
Test status
Simulation time 5524723927 ps
CPU time 12.52 seconds
Started Mar 19 03:09:14 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 210940 kb
Host smart-db321118-b8bd-4c8e-a794-bef94a09dcf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715108226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.715108226
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.745816492
Short name T570
Test name
Test status
Simulation time 4185879889 ps
CPU time 15.57 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:49:44 PM PDT 24
Peak memory 210816 kb
Host smart-e7e6aaa7-d8b6-4ffe-987a-39d10771774b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745816492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.745816492
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1603909495
Short name T220
Test name
Test status
Simulation time 109031002797 ps
CPU time 252.67 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:53:36 PM PDT 24
Peak memory 232900 kb
Host smart-8ac8b0d7-a9b8-407e-8bd5-fe8f93a7c66e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603909495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1603909495
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2255163247
Short name T397
Test name
Test status
Simulation time 39645098165 ps
CPU time 401.34 seconds
Started Mar 19 03:08:59 PM PDT 24
Finished Mar 19 03:15:41 PM PDT 24
Peak memory 235152 kb
Host smart-32ba5136-3e92-49a7-8b42-31876e6f5018
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255163247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2255163247
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.41350819
Short name T257
Test name
Test status
Simulation time 1275666767 ps
CPU time 17.18 seconds
Started Mar 19 03:09:04 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 211528 kb
Host smart-7826f7bb-23c6-4264-9137-96f1adbe8a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41350819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.41350819
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.452434596
Short name T500
Test name
Test status
Simulation time 1680270175 ps
CPU time 8.05 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 210852 kb
Host smart-b0015fa2-a259-4e3c-8730-ac38084af80f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452434596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.452434596
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.551289126
Short name T178
Test name
Test status
Simulation time 191439970 ps
CPU time 5.23 seconds
Started Mar 19 03:09:22 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 210856 kb
Host smart-2457bc04-9816-4a96-929e-6807ee65420b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551289126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.551289126
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2554721547
Short name T173
Test name
Test status
Simulation time 1444830286 ps
CPU time 12.16 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:49:40 PM PDT 24
Peak memory 213448 kb
Host smart-ab04f50b-de7e-4a63-9c52-50c73cf7271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554721547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2554721547
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3947544704
Short name T189
Test name
Test status
Simulation time 1045488800 ps
CPU time 10.17 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 218996 kb
Host smart-ed2b60e6-493a-4f30-8c93-392c19199f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947544704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3947544704
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2207016165
Short name T105
Test name
Test status
Simulation time 26295375486 ps
CPU time 56.51 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:50:16 PM PDT 24
Peak memory 213888 kb
Host smart-376f28de-33dd-40c3-9cb7-a23e4cf2ad14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207016165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2207016165
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2444848196
Short name T102
Test name
Test status
Simulation time 8134015882 ps
CPU time 50.2 seconds
Started Mar 19 03:08:56 PM PDT 24
Finished Mar 19 03:09:46 PM PDT 24
Peak memory 219092 kb
Host smart-7c73f34c-1ee0-47d7-b6c0-51a03b1ef7af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444848196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2444848196
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2849638078
Short name T66
Test name
Test status
Simulation time 7505143216 ps
CPU time 15.01 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:49:37 PM PDT 24
Peak memory 210928 kb
Host smart-0fd7e22c-8041-4b62-adde-5c122a42851e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849638078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2849638078
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3236949714
Short name T655
Test name
Test status
Simulation time 823538143 ps
CPU time 9.68 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 210904 kb
Host smart-71547e0a-0fbb-4a18-8beb-ec2935fec5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236949714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3236949714
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2984056484
Short name T681
Test name
Test status
Simulation time 47591577500 ps
CPU time 408.32 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:15:42 PM PDT 24
Peak memory 228448 kb
Host smart-e5b8fca6-a5c4-4a65-9efd-fd640236f148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984056484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2984056484
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3066324552
Short name T46
Test name
Test status
Simulation time 2398005086 ps
CPU time 79.57 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:50:41 PM PDT 24
Peak memory 218288 kb
Host smart-fcf617a7-cc74-44b9-a1ba-6ce5704e4be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066324552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3066324552
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2323789917
Short name T475
Test name
Test status
Simulation time 12924538033 ps
CPU time 29.05 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:09:22 PM PDT 24
Peak memory 211676 kb
Host smart-3da1bee7-37c1-4c4c-8141-22e2929aa234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323789917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2323789917
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2460956526
Short name T652
Test name
Test status
Simulation time 175813113 ps
CPU time 9.59 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:28 PM PDT 24
Peak memory 211532 kb
Host smart-2a55227e-9496-4722-8181-3067bff858de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460956526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2460956526
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2220357554
Short name T319
Test name
Test status
Simulation time 2176173414 ps
CPU time 13.14 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:49:41 PM PDT 24
Peak memory 210772 kb
Host smart-83f2f424-2d9a-4882-a3a9-8af96eb3edab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220357554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2220357554
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.255793747
Short name T278
Test name
Test status
Simulation time 7538768579 ps
CPU time 16.64 seconds
Started Mar 19 03:08:55 PM PDT 24
Finished Mar 19 03:09:12 PM PDT 24
Peak memory 210932 kb
Host smart-419bb444-464a-4780-927c-1552c9aee70e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255793747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.255793747
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1796042471
Short name T198
Test name
Test status
Simulation time 5824900486 ps
CPU time 26.03 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:47 PM PDT 24
Peak memory 214140 kb
Host smart-84287962-0cee-4b31-a311-d3e57b9a1cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796042471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1796042471
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1974983089
Short name T236
Test name
Test status
Simulation time 8954239957 ps
CPU time 19.13 seconds
Started Mar 19 03:09:07 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 219068 kb
Host smart-b9634d9d-1dd9-4d70-b30e-f3f4bbda08ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974983089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1974983089
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2014951891
Short name T361
Test name
Test status
Simulation time 4639593354 ps
CPU time 69.78 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:50:29 PM PDT 24
Peak memory 218580 kb
Host smart-f0851d57-caff-4988-a220-2e3a0a864c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014951891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2014951891
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.210773266
Short name T160
Test name
Test status
Simulation time 98780832 ps
CPU time 9.92 seconds
Started Mar 19 03:09:08 PM PDT 24
Finished Mar 19 03:09:18 PM PDT 24
Peak memory 210752 kb
Host smart-fbb1a67e-d59b-4d8f-9fe4-72629e5c58ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210773266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.210773266
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3126576750
Short name T627
Test name
Test status
Simulation time 11579913758 ps
CPU time 979.46 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:25:29 PM PDT 24
Peak memory 220920 kb
Host smart-a6f6910c-7e18-4347-aadc-69de4d476531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126576750 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3126576750
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1395327966
Short name T478
Test name
Test status
Simulation time 1891794293 ps
CPU time 10 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 02:49:30 PM PDT 24
Peak memory 210880 kb
Host smart-7963a907-ce6d-47dc-944c-7656fc8cb575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395327966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1395327966
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.55165445
Short name T624
Test name
Test status
Simulation time 5863042135 ps
CPU time 13.22 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 210940 kb
Host smart-27545f72-1db6-4aea-969d-2409165492e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55165445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.55165445
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1072316341
Short name T583
Test name
Test status
Simulation time 61539908780 ps
CPU time 590.92 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:19:07 PM PDT 24
Peak memory 233440 kb
Host smart-039d1c8f-d17b-4fff-a710-aa523897a9e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072316341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1072316341
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3281707435
Short name T529
Test name
Test status
Simulation time 30326397340 ps
CPU time 306.62 seconds
Started Mar 19 02:49:21 PM PDT 24
Finished Mar 19 02:54:29 PM PDT 24
Peak memory 236584 kb
Host smart-40bdcf7d-f9b7-48d2-b709-8b0117a2fd1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281707435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3281707435
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2630558258
Short name T162
Test name
Test status
Simulation time 24346502375 ps
CPU time 20.4 seconds
Started Mar 19 02:49:18 PM PDT 24
Finished Mar 19 02:49:40 PM PDT 24
Peak memory 211748 kb
Host smart-f301f4c1-094f-4e85-9736-645a1b92f536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630558258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2630558258
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3360641787
Short name T593
Test name
Test status
Simulation time 3526864450 ps
CPU time 30.71 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:09:40 PM PDT 24
Peak memory 210988 kb
Host smart-d77e7280-1ecc-4b4f-88dc-b634be56917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360641787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3360641787
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2200979854
Short name T113
Test name
Test status
Simulation time 400157729 ps
CPU time 7.88 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:49:35 PM PDT 24
Peak memory 210844 kb
Host smart-9e66c388-798c-4ffe-a50b-a565580980e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200979854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2200979854
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2155381491
Short name T296
Test name
Test status
Simulation time 3387905856 ps
CPU time 30.19 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:49:58 PM PDT 24
Peak memory 212860 kb
Host smart-660cf01c-51c0-44ae-a1f8-cbcfd8724b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155381491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2155381491
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3818498526
Short name T402
Test name
Test status
Simulation time 11283201930 ps
CPU time 25.97 seconds
Started Mar 19 03:09:00 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 219048 kb
Host smart-ff349094-d5f2-43f1-baa3-cca0a8d3d6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818498526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3818498526
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2101008557
Short name T79
Test name
Test status
Simulation time 12684873798 ps
CPU time 54.74 seconds
Started Mar 19 03:09:07 PM PDT 24
Finished Mar 19 03:10:02 PM PDT 24
Peak memory 216612 kb
Host smart-ae7661f4-de75-4c81-8cd1-a08f10d69014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101008557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2101008557
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2557213712
Short name T372
Test name
Test status
Simulation time 20301741178 ps
CPU time 38.51 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:50:07 PM PDT 24
Peak memory 215744 kb
Host smart-93780ea1-f529-4ec1-84df-b48c9b3e906c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557213712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2557213712
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.761658367
Short name T512
Test name
Test status
Simulation time 435395786294 ps
CPU time 3885.15 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 03:54:13 PM PDT 24
Peak memory 251960 kb
Host smart-a51b56fa-4d4b-4d6f-aa23-bb9dc6523d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761658367 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.761658367
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.104472539
Short name T530
Test name
Test status
Simulation time 947935035 ps
CPU time 10.6 seconds
Started Mar 19 02:49:29 PM PDT 24
Finished Mar 19 02:49:40 PM PDT 24
Peak memory 210852 kb
Host smart-517fc2cc-259d-4e04-9954-2ac808a1f45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104472539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.104472539
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.643833091
Short name T169
Test name
Test status
Simulation time 1745050925 ps
CPU time 14.24 seconds
Started Mar 19 03:09:27 PM PDT 24
Finished Mar 19 03:09:42 PM PDT 24
Peak memory 210808 kb
Host smart-54b8af82-9977-4d3f-aa99-4a20fdeb2b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643833091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.643833091
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3138466246
Short name T412
Test name
Test status
Simulation time 49425846003 ps
CPU time 186.15 seconds
Started Mar 19 03:09:12 PM PDT 24
Finished Mar 19 03:12:18 PM PDT 24
Peak memory 212432 kb
Host smart-1f5caf02-c7d2-49b3-9893-23e6e60c4532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138466246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3138466246
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.983603572
Short name T225
Test name
Test status
Simulation time 18499837247 ps
CPU time 309.69 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:54:31 PM PDT 24
Peak memory 228676 kb
Host smart-42c19296-d2a2-46ad-95c2-b992f4d11aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983603572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.983603572
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3560284176
Short name T265
Test name
Test status
Simulation time 3366288018 ps
CPU time 28.49 seconds
Started Mar 19 02:49:20 PM PDT 24
Finished Mar 19 02:49:51 PM PDT 24
Peak memory 211660 kb
Host smart-cc5f28c8-c155-45c9-9ae6-4502f83d8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560284176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3560284176
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.480084108
Short name T555
Test name
Test status
Simulation time 722387105 ps
CPU time 9.05 seconds
Started Mar 19 03:09:05 PM PDT 24
Finished Mar 19 03:09:14 PM PDT 24
Peak memory 211680 kb
Host smart-e3066ef6-72d4-44a6-9186-6a3a6017c6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480084108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.480084108
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1082082592
Short name T317
Test name
Test status
Simulation time 1332552352 ps
CPU time 12.22 seconds
Started Mar 19 03:09:07 PM PDT 24
Finished Mar 19 03:09:20 PM PDT 24
Peak memory 210700 kb
Host smart-c5d6fdd8-a6cf-44b2-91e0-757bdc411d96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082082592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1082082592
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1626562704
Short name T503
Test name
Test status
Simulation time 2283664249 ps
CPU time 11.74 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:49:34 PM PDT 24
Peak memory 210848 kb
Host smart-ce03d8db-088b-434c-a794-abfba5695903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626562704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1626562704
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1610202863
Short name T522
Test name
Test status
Simulation time 197385344 ps
CPU time 10.27 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:49:38 PM PDT 24
Peak memory 212832 kb
Host smart-ecd0b803-0aff-4531-baca-f056efe72287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610202863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1610202863
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2622162332
Short name T458
Test name
Test status
Simulation time 13696929259 ps
CPU time 33.91 seconds
Started Mar 19 03:09:01 PM PDT 24
Finished Mar 19 03:09:35 PM PDT 24
Peak memory 213484 kb
Host smart-670609ed-97dc-4bad-9ad8-591335ab4570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622162332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2622162332
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1465016802
Short name T404
Test name
Test status
Simulation time 23207488213 ps
CPU time 45.5 seconds
Started Mar 19 02:49:22 PM PDT 24
Finished Mar 19 02:50:08 PM PDT 24
Peak memory 219068 kb
Host smart-9d7409fa-70ec-4357-8e8b-66b316af2774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465016802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1465016802
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.948052984
Short name T621
Test name
Test status
Simulation time 8514411424 ps
CPU time 76.16 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:10:32 PM PDT 24
Peak memory 216700 kb
Host smart-34eda3fc-1399-4b42-ae6c-8be5ecad1e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948052984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.948052984
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2955957685
Short name T260
Test name
Test status
Simulation time 293708577 ps
CPU time 6.29 seconds
Started Mar 19 03:09:05 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 210888 kb
Host smart-6c5a3780-34a0-484c-b370-d2b557b72675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955957685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2955957685
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.408566292
Short name T671
Test name
Test status
Simulation time 7297185193 ps
CPU time 15.03 seconds
Started Mar 19 02:49:29 PM PDT 24
Finished Mar 19 02:49:44 PM PDT 24
Peak memory 210868 kb
Host smart-dcd71a5d-6c4f-49a5-8623-7ebd3ba79e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408566292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.408566292
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1681180143
Short name T547
Test name
Test status
Simulation time 96755373710 ps
CPU time 186.23 seconds
Started Mar 19 02:49:24 PM PDT 24
Finished Mar 19 02:52:30 PM PDT 24
Peak memory 238580 kb
Host smart-4bd8a1c1-cff0-4011-96df-70ddd591159c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681180143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1681180143
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2777698339
Short name T548
Test name
Test status
Simulation time 5155332977 ps
CPU time 124.81 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:11:15 PM PDT 24
Peak memory 229396 kb
Host smart-d09eef70-6895-498b-8143-a2f11aaa764e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777698339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2777698339
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2714523948
Short name T104
Test name
Test status
Simulation time 1266232850 ps
CPU time 16.66 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:23 PM PDT 24
Peak memory 210872 kb
Host smart-601de9d1-616c-4d31-b0c5-e91d488cf1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714523948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2714523948
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.428134976
Short name T462
Test name
Test status
Simulation time 1324014601 ps
CPU time 14.13 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:37 PM PDT 24
Peak memory 211544 kb
Host smart-43e8a612-cd3d-4606-a92d-1c493b0a257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428134976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.428134976
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2961934558
Short name T429
Test name
Test status
Simulation time 4179451259 ps
CPU time 11.08 seconds
Started Mar 19 03:09:05 PM PDT 24
Finished Mar 19 03:09:16 PM PDT 24
Peak memory 210892 kb
Host smart-1b750778-df86-4011-beba-72f6f2d395fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961934558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2961934558
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.953990445
Short name T625
Test name
Test status
Simulation time 1604378711 ps
CPU time 14.24 seconds
Started Mar 19 02:49:29 PM PDT 24
Finished Mar 19 02:49:43 PM PDT 24
Peak memory 210844 kb
Host smart-8dced6ff-2b7d-4178-a2af-cd1299fd8a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953990445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.953990445
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3885300573
Short name T182
Test name
Test status
Simulation time 17369773600 ps
CPU time 40.47 seconds
Started Mar 19 03:09:07 PM PDT 24
Finished Mar 19 03:09:48 PM PDT 24
Peak memory 218924 kb
Host smart-dff29901-04e9-431f-8327-52455b2dd17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885300573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3885300573
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.77902622
Short name T303
Test name
Test status
Simulation time 7328722486 ps
CPU time 30.07 seconds
Started Mar 19 02:49:23 PM PDT 24
Finished Mar 19 02:49:53 PM PDT 24
Peak memory 213964 kb
Host smart-ef6c2f61-5c65-4606-89ba-790c445fa6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77902622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.77902622
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1883352945
Short name T533
Test name
Test status
Simulation time 8642181603 ps
CPU time 92.66 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:10:45 PM PDT 24
Peak memory 218924 kb
Host smart-c5155576-37c8-4e84-b51b-dbafe6d82704
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883352945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1883352945
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.557674449
Short name T294
Test name
Test status
Simulation time 929065865 ps
CPU time 25.49 seconds
Started Mar 19 02:49:24 PM PDT 24
Finished Mar 19 02:49:49 PM PDT 24
Peak memory 216300 kb
Host smart-3456c30d-dd2a-4e0a-b588-972c05e12426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557674449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.557674449
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1999389296
Short name T623
Test name
Test status
Simulation time 20895652053 ps
CPU time 826.98 seconds
Started Mar 19 02:49:19 PM PDT 24
Finished Mar 19 03:03:08 PM PDT 24
Peak memory 233860 kb
Host smart-befe9dfd-8a97-47c2-a5a0-ea238c5bf596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999389296 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1999389296
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4021001223
Short name T517
Test name
Test status
Simulation time 2571462965 ps
CPU time 8.42 seconds
Started Mar 19 03:09:12 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 210940 kb
Host smart-d81b92ec-6a5b-42cc-ac7e-6473acb9ea46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021001223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4021001223
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.514864905
Short name T440
Test name
Test status
Simulation time 172006776 ps
CPU time 4.26 seconds
Started Mar 19 02:49:24 PM PDT 24
Finished Mar 19 02:49:29 PM PDT 24
Peak memory 210900 kb
Host smart-fe590df6-a7df-4fe2-877f-82c26a476e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514864905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.514864905
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3080017914
Short name T633
Test name
Test status
Simulation time 18643475029 ps
CPU time 154.22 seconds
Started Mar 19 03:09:10 PM PDT 24
Finished Mar 19 03:11:45 PM PDT 24
Peak memory 218348 kb
Host smart-487a4d39-2df9-4560-8e29-9d8bb2c8c153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080017914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3080017914
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3497786068
Short name T591
Test name
Test status
Simulation time 23058598711 ps
CPU time 220.61 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:53:09 PM PDT 24
Peak memory 224664 kb
Host smart-a4ea7f21-61fa-416b-9805-135f38f43176
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497786068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3497786068
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1056526619
Short name T21
Test name
Test status
Simulation time 169037395 ps
CPU time 9.51 seconds
Started Mar 19 02:49:32 PM PDT 24
Finished Mar 19 02:49:42 PM PDT 24
Peak memory 211620 kb
Host smart-6ff5743b-bb4d-4027-9b39-3a81f25d85f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056526619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1056526619
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2610171246
Short name T42
Test name
Test status
Simulation time 2191111502 ps
CPU time 22.18 seconds
Started Mar 19 03:09:14 PM PDT 24
Finished Mar 19 03:09:36 PM PDT 24
Peak memory 211708 kb
Host smart-6d7ccd8d-5473-43e3-93b5-1ae5421ec72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610171246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2610171246
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2789983062
Short name T193
Test name
Test status
Simulation time 1076063202 ps
CPU time 12.18 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:09:21 PM PDT 24
Peak memory 210840 kb
Host smart-309d4827-b630-42fa-b25e-18ae40bc0085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789983062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2789983062
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3222284620
Short name T387
Test name
Test status
Simulation time 517520376 ps
CPU time 8.53 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:49:37 PM PDT 24
Peak memory 210844 kb
Host smart-5a0734e1-d2fc-411d-a755-7a155f392106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222284620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3222284620
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4234350675
Short name T326
Test name
Test status
Simulation time 15748053601 ps
CPU time 29.9 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:49:59 PM PDT 24
Peak memory 219072 kb
Host smart-1a254dd0-28f2-49ef-a020-0726318d8af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234350675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4234350675
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.99950542
Short name T534
Test name
Test status
Simulation time 33162121554 ps
CPU time 25.77 seconds
Started Mar 19 03:09:06 PM PDT 24
Finished Mar 19 03:09:32 PM PDT 24
Peak memory 213844 kb
Host smart-56c08462-1d04-4568-a069-38ba1c301ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99950542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.99950542
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3702362956
Short name T514
Test name
Test status
Simulation time 5282261205 ps
CPU time 53.88 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:50:22 PM PDT 24
Peak memory 213100 kb
Host smart-138ebb85-1789-4056-a384-b865e6b0cb37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702362956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3702362956
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4268000059
Short name T295
Test name
Test status
Simulation time 12384459303 ps
CPU time 74.57 seconds
Started Mar 19 03:09:09 PM PDT 24
Finished Mar 19 03:10:24 PM PDT 24
Peak memory 219072 kb
Host smart-59eb09cc-02cd-45db-92e5-dc1bd06c7ee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268000059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4268000059
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2120480546
Short name T312
Test name
Test status
Simulation time 143145274 ps
CPU time 4.43 seconds
Started Mar 19 02:49:36 PM PDT 24
Finished Mar 19 02:49:41 PM PDT 24
Peak memory 210892 kb
Host smart-fac62731-0def-4c58-a3d0-498fe86fc1d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120480546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2120480546
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3760310079
Short name T386
Test name
Test status
Simulation time 12828949524 ps
CPU time 15.73 seconds
Started Mar 19 03:09:22 PM PDT 24
Finished Mar 19 03:09:38 PM PDT 24
Peak memory 210788 kb
Host smart-2dae3b11-df49-4bd9-af58-e9ed7b00c672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760310079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3760310079
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2752760632
Short name T7
Test name
Test status
Simulation time 55760547765 ps
CPU time 151.61 seconds
Started Mar 19 03:09:22 PM PDT 24
Finished Mar 19 03:11:53 PM PDT 24
Peak memory 220380 kb
Host smart-0fe27832-f764-458c-9c0d-b77f0ff37628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752760632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2752760632
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3507255945
Short name T526
Test name
Test status
Simulation time 17680395979 ps
CPU time 160.55 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:52:08 PM PDT 24
Peak memory 232648 kb
Host smart-7d227a36-776d-4980-b52a-f79a303f4781
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507255945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3507255945
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1523801937
Short name T409
Test name
Test status
Simulation time 4563156651 ps
CPU time 16.39 seconds
Started Mar 19 02:49:29 PM PDT 24
Finished Mar 19 02:49:45 PM PDT 24
Peak memory 211856 kb
Host smart-9a652aba-6557-46dc-ab47-6e760c1c6b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523801937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1523801937
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.638795014
Short name T488
Test name
Test status
Simulation time 2619468766 ps
CPU time 17.61 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 211556 kb
Host smart-5db36213-0aac-49e6-8792-aa48332b312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638795014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.638795014
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2505614733
Short name T101
Test name
Test status
Simulation time 2012138392 ps
CPU time 11.68 seconds
Started Mar 19 02:49:25 PM PDT 24
Finished Mar 19 02:49:37 PM PDT 24
Peak memory 210868 kb
Host smart-ee12ec79-26b5-41cc-b3d5-7cb2aa69b6f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505614733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2505614733
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3216653932
Short name T379
Test name
Test status
Simulation time 2152495209 ps
CPU time 11.63 seconds
Started Mar 19 03:09:14 PM PDT 24
Finished Mar 19 03:09:26 PM PDT 24
Peak memory 210836 kb
Host smart-ac886249-5f15-4a14-8557-01a3d9638bb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216653932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3216653932
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1731001686
Short name T352
Test name
Test status
Simulation time 1257618906 ps
CPU time 20.02 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:49:47 PM PDT 24
Peak memory 218988 kb
Host smart-5dcd86f1-2073-4fd9-b46f-3154ad1f716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731001686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1731001686
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.82036493
Short name T405
Test name
Test status
Simulation time 1047022295 ps
CPU time 18.06 seconds
Started Mar 19 03:09:14 PM PDT 24
Finished Mar 19 03:09:33 PM PDT 24
Peak memory 219004 kb
Host smart-bb2e3d1c-3d20-426e-8d45-49defe22d64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82036493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.82036493
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1814975375
Short name T562
Test name
Test status
Simulation time 2632205568 ps
CPU time 53.33 seconds
Started Mar 19 02:49:26 PM PDT 24
Finished Mar 19 02:50:20 PM PDT 24
Peak memory 216136 kb
Host smart-a2ceafab-a9bb-4d62-a42f-51941f39da02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814975375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1814975375
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2732542810
Short name T413
Test name
Test status
Simulation time 17348256809 ps
CPU time 71.6 seconds
Started Mar 19 03:08:53 PM PDT 24
Finished Mar 19 03:10:05 PM PDT 24
Peak memory 219008 kb
Host smart-ecd76238-9ba3-4a0b-9599-6aeef1a59dcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732542810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2732542810
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1603204687
Short name T171
Test name
Test status
Simulation time 1625047146 ps
CPU time 9.4 seconds
Started Mar 19 03:09:22 PM PDT 24
Finished Mar 19 03:09:31 PM PDT 24
Peak memory 210892 kb
Host smart-4509c939-bcb7-4bab-a48f-d1aaf386460b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603204687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1603204687
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.719365349
Short name T159
Test name
Test status
Simulation time 347922411 ps
CPU time 4.32 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:49:31 PM PDT 24
Peak memory 210856 kb
Host smart-a4a4bee2-671a-45d5-af59-91706b0ec57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719365349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.719365349
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.334579719
Short name T279
Test name
Test status
Simulation time 11069893636 ps
CPU time 139.54 seconds
Started Mar 19 03:09:11 PM PDT 24
Finished Mar 19 03:11:31 PM PDT 24
Peak memory 237616 kb
Host smart-c0c7fbd2-e513-41ff-b4d2-121552eb9112
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334579719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.334579719
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.513475227
Short name T525
Test name
Test status
Simulation time 28324919008 ps
CPU time 271.95 seconds
Started Mar 19 02:49:29 PM PDT 24
Finished Mar 19 02:54:01 PM PDT 24
Peak memory 228304 kb
Host smart-7eec485b-8769-422b-894e-5d6d74f919c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513475227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.513475227
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3626480817
Short name T8
Test name
Test status
Simulation time 665691996 ps
CPU time 9.45 seconds
Started Mar 19 03:09:13 PM PDT 24
Finished Mar 19 03:09:23 PM PDT 24
Peak memory 211448 kb
Host smart-bdb966e2-f319-4f61-981c-172498fdcd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626480817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3626480817
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.417060645
Short name T384
Test name
Test status
Simulation time 1887069095 ps
CPU time 21.19 seconds
Started Mar 19 02:49:41 PM PDT 24
Finished Mar 19 02:50:03 PM PDT 24
Peak memory 211652 kb
Host smart-24917718-a3a8-4798-8619-e1dcd57a1652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417060645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.417060645
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1825117193
Short name T630
Test name
Test status
Simulation time 7694555551 ps
CPU time 12.02 seconds
Started Mar 19 03:09:15 PM PDT 24
Finished Mar 19 03:09:28 PM PDT 24
Peak memory 210912 kb
Host smart-3b671425-9aaa-4968-b5bd-761dd0cd57c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825117193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1825117193
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4271326275
Short name T349
Test name
Test status
Simulation time 701449402 ps
CPU time 5.41 seconds
Started Mar 19 02:49:32 PM PDT 24
Finished Mar 19 02:49:39 PM PDT 24
Peak memory 210840 kb
Host smart-7dd2c31a-d879-4964-b83e-d6663ecc37da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271326275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4271326275
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4248324037
Short name T230
Test name
Test status
Simulation time 52551337497 ps
CPU time 37.36 seconds
Started Mar 19 02:49:27 PM PDT 24
Finished Mar 19 02:50:05 PM PDT 24
Peak memory 219072 kb
Host smart-ef324072-417e-4274-9d49-38f8c242f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248324037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4248324037
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.617043060
Short name T482
Test name
Test status
Simulation time 531235609 ps
CPU time 13.59 seconds
Started Mar 19 03:09:23 PM PDT 24
Finished Mar 19 03:09:37 PM PDT 24
Peak memory 212868 kb
Host smart-8e607101-63b7-43e0-9ef3-cc5b77b95d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617043060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.617043060
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2084799605
Short name T376
Test name
Test status
Simulation time 26977391812 ps
CPU time 44.42 seconds
Started Mar 19 02:49:28 PM PDT 24
Finished Mar 19 02:50:12 PM PDT 24
Peak memory 219072 kb
Host smart-21e789d1-7c9a-48eb-9f53-95f6e7578f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084799605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2084799605
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3740243891
Short name T287
Test name
Test status
Simulation time 2159164334 ps
CPU time 16.96 seconds
Started Mar 19 03:09:19 PM PDT 24
Finished Mar 19 03:09:36 PM PDT 24
Peak memory 219080 kb
Host smart-17741ef7-b906-4dac-bd99-4f8b1eee80a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740243891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3740243891
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1877353525
Short name T315
Test name
Test status
Simulation time 8278333144 ps
CPU time 16.46 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 210956 kb
Host smart-fbb9c7b1-2190-4b4f-8953-e3e9026ce201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877353525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1877353525
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4210750859
Short name T573
Test name
Test status
Simulation time 2659116744 ps
CPU time 12.72 seconds
Started Mar 19 02:48:42 PM PDT 24
Finished Mar 19 02:48:55 PM PDT 24
Peak memory 210972 kb
Host smart-eeea18c2-afe8-4de3-9337-6702181b559d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210750859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4210750859
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3786165750
Short name T535
Test name
Test status
Simulation time 433218864031 ps
CPU time 629.27 seconds
Started Mar 19 02:48:40 PM PDT 24
Finished Mar 19 02:59:09 PM PDT 24
Peak memory 236504 kb
Host smart-f027759e-6509-4398-923a-b8c263757c0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786165750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3786165750
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4043241513
Short name T501
Test name
Test status
Simulation time 13328520940 ps
CPU time 106.33 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:10:28 PM PDT 24
Peak memory 232776 kb
Host smart-b7a7b14c-9cf0-4adf-8cc0-3b8b6444d26a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043241513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4043241513
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1848852180
Short name T281
Test name
Test status
Simulation time 4714457650 ps
CPU time 30.63 seconds
Started Mar 19 02:48:40 PM PDT 24
Finished Mar 19 02:49:11 PM PDT 24
Peak memory 211908 kb
Host smart-a0a563dd-da6e-4d37-b273-fc0b0a3d8a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848852180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1848852180
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2752817261
Short name T158
Test name
Test status
Simulation time 874120097 ps
CPU time 9.31 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 211540 kb
Host smart-4b58ed2a-2206-4f3c-b847-e8a219b023f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752817261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2752817261
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3901449648
Short name T153
Test name
Test status
Simulation time 1063127620 ps
CPU time 7.23 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:49:01 PM PDT 24
Peak memory 210824 kb
Host smart-71fcbcdc-a11b-4b95-83c1-c24ba2dfddcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901449648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3901449648
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3963445497
Short name T601
Test name
Test status
Simulation time 1082590589 ps
CPU time 11.74 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:08:57 PM PDT 24
Peak memory 210864 kb
Host smart-af478082-242b-4a9e-90c0-7ef9f861bea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963445497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3963445497
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1339894370
Short name T403
Test name
Test status
Simulation time 2256225619 ps
CPU time 26.03 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:49:21 PM PDT 24
Peak memory 219072 kb
Host smart-552bcc1c-0904-414f-99a5-b6ed1e45bda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339894370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1339894370
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2272916362
Short name T300
Test name
Test status
Simulation time 7913160894 ps
CPU time 32.31 seconds
Started Mar 19 03:08:44 PM PDT 24
Finished Mar 19 03:09:17 PM PDT 24
Peak memory 219084 kb
Host smart-d82127b5-1854-4b8d-be27-5cb401ef4889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272916362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2272916362
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3375769369
Short name T385
Test name
Test status
Simulation time 20362897898 ps
CPU time 37.42 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:49:32 PM PDT 24
Peak memory 219056 kb
Host smart-66d4408f-40a9-4f87-bd89-ce1358ec3c42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375769369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3375769369
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3921076134
Short name T473
Test name
Test status
Simulation time 12005603366 ps
CPU time 36.31 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:09:27 PM PDT 24
Peak memory 213572 kb
Host smart-d190476d-c5e5-4876-9b1a-88dd2377fa37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921076134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3921076134
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2953489599
Short name T13
Test name
Test status
Simulation time 218976894469 ps
CPU time 2260.23 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:46:18 PM PDT 24
Peak memory 237396 kb
Host smart-91abd439-0914-4d73-b03c-94bd7dbfd1cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953489599 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2953489599
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3401564009
Short name T175
Test name
Test status
Simulation time 2307952729 ps
CPU time 12.46 seconds
Started Mar 19 03:08:51 PM PDT 24
Finished Mar 19 03:09:03 PM PDT 24
Peak memory 210860 kb
Host smart-df4f5ea7-29c9-43f9-a955-c23e7b61d9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401564009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3401564009
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3999726876
Short name T430
Test name
Test status
Simulation time 168208306 ps
CPU time 4.25 seconds
Started Mar 19 02:48:45 PM PDT 24
Finished Mar 19 02:48:50 PM PDT 24
Peak memory 210884 kb
Host smart-11181740-cd1e-457b-a4c3-eabcb768a663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999726876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3999726876
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3809133478
Short name T666
Test name
Test status
Simulation time 37543511510 ps
CPU time 287 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:13:22 PM PDT 24
Peak memory 211224 kb
Host smart-e479dc3d-c54b-420d-a1ae-e8b5b7436ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809133478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3809133478
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3994182951
Short name T483
Test name
Test status
Simulation time 33272059669 ps
CPU time 284.43 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:53:42 PM PDT 24
Peak memory 228068 kb
Host smart-7af4eaa8-106f-4055-8e9e-58d7c66e28a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994182951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3994182951
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1388485607
Short name T541
Test name
Test status
Simulation time 5392671678 ps
CPU time 24.04 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:49:18 PM PDT 24
Peak memory 211860 kb
Host smart-f4b9480a-676e-41a8-9665-dfca472e34d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388485607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1388485607
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2565567681
Short name T584
Test name
Test status
Simulation time 5554428873 ps
CPU time 18.08 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:09:01 PM PDT 24
Peak memory 211832 kb
Host smart-3e2260d3-1468-4567-8dc8-3d549317f844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565567681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2565567681
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2776784809
Short name T564
Test name
Test status
Simulation time 2898443264 ps
CPU time 13.69 seconds
Started Mar 19 02:48:42 PM PDT 24
Finished Mar 19 02:48:56 PM PDT 24
Peak memory 210912 kb
Host smart-e4c1a94e-6265-45e9-9ca8-10bef3640094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776784809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2776784809
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.387672168
Short name T519
Test name
Test status
Simulation time 1971308251 ps
CPU time 11.15 seconds
Started Mar 19 03:08:38 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 210848 kb
Host smart-bd282f2b-0a86-4aaa-b2b5-f233a85b224a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387672168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.387672168
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1693889160
Short name T307
Test name
Test status
Simulation time 3840002792 ps
CPU time 33.52 seconds
Started Mar 19 02:48:48 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 212788 kb
Host smart-d5f249d4-86d2-4ff7-b6b5-46bb24d4c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693889160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1693889160
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3028558492
Short name T420
Test name
Test status
Simulation time 5312395466 ps
CPU time 26.33 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:09:05 PM PDT 24
Peak memory 219068 kb
Host smart-b1173568-5657-4775-ae83-b6c9ad97690c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028558492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3028558492
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1146425830
Short name T600
Test name
Test status
Simulation time 2042041915 ps
CPU time 38.18 seconds
Started Mar 19 02:48:47 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 215224 kb
Host smart-4b30de6f-287e-4116-b71c-8ab35a984bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146425830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1146425830
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.822069304
Short name T237
Test name
Test status
Simulation time 2176698783 ps
CPU time 32.1 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:09:11 PM PDT 24
Peak memory 215500 kb
Host smart-c08b96ba-01e6-4bb4-a3f1-fa7b6b19260a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822069304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.822069304
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2580126308
Short name T285
Test name
Test status
Simulation time 1581507899 ps
CPU time 7.01 seconds
Started Mar 19 03:08:46 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 210828 kb
Host smart-38de7ed6-4afe-4909-ae4d-6012fa0a8e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580126308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2580126308
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3272981035
Short name T599
Test name
Test status
Simulation time 3007086493 ps
CPU time 8.61 seconds
Started Mar 19 02:48:45 PM PDT 24
Finished Mar 19 02:48:54 PM PDT 24
Peak memory 210944 kb
Host smart-15e5f2a9-cc27-4f5e-971b-84ef5d2d2ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272981035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3272981035
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1595466093
Short name T377
Test name
Test status
Simulation time 19606274748 ps
CPU time 123.58 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:10:43 PM PDT 24
Peak memory 228532 kb
Host smart-cd088c86-14a9-49cd-b05a-89092f4ca614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595466093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1595466093
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3811232962
Short name T311
Test name
Test status
Simulation time 46535045599 ps
CPU time 204.74 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:52:20 PM PDT 24
Peak memory 229432 kb
Host smart-decbd1c6-cdb1-4138-b69d-6dabe73f8ae5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811232962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3811232962
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.190552723
Short name T492
Test name
Test status
Simulation time 173833494 ps
CPU time 9.38 seconds
Started Mar 19 02:48:43 PM PDT 24
Finished Mar 19 02:48:52 PM PDT 24
Peak memory 211272 kb
Host smart-c7998283-f0c8-4bc0-aa3d-859eb976bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190552723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.190552723
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3283793058
Short name T433
Test name
Test status
Simulation time 1207261270 ps
CPU time 16.89 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:08:54 PM PDT 24
Peak memory 211412 kb
Host smart-665f7dce-1347-4927-95da-cdf1293cfc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283793058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3283793058
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2387831411
Short name T134
Test name
Test status
Simulation time 371498874 ps
CPU time 5.34 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 210844 kb
Host smart-1d71130b-53eb-4f0e-be99-7b43f69e8ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387831411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2387831411
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.444934676
Short name T231
Test name
Test status
Simulation time 2862373037 ps
CPU time 8.02 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:49:03 PM PDT 24
Peak memory 210836 kb
Host smart-507d466d-dec7-4654-b9af-047298f3e6d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444934676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.444934676
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2253995022
Short name T622
Test name
Test status
Simulation time 5021586036 ps
CPU time 26.77 seconds
Started Mar 19 02:48:55 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 212080 kb
Host smart-3c5b7781-9323-4aeb-8e66-f37791d198bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253995022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2253995022
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3682472967
Short name T668
Test name
Test status
Simulation time 11184695426 ps
CPU time 31.87 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:09:13 PM PDT 24
Peak memory 213296 kb
Host smart-dd74f476-ee7d-4c03-a821-52b2b6e77b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682472967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3682472967
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.184697782
Short name T103
Test name
Test status
Simulation time 4196973502 ps
CPU time 26.41 seconds
Started Mar 19 03:08:50 PM PDT 24
Finished Mar 19 03:09:17 PM PDT 24
Peak memory 212736 kb
Host smart-c7739461-ae83-4c80-afc5-89126a53c686
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184697782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.184697782
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3828313313
Short name T620
Test name
Test status
Simulation time 4534380682 ps
CPU time 59.53 seconds
Started Mar 19 02:48:56 PM PDT 24
Finished Mar 19 02:49:56 PM PDT 24
Peak memory 217084 kb
Host smart-7efa79f3-9604-42db-9573-f83fc85575c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828313313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3828313313
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2437165150
Short name T14
Test name
Test status
Simulation time 51798929537 ps
CPU time 2037.75 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:42:37 PM PDT 24
Peak memory 235592 kb
Host smart-cc2bc5c7-eed5-4b1a-bf33-f2ab9342dc9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437165150 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2437165150
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2916895173
Short name T286
Test name
Test status
Simulation time 7583736289 ps
CPU time 13.47 seconds
Started Mar 19 02:49:03 PM PDT 24
Finished Mar 19 02:49:18 PM PDT 24
Peak memory 210936 kb
Host smart-e46db6da-81c3-4e9f-9f75-fc3a377341f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916895173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2916895173
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.588653803
Short name T322
Test name
Test status
Simulation time 878939979 ps
CPU time 6.95 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:46 PM PDT 24
Peak memory 210900 kb
Host smart-150a0da2-928e-4432-8866-319938e872f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588653803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.588653803
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1594637276
Short name T357
Test name
Test status
Simulation time 5384930320 ps
CPU time 95.89 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:50:33 PM PDT 24
Peak memory 236592 kb
Host smart-f8206f31-ef13-4a6e-bbe0-f34835795e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594637276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1594637276
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.401377371
Short name T447
Test name
Test status
Simulation time 1567536518 ps
CPU time 57.92 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:09:43 PM PDT 24
Peak memory 236452 kb
Host smart-11e34751-3b4a-43fe-8d9a-d17af2c668b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401377371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.401377371
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1364997537
Short name T344
Test name
Test status
Simulation time 3181892144 ps
CPU time 28.07 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:49:23 PM PDT 24
Peak memory 211724 kb
Host smart-58c24409-6f58-415c-bb56-e59cbe036f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364997537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1364997537
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3545772733
Short name T161
Test name
Test status
Simulation time 182918194 ps
CPU time 9.37 seconds
Started Mar 19 03:08:39 PM PDT 24
Finished Mar 19 03:08:49 PM PDT 24
Peak memory 211444 kb
Host smart-7fde0153-e133-4555-8fc4-a04bcd38b5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545772733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3545772733
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1640204379
Short name T366
Test name
Test status
Simulation time 982187248 ps
CPU time 11.2 seconds
Started Mar 19 03:08:40 PM PDT 24
Finished Mar 19 03:08:52 PM PDT 24
Peak memory 210772 kb
Host smart-5288e610-f82e-4200-9f6b-a075cd166ec0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640204379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1640204379
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2667292616
Short name T448
Test name
Test status
Simulation time 910134806 ps
CPU time 11.04 seconds
Started Mar 19 02:48:52 PM PDT 24
Finished Mar 19 02:49:03 PM PDT 24
Peak memory 210860 kb
Host smart-e3a9f887-987f-4c47-84b4-f238f13fd360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667292616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2667292616
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2554468254
Short name T553
Test name
Test status
Simulation time 186829420 ps
CPU time 9.68 seconds
Started Mar 19 03:08:50 PM PDT 24
Finished Mar 19 03:09:00 PM PDT 24
Peak memory 213364 kb
Host smart-f2630b27-8240-44a0-861f-7b76dabf34ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554468254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2554468254
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4282689145
Short name T394
Test name
Test status
Simulation time 17154253806 ps
CPU time 46.08 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:49:40 PM PDT 24
Peak memory 213384 kb
Host smart-28905565-de5f-4b3d-8aca-c817ea7e950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282689145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4282689145
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3108842817
Short name T316
Test name
Test status
Simulation time 7121456001 ps
CPU time 73.84 seconds
Started Mar 19 03:08:31 PM PDT 24
Finished Mar 19 03:09:46 PM PDT 24
Peak memory 219100 kb
Host smart-c0f83b23-cd72-4900-b9f5-e6214ad27462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108842817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3108842817
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3200712842
Short name T81
Test name
Test status
Simulation time 29796343517 ps
CPU time 90.2 seconds
Started Mar 19 02:49:02 PM PDT 24
Finished Mar 19 02:50:32 PM PDT 24
Peak memory 219052 kb
Host smart-448b0d4b-74c2-442b-9fe3-bc35c2b33c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200712842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3200712842
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2302192677
Short name T628
Test name
Test status
Simulation time 4662182262 ps
CPU time 11.43 seconds
Started Mar 19 02:48:52 PM PDT 24
Finished Mar 19 02:49:03 PM PDT 24
Peak memory 210956 kb
Host smart-a90712be-d79e-43e8-a4fa-424b05ab3fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302192677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2302192677
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.673261627
Short name T2
Test name
Test status
Simulation time 1741379661 ps
CPU time 14.32 seconds
Started Mar 19 03:09:02 PM PDT 24
Finished Mar 19 03:09:17 PM PDT 24
Peak memory 210884 kb
Host smart-cadc867a-2c3b-410b-83f4-638f54154965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673261627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.673261627
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1028838152
Short name T441
Test name
Test status
Simulation time 54431043310 ps
CPU time 190.54 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:52:08 PM PDT 24
Peak memory 228512 kb
Host smart-7ad42814-f8ee-462c-8895-b05f80d56915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028838152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1028838152
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2788560859
Short name T298
Test name
Test status
Simulation time 23834311435 ps
CPU time 82.08 seconds
Started Mar 19 03:08:42 PM PDT 24
Finished Mar 19 03:10:04 PM PDT 24
Peak memory 229528 kb
Host smart-1b720cfc-f711-4d80-9f96-1cc7444ec483
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788560859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2788560859
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1853933838
Short name T489
Test name
Test status
Simulation time 19988729181 ps
CPU time 29.42 seconds
Started Mar 19 02:48:57 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 211796 kb
Host smart-2aa0732f-49be-4b85-9b25-f747f4b63980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853933838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1853933838
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.624860953
Short name T560
Test name
Test status
Simulation time 172077975 ps
CPU time 9.45 seconds
Started Mar 19 03:08:49 PM PDT 24
Finished Mar 19 03:08:59 PM PDT 24
Peak memory 210916 kb
Host smart-65b06fbe-d500-4bcd-887b-444c7bf2f4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624860953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.624860953
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4157908085
Short name T592
Test name
Test status
Simulation time 93793732 ps
CPU time 5.44 seconds
Started Mar 19 02:48:54 PM PDT 24
Finished Mar 19 02:49:00 PM PDT 24
Peak memory 210840 kb
Host smart-2714e110-95e5-4846-9f47-c1e081f8bbd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157908085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4157908085
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4186502660
Short name T306
Test name
Test status
Simulation time 3467616883 ps
CPU time 17.96 seconds
Started Mar 19 03:08:45 PM PDT 24
Finished Mar 19 03:09:03 PM PDT 24
Peak memory 210904 kb
Host smart-52be3a61-67fd-4adf-afec-c1806424ed90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186502660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4186502660
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1893368543
Short name T466
Test name
Test status
Simulation time 15333999446 ps
CPU time 22.62 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:56 PM PDT 24
Peak memory 213692 kb
Host smart-f3243aff-57e1-4d1d-a784-b8896a7d48a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893368543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1893368543
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2251657511
Short name T116
Test name
Test status
Simulation time 17015259016 ps
CPU time 35.14 seconds
Started Mar 19 02:48:50 PM PDT 24
Finished Mar 19 02:49:25 PM PDT 24
Peak memory 213180 kb
Host smart-2f8ebe2e-dd5f-4377-ba51-1d58193506a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251657511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2251657511
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1064202949
Short name T682
Test name
Test status
Simulation time 3496443147 ps
CPU time 32.15 seconds
Started Mar 19 02:48:50 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 213156 kb
Host smart-93325141-6bc0-476c-a3ab-a75c415e372f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064202949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1064202949
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1746811660
Short name T270
Test name
Test status
Simulation time 2566078936 ps
CPU time 16.32 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:08:53 PM PDT 24
Peak memory 211588 kb
Host smart-17cf87cd-53cf-49e5-a34d-214bd4e9ac6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746811660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1746811660
Directory /workspace/9.rom_ctrl_stress_all/latest
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