Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5017719

1

T1

56848

T3

52

T4

73

full_word

3219125

1

T1

35088

T3

10

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8236294	1			T1	91936		T3	62		T4	81
auto[TlIntgErrCmd]	191	1			T59	4		T60	4		T61	9
auto[TlIntgErrData]	177	1			T59	1		T60	2		T61	5
auto[TlIntgErrBoth]	182	1			T59	5		T60	4		T61	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1324051

1

T1

14524

T3

62

T4

81

auto[1]

6912793

1

T1

77412

T10

159241

T11

576893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	562002	1			T1	6132		T3	52		T4	73
auto[TlIntgErrNone]	partial	auto[1]	4455218	1			T1	50716		T10	102641		T11	373089
auto[TlIntgErrNone]	full_word	auto[0]	761782	1			T1	8392		T3	10		T4	8
auto[TlIntgErrNone]	full_word	auto[1]	2457292	1			T1	26696		T10	56600		T11	203804
auto[TlIntgErrCmd]	partial	auto[0]	80	1			T59	2		T60	2		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	87	1			T59	2		T60	2		T61	4
auto[TlIntgErrCmd]	full_word	auto[0]	13	1			T118	1		T115	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T61	2		T118	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	90	1			T59	1		T60	2		T61	3
auto[TlIntgErrData]	partial	auto[1]	75	1			T61	2		T122	1		T118	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T121	1		T126	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T116	1		T128	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	69	1			T59	1		T61	2		T122	2
auto[TlIntgErrBoth]	partial	auto[1]	98	1			T59	4		T60	3		T61	4
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T60	1		T115	2		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T118	1		T124	1		T120	1