Module Definition
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Module Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.44 100.00 33.33 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.32 100.00 85.29 100.00 100.00 u_rspfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_secure_ptrs.u_rptr 90.00 90.00
gen_secure_ptrs.u_wptr 90.00 90.00



Module Instance : tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.19 100.00 80.77 100.00 100.00 u_reqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.85 100.00 65.38 90.00 100.00 u_sramreqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Width=2,Secure=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00
ALWAYS7677100.00
ALWAYS8877100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
29 1 1
30 1 1
32 1 1
33 1 1
76 1 1
77 1 1
78 1 1
79 unreachable
80 1 1
81 1 1
82 1 1
83 1 1
MISSING_ELSE
88 1 1
89 1 1
90 1 1
91 unreachable
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE


Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Width=2,Secure=1 )
Line Coverage for Module self-instances :
SCORELINE
66.67 100.00
tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
29 1 1
30 1 1
32 1 1
33 1 1
72 1 1


Cond Coverage for Module : prim_fifo_sync_cnt
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 76 4 4 100.00
IF 88 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 78 if (clr_i) -3-: 80 if (wptr_wrap) -4-: 82 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T4
0 0 0 1 Covered T1,T3,T4
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 88 if ((!rst_ni)) -2-: 90 if (clr_i) -3-: 92 if (rptr_wrap) -4-: 94 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T4
0 0 0 1 Covered T1,T3,T4
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
29 1 1
30 1 1
32 1 1
33 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions3133.33
Logical3133.33
Non-Logical00
Event00

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00
ALWAYS7677100.00
ALWAYS8877100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
29 1 1
30 1 1
32 1 1
33 1 1
76 1 1
77 1 1
78 1 1
79 unreachable
80 1 1
81 1 1
82 1 1
83 1 1
MISSING_ELSE
88 1 1
89 1 1
90 1 1
91 unreachable
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 76 4 4 100.00
IF 88 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 78 if (clr_i) -3-: 80 if (wptr_wrap) -4-: 82 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T4
0 0 0 1 Covered T1,T3,T4
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 88 if ((!rst_ni)) -2-: 90 if (clr_i) -3-: 92 if (rptr_wrap) -4-: 94 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T4
0 0 0 1 Covered T1,T3,T4
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00
ALWAYS7677100.00
ALWAYS8877100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
29 1 1
30 1 1
32 1 1
33 1 1
76 1 1
77 1 1
78 1 1
79 unreachable
80 1 1
81 1 1
82 1 1
83 1 1
MISSING_ELSE
88 1 1
89 1 1
90 1 1
91 unreachable
92 1 1
93 1 1
94 1 1
95 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 76 4 4 100.00
IF 88 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 78 if (clr_i) -3-: 80 if (wptr_wrap) -4-: 82 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T4
0 0 0 1 Covered T1,T3,T4
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 88 if ((!rst_ni)) -2-: 90 if (clr_i) -3-: 92 if (rptr_wrap) -4-: 94 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T4
0 0 0 1 Covered T1,T3,T4
0 0 0 0 Covered T1,T2,T3

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