| T548 |
/workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2701387761 |
|
|
Mar 21 03:20:59 PM PDT 24 |
Mar 21 03:41:09 PM PDT 24 |
29819406828 ps |
| T549 |
/workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3816032160 |
|
|
Mar 21 03:22:30 PM PDT 24 |
Mar 21 03:22:46 PM PDT 24 |
7128794447 ps |
| T550 |
/workspace/coverage/default/26.rom_ctrl_max_throughput_chk.179355577 |
|
|
Mar 21 03:21:57 PM PDT 24 |
Mar 21 03:22:09 PM PDT 24 |
4299752234 ps |
| T551 |
/workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1703622340 |
|
|
Mar 21 03:20:50 PM PDT 24 |
Mar 21 03:21:02 PM PDT 24 |
1007436624 ps |
| T552 |
/workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2487220803 |
|
|
Mar 21 03:20:59 PM PDT 24 |
Mar 21 03:21:15 PM PDT 24 |
1816105264 ps |
| T553 |
/workspace/coverage/default/28.rom_ctrl_alert_test.1790831470 |
|
|
Mar 21 03:22:01 PM PDT 24 |
Mar 21 03:22:13 PM PDT 24 |
24793061125 ps |
| T554 |
/workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3341264134 |
|
|
Mar 21 03:22:45 PM PDT 24 |
Mar 21 03:23:09 PM PDT 24 |
2425337829 ps |
| T555 |
/workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4167670805 |
|
|
Mar 21 03:21:06 PM PDT 24 |
Mar 21 03:27:24 PM PDT 24 |
405089007712 ps |
| T556 |
/workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2018861883 |
|
|
Mar 21 01:36:26 PM PDT 24 |
Mar 21 01:42:43 PM PDT 24 |
154833317786 ps |
| T557 |
/workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1061811624 |
|
|
Mar 21 03:22:46 PM PDT 24 |
Mar 21 03:27:11 PM PDT 24 |
11079390520 ps |
| T558 |
/workspace/coverage/default/42.rom_ctrl_max_throughput_chk.608859444 |
|
|
Mar 21 01:36:33 PM PDT 24 |
Mar 21 01:36:39 PM PDT 24 |
367487610 ps |
| T559 |
/workspace/coverage/default/28.rom_ctrl_stress_all.1262580394 |
|
|
Mar 21 01:36:14 PM PDT 24 |
Mar 21 01:36:36 PM PDT 24 |
464779432 ps |
| T560 |
/workspace/coverage/default/5.rom_ctrl_smoke.3957337622 |
|
|
Mar 21 01:35:43 PM PDT 24 |
Mar 21 01:36:18 PM PDT 24 |
16036063977 ps |
| T561 |
/workspace/coverage/default/27.rom_ctrl_stress_all.3093110723 |
|
|
Mar 21 01:36:10 PM PDT 24 |
Mar 21 01:36:30 PM PDT 24 |
3916633687 ps |
| T562 |
/workspace/coverage/default/10.rom_ctrl_stress_all.3020146610 |
|
|
Mar 21 01:35:56 PM PDT 24 |
Mar 21 01:36:38 PM PDT 24 |
4636501939 ps |
| T563 |
/workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3165760965 |
|
|
Mar 21 03:22:59 PM PDT 24 |
Mar 21 03:23:12 PM PDT 24 |
1275257140 ps |
| T564 |
/workspace/coverage/default/42.rom_ctrl_smoke.4077042638 |
|
|
Mar 21 01:36:27 PM PDT 24 |
Mar 21 01:37:07 PM PDT 24 |
3934452688 ps |
| T565 |
/workspace/coverage/default/34.rom_ctrl_stress_all.86522339 |
|
|
Mar 21 01:36:17 PM PDT 24 |
Mar 21 01:36:34 PM PDT 24 |
370802211 ps |
| T566 |
/workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1951916165 |
|
|
Mar 21 03:22:46 PM PDT 24 |
Mar 21 03:22:51 PM PDT 24 |
100151773 ps |
| T567 |
/workspace/coverage/default/8.rom_ctrl_stress_all.1674035606 |
|
|
Mar 21 01:35:49 PM PDT 24 |
Mar 21 01:36:40 PM PDT 24 |
4700591973 ps |
| T568 |
/workspace/coverage/default/17.rom_ctrl_smoke.341159061 |
|
|
Mar 21 01:36:05 PM PDT 24 |
Mar 21 01:36:16 PM PDT 24 |
2949239207 ps |
| T569 |
/workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1094947995 |
|
|
Mar 21 01:35:44 PM PDT 24 |
Mar 21 01:35:54 PM PDT 24 |
914045229 ps |
| T570 |
/workspace/coverage/default/19.rom_ctrl_stress_all.2931172811 |
|
|
Mar 21 03:21:39 PM PDT 24 |
Mar 21 03:21:58 PM PDT 24 |
3676526201 ps |
| T571 |
/workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2720250911 |
|
|
Mar 21 01:36:00 PM PDT 24 |
Mar 21 01:36:14 PM PDT 24 |
3874647439 ps |
| T572 |
/workspace/coverage/default/25.rom_ctrl_smoke.1138412956 |
|
|
Mar 21 03:21:49 PM PDT 24 |
Mar 21 03:22:19 PM PDT 24 |
33976390019 ps |
| T573 |
/workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2708680595 |
|
|
Mar 21 03:22:21 PM PDT 24 |
Mar 21 03:22:32 PM PDT 24 |
1246243705 ps |
| T574 |
/workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1987552351 |
|
|
Mar 21 03:21:59 PM PDT 24 |
Mar 21 03:50:59 PM PDT 24 |
43078863402 ps |
| T575 |
/workspace/coverage/default/33.rom_ctrl_alert_test.823044111 |
|
|
Mar 21 01:36:18 PM PDT 24 |
Mar 21 01:36:23 PM PDT 24 |
516609635 ps |
| T576 |
/workspace/coverage/default/26.rom_ctrl_alert_test.2180955287 |
|
|
Mar 21 03:21:58 PM PDT 24 |
Mar 21 03:22:06 PM PDT 24 |
2145712435 ps |
| T577 |
/workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1771779952 |
|
|
Mar 21 03:21:51 PM PDT 24 |
Mar 21 03:22:00 PM PDT 24 |
293597142 ps |
| T578 |
/workspace/coverage/default/10.rom_ctrl_smoke.3678183399 |
|
|
Mar 21 01:36:08 PM PDT 24 |
Mar 21 01:36:18 PM PDT 24 |
348730204 ps |
| T579 |
/workspace/coverage/default/0.rom_ctrl_stress_all.1838401617 |
|
|
Mar 21 03:20:50 PM PDT 24 |
Mar 21 03:21:36 PM PDT 24 |
3436026969 ps |
| T580 |
/workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1116519439 |
|
|
Mar 21 01:35:44 PM PDT 24 |
Mar 21 01:37:19 PM PDT 24 |
1543460586 ps |
| T114 |
/workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2751016575 |
|
|
Mar 21 03:21:30 PM PDT 24 |
Mar 21 03:46:12 PM PDT 24 |
132794729879 ps |
| T581 |
/workspace/coverage/default/47.rom_ctrl_kmac_err_chk.289998658 |
|
|
Mar 21 03:22:47 PM PDT 24 |
Mar 21 03:23:01 PM PDT 24 |
2398575200 ps |
| T582 |
/workspace/coverage/default/46.rom_ctrl_smoke.2634380777 |
|
|
Mar 21 03:22:47 PM PDT 24 |
Mar 21 03:23:31 PM PDT 24 |
4642515194 ps |
| T583 |
/workspace/coverage/default/9.rom_ctrl_kmac_err_chk.784280842 |
|
|
Mar 21 01:36:01 PM PDT 24 |
Mar 21 01:36:13 PM PDT 24 |
1371944356 ps |
| T584 |
/workspace/coverage/default/40.rom_ctrl_smoke.2954772469 |
|
|
Mar 21 01:36:29 PM PDT 24 |
Mar 21 01:36:56 PM PDT 24 |
9874291635 ps |
| T585 |
/workspace/coverage/default/31.rom_ctrl_alert_test.930105050 |
|
|
Mar 21 01:36:17 PM PDT 24 |
Mar 21 01:36:21 PM PDT 24 |
332731836 ps |
| T586 |
/workspace/coverage/default/17.rom_ctrl_alert_test.870448002 |
|
|
Mar 21 03:21:38 PM PDT 24 |
Mar 21 03:21:50 PM PDT 24 |
2464436303 ps |
| T587 |
/workspace/coverage/default/6.rom_ctrl_alert_test.2799747967 |
|
|
Mar 21 01:35:45 PM PDT 24 |
Mar 21 01:35:56 PM PDT 24 |
3906409308 ps |
| T588 |
/workspace/coverage/default/37.rom_ctrl_alert_test.2901852361 |
|
|
Mar 21 01:36:30 PM PDT 24 |
Mar 21 01:36:41 PM PDT 24 |
3739338996 ps |
| T589 |
/workspace/coverage/default/21.rom_ctrl_smoke.3933000832 |
|
|
Mar 21 01:35:55 PM PDT 24 |
Mar 21 01:36:15 PM PDT 24 |
1692094153 ps |
| T590 |
/workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2116166609 |
|
|
Mar 21 03:22:01 PM PDT 24 |
Mar 21 03:28:53 PM PDT 24 |
45707834446 ps |
| T591 |
/workspace/coverage/default/43.rom_ctrl_stress_all.2416010729 |
|
|
Mar 21 01:36:32 PM PDT 24 |
Mar 21 01:36:52 PM PDT 24 |
381318637 ps |
| T592 |
/workspace/coverage/default/35.rom_ctrl_kmac_err_chk.446884191 |
|
|
Mar 21 01:36:10 PM PDT 24 |
Mar 21 01:36:20 PM PDT 24 |
177762993 ps |
| T593 |
/workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3550304879 |
|
|
Mar 21 01:36:04 PM PDT 24 |
Mar 21 01:40:28 PM PDT 24 |
97539624027 ps |
| T594 |
/workspace/coverage/default/30.rom_ctrl_smoke.2118323750 |
|
|
Mar 21 03:21:57 PM PDT 24 |
Mar 21 03:22:20 PM PDT 24 |
4120097234 ps |
| T595 |
/workspace/coverage/default/15.rom_ctrl_max_throughput_chk.126727238 |
|
|
Mar 21 03:21:30 PM PDT 24 |
Mar 21 03:21:47 PM PDT 24 |
7433848960 ps |
| T596 |
/workspace/coverage/default/32.rom_ctrl_kmac_err_chk.942691439 |
|
|
Mar 21 01:36:17 PM PDT 24 |
Mar 21 01:36:49 PM PDT 24 |
3674317269 ps |
| T597 |
/workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1751720481 |
|
|
Mar 21 01:36:37 PM PDT 24 |
Mar 21 01:36:45 PM PDT 24 |
344975225 ps |
| T598 |
/workspace/coverage/default/15.rom_ctrl_stress_all.2159686800 |
|
|
Mar 21 01:36:09 PM PDT 24 |
Mar 21 01:36:32 PM PDT 24 |
10778230512 ps |
| T599 |
/workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1911632099 |
|
|
Mar 21 03:22:11 PM PDT 24 |
Mar 21 03:23:22 PM PDT 24 |
9703628404 ps |
| T600 |
/workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.541109162 |
|
|
Mar 21 03:22:21 PM PDT 24 |
Mar 21 03:25:10 PM PDT 24 |
54609272975 ps |
| T601 |
/workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.385449554 |
|
|
Mar 21 01:36:05 PM PDT 24 |
Mar 21 01:38:26 PM PDT 24 |
6540254577 ps |
| T602 |
/workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2127835741 |
|
|
Mar 21 01:35:59 PM PDT 24 |
Mar 21 01:36:15 PM PDT 24 |
18804985153 ps |
| T603 |
/workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4253461107 |
|
|
Mar 21 01:36:16 PM PDT 24 |
Mar 21 03:37:13 PM PDT 24 |
125956174263 ps |
| T41 |
/workspace/coverage/default/0.rom_ctrl_sec_cm.626309321 |
|
|
Mar 21 01:35:43 PM PDT 24 |
Mar 21 01:36:46 PM PDT 24 |
11217601553 ps |
| T604 |
/workspace/coverage/default/27.rom_ctrl_stress_all.274183772 |
|
|
Mar 21 03:21:57 PM PDT 24 |
Mar 21 03:22:19 PM PDT 24 |
1022219578 ps |
| T605 |
/workspace/coverage/default/21.rom_ctrl_stress_all.2446202432 |
|
|
Mar 21 01:36:08 PM PDT 24 |
Mar 21 01:36:22 PM PDT 24 |
1340895646 ps |
| T606 |
/workspace/coverage/default/5.rom_ctrl_stress_all.889570719 |
|
|
Mar 21 03:20:59 PM PDT 24 |
Mar 21 03:21:43 PM PDT 24 |
9060308339 ps |
| T607 |
/workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.567292032 |
|
|
Mar 21 03:21:40 PM PDT 24 |
Mar 21 03:23:14 PM PDT 24 |
1634434289 ps |
| T608 |
/workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3693400666 |
|
|
Mar 21 01:36:05 PM PDT 24 |
Mar 21 01:43:50 PM PDT 24 |
43728062163 ps |
| T609 |
/workspace/coverage/default/4.rom_ctrl_kmac_err_chk.291601616 |
|
|
Mar 21 01:35:51 PM PDT 24 |
Mar 21 01:36:10 PM PDT 24 |
1466484828 ps |
| T610 |
/workspace/coverage/default/16.rom_ctrl_max_throughput_chk.246909158 |
|
|
Mar 21 03:21:31 PM PDT 24 |
Mar 21 03:21:48 PM PDT 24 |
2092949637 ps |
| T611 |
/workspace/coverage/default/10.rom_ctrl_kmac_err_chk.561914131 |
|
|
Mar 21 03:21:19 PM PDT 24 |
Mar 21 03:21:51 PM PDT 24 |
15376323482 ps |
| T612 |
/workspace/coverage/default/37.rom_ctrl_smoke.3041722527 |
|
|
Mar 21 03:22:21 PM PDT 24 |
Mar 21 03:22:57 PM PDT 24 |
3946517124 ps |
| T613 |
/workspace/coverage/default/49.rom_ctrl_kmac_err_chk.976915358 |
|
|
Mar 21 01:36:40 PM PDT 24 |
Mar 21 01:37:05 PM PDT 24 |
2559519874 ps |
| T614 |
/workspace/coverage/default/26.rom_ctrl_alert_test.2988627358 |
|
|
Mar 21 01:36:10 PM PDT 24 |
Mar 21 01:36:27 PM PDT 24 |
2113089087 ps |
| T615 |
/workspace/coverage/default/14.rom_ctrl_alert_test.524076436 |
|
|
Mar 21 01:36:03 PM PDT 24 |
Mar 21 01:36:18 PM PDT 24 |
3545609208 ps |
| T616 |
/workspace/coverage/default/3.rom_ctrl_alert_test.1215335511 |
|
|
Mar 21 03:21:00 PM PDT 24 |
Mar 21 03:21:14 PM PDT 24 |
4427969965 ps |
| T617 |
/workspace/coverage/default/25.rom_ctrl_max_throughput_chk.666393766 |
|
|
Mar 21 01:36:10 PM PDT 24 |
Mar 21 01:36:19 PM PDT 24 |
1272514190 ps |
| T618 |
/workspace/coverage/default/18.rom_ctrl_alert_test.1013341856 |
|
|
Mar 21 03:21:40 PM PDT 24 |
Mar 21 03:21:52 PM PDT 24 |
9383482888 ps |
| T619 |
/workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3516670490 |
|
|
Mar 21 01:36:08 PM PDT 24 |
Mar 21 01:36:28 PM PDT 24 |
6270999718 ps |
| T620 |
/workspace/coverage/default/27.rom_ctrl_smoke.4223580441 |
|
|
Mar 21 03:21:58 PM PDT 24 |
Mar 21 03:22:30 PM PDT 24 |
7250502925 ps |
| T621 |
/workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1214097002 |
|
|
Mar 21 01:36:33 PM PDT 24 |
Mar 21 01:36:58 PM PDT 24 |
10358246071 ps |
| T622 |
/workspace/coverage/default/49.rom_ctrl_stress_all.1593926381 |
|
|
Mar 21 03:23:00 PM PDT 24 |
Mar 21 03:23:27 PM PDT 24 |
2519087142 ps |
| T623 |
/workspace/coverage/default/48.rom_ctrl_smoke.1666052956 |
|
|
Mar 21 03:22:49 PM PDT 24 |
Mar 21 03:23:25 PM PDT 24 |
3935709907 ps |
| T624 |
/workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1848137974 |
|
|
Mar 21 03:22:35 PM PDT 24 |
Mar 21 03:22:45 PM PDT 24 |
3524990178 ps |
| T625 |
/workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3478400371 |
|
|
Mar 21 01:35:41 PM PDT 24 |
Mar 21 02:15:01 PM PDT 24 |
63781351517 ps |
| T626 |
/workspace/coverage/default/25.rom_ctrl_stress_all.2616436667 |
|
|
Mar 21 01:36:16 PM PDT 24 |
Mar 21 01:37:13 PM PDT 24 |
8849385904 ps |
| T627 |
/workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1239213476 |
|
|
Mar 21 03:22:31 PM PDT 24 |
Mar 21 03:24:22 PM PDT 24 |
2767474264 ps |
| T628 |
/workspace/coverage/default/28.rom_ctrl_smoke.998166648 |
|
|
Mar 21 01:36:10 PM PDT 24 |
Mar 21 01:36:20 PM PDT 24 |
727450708 ps |
| T629 |
/workspace/coverage/default/36.rom_ctrl_alert_test.3418913721 |
|
|
Mar 21 03:22:24 PM PDT 24 |
Mar 21 03:22:28 PM PDT 24 |
332825160 ps |
| T630 |
/workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2757656775 |
|
|
Mar 21 03:22:32 PM PDT 24 |
Mar 21 03:22:51 PM PDT 24 |
1544151339 ps |
| T631 |
/workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3372383866 |
|
|
Mar 21 01:36:08 PM PDT 24 |
Mar 21 01:36:21 PM PDT 24 |
6704753893 ps |
| T632 |
/workspace/coverage/default/4.rom_ctrl_smoke.688547714 |
|
|
Mar 21 03:21:00 PM PDT 24 |
Mar 21 03:21:40 PM PDT 24 |
3595125653 ps |
| T633 |
/workspace/coverage/default/43.rom_ctrl_alert_test.1703268811 |
|
|
Mar 21 03:22:49 PM PDT 24 |
Mar 21 03:23:00 PM PDT 24 |
4829102226 ps |
| T634 |
/workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2522031993 |
|
|
Mar 21 01:36:00 PM PDT 24 |
Mar 21 01:38:39 PM PDT 24 |
3598497383 ps |
| T635 |
/workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3322056482 |
|
|
Mar 21 01:36:06 PM PDT 24 |
Mar 21 01:36:41 PM PDT 24 |
24171991906 ps |
| T636 |
/workspace/coverage/default/24.rom_ctrl_smoke.3866289129 |
|
|
Mar 21 03:21:55 PM PDT 24 |
Mar 21 03:22:28 PM PDT 24 |
3282290031 ps |
| T637 |
/workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1360100808 |
|
|
Mar 21 01:36:16 PM PDT 24 |
Mar 21 01:36:36 PM PDT 24 |
6083416858 ps |
| T638 |
/workspace/coverage/default/46.rom_ctrl_stress_all.3999810686 |
|
|
Mar 21 03:22:47 PM PDT 24 |
Mar 21 03:23:09 PM PDT 24 |
413340164 ps |
| T639 |
/workspace/coverage/default/20.rom_ctrl_alert_test.2936866074 |
|
|
Mar 21 03:21:39 PM PDT 24 |
Mar 21 03:21:53 PM PDT 24 |
1512897751 ps |
| T640 |
/workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3815115470 |
|
|
Mar 21 01:36:03 PM PDT 24 |
Mar 21 01:36:13 PM PDT 24 |
735389667 ps |
| T641 |
/workspace/coverage/default/18.rom_ctrl_kmac_err_chk.704832319 |
|
|
Mar 21 01:36:07 PM PDT 24 |
Mar 21 01:36:18 PM PDT 24 |
347862413 ps |
| T642 |
/workspace/coverage/default/22.rom_ctrl_stress_all.2542028648 |
|
|
Mar 21 01:36:09 PM PDT 24 |
Mar 21 01:38:29 PM PDT 24 |
17114202312 ps |
| T643 |
/workspace/coverage/default/8.rom_ctrl_smoke.1974250323 |
|
|
Mar 21 03:21:00 PM PDT 24 |
Mar 21 03:21:11 PM PDT 24 |
764811392 ps |
| T644 |
/workspace/coverage/default/25.rom_ctrl_alert_test.1240826210 |
|
|
Mar 21 01:36:09 PM PDT 24 |
Mar 21 01:36:24 PM PDT 24 |
1701927074 ps |
| T645 |
/workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3296487686 |
|
|
Mar 21 01:36:13 PM PDT 24 |
Mar 21 01:36:30 PM PDT 24 |
7661567227 ps |
| T646 |
/workspace/coverage/default/41.rom_ctrl_smoke.2123030851 |
|
|
Mar 21 01:36:27 PM PDT 24 |
Mar 21 01:36:44 PM PDT 24 |
1209604493 ps |
| T647 |
/workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2677646242 |
|
|
Mar 21 01:36:12 PM PDT 24 |
Mar 21 01:36:20 PM PDT 24 |
2808516329 ps |
| T648 |
/workspace/coverage/default/12.rom_ctrl_stress_all.1732986791 |
|
|
Mar 21 01:36:03 PM PDT 24 |
Mar 21 01:36:55 PM PDT 24 |
18113573026 ps |
| T649 |
/workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3031586417 |
|
|
Mar 21 01:36:08 PM PDT 24 |
Mar 21 01:36:18 PM PDT 24 |
596685466 ps |
| T650 |
/workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3340777703 |
|
|
Mar 21 01:36:39 PM PDT 24 |
Mar 21 01:36:55 PM PDT 24 |
5672074860 ps |
| T651 |
/workspace/coverage/default/22.rom_ctrl_max_throughput_chk.988881567 |
|
|
Mar 21 03:21:48 PM PDT 24 |
Mar 21 03:21:54 PM PDT 24 |
190548077 ps |
| T652 |
/workspace/coverage/default/21.rom_ctrl_smoke.1410994212 |
|
|
Mar 21 03:21:42 PM PDT 24 |
Mar 21 03:22:11 PM PDT 24 |
51235011729 ps |
| T653 |
/workspace/coverage/default/19.rom_ctrl_alert_test.2839363997 |
|
|
Mar 21 03:21:40 PM PDT 24 |
Mar 21 03:21:47 PM PDT 24 |
1721263000 ps |
| T654 |
/workspace/coverage/default/43.rom_ctrl_stress_all.1741532771 |
|
|
Mar 21 03:22:32 PM PDT 24 |
Mar 21 03:23:20 PM PDT 24 |
8787595398 ps |
| T655 |
/workspace/coverage/default/34.rom_ctrl_max_throughput_chk.480384578 |
|
|
Mar 21 01:36:16 PM PDT 24 |
Mar 21 01:36:24 PM PDT 24 |
706734002 ps |
| T656 |
/workspace/coverage/default/35.rom_ctrl_alert_test.2386760325 |
|
|
Mar 21 03:22:22 PM PDT 24 |
Mar 21 03:22:27 PM PDT 24 |
169286099 ps |
| T657 |
/workspace/coverage/default/31.rom_ctrl_max_throughput_chk.806166421 |
|
|
Mar 21 03:22:12 PM PDT 24 |
Mar 21 03:22:27 PM PDT 24 |
1725152516 ps |
| T658 |
/workspace/coverage/default/0.rom_ctrl_alert_test.533013476 |
|
|
Mar 21 01:35:45 PM PDT 24 |
Mar 21 01:35:50 PM PDT 24 |
174962343 ps |
| T659 |
/workspace/coverage/default/9.rom_ctrl_alert_test.1036338904 |
|
|
Mar 21 01:36:06 PM PDT 24 |
Mar 21 01:36:17 PM PDT 24 |
1039026758 ps |
| T660 |
/workspace/coverage/default/45.rom_ctrl_smoke.815961749 |
|
|
Mar 21 01:36:35 PM PDT 24 |
Mar 21 01:36:55 PM PDT 24 |
4145732382 ps |
| T661 |
/workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2571223933 |
|
|
Mar 21 03:22:47 PM PDT 24 |
Mar 21 03:24:51 PM PDT 24 |
7544935486 ps |
| T662 |
/workspace/coverage/default/30.rom_ctrl_alert_test.2128375080 |
|
|
Mar 21 03:22:09 PM PDT 24 |
Mar 21 03:22:19 PM PDT 24 |
781244357 ps |
| T663 |
/workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1208028164 |
|
|
Mar 21 03:21:51 PM PDT 24 |
Mar 21 03:30:36 PM PDT 24 |
202624143688 ps |
| T664 |
/workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1890876537 |
|
|
Mar 21 03:22:22 PM PDT 24 |
Mar 21 03:22:42 PM PDT 24 |
6809140488 ps |
| T665 |
/workspace/coverage/default/45.rom_ctrl_stress_all.1270972779 |
|
|
Mar 21 03:22:46 PM PDT 24 |
Mar 21 03:22:53 PM PDT 24 |
431666894 ps |
| T666 |
/workspace/coverage/default/41.rom_ctrl_alert_test.1128162365 |
|
|
Mar 21 03:22:32 PM PDT 24 |
Mar 21 03:22:41 PM PDT 24 |
591132986 ps |
| T667 |
/workspace/coverage/default/16.rom_ctrl_smoke.1619900017 |
|
|
Mar 21 03:21:40 PM PDT 24 |
Mar 21 03:22:13 PM PDT 24 |
50860919553 ps |
| T668 |
/workspace/coverage/default/32.rom_ctrl_smoke.3000560017 |
|
|
Mar 21 03:22:09 PM PDT 24 |
Mar 21 03:22:37 PM PDT 24 |
2851154762 ps |
| T669 |
/workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1537508818 |
|
|
Mar 21 01:36:43 PM PDT 24 |
Mar 21 01:41:12 PM PDT 24 |
25902290321 ps |
| T670 |
/workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2551405654 |
|
|
Mar 21 03:22:46 PM PDT 24 |
Mar 21 03:25:14 PM PDT 24 |
2322953048 ps |
| T671 |
/workspace/coverage/default/24.rom_ctrl_kmac_err_chk.396868625 |
|
|
Mar 21 01:36:11 PM PDT 24 |
Mar 21 01:36:41 PM PDT 24 |
3591544930 ps |
| T672 |
/workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1234826141 |
|
|
Mar 21 01:35:57 PM PDT 24 |
Mar 21 01:36:03 PM PDT 24 |
418189691 ps |
| T673 |
/workspace/coverage/default/29.rom_ctrl_stress_all.3633048079 |
|
|
Mar 21 03:22:04 PM PDT 24 |
Mar 21 03:23:35 PM PDT 24 |
11521251530 ps |
| T674 |
/workspace/coverage/default/35.rom_ctrl_alert_test.2272355536 |
|
|
Mar 21 01:36:14 PM PDT 24 |
Mar 21 01:36:27 PM PDT 24 |
2628312780 ps |
| T675 |
/workspace/coverage/default/7.rom_ctrl_stress_all.3156204979 |
|
|
Mar 21 01:35:47 PM PDT 24 |
Mar 21 01:36:30 PM PDT 24 |
8266980916 ps |
| T676 |
/workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3652693554 |
|
|
Mar 21 01:36:29 PM PDT 24 |
Mar 21 01:36:54 PM PDT 24 |
3588180398 ps |
| T677 |
/workspace/coverage/default/1.rom_ctrl_stress_all.1456215609 |
|
|
Mar 21 03:20:47 PM PDT 24 |
Mar 21 03:21:47 PM PDT 24 |
30273990380 ps |
| T678 |
/workspace/coverage/default/11.rom_ctrl_alert_test.728970103 |
|
|
Mar 21 03:21:31 PM PDT 24 |
Mar 21 03:21:45 PM PDT 24 |
2975786366 ps |
| T679 |
/workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4282911782 |
|
|
Mar 21 03:22:00 PM PDT 24 |
Mar 21 03:26:02 PM PDT 24 |
22061970280 ps |
| T680 |
/workspace/coverage/default/0.rom_ctrl_stress_all.4111641654 |
|
|
Mar 21 01:35:37 PM PDT 24 |
Mar 21 01:36:51 PM PDT 24 |
12514373566 ps |
| T681 |
/workspace/coverage/default/36.rom_ctrl_stress_all.2279491144 |
|
|
Mar 21 03:22:21 PM PDT 24 |
Mar 21 03:22:46 PM PDT 24 |
1416982537 ps |
| T682 |
/workspace/coverage/default/9.rom_ctrl_max_throughput_chk.669445899 |
|
|
Mar 21 03:21:08 PM PDT 24 |
Mar 21 03:21:25 PM PDT 24 |
1713306851 ps |
| T683 |
/workspace/coverage/default/42.rom_ctrl_kmac_err_chk.745405014 |
|
|
Mar 21 01:36:26 PM PDT 24 |
Mar 21 01:36:44 PM PDT 24 |
1269967894 ps |
| T684 |
/workspace/coverage/default/31.rom_ctrl_kmac_err_chk.540557106 |
|
|
Mar 21 01:36:16 PM PDT 24 |
Mar 21 01:36:35 PM PDT 24 |
1350139954 ps |
| T685 |
/workspace/coverage/default/29.rom_ctrl_smoke.1071196342 |
|
|
Mar 21 01:36:12 PM PDT 24 |
Mar 21 01:36:29 PM PDT 24 |
3600140443 ps |
| T686 |
/workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2146227264 |
|
|
Mar 21 01:36:33 PM PDT 24 |
Mar 21 01:41:22 PM PDT 24 |
48830554018 ps |
| T687 |
/workspace/coverage/default/38.rom_ctrl_smoke.4274210987 |
|
|
Mar 21 03:22:31 PM PDT 24 |
Mar 21 03:23:00 PM PDT 24 |
10229762808 ps |
| T688 |
/workspace/coverage/default/34.rom_ctrl_alert_test.176246381 |
|
|
Mar 21 03:22:26 PM PDT 24 |
Mar 21 03:22:37 PM PDT 24 |
4078018746 ps |
| T689 |
/workspace/coverage/default/47.rom_ctrl_alert_test.3192147193 |
|
|
Mar 21 03:22:48 PM PDT 24 |
Mar 21 03:23:03 PM PDT 24 |
1941791688 ps |
| T62 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3693818589 |
|
|
Mar 21 01:37:44 PM PDT 24 |
Mar 21 01:37:53 PM PDT 24 |
1268350056 ps |
| T690 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1693391844 |
|
|
Mar 21 01:37:20 PM PDT 24 |
Mar 21 01:37:29 PM PDT 24 |
174477566 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2303366956 |
|
|
Mar 21 01:37:26 PM PDT 24 |
Mar 21 01:37:35 PM PDT 24 |
972279682 ps |
| T59 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2196808161 |
|
|
Mar 21 01:37:24 PM PDT 24 |
Mar 21 01:38:58 PM PDT 24 |
2394604478 ps |
| T104 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.445460616 |
|
|
Mar 21 01:37:33 PM PDT 24 |
Mar 21 01:39:34 PM PDT 24 |
40253992639 ps |
| T691 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1871405205 |
|
|
Mar 21 01:37:30 PM PDT 24 |
Mar 21 01:37:57 PM PDT 24 |
2884794087 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4263640683 |
|
|
Mar 21 01:37:24 PM PDT 24 |
Mar 21 01:39:10 PM PDT 24 |
4304075585 ps |
| T68 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.818108454 |
|
|
Mar 21 02:36:19 PM PDT 24 |
Mar 21 02:38:45 PM PDT 24 |
59688863326 ps |
| T692 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2948038502 |
|
|
Mar 21 01:37:43 PM PDT 24 |
Mar 21 01:38:06 PM PDT 24 |
14205488341 ps |
| T693 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.994504369 |
|
|
Mar 21 01:37:45 PM PDT 24 |
Mar 21 01:38:05 PM PDT 24 |
1116300706 ps |
| T694 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2917924246 |
|
|
Mar 21 01:37:46 PM PDT 24 |
Mar 21 01:38:00 PM PDT 24 |
167603975 ps |
| T695 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1020739794 |
|
|
Mar 21 02:36:21 PM PDT 24 |
Mar 21 02:36:31 PM PDT 24 |
2498950968 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3391082814 |
|
|
Mar 21 02:36:09 PM PDT 24 |
Mar 21 02:37:07 PM PDT 24 |
4286958029 ps |
| T70 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3747348480 |
|
|
Mar 21 02:36:35 PM PDT 24 |
Mar 21 02:36:44 PM PDT 24 |
170862277 ps |
| T105 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.586911839 |
|
|
Mar 21 02:36:20 PM PDT 24 |
Mar 21 02:36:41 PM PDT 24 |
2288359216 ps |
| T106 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4122882876 |
|
|
Mar 21 02:36:20 PM PDT 24 |
Mar 21 02:36:41 PM PDT 24 |
9989178638 ps |
| T696 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2370671629 |
|
|
Mar 21 01:37:24 PM PDT 24 |
Mar 21 01:37:53 PM PDT 24 |
6414046941 ps |
| T71 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.390275833 |
|
|
Mar 21 01:37:32 PM PDT 24 |
Mar 21 01:37:58 PM PDT 24 |
2783724720 ps |
| T61 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.784694864 |
|
|
Mar 21 02:36:40 PM PDT 24 |
Mar 21 02:39:20 PM PDT 24 |
781765090 ps |
| T72 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3315322923 |
|
|
Mar 21 01:37:22 PM PDT 24 |
Mar 21 01:38:18 PM PDT 24 |
4156287783 ps |
| T697 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2853409214 |
|
|
Mar 21 02:36:38 PM PDT 24 |
Mar 21 02:36:57 PM PDT 24 |
3944549340 ps |
| T698 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1969987392 |
|
|
Mar 21 02:36:21 PM PDT 24 |
Mar 21 02:36:29 PM PDT 24 |
688554955 ps |
| T699 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2947655140 |
|
|
Mar 21 02:36:37 PM PDT 24 |
Mar 21 02:37:00 PM PDT 24 |
4664368249 ps |
| T700 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.659813637 |
|
|
Mar 21 01:37:44 PM PDT 24 |
Mar 21 01:37:53 PM PDT 24 |
629074640 ps |
| T122 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3831015298 |
|
|
Mar 21 01:37:44 PM PDT 24 |
Mar 21 01:39:12 PM PDT 24 |
2975960137 ps |
| T123 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.514352979 |
|
|
Mar 21 02:36:24 PM PDT 24 |
Mar 21 02:37:56 PM PDT 24 |
7447070701 ps |
| T701 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.628406430 |
|
|
Mar 21 01:37:30 PM PDT 24 |
Mar 21 01:37:55 PM PDT 24 |
5095713051 ps |
| T702 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1415401458 |
|
|
Mar 21 01:37:22 PM PDT 24 |
Mar 21 01:37:39 PM PDT 24 |
4928857418 ps |
| T73 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.541657735 |
|
|
Mar 21 02:36:33 PM PDT 24 |
Mar 21 02:36:42 PM PDT 24 |
174590260 ps |
| T703 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1064575444 |
|
|
Mar 21 02:36:20 PM PDT 24 |
Mar 21 02:36:50 PM PDT 24 |
21283147823 ps |
| T74 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.422386895 |
|
|
Mar 21 01:37:30 PM PDT 24 |
Mar 21 01:37:53 PM PDT 24 |
15289604525 ps |
| T704 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2898589994 |
|
|
Mar 21 02:36:24 PM PDT 24 |
Mar 21 02:36:53 PM PDT 24 |
5786541864 ps |
| T118 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1247138603 |
|
|
Mar 21 01:37:47 PM PDT 24 |
Mar 21 01:40:24 PM PDT 24 |
1511069985 ps |
| T75 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2951156155 |
|
|
Mar 21 01:37:33 PM PDT 24 |
Mar 21 01:38:10 PM PDT 24 |
2857774455 ps |
| T705 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2811220214 |
|
|
Mar 21 02:36:11 PM PDT 24 |
Mar 21 02:36:25 PM PDT 24 |
1508764209 ps |
| T76 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3687748065 |
|
|
Mar 21 01:37:39 PM PDT 24 |
Mar 21 01:40:11 PM PDT 24 |
76031646046 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.978801467 |
|
|
Mar 21 02:36:21 PM PDT 24 |
Mar 21 02:38:22 PM PDT 24 |
10345827605 ps |
| T706 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.816800919 |
|
|
Mar 21 02:36:13 PM PDT 24 |
Mar 21 02:39:07 PM PDT 24 |
20235277189 ps |
| T119 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.321226397 |
|
|
Mar 21 01:37:34 PM PDT 24 |
Mar 21 01:40:20 PM PDT 24 |
10493909535 ps |
| T124 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2998454601 |
|
|
Mar 21 02:36:27 PM PDT 24 |
Mar 21 02:38:01 PM PDT 24 |
7791818163 ps |
| T707 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1465085272 |
|
|
Mar 21 02:36:36 PM PDT 24 |
Mar 21 02:37:04 PM PDT 24 |
12494358197 ps |
| T84 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.91886898 |
|
|
Mar 21 01:37:43 PM PDT 24 |
Mar 21 01:37:51 PM PDT 24 |
661584032 ps |
| T107 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3171527338 |
|
|
Mar 21 01:37:35 PM PDT 24 |
Mar 21 01:37:52 PM PDT 24 |
2521230011 ps |
| T112 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2523228487 |
|
|
Mar 21 01:37:33 PM PDT 24 |
Mar 21 01:38:43 PM PDT 24 |
4126923337 ps |
| T120 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.482501873 |
|
|
Mar 21 02:36:27 PM PDT 24 |
Mar 21 02:39:14 PM PDT 24 |
13557186698 ps |
| T708 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2617993102 |
|
|
Mar 21 02:36:32 PM PDT 24 |
Mar 21 02:37:29 PM PDT 24 |
2660916905 ps |
| T709 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1114332956 |
|
|
Mar 21 01:37:31 PM PDT 24 |
Mar 21 01:38:01 PM PDT 24 |
11974916707 ps |
| T710 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4241169623 |
|
|
Mar 21 01:37:37 PM PDT 24 |
Mar 21 01:38:15 PM PDT 24 |
1648896508 ps |
| T711 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3260926350 |
|
|
Mar 21 02:36:14 PM PDT 24 |
Mar 21 02:36:24 PM PDT 24 |
687039316 ps |
| T712 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2249531264 |
|
|
Mar 21 02:36:13 PM PDT 24 |
Mar 21 02:36:24 PM PDT 24 |
688196918 ps |
| T713 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3323146667 |
|
|
Mar 21 01:37:46 PM PDT 24 |
Mar 21 01:38:06 PM PDT 24 |
1685439735 ps |
| T714 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1527021545 |
|
|
Mar 21 02:36:09 PM PDT 24 |
Mar 21 02:36:28 PM PDT 24 |
989178787 ps |
| T715 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3314062462 |
|
|
Mar 21 02:36:35 PM PDT 24 |
Mar 21 02:36:53 PM PDT 24 |
5123950265 ps |
| T716 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1812213009 |
|
|
Mar 21 01:37:33 PM PDT 24 |
Mar 21 01:37:52 PM PDT 24 |
1234497085 ps |
| T717 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1351031511 |
|
|
Mar 21 02:36:40 PM PDT 24 |
Mar 21 02:37:04 PM PDT 24 |
11190607961 ps |
| T85 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2401542082 |
|
|
Mar 21 01:37:34 PM PDT 24 |
Mar 21 01:39:12 PM PDT 24 |
41611269331 ps |
| T86 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1686774125 |
|
|
Mar 21 01:37:47 PM PDT 24 |
Mar 21 01:39:00 PM PDT 24 |
12764535667 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3853853455 |
|
|
Mar 21 02:36:11 PM PDT 24 |
Mar 21 02:36:48 PM PDT 24 |
718514455 ps |
| T92 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.980833510 |
|
|
Mar 21 02:36:36 PM PDT 24 |
Mar 21 02:37:00 PM PDT 24 |
2760444302 ps |
| T718 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1190285437 |
|
|
Mar 21 01:37:44 PM PDT 24 |
Mar 21 01:38:04 PM PDT 24 |
7475635590 ps |
| T719 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3089078889 |
|
|
Mar 21 02:36:33 PM PDT 24 |
Mar 21 02:39:55 PM PDT 24 |
25598170273 ps |
| T115 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2859450954 |
|
|
Mar 21 02:36:36 PM PDT 24 |
Mar 21 02:37:57 PM PDT 24 |
954745512 ps |
| T720 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2477677736 |
|
|
Mar 21 02:36:13 PM PDT 24 |
Mar 21 02:36:31 PM PDT 24 |
680032547 ps |
| T721 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2997807689 |
|
|
Mar 21 02:36:31 PM PDT 24 |
Mar 21 02:37:01 PM PDT 24 |
13512791234 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1682440628 |
|
|
Mar 21 02:36:10 PM PDT 24 |
Mar 21 02:37:48 PM PDT 24 |
18395643068 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2191240736 |
|
|
Mar 21 01:37:22 PM PDT 24 |
Mar 21 01:39:33 PM PDT 24 |
49428312186 ps |
| T722 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2319034065 |
|
|
Mar 21 01:37:34 PM PDT 24 |
Mar 21 01:39:00 PM PDT 24 |
16507487254 ps |
| T91 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2769223930 |
|
|
Mar 21 01:37:43 PM PDT 24 |
Mar 21 01:38:22 PM PDT 24 |
691993990 ps |
| T723 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1476580105 |
|
|
Mar 21 01:37:24 PM PDT 24 |
Mar 21 01:37:47 PM PDT 24 |
10023640774 ps |
| T724 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1917610418 |
|
|
Mar 21 01:37:24 PM PDT 24 |
Mar 21 01:37:49 PM PDT 24 |
7574943386 ps |
| T725 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1843111751 |
|
|
Mar 21 01:37:46 PM PDT 24 |
Mar 21 01:39:18 PM PDT 24 |
17131850627 ps |
| T726 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3698008923 |
|
|
Mar 21 01:37:33 PM PDT 24 |
Mar 21 01:37:57 PM PDT 24 |
7861041599 ps |
| T727 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3526820806 |
|
|
Mar 21 02:36:09 PM PDT 24 |
Mar 21 02:36:25 PM PDT 24 |
1582925048 ps |
| T728 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1029879018 |
|
|
Mar 21 01:37:37 PM PDT 24 |
Mar 21 01:38:05 PM PDT 24 |
14090023312 ps |
| T729 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4065266506 |
|
|
Mar 21 02:36:36 PM PDT 24 |
Mar 21 02:37:57 PM PDT 24 |
3645879753 ps |
| T125 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3283030765 |
|
|
Mar 21 02:36:22 PM PDT 24 |
Mar 21 02:37:43 PM PDT 24 |
986688885 ps |
| T730 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2627203035 |
|
|
Mar 21 02:36:34 PM PDT 24 |
Mar 21 02:36:58 PM PDT 24 |
1646178832 ps |
| T731 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2813273686 |
|
|
Mar 21 02:36:22 PM PDT 24 |
Mar 21 02:36:54 PM PDT 24 |
16925490734 ps |
| T732 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.53442963 |
|
|
Mar 21 01:37:43 PM PDT 24 |
Mar 21 01:39:05 PM PDT 24 |
236279892 ps |
| T733 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.378863565 |
|
|
Mar 21 01:37:48 PM PDT 24 |
Mar 21 01:38:21 PM PDT 24 |
15840180667 ps |
| T734 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1002466543 |
|
|
Mar 21 02:36:20 PM PDT 24 |
Mar 21 02:36:33 PM PDT 24 |
612768070 ps |
| T735 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.976004536 |
|
|
Mar 21 02:36:22 PM PDT 24 |
Mar 21 02:39:49 PM PDT 24 |
24703054991 ps |
| T736 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.215979330 |
|
|
Mar 21 01:37:44 PM PDT 24 |
Mar 21 01:38:23 PM PDT 24 |
4368858389 ps |
| T93 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.893264872 |
|
|
Mar 21 01:37:25 PM PDT 24 |
Mar 21 01:38:47 PM PDT 24 |
73143346647 ps |
| T737 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.553758112 |
|
|
Mar 21 01:37:37 PM PDT 24 |
Mar 21 01:38:04 PM PDT 24 |
7237389779 ps |
| T738 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2217281885 |
|
|
Mar 21 01:37:45 PM PDT 24 |
Mar 21 01:39:38 PM PDT 24 |
13136335655 ps |
| T739 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2435055899 |
|
|
Mar 21 01:37:21 PM PDT 24 |
Mar 21 01:37:44 PM PDT 24 |
16360335893 ps |
| T129 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3635832020 |
|
|
Mar 21 01:37:45 PM PDT 24 |
Mar 21 01:40:33 PM PDT 24 |
10113936505 ps |
| T121 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.440401972 |
|
|
Mar 21 01:37:34 PM PDT 24 |
Mar 21 01:39:07 PM PDT 24 |
2172121099 ps |
| T740 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3002616120 |
|
|
Mar 21 02:36:17 PM PDT 24 |
Mar 21 02:36:27 PM PDT 24 |
636698022 ps |
| T741 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4098012544 |
|
|
Mar 21 02:36:09 PM PDT 24 |
Mar 21 02:36:19 PM PDT 24 |
1101648307 ps |
| T742 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1945274754 |
|
|
Mar 21 01:37:37 PM PDT 24 |
Mar 21 01:37:52 PM PDT 24 |
4274712485 ps |
| T743 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3270155866 |
|
|
Mar 21 02:36:29 PM PDT 24 |
Mar 21 02:36:44 PM PDT 24 |
948544971 ps |
| T744 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2958036228 |
|
|
Mar 21 02:36:08 PM PDT 24 |
Mar 21 02:36:26 PM PDT 24 |
5799851328 ps |
| T745 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2357267923 |
|
|
Mar 21 01:37:36 PM PDT 24 |
Mar 21 01:37:47 PM PDT 24 |
1865355557 ps |
| T746 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2111193640 |
|
|
Mar 21 01:37:45 PM PDT 24 |
Mar 21 01:37:59 PM PDT 24 |
174259635 ps |
| T747 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1358214094 |
|
|
Mar 21 02:36:10 PM PDT 24 |
Mar 21 02:36:44 PM PDT 24 |
13655975239 ps |
| T748 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3635426641 |
|
|
Mar 21 01:37:31 PM PDT 24 |
Mar 21 01:37:49 PM PDT 24 |
1483759643 ps |
| T749 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3891126136 |
|
|
Mar 21 02:36:13 PM PDT 24 |
Mar 21 02:36:35 PM PDT 24 |
16452217544 ps |
| T750 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2872052270 |
|
|
Mar 21 02:36:22 PM PDT 24 |
Mar 21 02:38:04 PM PDT 24 |
10830000314 ps |
| T751 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2175385679 |
|
|
Mar 21 01:37:48 PM PDT 24 |
Mar 21 01:37:57 PM PDT 24 |
182104800 ps |
| T752 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4270305693 |
|
|
Mar 21 01:37:39 PM PDT 24 |
Mar 21 01:38:11 PM PDT 24 |
4037114929 ps |
| T753 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1543598368 |
|
|
Mar 21 02:36:28 PM PDT 24 |
Mar 21 02:37:01 PM PDT 24 |
46521531717 ps |
| T754 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1522377235 |
|
|
Mar 21 01:37:34 PM PDT 24 |
Mar 21 01:37:59 PM PDT 24 |
17808644935 ps |
| T755 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1502726605 |
|
|
Mar 21 01:37:23 PM PDT 24 |
Mar 21 01:37:41 PM PDT 24 |
1406954795 ps |
| T756 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1416012509 |
|
|
Mar 21 02:36:39 PM PDT 24 |
Mar 21 02:38:11 PM PDT 24 |
6955635757 ps |