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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 96.97 92.65 97.88 100.00 98.36 98.04 99.07


Total test records in report: 934
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T757 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2700730399 Mar 21 02:36:11 PM PDT 24 Mar 21 02:36:20 PM PDT 24 174169381 ps
T758 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.317507442 Mar 21 02:36:20 PM PDT 24 Mar 21 02:36:49 PM PDT 24 4006761446 ps
T759 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4117089351 Mar 21 01:37:45 PM PDT 24 Mar 21 01:38:14 PM PDT 24 13793231751 ps
T760 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2398099692 Mar 21 02:36:36 PM PDT 24 Mar 21 02:36:58 PM PDT 24 2167407113 ps
T761 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.113191605 Mar 21 01:37:37 PM PDT 24 Mar 21 01:37:49 PM PDT 24 590629908 ps
T762 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3052921774 Mar 21 02:36:20 PM PDT 24 Mar 21 02:37:42 PM PDT 24 948065587 ps
T763 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.341163285 Mar 21 01:37:31 PM PDT 24 Mar 21 01:37:43 PM PDT 24 3271248569 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3463085439 Mar 21 02:36:20 PM PDT 24 Mar 21 02:38:01 PM PDT 24 3828046045 ps
T764 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.682344566 Mar 21 02:36:38 PM PDT 24 Mar 21 02:37:04 PM PDT 24 13683941757 ps
T765 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.56696894 Mar 21 02:36:22 PM PDT 24 Mar 21 02:38:56 PM PDT 24 95690315367 ps
T766 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2222775978 Mar 21 01:37:30 PM PDT 24 Mar 21 01:38:01 PM PDT 24 3760602207 ps
T767 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1021309602 Mar 21 02:36:36 PM PDT 24 Mar 21 02:36:49 PM PDT 24 2631034275 ps
T768 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.678796028 Mar 21 01:37:43 PM PDT 24 Mar 21 01:38:16 PM PDT 24 17504200753 ps
T769 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2751746984 Mar 21 02:36:17 PM PDT 24 Mar 21 02:36:27 PM PDT 24 635046289 ps
T770 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.138397180 Mar 21 01:37:33 PM PDT 24 Mar 21 01:39:18 PM PDT 24 24574381247 ps
T771 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1760663137 Mar 21 01:37:33 PM PDT 24 Mar 21 01:37:47 PM PDT 24 751311847 ps
T772 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2740738856 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:49 PM PDT 24 14334670351 ps
T773 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3639289109 Mar 21 02:36:12 PM PDT 24 Mar 21 02:36:22 PM PDT 24 504129558 ps
T774 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2972787205 Mar 21 02:36:35 PM PDT 24 Mar 21 02:36:45 PM PDT 24 179667744 ps
T775 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3776475592 Mar 21 01:37:26 PM PDT 24 Mar 21 01:37:36 PM PDT 24 1076372671 ps
T776 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3056535241 Mar 21 02:36:32 PM PDT 24 Mar 21 02:36:57 PM PDT 24 22399443615 ps
T777 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1120226352 Mar 21 02:36:13 PM PDT 24 Mar 21 02:36:26 PM PDT 24 4575120138 ps
T778 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3599800742 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:51 PM PDT 24 3831647681 ps
T779 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.41529584 Mar 21 02:36:13 PM PDT 24 Mar 21 02:36:45 PM PDT 24 16417272967 ps
T780 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2814989139 Mar 21 01:37:33 PM PDT 24 Mar 21 01:37:55 PM PDT 24 2196528763 ps
T781 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3591392966 Mar 21 01:37:39 PM PDT 24 Mar 21 01:38:10 PM PDT 24 9819835709 ps
T782 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4138588213 Mar 21 01:37:30 PM PDT 24 Mar 21 01:37:51 PM PDT 24 7603387015 ps
T783 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2841085901 Mar 21 02:36:29 PM PDT 24 Mar 21 02:36:58 PM PDT 24 3415129773 ps
T784 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.837741887 Mar 21 02:36:38 PM PDT 24 Mar 21 02:37:11 PM PDT 24 3914770772 ps
T785 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1318021521 Mar 21 02:36:38 PM PDT 24 Mar 21 02:37:11 PM PDT 24 13909598600 ps
T786 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.861602000 Mar 21 01:37:44 PM PDT 24 Mar 21 01:38:00 PM PDT 24 1028190903 ps
T787 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.848219377 Mar 21 01:37:32 PM PDT 24 Mar 21 01:37:54 PM PDT 24 5145714462 ps
T788 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4102067300 Mar 21 02:36:29 PM PDT 24 Mar 21 02:36:59 PM PDT 24 3621059824 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2958896521 Mar 21 02:36:09 PM PDT 24 Mar 21 02:38:52 PM PDT 24 1286783588 ps
T789 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1628276093 Mar 21 02:36:23 PM PDT 24 Mar 21 02:36:33 PM PDT 24 390411876 ps
T790 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2645057067 Mar 21 02:36:10 PM PDT 24 Mar 21 02:36:47 PM PDT 24 3757960187 ps
T791 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.658001300 Mar 21 02:36:21 PM PDT 24 Mar 21 02:37:37 PM PDT 24 25815360675 ps
T792 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2563643908 Mar 21 01:37:43 PM PDT 24 Mar 21 01:37:52 PM PDT 24 2355079399 ps
T793 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3338658797 Mar 21 01:37:36 PM PDT 24 Mar 21 01:38:09 PM PDT 24 6965798228 ps
T794 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3423023556 Mar 21 02:36:10 PM PDT 24 Mar 21 02:36:28 PM PDT 24 1610234784 ps
T795 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3450369484 Mar 21 01:37:37 PM PDT 24 Mar 21 01:39:13 PM PDT 24 2985812425 ps
T796 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4147351639 Mar 21 01:37:33 PM PDT 24 Mar 21 01:37:54 PM PDT 24 2143662085 ps
T797 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3207540278 Mar 21 02:36:30 PM PDT 24 Mar 21 02:37:58 PM PDT 24 17181745168 ps
T798 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.593540489 Mar 21 02:36:34 PM PDT 24 Mar 21 02:36:45 PM PDT 24 363883227 ps
T799 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2705745381 Mar 21 02:36:13 PM PDT 24 Mar 21 02:38:12 PM PDT 24 13147623247 ps
T800 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2891724210 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:52 PM PDT 24 3140906215 ps
T801 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4234011269 Mar 21 01:37:28 PM PDT 24 Mar 21 01:37:42 PM PDT 24 1451383409 ps
T802 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.842534830 Mar 21 02:36:39 PM PDT 24 Mar 21 02:37:13 PM PDT 24 15473263026 ps
T803 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.107854468 Mar 21 02:36:33 PM PDT 24 Mar 21 02:37:09 PM PDT 24 8035740430 ps
T804 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4187929284 Mar 21 02:36:34 PM PDT 24 Mar 21 02:37:04 PM PDT 24 19471135219 ps
T805 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2156061191 Mar 21 02:36:35 PM PDT 24 Mar 21 02:36:44 PM PDT 24 688247863 ps
T126 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1717409541 Mar 21 02:36:17 PM PDT 24 Mar 21 02:39:17 PM PDT 24 10361628292 ps
T806 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.785667160 Mar 21 02:36:34 PM PDT 24 Mar 21 02:36:56 PM PDT 24 2056645450 ps
T807 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3776365760 Mar 21 01:37:31 PM PDT 24 Mar 21 01:37:41 PM PDT 24 1032330919 ps
T808 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.778717341 Mar 21 01:37:32 PM PDT 24 Mar 21 01:37:49 PM PDT 24 1628525223 ps
T809 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2939764979 Mar 21 02:36:08 PM PDT 24 Mar 21 02:36:21 PM PDT 24 3405681509 ps
T810 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1261834946 Mar 21 02:36:36 PM PDT 24 Mar 21 02:37:03 PM PDT 24 5295923720 ps
T811 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2743818301 Mar 21 01:37:23 PM PDT 24 Mar 21 01:40:29 PM PDT 24 110463529172 ps
T812 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1886962609 Mar 21 02:36:11 PM PDT 24 Mar 21 02:36:23 PM PDT 24 982790736 ps
T813 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3237360353 Mar 21 01:37:33 PM PDT 24 Mar 21 01:37:43 PM PDT 24 249272677 ps
T814 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3538373712 Mar 21 01:37:34 PM PDT 24 Mar 21 01:37:44 PM PDT 24 257443168 ps
T815 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.801748192 Mar 21 02:36:36 PM PDT 24 Mar 21 02:37:58 PM PDT 24 273383295 ps
T816 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1254989587 Mar 21 01:37:23 PM PDT 24 Mar 21 01:37:56 PM PDT 24 8046179613 ps
T817 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2087174853 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:55 PM PDT 24 15039953025 ps
T818 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.433090651 Mar 21 02:36:27 PM PDT 24 Mar 21 02:36:36 PM PDT 24 345961594 ps
T819 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1226510439 Mar 21 02:36:10 PM PDT 24 Mar 21 02:36:34 PM PDT 24 5534043687 ps
T820 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2639606169 Mar 21 01:37:44 PM PDT 24 Mar 21 01:37:52 PM PDT 24 338358017 ps
T821 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4194410168 Mar 21 02:36:26 PM PDT 24 Mar 21 02:36:58 PM PDT 24 12723816534 ps
T822 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1277163362 Mar 21 01:37:31 PM PDT 24 Mar 21 01:37:47 PM PDT 24 2663139296 ps
T823 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3390709275 Mar 21 02:36:17 PM PDT 24 Mar 21 02:36:27 PM PDT 24 331965867 ps
T824 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.752374723 Mar 21 02:36:37 PM PDT 24 Mar 21 02:37:02 PM PDT 24 4232910082 ps
T825 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1656527385 Mar 21 01:37:33 PM PDT 24 Mar 21 01:37:52 PM PDT 24 7484766660 ps
T826 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4072134670 Mar 21 02:36:21 PM PDT 24 Mar 21 02:36:33 PM PDT 24 434373289 ps
T827 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2378556883 Mar 21 02:36:12 PM PDT 24 Mar 21 02:36:47 PM PDT 24 3886302218 ps
T828 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.569510239 Mar 21 01:37:32 PM PDT 24 Mar 21 01:38:56 PM PDT 24 305798509 ps
T829 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2311012730 Mar 21 01:37:31 PM PDT 24 Mar 21 01:38:59 PM PDT 24 3658046068 ps
T128 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1775777082 Mar 21 02:36:11 PM PDT 24 Mar 21 02:39:05 PM PDT 24 7111687209 ps
T830 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1714256088 Mar 21 01:37:44 PM PDT 24 Mar 21 01:38:14 PM PDT 24 3758432357 ps
T831 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.963092462 Mar 21 01:37:34 PM PDT 24 Mar 21 01:37:59 PM PDT 24 2399826113 ps
T832 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2885688574 Mar 21 02:36:22 PM PDT 24 Mar 21 02:38:59 PM PDT 24 1218854532 ps
T833 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3422307837 Mar 21 01:37:37 PM PDT 24 Mar 21 01:37:52 PM PDT 24 1123887720 ps
T834 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.887209315 Mar 21 01:37:28 PM PDT 24 Mar 21 01:37:58 PM PDT 24 14550444763 ps
T835 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.994958339 Mar 21 02:36:38 PM PDT 24 Mar 21 02:37:10 PM PDT 24 15444627835 ps
T836 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1528171509 Mar 21 01:37:23 PM PDT 24 Mar 21 01:37:38 PM PDT 24 1084990227 ps
T837 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3665552129 Mar 21 02:36:34 PM PDT 24 Mar 21 02:39:01 PM PDT 24 14817018371 ps
T838 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3917462162 Mar 21 02:36:34 PM PDT 24 Mar 21 02:36:43 PM PDT 24 2060016206 ps
T839 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.248483979 Mar 21 02:36:36 PM PDT 24 Mar 21 02:38:25 PM PDT 24 24298565779 ps
T840 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3290004776 Mar 21 02:36:10 PM PDT 24 Mar 21 02:36:24 PM PDT 24 5103414607 ps
T841 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2869504541 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:54 PM PDT 24 4050845517 ps
T842 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1849320285 Mar 21 01:37:38 PM PDT 24 Mar 21 01:40:24 PM PDT 24 3207708310 ps
T843 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3086613247 Mar 21 02:36:09 PM PDT 24 Mar 21 02:36:19 PM PDT 24 1831307865 ps
T127 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.190705838 Mar 21 01:37:33 PM PDT 24 Mar 21 01:40:11 PM PDT 24 309677342 ps
T844 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2607919607 Mar 21 01:37:32 PM PDT 24 Mar 21 01:37:44 PM PDT 24 203808039 ps
T845 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1737999959 Mar 21 01:37:33 PM PDT 24 Mar 21 01:38:09 PM PDT 24 18224241685 ps
T846 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1050848195 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:43 PM PDT 24 2040000945 ps
T847 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.861795272 Mar 21 02:36:34 PM PDT 24 Mar 21 02:39:14 PM PDT 24 7697511029 ps
T848 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1219384541 Mar 21 02:36:35 PM PDT 24 Mar 21 02:36:53 PM PDT 24 1345130216 ps
T849 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3637673110 Mar 21 02:36:34 PM PDT 24 Mar 21 02:37:02 PM PDT 24 2300931535 ps
T850 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1724429124 Mar 21 01:37:46 PM PDT 24 Mar 21 01:38:10 PM PDT 24 34061240224 ps
T851 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2301058415 Mar 21 01:37:45 PM PDT 24 Mar 21 01:37:54 PM PDT 24 167426174 ps
T852 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.103962334 Mar 21 01:37:21 PM PDT 24 Mar 21 01:37:41 PM PDT 24 1814640897 ps
T853 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3311207514 Mar 21 02:36:09 PM PDT 24 Mar 21 02:36:46 PM PDT 24 18545614053 ps
T854 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2313428921 Mar 21 02:36:10 PM PDT 24 Mar 21 02:36:41 PM PDT 24 8029720114 ps
T855 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2396486044 Mar 21 01:37:21 PM PDT 24 Mar 21 01:37:46 PM PDT 24 14466911677 ps
T856 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3600935697 Mar 21 01:37:30 PM PDT 24 Mar 21 01:38:01 PM PDT 24 6097647069 ps
T857 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4041780429 Mar 21 01:37:43 PM PDT 24 Mar 21 01:38:02 PM PDT 24 905664887 ps
T858 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.858548132 Mar 21 01:37:24 PM PDT 24 Mar 21 01:37:55 PM PDT 24 11168213866 ps
T859 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2274404385 Mar 21 02:36:27 PM PDT 24 Mar 21 02:36:36 PM PDT 24 338981419 ps
T860 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3208009658 Mar 21 02:36:22 PM PDT 24 Mar 21 02:36:30 PM PDT 24 687717380 ps
T861 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.533535627 Mar 21 02:36:10 PM PDT 24 Mar 21 02:36:43 PM PDT 24 17774070788 ps
T862 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.558887786 Mar 21 01:37:37 PM PDT 24 Mar 21 01:38:00 PM PDT 24 2132811435 ps
T863 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2427197521 Mar 21 01:37:32 PM PDT 24 Mar 21 01:37:49 PM PDT 24 5070021037 ps
T864 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2042052708 Mar 21 02:36:33 PM PDT 24 Mar 21 02:38:01 PM PDT 24 4863478736 ps
T865 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.866937973 Mar 21 01:37:34 PM PDT 24 Mar 21 01:38:06 PM PDT 24 7689000613 ps
T866 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1604612269 Mar 21 01:37:32 PM PDT 24 Mar 21 01:40:09 PM PDT 24 67170178032 ps
T867 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3578186243 Mar 21 01:37:44 PM PDT 24 Mar 21 01:39:43 PM PDT 24 100976790394 ps
T868 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3383753230 Mar 21 02:36:08 PM PDT 24 Mar 21 02:36:30 PM PDT 24 15895167400 ps
T869 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3301205038 Mar 21 02:36:11 PM PDT 24 Mar 21 02:36:45 PM PDT 24 8696241137 ps
T870 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3302688935 Mar 21 01:37:36 PM PDT 24 Mar 21 01:38:06 PM PDT 24 3741173871 ps
T871 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2313657114 Mar 21 01:37:46 PM PDT 24 Mar 21 01:40:27 PM PDT 24 972488918 ps
T872 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4127220430 Mar 21 02:36:38 PM PDT 24 Mar 21 02:38:12 PM PDT 24 8138830636 ps
T873 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4278735937 Mar 21 02:36:09 PM PDT 24 Mar 21 02:36:18 PM PDT 24 719420908 ps
T874 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2281862124 Mar 21 02:36:08 PM PDT 24 Mar 21 02:36:16 PM PDT 24 174492763 ps
T875 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3097133352 Mar 21 02:36:21 PM PDT 24 Mar 21 02:36:55 PM PDT 24 7090946862 ps
T876 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1693967287 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:35 PM PDT 24 1540550996 ps
T877 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2377076597 Mar 21 02:36:28 PM PDT 24 Mar 21 02:37:03 PM PDT 24 8096621944 ps
T878 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3666746062 Mar 21 01:37:44 PM PDT 24 Mar 21 01:39:44 PM PDT 24 10863079641 ps
T879 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.199765390 Mar 21 02:36:13 PM PDT 24 Mar 21 02:36:27 PM PDT 24 8227491067 ps
T880 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1205599166 Mar 21 01:37:33 PM PDT 24 Mar 21 01:37:46 PM PDT 24 2380323866 ps
T881 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4028742579 Mar 21 01:37:36 PM PDT 24 Mar 21 01:37:56 PM PDT 24 2008317117 ps
T882 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3104377591 Mar 21 01:37:22 PM PDT 24 Mar 21 01:38:52 PM PDT 24 3062130948 ps
T883 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3070871192 Mar 21 02:36:36 PM PDT 24 Mar 21 02:38:06 PM PDT 24 1263167858 ps
T884 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.331901800 Mar 21 02:36:08 PM PDT 24 Mar 21 02:37:41 PM PDT 24 5840270113 ps
T885 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.426990706 Mar 21 01:37:31 PM PDT 24 Mar 21 01:37:53 PM PDT 24 4830348153 ps
T886 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3017114522 Mar 21 01:37:33 PM PDT 24 Mar 21 01:37:53 PM PDT 24 9670954824 ps
T887 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1281632538 Mar 21 02:36:30 PM PDT 24 Mar 21 02:37:00 PM PDT 24 3471276393 ps
T888 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3582722516 Mar 21 02:36:27 PM PDT 24 Mar 21 02:36:36 PM PDT 24 338729600 ps
T889 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1638188364 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:48 PM PDT 24 2894541862 ps
T890 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.532174254 Mar 21 01:37:46 PM PDT 24 Mar 21 01:38:10 PM PDT 24 8521316499 ps
T891 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2587208630 Mar 21 02:36:37 PM PDT 24 Mar 21 02:38:48 PM PDT 24 35708606914 ps
T892 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.29044926 Mar 21 01:37:44 PM PDT 24 Mar 21 01:38:00 PM PDT 24 1237655825 ps
T893 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1308095329 Mar 21 02:36:34 PM PDT 24 Mar 21 02:36:43 PM PDT 24 743628425 ps
T894 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3532329843 Mar 21 01:37:29 PM PDT 24 Mar 21 01:37:46 PM PDT 24 17788203162 ps
T895 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.647374841 Mar 21 01:37:23 PM PDT 24 Mar 21 01:37:46 PM PDT 24 2328454202 ps
T896 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.294149971 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:53 PM PDT 24 11215036640 ps
T897 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2811304297 Mar 21 01:37:37 PM PDT 24 Mar 21 01:39:00 PM PDT 24 951567485 ps
T898 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2365375219 Mar 21 01:37:33 PM PDT 24 Mar 21 01:40:54 PM PDT 24 163802393609 ps
T899 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.173155750 Mar 21 01:37:34 PM PDT 24 Mar 21 01:37:42 PM PDT 24 661427857 ps
T900 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2792394818 Mar 21 02:36:36 PM PDT 24 Mar 21 02:38:12 PM PDT 24 27512453021 ps
T901 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2879896367 Mar 21 02:36:32 PM PDT 24 Mar 21 02:36:50 PM PDT 24 943353387 ps
T902 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2933874794 Mar 21 01:37:39 PM PDT 24 Mar 21 01:37:59 PM PDT 24 4224168193 ps
T903 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.579357574 Mar 21 02:36:27 PM PDT 24 Mar 21 02:36:56 PM PDT 24 7509407313 ps
T904 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.297333611 Mar 21 01:37:24 PM PDT 24 Mar 21 01:37:46 PM PDT 24 2130247813 ps
T905 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2805010887 Mar 21 02:36:37 PM PDT 24 Mar 21 02:36:49 PM PDT 24 338876209 ps
T906 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1722363955 Mar 21 01:37:35 PM PDT 24 Mar 21 01:38:04 PM PDT 24 14714301393 ps
T907 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1211406160 Mar 21 01:37:46 PM PDT 24 Mar 21 01:40:30 PM PDT 24 22400027050 ps
T908 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3130238660 Mar 21 02:36:21 PM PDT 24 Mar 21 02:36:48 PM PDT 24 6161265908 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1834566661 Mar 21 02:36:22 PM PDT 24 Mar 21 02:36:37 PM PDT 24 3929505098 ps
T909 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.288374655 Mar 21 02:36:08 PM PDT 24 Mar 21 02:36:45 PM PDT 24 4436414337 ps
T910 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3274775700 Mar 21 02:36:27 PM PDT 24 Mar 21 02:36:45 PM PDT 24 2371340695 ps
T911 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2288096572 Mar 21 01:37:22 PM PDT 24 Mar 21 01:37:47 PM PDT 24 2816592106 ps
T912 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2149342295 Mar 21 02:36:09 PM PDT 24 Mar 21 02:36:44 PM PDT 24 12588109531 ps
T913 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3306192601 Mar 21 01:37:28 PM PDT 24 Mar 21 01:37:52 PM PDT 24 11580739416 ps
T914 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4130429633 Mar 21 02:36:35 PM PDT 24 Mar 21 02:36:59 PM PDT 24 8201283174 ps
T915 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3885536522 Mar 21 02:36:35 PM PDT 24 Mar 21 02:38:36 PM PDT 24 81078806878 ps
T916 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2857803875 Mar 21 01:37:45 PM PDT 24 Mar 21 01:38:07 PM PDT 24 9271313609 ps
T917 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2796325504 Mar 21 02:36:32 PM PDT 24 Mar 21 02:37:03 PM PDT 24 3126171882 ps
T918 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.486126076 Mar 21 01:37:35 PM PDT 24 Mar 21 01:39:00 PM PDT 24 1973252628 ps
T919 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1608669388 Mar 21 01:37:34 PM PDT 24 Mar 21 01:38:00 PM PDT 24 5440928538 ps
T920 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.847630392 Mar 21 02:36:36 PM PDT 24 Mar 21 02:36:47 PM PDT 24 1098451305 ps
T921 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3863576017 Mar 21 01:37:31 PM PDT 24 Mar 21 01:38:52 PM PDT 24 466889603 ps
T922 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1115486481 Mar 21 02:36:21 PM PDT 24 Mar 21 02:39:26 PM PDT 24 21698374484 ps
T923 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1375779110 Mar 21 01:37:31 PM PDT 24 Mar 21 01:37:53 PM PDT 24 1611162500 ps
T924 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1227134264 Mar 21 02:36:22 PM PDT 24 Mar 21 02:36:50 PM PDT 24 6446348162 ps
T925 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1862423137 Mar 21 02:36:28 PM PDT 24 Mar 21 02:36:51 PM PDT 24 1560311345 ps
T926 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4294777222 Mar 21 01:37:32 PM PDT 24 Mar 21 01:40:27 PM PDT 24 4570691866 ps
T927 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2210103035 Mar 21 02:36:20 PM PDT 24 Mar 21 02:36:41 PM PDT 24 2842250130 ps
T928 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3180184914 Mar 21 02:36:11 PM PDT 24 Mar 21 02:36:23 PM PDT 24 506573814 ps
T929 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.931034840 Mar 21 01:37:34 PM PDT 24 Mar 21 01:38:01 PM PDT 24 5677147645 ps
T930 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2275516626 Mar 21 02:36:22 PM PDT 24 Mar 21 02:36:31 PM PDT 24 332444806 ps
T931 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1448165921 Mar 21 02:36:35 PM PDT 24 Mar 21 02:37:01 PM PDT 24 2894424843 ps
T932 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.815097695 Mar 21 02:36:12 PM PDT 24 Mar 21 02:36:24 PM PDT 24 363334775 ps
T933 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2711065522 Mar 21 02:36:35 PM PDT 24 Mar 21 02:36:50 PM PDT 24 1917092925 ps
T934 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.501841152 Mar 21 01:37:47 PM PDT 24 Mar 21 01:38:08 PM PDT 24 2098496394 ps

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.150117613
Short name T10
Test name
Test status
Simulation time 119930773958 ps
CPU time 4392.82 seconds
Started Mar 21 01:36:40 PM PDT 24
Finished Mar 21 02:49:53 PM PDT 24
Peak memory 229912 kb
Host smart-70d477e4-3cea-47d1-bb1e-d2caf82d8cc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150117613 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.150117613
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1653246464
Short name T2
Test name
Test status
Simulation time 2042089459 ps
CPU time 145.19 seconds
Started Mar 21 03:21:00 PM PDT 24
Finished Mar 21 03:23:25 PM PDT 24
Peak memory 228704 kb
Host smart-d6043fbb-4158-47ba-9851-f43d17102c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653246464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1653246464
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1488659195
Short name T50
Test name
Test status
Simulation time 110663138790 ps
CPU time 303.5 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:41:17 PM PDT 24
Peak memory 212368 kb
Host smart-b3cfd825-1f35-4a1c-b910-2d163ba002cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488659195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1488659195
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3002771585
Short name T19
Test name
Test status
Simulation time 102963427053 ps
CPU time 280.5 seconds
Started Mar 21 03:21:42 PM PDT 24
Finished Mar 21 03:26:23 PM PDT 24
Peak memory 237612 kb
Host smart-a9b5f5d2-e76d-4a09-8666-946325702145
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002771585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3002771585
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1247138603
Short name T118
Test name
Test status
Simulation time 1511069985 ps
CPU time 156.36 seconds
Started Mar 21 01:37:47 PM PDT 24
Finished Mar 21 01:40:24 PM PDT 24
Peak memory 213820 kb
Host smart-c4c27572-98fd-45ff-a67d-8929f58f2d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247138603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1247138603
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2406688222
Short name T40
Test name
Test status
Simulation time 584598345 ps
CPU time 54.86 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:21:44 PM PDT 24
Peak memory 237668 kb
Host smart-5ce2b61c-a354-44d0-8127-74f0196b373b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406688222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2406688222
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2320442449
Short name T12
Test name
Test status
Simulation time 29698190974 ps
CPU time 1147.43 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:55:21 PM PDT 24
Peak memory 227364 kb
Host smart-2a74b358-2870-4aef-99d6-71f4ebb7b159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320442449 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2320442449
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3747348480
Short name T70
Test name
Test status
Simulation time 170862277 ps
CPU time 8.23 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:36:44 PM PDT 24
Peak memory 211332 kb
Host smart-5280551b-4246-49df-8116-3e4d62f83959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747348480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3747348480
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4143642548
Short name T7
Test name
Test status
Simulation time 1193767265 ps
CPU time 16.91 seconds
Started Mar 21 03:20:58 PM PDT 24
Finished Mar 21 03:21:15 PM PDT 24
Peak memory 211676 kb
Host smart-a723556c-e46f-4dc3-964d-4d7595fe7d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143642548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4143642548
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2859450954
Short name T115
Test name
Test status
Simulation time 954745512 ps
CPU time 81.06 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:37:57 PM PDT 24
Peak memory 213628 kb
Host smart-16a7e7f0-58b3-4265-84df-ccd7b4b642d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859450954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2859450954
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4082393730
Short name T65
Test name
Test status
Simulation time 6129278107 ps
CPU time 13.02 seconds
Started Mar 21 01:35:55 PM PDT 24
Finished Mar 21 01:36:08 PM PDT 24
Peak memory 210860 kb
Host smart-517c58c0-56f3-4726-9429-1dcd3fc2ffa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082393730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4082393730
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3734849546
Short name T58
Test name
Test status
Simulation time 44428043614 ps
CPU time 9745.9 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 04:18:37 PM PDT 24
Peak memory 228036 kb
Host smart-81847810-c8f0-4aef-847a-4b5fbf647459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734849546 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3734849546
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1267401314
Short name T163
Test name
Test status
Simulation time 1013378561 ps
CPU time 15.69 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:21:05 PM PDT 24
Peak memory 211528 kb
Host smart-536b5621-2fa6-4a49-a034-0e7918870fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267401314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1267401314
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2791841434
Short name T272
Test name
Test status
Simulation time 520922484 ps
CPU time 9.64 seconds
Started Mar 21 01:35:49 PM PDT 24
Finished Mar 21 01:35:59 PM PDT 24
Peak memory 211476 kb
Host smart-663fc584-9db8-49f1-b554-0bba655b768c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791841434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2791841434
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1717409541
Short name T126
Test name
Test status
Simulation time 10361628292 ps
CPU time 178.56 seconds
Started Mar 21 02:36:17 PM PDT 24
Finished Mar 21 02:39:17 PM PDT 24
Peak memory 214292 kb
Host smart-bf0287c8-525d-4acb-9594-0be3722aea24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717409541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1717409541
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1775777082
Short name T128
Test name
Test status
Simulation time 7111687209 ps
CPU time 174.23 seconds
Started Mar 21 02:36:11 PM PDT 24
Finished Mar 21 02:39:05 PM PDT 24
Peak memory 214176 kb
Host smart-f570d427-ef9c-428b-a1e6-2ea374d38b53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775777082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1775777082
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3315322923
Short name T72
Test name
Test status
Simulation time 4156287783 ps
CPU time 56.31 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:38:18 PM PDT 24
Peak memory 215600 kb
Host smart-ce79c64e-6405-4a65-831a-e6b22e2d4057
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315322923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3315322923
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.180469799
Short name T82
Test name
Test status
Simulation time 6481112987 ps
CPU time 72.64 seconds
Started Mar 21 03:21:34 PM PDT 24
Finished Mar 21 03:22:47 PM PDT 24
Peak memory 219052 kb
Host smart-4d72f55d-3a7b-41d3-9558-6f797daa0c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180469799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.180469799
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.420408820
Short name T215
Test name
Test status
Simulation time 35673320775 ps
CPU time 359.28 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 03:27:28 PM PDT 24
Peak memory 228636 kb
Host smart-b02bde09-7e35-4751-9e3a-699937c13f03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420408820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.420408820
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2791382252
Short name T94
Test name
Test status
Simulation time 2822251803 ps
CPU time 13.16 seconds
Started Mar 21 03:20:50 PM PDT 24
Finished Mar 21 03:21:03 PM PDT 24
Peak memory 210904 kb
Host smart-017f9ac2-f785-4408-acf6-8b68dc4b59e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791382252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2791382252
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1358214094
Short name T747
Test name
Test status
Simulation time 13655975239 ps
CPU time 33.12 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:44 PM PDT 24
Peak memory 212188 kb
Host smart-db47e7d9-cb1e-4bad-81cc-fa416b4ce5f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358214094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1358214094
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3422307837
Short name T833
Test name
Test status
Simulation time 1123887720 ps
CPU time 14.92 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 211304 kb
Host smart-43f5fc1a-2089-47f3-b606-9b95889159d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422307837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3422307837
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1476580105
Short name T723
Test name
Test status
Simulation time 10023640774 ps
CPU time 22.18 seconds
Started Mar 21 01:37:24 PM PDT 24
Finished Mar 21 01:37:47 PM PDT 24
Peak memory 211772 kb
Host smart-96650b73-099c-4efa-9bed-07a71488ad6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476580105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1476580105
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2700730399
Short name T757
Test name
Test status
Simulation time 174169381 ps
CPU time 8.68 seconds
Started Mar 21 02:36:11 PM PDT 24
Finished Mar 21 02:36:20 PM PDT 24
Peak memory 211292 kb
Host smart-1ac12f59-0f15-4509-a256-b7ccb1bd9e54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700730399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2700730399
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2645057067
Short name T790
Test name
Test status
Simulation time 3757960187 ps
CPU time 36.93 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:47 PM PDT 24
Peak memory 212120 kb
Host smart-bd2cf4ab-a7bb-4728-b603-155aa87929cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645057067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2645057067
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.553758112
Short name T737
Test name
Test status
Simulation time 7237389779 ps
CPU time 26.45 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:38:04 PM PDT 24
Peak memory 212148 kb
Host smart-f930ce49-85c3-4fd9-8ad8-989dfe3421da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553758112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.553758112
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1886962609
Short name T812
Test name
Test status
Simulation time 982790736 ps
CPU time 12.55 seconds
Started Mar 21 02:36:11 PM PDT 24
Finished Mar 21 02:36:23 PM PDT 24
Peak memory 214400 kb
Host smart-6084de0d-f819-46a4-a204-423f2f5ba797
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886962609 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1886962609
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.887209315
Short name T834
Test name
Test status
Simulation time 14550444763 ps
CPU time 29.74 seconds
Started Mar 21 01:37:28 PM PDT 24
Finished Mar 21 01:37:58 PM PDT 24
Peak memory 216772 kb
Host smart-a45ede0c-a406-4db8-a5d1-e0acfb2b042b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887209315 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.887209315
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1254989587
Short name T816
Test name
Test status
Simulation time 8046179613 ps
CPU time 32.41 seconds
Started Mar 21 01:37:23 PM PDT 24
Finished Mar 21 01:37:56 PM PDT 24
Peak memory 211980 kb
Host smart-e3791cc0-2bb7-43c2-8d78-5c871f130972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254989587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1254989587
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3639289109
Short name T773
Test name
Test status
Simulation time 504129558 ps
CPU time 9.8 seconds
Started Mar 21 02:36:12 PM PDT 24
Finished Mar 21 02:36:22 PM PDT 24
Peak memory 211292 kb
Host smart-bedf3bf0-1b57-4273-a7c0-29d66156ffa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639289109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3639289109
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1120226352
Short name T777
Test name
Test status
Simulation time 4575120138 ps
CPU time 13.2 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:36:26 PM PDT 24
Peak memory 211308 kb
Host smart-1cf1c823-c821-4666-92e6-de46a237ff52
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120226352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1120226352
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2396486044
Short name T855
Test name
Test status
Simulation time 14466911677 ps
CPU time 25.11 seconds
Started Mar 21 01:37:21 PM PDT 24
Finished Mar 21 01:37:46 PM PDT 24
Peak memory 211264 kb
Host smart-2c8058b9-62d8-42be-9340-748c61c59e2c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396486044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2396486044
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.199765390
Short name T879
Test name
Test status
Simulation time 8227491067 ps
CPU time 13.57 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:36:27 PM PDT 24
Peak memory 211320 kb
Host smart-e2ea5f69-c891-42cf-bd28-04946b70ae43
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199765390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
199765390
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3306192601
Short name T913
Test name
Test status
Simulation time 11580739416 ps
CPU time 23.03 seconds
Started Mar 21 01:37:28 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 211268 kb
Host smart-8f1c2561-2ed4-4ba8-bc7b-56d43e670281
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306192601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3306192601
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2705745381
Short name T799
Test name
Test status
Simulation time 13147623247 ps
CPU time 118.47 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:38:12 PM PDT 24
Peak memory 213716 kb
Host smart-74c55269-3b9a-4686-ac71-ff0f0129ebed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705745381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2705745381
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.893264872
Short name T93
Test name
Test status
Simulation time 73143346647 ps
CPU time 82.2 seconds
Started Mar 21 01:37:25 PM PDT 24
Finished Mar 21 01:38:47 PM PDT 24
Peak memory 214488 kb
Host smart-be9fec7f-a372-49a6-af0b-0654b2827152
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893264872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.893264872
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1812213009
Short name T716
Test name
Test status
Simulation time 1234497085 ps
CPU time 18.71 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 212460 kb
Host smart-28e1187a-070d-4d86-89dc-b54223ca4bec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812213009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1812213009
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2958036228
Short name T744
Test name
Test status
Simulation time 5799851328 ps
CPU time 17.89 seconds
Started Mar 21 02:36:08 PM PDT 24
Finished Mar 21 02:36:26 PM PDT 24
Peak memory 212468 kb
Host smart-17288f3a-a537-4727-b616-afce9cf4d9d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958036228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2958036228
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2249531264
Short name T712
Test name
Test status
Simulation time 688196918 ps
CPU time 10.59 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:36:24 PM PDT 24
Peak memory 218052 kb
Host smart-e89b2145-48a8-4b10-aa47-3922bc5bfabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249531264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2249531264
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2891724210
Short name T800
Test name
Test status
Simulation time 3140906215 ps
CPU time 28.67 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 218468 kb
Host smart-3dffa0a9-3251-4632-9758-5782f6e1192e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891724210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2891724210
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2196808161
Short name T59
Test name
Test status
Simulation time 2394604478 ps
CPU time 94.56 seconds
Started Mar 21 01:37:24 PM PDT 24
Finished Mar 21 01:38:58 PM PDT 24
Peak memory 213356 kb
Host smart-9f91396b-7cd7-4593-b394-7723082e9cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196808161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2196808161
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2751746984
Short name T769
Test name
Test status
Simulation time 635046289 ps
CPU time 8.4 seconds
Started Mar 21 02:36:17 PM PDT 24
Finished Mar 21 02:36:27 PM PDT 24
Peak memory 211304 kb
Host smart-13ef8b02-7dd0-413c-ac63-81286bcefb12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751746984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2751746984
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4234011269
Short name T801
Test name
Test status
Simulation time 1451383409 ps
CPU time 13.12 seconds
Started Mar 21 01:37:28 PM PDT 24
Finished Mar 21 01:37:42 PM PDT 24
Peak memory 211364 kb
Host smart-eceeaa27-8321-45a9-899e-3c202e27c258
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234011269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4234011269
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3086613247
Short name T843
Test name
Test status
Simulation time 1831307865 ps
CPU time 8.87 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:36:19 PM PDT 24
Peak memory 211316 kb
Host smart-1f69d0a1-c450-4138-8a59-b811686e6029
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086613247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3086613247
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.628406430
Short name T701
Test name
Test status
Simulation time 5095713051 ps
CPU time 24.52 seconds
Started Mar 21 01:37:30 PM PDT 24
Finished Mar 21 01:37:55 PM PDT 24
Peak memory 212240 kb
Host smart-7a3b111a-99e7-4d24-9f39-36f9507c783c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628406430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.628406430
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2477677736
Short name T720
Test name
Test status
Simulation time 680032547 ps
CPU time 15.69 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:36:31 PM PDT 24
Peak memory 212232 kb
Host smart-c8293f41-9ea4-45f5-a79c-2f5f248c8900
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477677736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2477677736
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2740738856
Short name T772
Test name
Test status
Simulation time 14334670351 ps
CPU time 26.39 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:49 PM PDT 24
Peak memory 212240 kb
Host smart-8bcc5d1b-de16-4d52-8d7a-4e1ef1656cc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740738856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2740738856
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2288096572
Short name T911
Test name
Test status
Simulation time 2816592106 ps
CPU time 23.98 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:47 PM PDT 24
Peak memory 216028 kb
Host smart-ea5a04b0-eb36-48b2-876d-afb884687cfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288096572 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2288096572
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3301205038
Short name T869
Test name
Test status
Simulation time 8696241137 ps
CPU time 33.33 seconds
Started Mar 21 02:36:11 PM PDT 24
Finished Mar 21 02:36:45 PM PDT 24
Peak memory 218016 kb
Host smart-e5ee265f-55e5-4798-9d86-48d898cc8620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301205038 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3301205038
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1050848195
Short name T846
Test name
Test status
Simulation time 2040000945 ps
CPU time 21.23 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:43 PM PDT 24
Peak memory 211700 kb
Host smart-8629abfa-2586-499f-a9a7-87d26323b58b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050848195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1050848195
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3526820806
Short name T727
Test name
Test status
Simulation time 1582925048 ps
CPU time 14.94 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:36:25 PM PDT 24
Peak memory 211272 kb
Host smart-cdad08b5-0e96-482b-83b7-4277c14c7298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526820806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3526820806
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1693391844
Short name T690
Test name
Test status
Simulation time 174477566 ps
CPU time 8.08 seconds
Started Mar 21 01:37:20 PM PDT 24
Finished Mar 21 01:37:29 PM PDT 24
Peak memory 211192 kb
Host smart-8c17efba-54b6-4e2a-9180-c6dcc985e95e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693391844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1693391844
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4278735937
Short name T873
Test name
Test status
Simulation time 719420908 ps
CPU time 8.18 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:36:18 PM PDT 24
Peak memory 211232 kb
Host smart-f207da7f-2501-4824-b97b-8ec58b7bb9cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278735937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4278735937
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1415401458
Short name T702
Test name
Test status
Simulation time 4928857418 ps
CPU time 15.7 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:39 PM PDT 24
Peak memory 211288 kb
Host smart-8ce57f27-2048-4c8d-b194-3271967b8e1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415401458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1415401458
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2811220214
Short name T705
Test name
Test status
Simulation time 1508764209 ps
CPU time 13.22 seconds
Started Mar 21 02:36:11 PM PDT 24
Finished Mar 21 02:36:25 PM PDT 24
Peak memory 211272 kb
Host smart-4be9fd39-d15d-47a3-a394-452af19b2375
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811220214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2811220214
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2191240736
Short name T90
Test name
Test status
Simulation time 49428312186 ps
CPU time 131.53 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:39:33 PM PDT 24
Peak memory 215448 kb
Host smart-be33c6e2-5cef-4359-b774-07c22a82acf8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191240736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2191240736
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3391082814
Short name T69
Test name
Test status
Simulation time 4286958029 ps
CPU time 56.7 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:37:07 PM PDT 24
Peak memory 215456 kb
Host smart-6c3d663d-3166-4865-85ca-2c9a13054fa2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391082814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3391082814
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1226510439
Short name T819
Test name
Test status
Simulation time 5534043687 ps
CPU time 24.3 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:34 PM PDT 24
Peak memory 212624 kb
Host smart-af592859-0639-4b8a-8e8a-82b9f4bb513e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226510439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1226510439
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2222775978
Short name T766
Test name
Test status
Simulation time 3760602207 ps
CPU time 30.25 seconds
Started Mar 21 01:37:30 PM PDT 24
Finished Mar 21 01:38:01 PM PDT 24
Peak memory 212212 kb
Host smart-44bb18a9-2f4f-4575-8169-74bb31f0d6dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222775978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2222775978
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1737999959
Short name T845
Test name
Test status
Simulation time 18224241685 ps
CPU time 35.25 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:38:09 PM PDT 24
Peak memory 217448 kb
Host smart-4a145d37-a7b5-49b6-8036-a1d75f50e79f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737999959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1737999959
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3311207514
Short name T853
Test name
Test status
Simulation time 18545614053 ps
CPU time 35.39 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:36:46 PM PDT 24
Peak memory 217436 kb
Host smart-fed0b48d-cd0e-465e-b2e7-7aa5d3d50c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311207514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3311207514
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.321226397
Short name T119
Test name
Test status
Simulation time 10493909535 ps
CPU time 164.98 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:40:20 PM PDT 24
Peak memory 214180 kb
Host smart-80220247-83f8-4dbf-b390-836da3a49d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321226397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.321226397
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1227134264
Short name T924
Test name
Test status
Simulation time 6446348162 ps
CPU time 27.56 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:36:50 PM PDT 24
Peak memory 218024 kb
Host smart-4ffa68b2-afa8-4d5c-9a4a-9bef722ad17b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227134264 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1227134264
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1656527385
Short name T825
Test name
Test status
Simulation time 7484766660 ps
CPU time 19.27 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 218216 kb
Host smart-39744d5f-bb38-4c1e-9ec7-d61171b04283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656527385 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1656527385
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2814989139
Short name T780
Test name
Test status
Simulation time 2196528763 ps
CPU time 21.09 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:55 PM PDT 24
Peak memory 211812 kb
Host smart-f436a8e6-1d72-49f8-a94a-441c60eefa7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814989139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2814989139
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.579357574
Short name T903
Test name
Test status
Simulation time 7509407313 ps
CPU time 28.8 seconds
Started Mar 21 02:36:27 PM PDT 24
Finished Mar 21 02:36:56 PM PDT 24
Peak memory 212260 kb
Host smart-d08e5586-9e48-4022-9c86-43b68e38180c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579357574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.579357574
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2319034065
Short name T722
Test name
Test status
Simulation time 16507487254 ps
CPU time 85.87 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:39:00 PM PDT 24
Peak memory 214752 kb
Host smart-25185f28-3d04-4028-a5a1-2c8d74c1e170
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319034065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2319034065
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.976004536
Short name T735
Test name
Test status
Simulation time 24703054991 ps
CPU time 206.53 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:39:49 PM PDT 24
Peak memory 214740 kb
Host smart-0c0c1478-6a31-4477-9727-976e533a3921
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976004536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.976004536
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1722363955
Short name T906
Test name
Test status
Simulation time 14714301393 ps
CPU time 29.08 seconds
Started Mar 21 01:37:35 PM PDT 24
Finished Mar 21 01:38:04 PM PDT 24
Peak memory 212492 kb
Host smart-f6df2ba4-8939-4612-bbc1-8d7de6a34a8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722363955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1722363955
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4122882876
Short name T106
Test name
Test status
Simulation time 9989178638 ps
CPU time 21.12 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:36:41 PM PDT 24
Peak memory 212780 kb
Host smart-75ddb86e-d2c9-43f0-864c-d98d1f789b15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122882876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4122882876
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1002466543
Short name T734
Test name
Test status
Simulation time 612768070 ps
CPU time 12.05 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:36:33 PM PDT 24
Peak memory 217416 kb
Host smart-95cab060-1acc-4b5e-aa1c-0b27a83791ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002466543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1002466543
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3635426641
Short name T748
Test name
Test status
Simulation time 1483759643 ps
CPU time 18.11 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:37:49 PM PDT 24
Peak memory 218572 kb
Host smart-bfbb09c1-ef2f-4e62-9996-b80cdcabe66a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635426641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3635426641
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.190705838
Short name T127
Test name
Test status
Simulation time 309677342 ps
CPU time 157.39 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:40:11 PM PDT 24
Peak memory 213944 kb
Host smart-e30a866e-9b51-47e8-85ed-6037c6ff41aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190705838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.190705838
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3283030765
Short name T125
Test name
Test status
Simulation time 986688885 ps
CPU time 80.49 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:37:43 PM PDT 24
Peak memory 213668 kb
Host smart-e948c0da-b890-4c36-bcb2-d32eb7e24719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283030765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3283030765
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1448165921
Short name T931
Test name
Test status
Simulation time 2894424843 ps
CPU time 24.52 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:37:01 PM PDT 24
Peak memory 215880 kb
Host smart-4141b6f4-a5b3-44fb-936b-6c7ea43444ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448165921 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1448165921
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4270305693
Short name T752
Test name
Test status
Simulation time 4037114929 ps
CPU time 31.8 seconds
Started Mar 21 01:37:39 PM PDT 24
Finished Mar 21 01:38:11 PM PDT 24
Peak memory 216520 kb
Host smart-f524799b-abed-4315-b8b2-1758c7f9e339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270305693 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4270305693
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2156061191
Short name T805
Test name
Test status
Simulation time 688247863 ps
CPU time 7.91 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:36:44 PM PDT 24
Peak memory 211256 kb
Host smart-df32d0f3-4a55-46ad-a44a-6aa6eb69b499
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156061191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2156061191
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3538373712
Short name T814
Test name
Test status
Simulation time 257443168 ps
CPU time 9.89 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:37:44 PM PDT 24
Peak memory 211276 kb
Host smart-eb662c6c-7c02-4618-af7b-88969c2820c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538373712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3538373712
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2523228487
Short name T112
Test name
Test status
Simulation time 4126923337 ps
CPU time 69.77 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:38:43 PM PDT 24
Peak memory 215480 kb
Host smart-6885c19f-eb24-48ca-9808-c81c75dfb05a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523228487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2523228487
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.818108454
Short name T68
Test name
Test status
Simulation time 59688863326 ps
CPU time 144.96 seconds
Started Mar 21 02:36:19 PM PDT 24
Finished Mar 21 02:38:45 PM PDT 24
Peak memory 215488 kb
Host smart-2e2a993a-4c71-4410-a056-dbe283a82924
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818108454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.818108454
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3171527338
Short name T107
Test name
Test status
Simulation time 2521230011 ps
CPU time 16.81 seconds
Started Mar 21 01:37:35 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 211436 kb
Host smart-cb02dfdd-18b2-472a-820a-451766ca856b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171527338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3171527338
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3917462162
Short name T838
Test name
Test status
Simulation time 2060016206 ps
CPU time 8.37 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:36:43 PM PDT 24
Peak memory 211308 kb
Host smart-5562a3a8-4f5f-41c8-aeed-37002fb2e69b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917462162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3917462162
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3637673110
Short name T849
Test name
Test status
Simulation time 2300931535 ps
CPU time 25.69 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:37:02 PM PDT 24
Peak memory 218368 kb
Host smart-a76a3886-349f-4e6f-9ae5-c676855a891a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637673110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3637673110
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.963092462
Short name T831
Test name
Test status
Simulation time 2399826113 ps
CPU time 24.43 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:37:59 PM PDT 24
Peak memory 217244 kb
Host smart-695aa6af-4e04-463b-ae07-7e359081b8fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963092462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.963092462
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2042052708
Short name T864
Test name
Test status
Simulation time 4863478736 ps
CPU time 87.09 seconds
Started Mar 21 02:36:33 PM PDT 24
Finished Mar 21 02:38:01 PM PDT 24
Peak memory 212636 kb
Host smart-6375b409-ebd8-4b5e-a29d-3cb2064d742e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042052708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2042052708
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2311012730
Short name T829
Test name
Test status
Simulation time 3658046068 ps
CPU time 87.22 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:38:59 PM PDT 24
Peak memory 213664 kb
Host smart-0b95e05d-4e75-437b-be9e-0efff49cb59a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311012730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2311012730
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1308095329
Short name T893
Test name
Test status
Simulation time 743628425 ps
CPU time 9.59 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:36:43 PM PDT 24
Peak memory 217004 kb
Host smart-f7445056-0085-4217-80b9-1f262268fe6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308095329 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1308095329
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3338658797
Short name T793
Test name
Test status
Simulation time 6965798228 ps
CPU time 33.12 seconds
Started Mar 21 01:37:36 PM PDT 24
Finished Mar 21 01:38:09 PM PDT 24
Peak memory 217280 kb
Host smart-aa21ac02-7755-4815-bf26-6914f20d91f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338658797 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3338658797
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2563643908
Short name T792
Test name
Test status
Simulation time 2355079399 ps
CPU time 8.21 seconds
Started Mar 21 01:37:43 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 211356 kb
Host smart-d78b8c27-295c-44bb-8bc5-1ac7a25dfb2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563643908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2563643908
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.980833510
Short name T92
Test name
Test status
Simulation time 2760444302 ps
CPU time 23.82 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:37:00 PM PDT 24
Peak memory 211928 kb
Host smart-aec9aa14-a8cd-4ab4-a3e3-2f45ad157589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980833510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.980833510
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2587208630
Short name T891
Test name
Test status
Simulation time 35708606914 ps
CPU time 131.15 seconds
Started Mar 21 02:36:37 PM PDT 24
Finished Mar 21 02:38:48 PM PDT 24
Peak memory 213464 kb
Host smart-e965b678-bd61-4b0a-aad9-ee0d1e8d3884
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587208630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2587208630
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3687748065
Short name T76
Test name
Test status
Simulation time 76031646046 ps
CPU time 151.77 seconds
Started Mar 21 01:37:39 PM PDT 24
Finished Mar 21 01:40:11 PM PDT 24
Peak memory 215424 kb
Host smart-0d0d4674-f7a8-4303-ac56-e18f9ccdc2d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687748065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3687748065
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3302688935
Short name T870
Test name
Test status
Simulation time 3741173871 ps
CPU time 29.65 seconds
Started Mar 21 01:37:36 PM PDT 24
Finished Mar 21 01:38:06 PM PDT 24
Peak memory 212088 kb
Host smart-16f9e6cf-09f4-46c1-9ec9-3523d661ddfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302688935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3302688935
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3314062462
Short name T715
Test name
Test status
Simulation time 5123950265 ps
CPU time 16.65 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:36:53 PM PDT 24
Peak memory 211384 kb
Host smart-b1c7538d-ac58-433f-bef7-1a343617c787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314062462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3314062462
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2805010887
Short name T905
Test name
Test status
Simulation time 338876209 ps
CPU time 11.56 seconds
Started Mar 21 02:36:37 PM PDT 24
Finished Mar 21 02:36:49 PM PDT 24
Peak memory 217280 kb
Host smart-9ef126cc-bd74-4de3-b7d4-6a0da63ed55e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805010887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2805010887
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2933874794
Short name T902
Test name
Test status
Simulation time 4224168193 ps
CPU time 19.71 seconds
Started Mar 21 01:37:39 PM PDT 24
Finished Mar 21 01:37:59 PM PDT 24
Peak memory 218536 kb
Host smart-d7d416dc-1cdf-400f-95a2-6b01d984f323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933874794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2933874794
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1416012509
Short name T756
Test name
Test status
Simulation time 6955635757 ps
CPU time 91.4 seconds
Started Mar 21 02:36:39 PM PDT 24
Finished Mar 21 02:38:11 PM PDT 24
Peak memory 213944 kb
Host smart-aa7051aa-9d1e-4bfe-be28-a5e10fee8a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416012509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1416012509
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.486126076
Short name T918
Test name
Test status
Simulation time 1973252628 ps
CPU time 84.68 seconds
Started Mar 21 01:37:35 PM PDT 24
Finished Mar 21 01:39:00 PM PDT 24
Peak memory 214292 kb
Host smart-24fa6800-b7ff-4dcc-9eeb-fbd67f7679ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486126076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.486126076
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1465085272
Short name T707
Test name
Test status
Simulation time 12494358197 ps
CPU time 27.43 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:37:04 PM PDT 24
Peak memory 214756 kb
Host smart-8119dca2-2137-4a29-9e45-e26ee3cc8f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465085272 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1465085272
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3017114522
Short name T886
Test name
Test status
Simulation time 9670954824 ps
CPU time 18.71 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 215116 kb
Host smart-a5bff528-350f-4153-be5f-86031fd09534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017114522 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3017114522
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4028742579
Short name T881
Test name
Test status
Simulation time 2008317117 ps
CPU time 19.89 seconds
Started Mar 21 01:37:36 PM PDT 24
Finished Mar 21 01:37:56 PM PDT 24
Peak memory 212164 kb
Host smart-5adb6499-2a86-4e61-8957-4ca398d0409a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028742579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4028742579
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2401542082
Short name T85
Test name
Test status
Simulation time 41611269331 ps
CPU time 97.63 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:39:12 PM PDT 24
Peak memory 213508 kb
Host smart-f9ee07a6-ab1c-471b-900f-9d3729877159
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401542082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2401542082
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3665552129
Short name T837
Test name
Test status
Simulation time 14817018371 ps
CPU time 146.35 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:39:01 PM PDT 24
Peak memory 215464 kb
Host smart-7744cdfa-316c-465f-af32-e240db29296e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665552129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3665552129
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1205599166
Short name T880
Test name
Test status
Simulation time 2380323866 ps
CPU time 12.79 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:46 PM PDT 24
Peak memory 211316 kb
Host smart-ca3ffe09-9c0c-4f0c-bd55-bd57e5a95ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205599166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1205599166
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2796325504
Short name T917
Test name
Test status
Simulation time 3126171882 ps
CPU time 30.06 seconds
Started Mar 21 02:36:32 PM PDT 24
Finished Mar 21 02:37:03 PM PDT 24
Peak memory 212444 kb
Host smart-b0ca7910-0431-4b30-ac08-ee972369e043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796325504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2796325504
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2607919607
Short name T844
Test name
Test status
Simulation time 203808039 ps
CPU time 11.67 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:37:44 PM PDT 24
Peak memory 217372 kb
Host smart-9c659905-4a2b-450d-a86f-955e9e9a7886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607919607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2607919607
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.847630392
Short name T920
Test name
Test status
Simulation time 1098451305 ps
CPU time 11.12 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:36:47 PM PDT 24
Peak memory 217188 kb
Host smart-219ce2cb-d5af-4e04-adb3-eeabb46695e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847630392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.847630392
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2811304297
Short name T897
Test name
Test status
Simulation time 951567485 ps
CPU time 82.49 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:39:00 PM PDT 24
Peak memory 213732 kb
Host smart-ae3cbe91-de97-4dcc-b902-a63da43ab90b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811304297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2811304297
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.784694864
Short name T61
Test name
Test status
Simulation time 781765090 ps
CPU time 159.8 seconds
Started Mar 21 02:36:40 PM PDT 24
Finished Mar 21 02:39:20 PM PDT 24
Peak memory 213932 kb
Host smart-a12d4dc3-9e7a-454a-a2c9-9011d9e550a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784694864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.784694864
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1714256088
Short name T830
Test name
Test status
Simulation time 3758432357 ps
CPU time 30.2 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:38:14 PM PDT 24
Peak memory 216252 kb
Host smart-588a024c-3359-4ca2-a26a-b9119ad80c10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714256088 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1714256088
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2972787205
Short name T774
Test name
Test status
Simulation time 179667744 ps
CPU time 8.94 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:36:45 PM PDT 24
Peak memory 215888 kb
Host smart-a821e7ea-0640-481b-84b2-48944a5353fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972787205 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2972787205
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1351031511
Short name T717
Test name
Test status
Simulation time 11190607961 ps
CPU time 24.64 seconds
Started Mar 21 02:36:40 PM PDT 24
Finished Mar 21 02:37:04 PM PDT 24
Peak memory 212256 kb
Host smart-4ec27198-afd5-4909-8da4-09e7e279b3eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351031511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1351031511
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.501841152
Short name T934
Test name
Test status
Simulation time 2098496394 ps
CPU time 20.95 seconds
Started Mar 21 01:37:47 PM PDT 24
Finished Mar 21 01:38:08 PM PDT 24
Peak memory 211884 kb
Host smart-978f2f2e-0e6e-483e-91bd-547a2f1b1641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501841152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.501841152
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2617993102
Short name T708
Test name
Test status
Simulation time 2660916905 ps
CPU time 57.01 seconds
Started Mar 21 02:36:32 PM PDT 24
Finished Mar 21 02:37:29 PM PDT 24
Peak memory 214480 kb
Host smart-2d00823d-9f36-44b3-9dd8-198a1c58a7f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617993102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2617993102
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2769223930
Short name T91
Test name
Test status
Simulation time 691993990 ps
CPU time 37.7 seconds
Started Mar 21 01:37:43 PM PDT 24
Finished Mar 21 01:38:22 PM PDT 24
Peak memory 213324 kb
Host smart-9dd5067b-2b8d-46e5-aad8-7aac962ea573
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769223930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2769223930
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2857803875
Short name T916
Test name
Test status
Simulation time 9271313609 ps
CPU time 21.62 seconds
Started Mar 21 01:37:45 PM PDT 24
Finished Mar 21 01:38:07 PM PDT 24
Peak memory 212468 kb
Host smart-617f07ea-2730-411d-bdb2-d14270e329bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857803875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2857803875
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2879896367
Short name T901
Test name
Test status
Simulation time 943353387 ps
CPU time 17.9 seconds
Started Mar 21 02:36:32 PM PDT 24
Finished Mar 21 02:36:50 PM PDT 24
Peak memory 212404 kb
Host smart-c72b52a1-8941-4ddf-adce-fb3cab864ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879896367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2879896367
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.107854468
Short name T803
Test name
Test status
Simulation time 8035740430 ps
CPU time 35.26 seconds
Started Mar 21 02:36:33 PM PDT 24
Finished Mar 21 02:37:09 PM PDT 24
Peak memory 217780 kb
Host smart-74822d77-30b2-43ba-aa74-ef0df73cd640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107854468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.107854468
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2111193640
Short name T746
Test name
Test status
Simulation time 174259635 ps
CPU time 13.63 seconds
Started Mar 21 01:37:45 PM PDT 24
Finished Mar 21 01:37:59 PM PDT 24
Peak memory 217608 kb
Host smart-32217eb7-74ea-40e6-a564-7600e2fcee15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111193640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2111193640
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2313657114
Short name T871
Test name
Test status
Simulation time 972488918 ps
CPU time 161.44 seconds
Started Mar 21 01:37:46 PM PDT 24
Finished Mar 21 01:40:27 PM PDT 24
Peak memory 214048 kb
Host smart-14a6d018-63b0-44c5-8a5a-9527fd0b6f97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313657114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2313657114
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3070871192
Short name T883
Test name
Test status
Simulation time 1263167858 ps
CPU time 89.32 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:38:06 PM PDT 24
Peak memory 213336 kb
Host smart-3d563f55-bae9-4d97-b534-1a338d4defed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070871192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3070871192
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2948038502
Short name T692
Test name
Test status
Simulation time 14205488341 ps
CPU time 21.81 seconds
Started Mar 21 01:37:43 PM PDT 24
Finished Mar 21 01:38:06 PM PDT 24
Peak memory 217512 kb
Host smart-38b4265b-559a-415e-87f3-ace9ca41e1c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948038502 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2948038502
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3056535241
Short name T776
Test name
Test status
Simulation time 22399443615 ps
CPU time 24.83 seconds
Started Mar 21 02:36:32 PM PDT 24
Finished Mar 21 02:36:57 PM PDT 24
Peak memory 213812 kb
Host smart-0fe5a9a0-b279-4839-95e7-f25cc1df52c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056535241 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3056535241
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4117089351
Short name T759
Test name
Test status
Simulation time 13793231751 ps
CPU time 28.54 seconds
Started Mar 21 01:37:45 PM PDT 24
Finished Mar 21 01:38:14 PM PDT 24
Peak memory 212180 kb
Host smart-2f7cf507-34f8-496a-8379-a8274904f1aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117089351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4117089351
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4187929284
Short name T804
Test name
Test status
Simulation time 19471135219 ps
CPU time 29.59 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:37:04 PM PDT 24
Peak memory 211332 kb
Host smart-b4bc20c3-5b9b-4d31-8eaf-b8b64efd5226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187929284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4187929284
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1843111751
Short name T725
Test name
Test status
Simulation time 17131850627 ps
CPU time 91 seconds
Started Mar 21 01:37:46 PM PDT 24
Finished Mar 21 01:39:18 PM PDT 24
Peak memory 214592 kb
Host smart-9cf162eb-d8ad-4b64-a183-4726353f8467
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843111751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1843111751
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3089078889
Short name T719
Test name
Test status
Simulation time 25598170273 ps
CPU time 202.01 seconds
Started Mar 21 02:36:33 PM PDT 24
Finished Mar 21 02:39:55 PM PDT 24
Peak memory 215680 kb
Host smart-2ccdc104-9af4-4303-906b-473e67e34fb2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089078889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3089078889
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.29044926
Short name T892
Test name
Test status
Simulation time 1237655825 ps
CPU time 16.32 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:38:00 PM PDT 24
Peak memory 211396 kb
Host smart-b522bba6-64e6-4d91-ac5e-c737aa59c6cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29044926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ct
rl_same_csr_outstanding.29044926
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.842534830
Short name T802
Test name
Test status
Simulation time 15473263026 ps
CPU time 33.79 seconds
Started Mar 21 02:36:39 PM PDT 24
Finished Mar 21 02:37:13 PM PDT 24
Peak memory 212876 kb
Host smart-a8efe478-9db3-4900-99fd-b2e5a09a4c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842534830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.842534830
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1261834946
Short name T810
Test name
Test status
Simulation time 5295923720 ps
CPU time 26.65 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:37:03 PM PDT 24
Peak memory 218568 kb
Host smart-12a31cfd-7cc2-46ea-b8c1-52df9bec2226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261834946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1261834946
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2917924246
Short name T694
Test name
Test status
Simulation time 167603975 ps
CPU time 12.75 seconds
Started Mar 21 01:37:46 PM PDT 24
Finished Mar 21 01:38:00 PM PDT 24
Peak memory 217408 kb
Host smart-20085bf2-ffac-4a18-ae7b-8c0f08e29db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917924246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2917924246
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1211406160
Short name T907
Test name
Test status
Simulation time 22400027050 ps
CPU time 164.17 seconds
Started Mar 21 01:37:46 PM PDT 24
Finished Mar 21 01:40:30 PM PDT 24
Peak memory 214352 kb
Host smart-f3e73afa-3d8c-45ec-8051-1b61e9eac2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211406160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1211406160
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.801748192
Short name T815
Test name
Test status
Simulation time 273383295 ps
CPU time 81.57 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:37:58 PM PDT 24
Peak memory 213492 kb
Host smart-28a87fdc-dc66-4c6a-a849-d1b4aa8e9cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801748192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.801748192
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2398099692
Short name T760
Test name
Test status
Simulation time 2167407113 ps
CPU time 21.32 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:36:58 PM PDT 24
Peak memory 217836 kb
Host smart-a2355795-feaa-4614-9da1-a79862f2b94c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398099692 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2398099692
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.659813637
Short name T700
Test name
Test status
Simulation time 629074640 ps
CPU time 8.67 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 216264 kb
Host smart-2c16c3e9-0a54-4caf-9454-fed30c7bedd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659813637 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.659813637
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1724429124
Short name T850
Test name
Test status
Simulation time 34061240224 ps
CPU time 23.62 seconds
Started Mar 21 01:37:46 PM PDT 24
Finished Mar 21 01:38:10 PM PDT 24
Peak memory 212236 kb
Host smart-fb52ea8c-6152-4be0-a0a2-a281d5504add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724429124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1724429124
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.837741887
Short name T784
Test name
Test status
Simulation time 3914770772 ps
CPU time 31.51 seconds
Started Mar 21 02:36:38 PM PDT 24
Finished Mar 21 02:37:11 PM PDT 24
Peak memory 212024 kb
Host smart-7cc71b87-3eb1-4952-84ec-dbcbc11c7a16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837741887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.837741887
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.248483979
Short name T839
Test name
Test status
Simulation time 24298565779 ps
CPU time 108.96 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:38:25 PM PDT 24
Peak memory 214484 kb
Host smart-816649af-88e7-4b13-b6e3-fd9be5b31b61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248483979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.248483979
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3578186243
Short name T867
Test name
Test status
Simulation time 100976790394 ps
CPU time 118.1 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:39:43 PM PDT 24
Peak memory 213748 kb
Host smart-ed940be3-f495-40ee-a2ae-3647d8035751
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578186243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3578186243
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2301058415
Short name T851
Test name
Test status
Simulation time 167426174 ps
CPU time 8.39 seconds
Started Mar 21 01:37:45 PM PDT 24
Finished Mar 21 01:37:54 PM PDT 24
Peak memory 211280 kb
Host smart-e0ae7144-2907-4e7c-9fcb-53ae13e43b9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301058415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2301058415
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.682344566
Short name T764
Test name
Test status
Simulation time 13683941757 ps
CPU time 24.75 seconds
Started Mar 21 02:36:38 PM PDT 24
Finished Mar 21 02:37:04 PM PDT 24
Peak memory 212476 kb
Host smart-a84a5179-32b6-4f80-a10d-ac5b41925434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682344566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.682344566
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2853409214
Short name T697
Test name
Test status
Simulation time 3944549340 ps
CPU time 17.81 seconds
Started Mar 21 02:36:38 PM PDT 24
Finished Mar 21 02:36:57 PM PDT 24
Peak memory 217424 kb
Host smart-28f8c7d8-3294-4a39-9f67-d31fdc2e02aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853409214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2853409214
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.994504369
Short name T693
Test name
Test status
Simulation time 1116300706 ps
CPU time 20.03 seconds
Started Mar 21 01:37:45 PM PDT 24
Finished Mar 21 01:38:05 PM PDT 24
Peak memory 217304 kb
Host smart-75b742c0-15a1-4f84-888a-92532e43eef3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994504369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.994504369
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3635832020
Short name T129
Test name
Test status
Simulation time 10113936505 ps
CPU time 167.74 seconds
Started Mar 21 01:37:45 PM PDT 24
Finished Mar 21 01:40:33 PM PDT 24
Peak memory 214224 kb
Host smart-3bee8907-1526-4664-b82d-3aaaa5c2da79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635832020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3635832020
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4127220430
Short name T872
Test name
Test status
Simulation time 8138830636 ps
CPU time 92.68 seconds
Started Mar 21 02:36:38 PM PDT 24
Finished Mar 21 02:38:12 PM PDT 24
Peak memory 213968 kb
Host smart-daff7ff6-2d8a-46a8-a6df-02dbe99686d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127220430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4127220430
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2947655140
Short name T699
Test name
Test status
Simulation time 4664368249 ps
CPU time 22.64 seconds
Started Mar 21 02:36:37 PM PDT 24
Finished Mar 21 02:37:00 PM PDT 24
Peak memory 217088 kb
Host smart-9d50b752-7441-4f2e-927e-4c8a9b4a69d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947655140 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2947655140
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.678796028
Short name T768
Test name
Test status
Simulation time 17504200753 ps
CPU time 32.35 seconds
Started Mar 21 01:37:43 PM PDT 24
Finished Mar 21 01:38:16 PM PDT 24
Peak memory 216988 kb
Host smart-a6fbeafb-2b7a-43d0-8199-38bcf6abf87c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678796028 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.678796028
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1021309602
Short name T767
Test name
Test status
Simulation time 2631034275 ps
CPU time 12.7 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:36:49 PM PDT 24
Peak memory 211360 kb
Host smart-eecb7ce2-2085-48ad-9262-25e5aee8dbfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021309602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1021309602
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.91886898
Short name T84
Test name
Test status
Simulation time 661584032 ps
CPU time 8.1 seconds
Started Mar 21 01:37:43 PM PDT 24
Finished Mar 21 01:37:51 PM PDT 24
Peak memory 211292 kb
Host smart-d83ebc34-3034-46a6-a9cb-a19af8b6da03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91886898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.91886898
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3207540278
Short name T797
Test name
Test status
Simulation time 17181745168 ps
CPU time 87.54 seconds
Started Mar 21 02:36:30 PM PDT 24
Finished Mar 21 02:37:58 PM PDT 24
Peak memory 214448 kb
Host smart-07c4446c-1f12-427d-a6ce-9f3583de092d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207540278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3207540278
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3666746062
Short name T878
Test name
Test status
Simulation time 10863079641 ps
CPU time 119.35 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:39:44 PM PDT 24
Peak memory 215620 kb
Host smart-8527c373-71ba-4964-86cb-c0fbf4e12b36
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666746062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3666746062
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1190285437
Short name T718
Test name
Test status
Simulation time 7475635590 ps
CPU time 20.15 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:38:04 PM PDT 24
Peak memory 212432 kb
Host smart-b7529473-1f12-4a5d-9d76-bdb900e00d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190285437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1190285437
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.994958339
Short name T835
Test name
Test status
Simulation time 15444627835 ps
CPU time 30.61 seconds
Started Mar 21 02:36:38 PM PDT 24
Finished Mar 21 02:37:10 PM PDT 24
Peak memory 212716 kb
Host smart-8fcd5107-4a11-4d99-a7e4-3f66293ef1b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994958339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.994958339
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1318021521
Short name T785
Test name
Test status
Simulation time 13909598600 ps
CPU time 31.63 seconds
Started Mar 21 02:36:38 PM PDT 24
Finished Mar 21 02:37:11 PM PDT 24
Peak memory 218560 kb
Host smart-0d588f6d-7339-41b2-b83c-86fd38712b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318021521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1318021521
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.215979330
Short name T736
Test name
Test status
Simulation time 4368858389 ps
CPU time 37.82 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:38:23 PM PDT 24
Peak memory 218044 kb
Host smart-b57caf6f-a453-47eb-b324-2fc3ead05419
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215979330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.215979330
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.378863565
Short name T733
Test name
Test status
Simulation time 15840180667 ps
CPU time 32.62 seconds
Started Mar 21 01:37:48 PM PDT 24
Finished Mar 21 01:38:21 PM PDT 24
Peak memory 218604 kb
Host smart-e65e64c7-dea7-4e8b-b99d-2cca0bdee100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378863565 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.378863565
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.785667160
Short name T806
Test name
Test status
Simulation time 2056645450 ps
CPU time 22.05 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:36:56 PM PDT 24
Peak memory 217052 kb
Host smart-72f9902f-c758-4393-a24e-589afc510a5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785667160 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.785667160
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2639606169
Short name T820
Test name
Test status
Simulation time 338358017 ps
CPU time 8.11 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 211264 kb
Host smart-74f90847-2856-49c6-9ac3-6a447d082311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639606169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2639606169
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2711065522
Short name T933
Test name
Test status
Simulation time 1917092925 ps
CPU time 13.69 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:36:50 PM PDT 24
Peak memory 211332 kb
Host smart-1eaa2bc0-8990-48b4-a39f-df89a94fd431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711065522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2711065522
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2217281885
Short name T738
Test name
Test status
Simulation time 13136335655 ps
CPU time 113.29 seconds
Started Mar 21 01:37:45 PM PDT 24
Finished Mar 21 01:39:38 PM PDT 24
Peak memory 214448 kb
Host smart-c3a3c545-d2e8-4ba4-858e-503d8a41c1c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217281885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2217281885
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4065266506
Short name T729
Test name
Test status
Simulation time 3645879753 ps
CPU time 80.7 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:37:57 PM PDT 24
Peak memory 214860 kb
Host smart-339ebf69-b407-4410-80ac-115461d3e56a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065266506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4065266506
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.541657735
Short name T73
Test name
Test status
Simulation time 174590260 ps
CPU time 8.58 seconds
Started Mar 21 02:36:33 PM PDT 24
Finished Mar 21 02:36:42 PM PDT 24
Peak memory 211496 kb
Host smart-bd5d4ff1-3afc-4a4c-8af8-96e46b8be952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541657735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.541657735
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.861602000
Short name T786
Test name
Test status
Simulation time 1028190903 ps
CPU time 14.8 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:38:00 PM PDT 24
Peak memory 211212 kb
Host smart-f3ef772d-af65-42de-b3b6-95ff5d3d3b20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861602000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.861602000
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4041780429
Short name T857
Test name
Test status
Simulation time 905664887 ps
CPU time 18.01 seconds
Started Mar 21 01:37:43 PM PDT 24
Finished Mar 21 01:38:02 PM PDT 24
Peak memory 218464 kb
Host smart-62bfa8a3-30e7-43f2-9627-160eaa1a43c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041780429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4041780429
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.752374723
Short name T824
Test name
Test status
Simulation time 4232910082 ps
CPU time 25.21 seconds
Started Mar 21 02:36:37 PM PDT 24
Finished Mar 21 02:37:02 PM PDT 24
Peak memory 217580 kb
Host smart-0708e260-2c2f-4b9e-b834-c7605df965ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752374723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.752374723
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2792394818
Short name T900
Test name
Test status
Simulation time 27512453021 ps
CPU time 96.19 seconds
Started Mar 21 02:36:36 PM PDT 24
Finished Mar 21 02:38:12 PM PDT 24
Peak memory 213864 kb
Host smart-66315ae8-e7dd-4771-9bd6-ddcb84a2d538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792394818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2792394818
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.53442963
Short name T732
Test name
Test status
Simulation time 236279892 ps
CPU time 81.03 seconds
Started Mar 21 01:37:43 PM PDT 24
Finished Mar 21 01:39:05 PM PDT 24
Peak memory 213792 kb
Host smart-6327f9c4-3826-433f-b94d-31267cdb5953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53442963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_int
g_err.53442963
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2175385679
Short name T751
Test name
Test status
Simulation time 182104800 ps
CPU time 9.39 seconds
Started Mar 21 01:37:48 PM PDT 24
Finished Mar 21 01:37:57 PM PDT 24
Peak memory 217464 kb
Host smart-a341ea93-da22-4762-b9a0-db7b354b22c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175385679 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2175385679
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.593540489
Short name T798
Test name
Test status
Simulation time 363883227 ps
CPU time 8.99 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:36:45 PM PDT 24
Peak memory 216708 kb
Host smart-4f4fdf85-2ec5-4b6c-a0f2-b70a8b354136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593540489 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.593540489
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1219384541
Short name T848
Test name
Test status
Simulation time 1345130216 ps
CPU time 16.84 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:36:53 PM PDT 24
Peak memory 211240 kb
Host smart-9c5292ff-9bdb-4839-b6b2-1cbd252c0f91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219384541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1219384541
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3693818589
Short name T62
Test name
Test status
Simulation time 1268350056 ps
CPU time 8.16 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 211336 kb
Host smart-77058136-c583-4fbb-968a-7a2ac544b840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693818589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3693818589
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1686774125
Short name T86
Test name
Test status
Simulation time 12764535667 ps
CPU time 73.49 seconds
Started Mar 21 01:37:47 PM PDT 24
Finished Mar 21 01:39:00 PM PDT 24
Peak memory 214604 kb
Host smart-6992ec66-c90e-4bec-8310-68dae94badeb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686774125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1686774125
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3885536522
Short name T915
Test name
Test status
Simulation time 81078806878 ps
CPU time 119.34 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:38:36 PM PDT 24
Peak memory 213452 kb
Host smart-65f16160-e6ef-4316-af2f-c5f484b93de8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885536522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3885536522
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2627203035
Short name T730
Test name
Test status
Simulation time 1646178832 ps
CPU time 21.84 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:36:58 PM PDT 24
Peak memory 212212 kb
Host smart-8ea545e3-7dd6-4784-a499-3012092e5b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627203035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2627203035
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3323146667
Short name T713
Test name
Test status
Simulation time 1685439735 ps
CPU time 18.56 seconds
Started Mar 21 01:37:46 PM PDT 24
Finished Mar 21 01:38:06 PM PDT 24
Peak memory 212024 kb
Host smart-a2a96053-c74a-4dd5-8ef1-72657cab3093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323146667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3323146667
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4130429633
Short name T914
Test name
Test status
Simulation time 8201283174 ps
CPU time 23.15 seconds
Started Mar 21 02:36:35 PM PDT 24
Finished Mar 21 02:36:59 PM PDT 24
Peak memory 218796 kb
Host smart-1c999f22-f178-4b44-a9d8-bb17216a5674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130429633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4130429633
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.532174254
Short name T890
Test name
Test status
Simulation time 8521316499 ps
CPU time 24.43 seconds
Started Mar 21 01:37:46 PM PDT 24
Finished Mar 21 01:38:10 PM PDT 24
Peak memory 218736 kb
Host smart-08ed2dfc-21fd-4105-b934-2e75dc6854c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532174254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.532174254
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3831015298
Short name T122
Test name
Test status
Simulation time 2975960137 ps
CPU time 87.79 seconds
Started Mar 21 01:37:44 PM PDT 24
Finished Mar 21 01:39:12 PM PDT 24
Peak memory 213276 kb
Host smart-cad92c27-68a7-4c0b-a980-7f3897af7d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831015298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3831015298
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.861795272
Short name T847
Test name
Test status
Simulation time 7697511029 ps
CPU time 159.35 seconds
Started Mar 21 02:36:34 PM PDT 24
Finished Mar 21 02:39:14 PM PDT 24
Peak memory 214356 kb
Host smart-9bb67fa3-5572-4016-934f-1ebb89299002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861795272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.861795272
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.297333611
Short name T904
Test name
Test status
Simulation time 2130247813 ps
CPU time 20.84 seconds
Started Mar 21 01:37:24 PM PDT 24
Finished Mar 21 01:37:46 PM PDT 24
Peak memory 211816 kb
Host smart-99055356-23cc-4bad-ade1-9cbf2606a0c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297333611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.297333611
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3180184914
Short name T928
Test name
Test status
Simulation time 506573814 ps
CPU time 11.69 seconds
Started Mar 21 02:36:11 PM PDT 24
Finished Mar 21 02:36:23 PM PDT 24
Peak memory 211296 kb
Host smart-115aea22-7481-47c4-97f0-1cf0b87c8a9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180184914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3180184914
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1502726605
Short name T755
Test name
Test status
Simulation time 1406954795 ps
CPU time 17.73 seconds
Started Mar 21 01:37:23 PM PDT 24
Finished Mar 21 01:37:41 PM PDT 24
Peak memory 211304 kb
Host smart-8b93d290-4295-49fa-b1b3-5bbeb83c9f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502726605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1502726605
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3002616120
Short name T740
Test name
Test status
Simulation time 636698022 ps
CPU time 8.97 seconds
Started Mar 21 02:36:17 PM PDT 24
Finished Mar 21 02:36:27 PM PDT 24
Peak memory 211304 kb
Host smart-24e1f9f8-49f7-44fc-8af4-5a07c227f230
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002616120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3002616120
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1527021545
Short name T714
Test name
Test status
Simulation time 989178787 ps
CPU time 17.76 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:36:28 PM PDT 24
Peak memory 212208 kb
Host smart-2eba1034-71ea-4c75-a68a-3fc559bceb42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527021545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1527021545
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.294149971
Short name T896
Test name
Test status
Simulation time 11215036640 ps
CPU time 30.52 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 212480 kb
Host smart-be107f26-c3e7-4e65-b01f-f838400292d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294149971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.294149971
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1528171509
Short name T836
Test name
Test status
Simulation time 1084990227 ps
CPU time 15.4 seconds
Started Mar 21 01:37:23 PM PDT 24
Finished Mar 21 01:37:38 PM PDT 24
Peak memory 216216 kb
Host smart-2b245dbb-bbe1-4341-a1ab-4d51cde96c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528171509 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1528171509
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3260926350
Short name T711
Test name
Test status
Simulation time 687039316 ps
CPU time 9.16 seconds
Started Mar 21 02:36:14 PM PDT 24
Finished Mar 21 02:36:24 PM PDT 24
Peak memory 217784 kb
Host smart-24585b4f-6cf9-4d55-8dca-ab301b99aac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260926350 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3260926350
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1608669388
Short name T919
Test name
Test status
Simulation time 5440928538 ps
CPU time 25.81 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:38:00 PM PDT 24
Peak memory 211696 kb
Host smart-590a3204-7011-4a99-bcfd-e0ba13ab23b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608669388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1608669388
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2939764979
Short name T809
Test name
Test status
Simulation time 3405681509 ps
CPU time 13.35 seconds
Started Mar 21 02:36:08 PM PDT 24
Finished Mar 21 02:36:21 PM PDT 24
Peak memory 212008 kb
Host smart-59d8be5e-0325-47c9-8238-37e6666b80bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939764979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2939764979
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1029879018
Short name T728
Test name
Test status
Simulation time 14090023312 ps
CPU time 27.98 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:38:05 PM PDT 24
Peak memory 211288 kb
Host smart-93d0bf93-88ee-4726-9694-e17264c240f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029879018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1029879018
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3891126136
Short name T749
Test name
Test status
Simulation time 16452217544 ps
CPU time 22.09 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:36:35 PM PDT 24
Peak memory 211352 kb
Host smart-74f50519-9ef9-4193-bc75-af6d0463ec38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891126136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3891126136
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2435055899
Short name T739
Test name
Test status
Simulation time 16360335893 ps
CPU time 23.39 seconds
Started Mar 21 01:37:21 PM PDT 24
Finished Mar 21 01:37:44 PM PDT 24
Peak memory 211260 kb
Host smart-14dee380-3c06-4b7d-8a51-82d0b0bca953
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435055899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2435055899
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.41529584
Short name T779
Test name
Test status
Simulation time 16417272967 ps
CPU time 30.18 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:36:45 PM PDT 24
Peak memory 211332 kb
Host smart-3c81a1c4-965f-4d02-aac8-af3150f7164f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41529584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.41529584
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3853853455
Short name T88
Test name
Test status
Simulation time 718514455 ps
CPU time 37.75 seconds
Started Mar 21 02:36:11 PM PDT 24
Finished Mar 21 02:36:48 PM PDT 24
Peak memory 213312 kb
Host smart-41b886cd-2d4c-4873-9970-6d234bc7f173
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853853455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3853853455
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3599800742
Short name T778
Test name
Test status
Simulation time 3831647681 ps
CPU time 29.11 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:51 PM PDT 24
Peak memory 211868 kb
Host smart-ae7174c3-1a11-4178-a245-b4bfcddbd52c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599800742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3599800742
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.815097695
Short name T932
Test name
Test status
Simulation time 363334775 ps
CPU time 12.18 seconds
Started Mar 21 02:36:12 PM PDT 24
Finished Mar 21 02:36:24 PM PDT 24
Peak memory 212616 kb
Host smart-3675d4ec-9069-4a8b-a68b-d21d1e682d88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815097695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.815097695
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1760663137
Short name T771
Test name
Test status
Simulation time 751311847 ps
CPU time 13.31 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:47 PM PDT 24
Peak memory 217476 kb
Host smart-3187be7a-2222-44c4-b89a-0df6521c2788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760663137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1760663137
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.288374655
Short name T909
Test name
Test status
Simulation time 4436414337 ps
CPU time 36.44 seconds
Started Mar 21 02:36:08 PM PDT 24
Finished Mar 21 02:36:45 PM PDT 24
Peak memory 219088 kb
Host smart-aa9393b2-fcd5-4ec7-b5fc-4b4e52a5a9fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288374655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.288374655
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2958896521
Short name T117
Test name
Test status
Simulation time 1286783588 ps
CPU time 161.78 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:38:52 PM PDT 24
Peak memory 214084 kb
Host smart-337a0338-f4b6-466a-8f12-e9e009eb4efe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958896521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2958896521
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4263640683
Short name T60
Test name
Test status
Simulation time 4304075585 ps
CPU time 104.45 seconds
Started Mar 21 01:37:24 PM PDT 24
Finished Mar 21 01:39:10 PM PDT 24
Peak memory 213872 kb
Host smart-26d59028-a601-43c4-a176-87dfdddbd371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263640683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4263640683
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1638188364
Short name T889
Test name
Test status
Simulation time 2894541862 ps
CPU time 25.35 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:48 PM PDT 24
Peak memory 211384 kb
Host smart-3480c3a6-0132-4369-8a83-1612afc2d9db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638188364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1638188364
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2313428921
Short name T854
Test name
Test status
Simulation time 8029720114 ps
CPU time 31.24 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:41 PM PDT 24
Peak memory 211804 kb
Host smart-1770c8ef-cafc-4ff0-90d5-978f36d2d8e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313428921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2313428921
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4098012544
Short name T741
Test name
Test status
Simulation time 1101648307 ps
CPU time 8.43 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:36:19 PM PDT 24
Peak memory 211300 kb
Host smart-d2d239b0-bb97-4b1d-9489-6715fe09d3a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098012544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4098012544
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.931034840
Short name T929
Test name
Test status
Simulation time 5677147645 ps
CPU time 25.95 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:38:01 PM PDT 24
Peak memory 212324 kb
Host smart-4f737b3f-024d-460a-89d7-47f788b2d73c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931034840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.931034840
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2149342295
Short name T912
Test name
Test status
Simulation time 12588109531 ps
CPU time 33.57 seconds
Started Mar 21 02:36:09 PM PDT 24
Finished Mar 21 02:36:44 PM PDT 24
Peak memory 212424 kb
Host smart-08c278e1-aabc-4de8-9a3c-12d682e6a64b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149342295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2149342295
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.558887786
Short name T862
Test name
Test status
Simulation time 2132811435 ps
CPU time 22.41 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:38:00 PM PDT 24
Peak memory 211728 kb
Host smart-61899bdb-042b-4282-a71e-e371aa729cf4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558887786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.558887786
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3383753230
Short name T868
Test name
Test status
Simulation time 15895167400 ps
CPU time 22.09 seconds
Started Mar 21 02:36:08 PM PDT 24
Finished Mar 21 02:36:30 PM PDT 24
Peak memory 216312 kb
Host smart-fa7f2adc-4496-4f3a-9b85-b2177de86c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383753230 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3383753230
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.647374841
Short name T895
Test name
Test status
Simulation time 2328454202 ps
CPU time 22.87 seconds
Started Mar 21 01:37:23 PM PDT 24
Finished Mar 21 01:37:46 PM PDT 24
Peak memory 217540 kb
Host smart-7a375440-aa87-42ff-af3b-cfbdd6314c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647374841 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.647374841
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.103962334
Short name T852
Test name
Test status
Simulation time 1814640897 ps
CPU time 19.46 seconds
Started Mar 21 01:37:21 PM PDT 24
Finished Mar 21 01:37:41 PM PDT 24
Peak memory 211916 kb
Host smart-976e6d0b-4127-49ef-ac93-2001995e0122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103962334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.103962334
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3390709275
Short name T823
Test name
Test status
Simulation time 331965867 ps
CPU time 8.33 seconds
Started Mar 21 02:36:17 PM PDT 24
Finished Mar 21 02:36:27 PM PDT 24
Peak memory 211292 kb
Host smart-6e4a57ce-e29b-4348-bed0-0e86ef660abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390709275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3390709275
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2357267923
Short name T745
Test name
Test status
Simulation time 1865355557 ps
CPU time 10.68 seconds
Started Mar 21 01:37:36 PM PDT 24
Finished Mar 21 01:37:47 PM PDT 24
Peak memory 211224 kb
Host smart-0f69833f-8ec7-45be-9c07-aed07fc9661d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357267923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2357267923
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3423023556
Short name T794
Test name
Test status
Simulation time 1610234784 ps
CPU time 18.38 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:28 PM PDT 24
Peak memory 211232 kb
Host smart-2b401ddc-5c96-4e8a-90fd-c5def841005c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423023556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3423023556
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2281862124
Short name T874
Test name
Test status
Simulation time 174492763 ps
CPU time 8.36 seconds
Started Mar 21 02:36:08 PM PDT 24
Finished Mar 21 02:36:16 PM PDT 24
Peak memory 211248 kb
Host smart-7b836fdc-951d-4b86-a900-d5ef096664c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281862124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2281862124
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2869504541
Short name T841
Test name
Test status
Simulation time 4050845517 ps
CPU time 31.29 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:54 PM PDT 24
Peak memory 211240 kb
Host smart-13aba12f-4a81-4b9e-99b4-43a390093261
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869504541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2869504541
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2743818301
Short name T811
Test name
Test status
Simulation time 110463529172 ps
CPU time 185.85 seconds
Started Mar 21 01:37:23 PM PDT 24
Finished Mar 21 01:40:29 PM PDT 24
Peak memory 215536 kb
Host smart-029026ad-6c2d-4863-9f27-75d81b286367
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743818301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2743818301
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.816800919
Short name T706
Test name
Test status
Simulation time 20235277189 ps
CPU time 174.24 seconds
Started Mar 21 02:36:13 PM PDT 24
Finished Mar 21 02:39:07 PM PDT 24
Peak memory 214460 kb
Host smart-1bd17747-da44-4fd5-b3e6-da1a08e5222e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816800919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.816800919
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1917610418
Short name T724
Test name
Test status
Simulation time 7574943386 ps
CPU time 23.47 seconds
Started Mar 21 01:37:24 PM PDT 24
Finished Mar 21 01:37:49 PM PDT 24
Peak memory 212700 kb
Host smart-776972e7-5452-4e08-b592-9e74e54546a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917610418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1917610418
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3290004776
Short name T840
Test name
Test status
Simulation time 5103414607 ps
CPU time 13.93 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:24 PM PDT 24
Peak memory 211656 kb
Host smart-f1d6d54e-5f09-4dd1-acc1-b09030038347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290004776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3290004776
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2087174853
Short name T817
Test name
Test status
Simulation time 15039953025 ps
CPU time 32.07 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:55 PM PDT 24
Peak memory 217496 kb
Host smart-7a0fb930-7fe1-49e1-9c82-0a3e7f03b21e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087174853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2087174853
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.533535627
Short name T861
Test name
Test status
Simulation time 17774070788 ps
CPU time 33.37 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:36:43 PM PDT 24
Peak memory 218944 kb
Host smart-a3bb3ea0-0580-4742-9346-6955b861134c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533535627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.533535627
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.331901800
Short name T884
Test name
Test status
Simulation time 5840270113 ps
CPU time 92.58 seconds
Started Mar 21 02:36:08 PM PDT 24
Finished Mar 21 02:37:41 PM PDT 24
Peak memory 213576 kb
Host smart-405a0792-6a7f-42f7-9acb-0ae94383d96f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331901800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.331901800
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3450369484
Short name T795
Test name
Test status
Simulation time 2985812425 ps
CPU time 95.14 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:39:13 PM PDT 24
Peak memory 214596 kb
Host smart-4d64061c-1a10-429e-9d7c-53b8b8c30b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450369484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3450369484
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3270155866
Short name T743
Test name
Test status
Simulation time 948544971 ps
CPU time 13.84 seconds
Started Mar 21 02:36:29 PM PDT 24
Finished Mar 21 02:36:44 PM PDT 24
Peak memory 211672 kb
Host smart-509d6be9-4924-4816-a4e7-8a7abbafb372
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270155866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3270155866
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3776475592
Short name T775
Test name
Test status
Simulation time 1076372671 ps
CPU time 9.79 seconds
Started Mar 21 01:37:26 PM PDT 24
Finished Mar 21 01:37:36 PM PDT 24
Peak memory 211268 kb
Host smart-cf113d75-0d5e-489d-ae96-f6028e5edf15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776475592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3776475592
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1945274754
Short name T742
Test name
Test status
Simulation time 4274712485 ps
CPU time 15.25 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:37:52 PM PDT 24
Peak memory 211348 kb
Host smart-c75fd7fb-e296-40d4-9f77-ac6e4ff468ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945274754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1945274754
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2275516626
Short name T930
Test name
Test status
Simulation time 332444806 ps
CPU time 8.52 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:36:31 PM PDT 24
Peak memory 211332 kb
Host smart-a62a545d-1aa1-4bfa-998b-712cadfcab84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275516626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2275516626
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1862423137
Short name T925
Test name
Test status
Simulation time 1560311345 ps
CPU time 21.23 seconds
Started Mar 21 02:36:28 PM PDT 24
Finished Mar 21 02:36:51 PM PDT 24
Peak memory 211456 kb
Host smart-8e52dcb9-e8c6-44bc-9630-24f4ee85dc1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862423137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1862423137
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3591392966
Short name T781
Test name
Test status
Simulation time 9819835709 ps
CPU time 30.78 seconds
Started Mar 21 01:37:39 PM PDT 24
Finished Mar 21 01:38:10 PM PDT 24
Peak memory 211968 kb
Host smart-cf9a2b7d-8d11-4a03-93d1-4a6ede03e283
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591392966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3591392966
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.113191605
Short name T761
Test name
Test status
Simulation time 590629908 ps
CPU time 11.97 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:37:49 PM PDT 24
Peak memory 213784 kb
Host smart-14291087-0232-4eb2-979d-196491af95dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113191605 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.113191605
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2841085901
Short name T783
Test name
Test status
Simulation time 3415129773 ps
CPU time 28.11 seconds
Started Mar 21 02:36:29 PM PDT 24
Finished Mar 21 02:36:58 PM PDT 24
Peak memory 217192 kb
Host smart-c13f78a7-d490-4aca-b066-3dd9f769d452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841085901 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2841085901
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1693967287
Short name T876
Test name
Test status
Simulation time 1540550996 ps
CPU time 13.09 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:37:35 PM PDT 24
Peak memory 211304 kb
Host smart-c47abfd3-d73d-4ce3-b3dc-d52c5e331e22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693967287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1693967287
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.317507442
Short name T758
Test name
Test status
Simulation time 4006761446 ps
CPU time 29.4 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:36:49 PM PDT 24
Peak memory 211760 kb
Host smart-fd555189-9869-4d7e-875d-14aef589628b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317507442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.317507442
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2370671629
Short name T696
Test name
Test status
Simulation time 6414046941 ps
CPU time 27.43 seconds
Started Mar 21 01:37:24 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 211328 kb
Host smart-71bd8312-c6d1-451c-b813-be37add38da3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370671629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2370671629
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3208009658
Short name T860
Test name
Test status
Simulation time 687717380 ps
CPU time 8.25 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:36:30 PM PDT 24
Peak memory 211212 kb
Host smart-2969f59f-d8ed-43bf-aaf1-d52b78fead38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208009658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3208009658
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.173155750
Short name T899
Test name
Test status
Simulation time 661427857 ps
CPU time 7.87 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:37:42 PM PDT 24
Peak memory 211172 kb
Host smart-e6bfd787-e7b9-4750-bd6a-0e7f7d0e712b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173155750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
173155750
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1969987392
Short name T698
Test name
Test status
Simulation time 688554955 ps
CPU time 8.08 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:36:29 PM PDT 24
Peak memory 211260 kb
Host smart-1bf2d1ad-09bc-4083-9577-1ef0c8ec385b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969987392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1969987392
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.138397180
Short name T770
Test name
Test status
Simulation time 24574381247 ps
CPU time 104.52 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:39:18 PM PDT 24
Peak memory 214504 kb
Host smart-ab3d29e4-b9fd-4e3a-a30d-dcf970a3cc06
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138397180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.138397180
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1682440628
Short name T89
Test name
Test status
Simulation time 18395643068 ps
CPU time 97.15 seconds
Started Mar 21 02:36:10 PM PDT 24
Finished Mar 21 02:37:48 PM PDT 24
Peak memory 214436 kb
Host smart-bc00bca1-7bc2-4e53-b0bf-ca8a3e9c017c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682440628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1682440628
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2210103035
Short name T927
Test name
Test status
Simulation time 2842250130 ps
CPU time 20.84 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:36:41 PM PDT 24
Peak memory 212608 kb
Host smart-54b08c5d-abca-44fa-bb5f-e42606201052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210103035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2210103035
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2303366956
Short name T63
Test name
Test status
Simulation time 972279682 ps
CPU time 8.26 seconds
Started Mar 21 01:37:26 PM PDT 24
Finished Mar 21 01:37:35 PM PDT 24
Peak memory 211268 kb
Host smart-622fb8a9-a9b4-45a2-b03b-d5607987c349
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303366956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2303366956
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1871405205
Short name T691
Test name
Test status
Simulation time 2884794087 ps
CPU time 26.44 seconds
Started Mar 21 01:37:30 PM PDT 24
Finished Mar 21 01:37:57 PM PDT 24
Peak memory 218156 kb
Host smart-8f75ebd9-5da8-4ffe-adc4-dfab9c179c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871405205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1871405205
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2378556883
Short name T827
Test name
Test status
Simulation time 3886302218 ps
CPU time 34.3 seconds
Started Mar 21 02:36:12 PM PDT 24
Finished Mar 21 02:36:47 PM PDT 24
Peak memory 217264 kb
Host smart-e7c6484b-93d7-43c9-9d53-1536d98ff242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378556883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2378556883
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3104377591
Short name T882
Test name
Test status
Simulation time 3062130948 ps
CPU time 89.48 seconds
Started Mar 21 01:37:22 PM PDT 24
Finished Mar 21 01:38:52 PM PDT 24
Peak memory 213320 kb
Host smart-7a47d033-e4a9-49c2-9bce-06b8a686199d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104377591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3104377591
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.514352979
Short name T123
Test name
Test status
Simulation time 7447070701 ps
CPU time 91.27 seconds
Started Mar 21 02:36:24 PM PDT 24
Finished Mar 21 02:37:56 PM PDT 24
Peak memory 213976 kb
Host smart-75c29e4b-799f-465b-9b1c-ba1e2fed5c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514352979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.514352979
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4072134670
Short name T826
Test name
Test status
Simulation time 434373289 ps
CPU time 11.82 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:36:33 PM PDT 24
Peak memory 216200 kb
Host smart-cec9852e-c8aa-412d-af24-7eb1b4801759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072134670 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4072134670
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.778717341
Short name T808
Test name
Test status
Simulation time 1628525223 ps
CPU time 17.56 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:37:49 PM PDT 24
Peak memory 216256 kb
Host smart-19dcc531-d6d1-4ad2-99a0-aba55363e66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778717341 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.778717341
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1834566661
Short name T87
Test name
Test status
Simulation time 3929505098 ps
CPU time 14.39 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:36:37 PM PDT 24
Peak memory 211340 kb
Host smart-bba00497-7a47-495e-99b2-3ef39d7d2aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834566661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1834566661
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3776365760
Short name T807
Test name
Test status
Simulation time 1032330919 ps
CPU time 9.89 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:37:41 PM PDT 24
Peak memory 211264 kb
Host smart-b0e4278a-7ad8-4d44-a4d6-7e66cc2f5eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776365760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3776365760
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4241169623
Short name T710
Test name
Test status
Simulation time 1648896508 ps
CPU time 37.79 seconds
Started Mar 21 01:37:37 PM PDT 24
Finished Mar 21 01:38:15 PM PDT 24
Peak memory 213360 kb
Host smart-eb7c2540-be2a-4de1-8345-f3cd066d15a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241169623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4241169623
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.56696894
Short name T765
Test name
Test status
Simulation time 95690315367 ps
CPU time 152.84 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:38:56 PM PDT 24
Peak memory 215564 kb
Host smart-c74b087d-a8db-4c19-b09c-cd1dc3f90017
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56696894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pass
thru_mem_tl_intg_err.56696894
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4138588213
Short name T782
Test name
Test status
Simulation time 7603387015 ps
CPU time 20.53 seconds
Started Mar 21 01:37:30 PM PDT 24
Finished Mar 21 01:37:51 PM PDT 24
Peak memory 211476 kb
Host smart-6345e589-2d59-492f-822d-1cbb20f5187f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138588213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4138588213
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.433090651
Short name T818
Test name
Test status
Simulation time 345961594 ps
CPU time 8.06 seconds
Started Mar 21 02:36:27 PM PDT 24
Finished Mar 21 02:36:36 PM PDT 24
Peak memory 211284 kb
Host smart-e52e2157-677a-4cc5-ac00-1d0fb434bef3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433090651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.433090651
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2377076597
Short name T877
Test name
Test status
Simulation time 8096621944 ps
CPU time 34.39 seconds
Started Mar 21 02:36:28 PM PDT 24
Finished Mar 21 02:37:03 PM PDT 24
Peak memory 218840 kb
Host smart-f86427aa-f342-4240-b7b4-8fa8a6ace35b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377076597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2377076597
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.858548132
Short name T858
Test name
Test status
Simulation time 11168213866 ps
CPU time 29.98 seconds
Started Mar 21 01:37:24 PM PDT 24
Finished Mar 21 01:37:55 PM PDT 24
Peak memory 219028 kb
Host smart-834ee80e-6190-4aa9-b792-0fdb33e4ff18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858548132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.858548132
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1849320285
Short name T842
Test name
Test status
Simulation time 3207708310 ps
CPU time 166.1 seconds
Started Mar 21 01:37:38 PM PDT 24
Finished Mar 21 01:40:24 PM PDT 24
Peak memory 213996 kb
Host smart-c5142b38-08c3-4f10-a7c2-cef81a3708fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849320285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1849320285
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3052921774
Short name T762
Test name
Test status
Simulation time 948065587 ps
CPU time 81.75 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:37:42 PM PDT 24
Peak memory 213668 kb
Host smart-5a64e7bd-1293-420e-9ac2-dda3ebbd689a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052921774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3052921774
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1020739794
Short name T695
Test name
Test status
Simulation time 2498950968 ps
CPU time 9.71 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:36:31 PM PDT 24
Peak memory 213904 kb
Host smart-10b8dd62-c328-424e-a14d-14a6c4c7af15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020739794 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1020739794
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1522377235
Short name T754
Test name
Test status
Simulation time 17808644935 ps
CPU time 24.25 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:37:59 PM PDT 24
Peak memory 219080 kb
Host smart-6a89f4d1-92c1-4257-a946-8ebd46fedc6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522377235 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1522377235
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2274404385
Short name T859
Test name
Test status
Simulation time 338981419 ps
CPU time 8.27 seconds
Started Mar 21 02:36:27 PM PDT 24
Finished Mar 21 02:36:36 PM PDT 24
Peak memory 211316 kb
Host smart-4527d250-2289-41e6-8c78-8da6412a9220
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274404385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2274404385
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.426990706
Short name T885
Test name
Test status
Simulation time 4830348153 ps
CPU time 22.54 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 211588 kb
Host smart-6b381b38-8740-4b36-9715-4b7db2c195a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426990706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.426990706
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2365375219
Short name T898
Test name
Test status
Simulation time 163802393609 ps
CPU time 201.01 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:40:54 PM PDT 24
Peak memory 215472 kb
Host smart-111bc027-82b7-4ef7-973f-7acece3f2de3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365375219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2365375219
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.658001300
Short name T791
Test name
Test status
Simulation time 25815360675 ps
CPU time 75.4 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:37:37 PM PDT 24
Peak memory 213424 kb
Host smart-1cb8ab15-4b8f-4046-9707-4e8a03a43873
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658001300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.658001300
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2427197521
Short name T863
Test name
Test status
Simulation time 5070021037 ps
CPU time 16.89 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:37:49 PM PDT 24
Peak memory 211372 kb
Host smart-38b0d7c7-8175-431f-8a64-686b87ec4f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427197521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2427197521
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4194410168
Short name T821
Test name
Test status
Simulation time 12723816534 ps
CPU time 30.36 seconds
Started Mar 21 02:36:26 PM PDT 24
Finished Mar 21 02:36:58 PM PDT 24
Peak memory 212652 kb
Host smart-6f3643d6-6e32-4d63-aeee-aa2f72bcf6e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194410168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4194410168
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1375779110
Short name T923
Test name
Test status
Simulation time 1611162500 ps
CPU time 22.32 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 218432 kb
Host smart-d93d7cde-8b5f-4121-b168-70b9ea654380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375779110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1375779110
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1543598368
Short name T753
Test name
Test status
Simulation time 46521531717 ps
CPU time 32.26 seconds
Started Mar 21 02:36:28 PM PDT 24
Finished Mar 21 02:37:01 PM PDT 24
Peak memory 218980 kb
Host smart-66d263c8-ff01-4e21-8868-1700541726ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543598368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1543598368
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.482501873
Short name T120
Test name
Test status
Simulation time 13557186698 ps
CPU time 166.69 seconds
Started Mar 21 02:36:27 PM PDT 24
Finished Mar 21 02:39:14 PM PDT 24
Peak memory 214176 kb
Host smart-381bea2e-4661-457a-ace4-ad8868b4c76d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482501873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.482501873
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.569510239
Short name T828
Test name
Test status
Simulation time 305798509 ps
CPU time 83.94 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:38:56 PM PDT 24
Peak memory 213548 kb
Host smart-d3946af2-524b-4e63-a939-c53230caae21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569510239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.569510239
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3274775700
Short name T910
Test name
Test status
Simulation time 2371340695 ps
CPU time 17.23 seconds
Started Mar 21 02:36:27 PM PDT 24
Finished Mar 21 02:36:45 PM PDT 24
Peak memory 217272 kb
Host smart-e2e7eaa0-2180-4053-84c2-318ca30fee97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274775700 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3274775700
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.341163285
Short name T763
Test name
Test status
Simulation time 3271248569 ps
CPU time 12.1 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:37:43 PM PDT 24
Peak memory 216180 kb
Host smart-31d9c579-a78e-43b3-986b-866a93bfea84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341163285 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.341163285
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4102067300
Short name T788
Test name
Test status
Simulation time 3621059824 ps
CPU time 29.4 seconds
Started Mar 21 02:36:29 PM PDT 24
Finished Mar 21 02:36:59 PM PDT 24
Peak memory 212088 kb
Host smart-b5a45908-c70b-47b2-be0f-71b8e441b14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102067300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4102067300
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.422386895
Short name T74
Test name
Test status
Simulation time 15289604525 ps
CPU time 22.56 seconds
Started Mar 21 01:37:30 PM PDT 24
Finished Mar 21 01:37:53 PM PDT 24
Peak memory 212300 kb
Host smart-fa510f1c-790e-4a78-9626-82f34b7d14bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422386895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.422386895
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2951156155
Short name T75
Test name
Test status
Simulation time 2857774455 ps
CPU time 37.09 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:38:10 PM PDT 24
Peak memory 213732 kb
Host smart-3970563f-33f3-4b62-828c-35270f8bb846
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951156155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2951156155
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.978801467
Short name T83
Test name
Test status
Simulation time 10345827605 ps
CPU time 120.83 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:38:22 PM PDT 24
Peak memory 215796 kb
Host smart-846d072c-3903-4fe8-8597-c91a7839c8e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978801467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.978801467
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1281632538
Short name T887
Test name
Test status
Simulation time 3471276393 ps
CPU time 29.34 seconds
Started Mar 21 02:36:30 PM PDT 24
Finished Mar 21 02:37:00 PM PDT 24
Peak memory 212416 kb
Host smart-b3828e28-af3e-4451-9db7-430414098821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281632538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1281632538
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.866937973
Short name T865
Test name
Test status
Simulation time 7689000613 ps
CPU time 31.62 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:38:06 PM PDT 24
Peak memory 212220 kb
Host smart-36aae36f-e6c0-49bd-94e3-b70e20d8af6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866937973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.866937973
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1114332956
Short name T709
Test name
Test status
Simulation time 11974916707 ps
CPU time 30.3 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:38:01 PM PDT 24
Peak memory 217896 kb
Host smart-60c50ef2-eae9-40fb-930f-fc541f292e21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114332956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1114332956
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3097133352
Short name T875
Test name
Test status
Simulation time 7090946862 ps
CPU time 32.97 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:36:55 PM PDT 24
Peak memory 218744 kb
Host smart-dcee1b11-77ef-49b4-af3c-267eccd74cca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097133352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3097133352
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2885688574
Short name T832
Test name
Test status
Simulation time 1218854532 ps
CPU time 156.14 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:38:59 PM PDT 24
Peak memory 214152 kb
Host smart-e01021c0-b80b-41d0-a3ce-9fa53a1a2b47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885688574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2885688574
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4294777222
Short name T926
Test name
Test status
Simulation time 4570691866 ps
CPU time 175.67 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:40:27 PM PDT 24
Peak memory 214356 kb
Host smart-f43daf26-b05d-41f6-bc52-b600136e2458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294777222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4294777222
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2997807689
Short name T721
Test name
Test status
Simulation time 13512791234 ps
CPU time 29.67 seconds
Started Mar 21 02:36:31 PM PDT 24
Finished Mar 21 02:37:01 PM PDT 24
Peak memory 215672 kb
Host smart-d8dba0fc-58fe-41ac-9108-39dd283b64e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997807689 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2997807689
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3532329843
Short name T894
Test name
Test status
Simulation time 17788203162 ps
CPU time 17 seconds
Started Mar 21 01:37:29 PM PDT 24
Finished Mar 21 01:37:46 PM PDT 24
Peak memory 218128 kb
Host smart-09e2e281-0db2-4876-9b53-7b7c2f131b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532329843 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3532329843
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1277163362
Short name T822
Test name
Test status
Simulation time 2663139296 ps
CPU time 16.57 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:37:47 PM PDT 24
Peak memory 211764 kb
Host smart-02e67216-8167-41ad-8afc-aa0007d79770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277163362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1277163362
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2813273686
Short name T731
Test name
Test status
Simulation time 16925490734 ps
CPU time 31.29 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:36:54 PM PDT 24
Peak memory 212472 kb
Host smart-514851a9-f9de-4a02-8330-af000d5d12a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813273686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2813273686
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2872052270
Short name T750
Test name
Test status
Simulation time 10830000314 ps
CPU time 101.39 seconds
Started Mar 21 02:36:22 PM PDT 24
Finished Mar 21 02:38:04 PM PDT 24
Peak memory 214820 kb
Host smart-d84e3c7a-9608-4e49-9ff1-33200cd05762
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872052270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2872052270
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.445460616
Short name T104
Test name
Test status
Simulation time 40253992639 ps
CPU time 120.79 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:39:34 PM PDT 24
Peak memory 214464 kb
Host smart-745f9266-4e9e-43e7-943e-5fbfe3302753
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445460616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.445460616
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3237360353
Short name T813
Test name
Test status
Simulation time 249272677 ps
CPU time 10.14 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:43 PM PDT 24
Peak memory 211300 kb
Host smart-e43dc42f-6198-483a-b607-03ef87d8dd31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237360353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3237360353
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.586911839
Short name T105
Test name
Test status
Simulation time 2288359216 ps
CPU time 21.36 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:36:41 PM PDT 24
Peak memory 212448 kb
Host smart-6d673673-60cc-444d-b0a3-18487de6fa9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586911839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.586911839
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2898589994
Short name T704
Test name
Test status
Simulation time 5786541864 ps
CPU time 29.57 seconds
Started Mar 21 02:36:24 PM PDT 24
Finished Mar 21 02:36:53 PM PDT 24
Peak memory 217976 kb
Host smart-7ca459d7-c4ae-4613-ae30-421d3794c21d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898589994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2898589994
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3698008923
Short name T726
Test name
Test status
Simulation time 7861041599 ps
CPU time 23.15 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:57 PM PDT 24
Peak memory 217436 kb
Host smart-61726a3f-1877-4436-898e-fec8a31902ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698008923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3698008923
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2998454601
Short name T124
Test name
Test status
Simulation time 7791818163 ps
CPU time 93.73 seconds
Started Mar 21 02:36:27 PM PDT 24
Finished Mar 21 02:38:01 PM PDT 24
Peak memory 213676 kb
Host smart-ad8667f4-36e7-4d95-92c2-c893ac2cbe12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998454601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2998454601
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.440401972
Short name T121
Test name
Test status
Simulation time 2172121099 ps
CPU time 93.03 seconds
Started Mar 21 01:37:34 PM PDT 24
Finished Mar 21 01:39:07 PM PDT 24
Peak memory 213312 kb
Host smart-c65eea61-e619-407d-98fb-0b01cf99160e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440401972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.440401972
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3130238660
Short name T908
Test name
Test status
Simulation time 6161265908 ps
CPU time 27.28 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:36:48 PM PDT 24
Peak memory 219008 kb
Host smart-7c39cdd8-0f39-4f4e-b214-9bf6a0759c6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130238660 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3130238660
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.848219377
Short name T787
Test name
Test status
Simulation time 5145714462 ps
CPU time 22.27 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:37:54 PM PDT 24
Peak memory 218644 kb
Host smart-0ff1547d-c1b3-4d40-a476-d5e50e02c250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848219377 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.848219377
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1628276093
Short name T789
Test name
Test status
Simulation time 390411876 ps
CPU time 10.24 seconds
Started Mar 21 02:36:23 PM PDT 24
Finished Mar 21 02:36:33 PM PDT 24
Peak memory 211284 kb
Host smart-7467f183-19b0-4925-a209-72a74e988592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628276093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1628276093
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4147351639
Short name T796
Test name
Test status
Simulation time 2143662085 ps
CPU time 21.71 seconds
Started Mar 21 01:37:33 PM PDT 24
Finished Mar 21 01:37:54 PM PDT 24
Peak memory 212016 kb
Host smart-71baf3b2-4a53-4506-a760-a8ca3d499cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147351639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4147351639
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1115486481
Short name T922
Test name
Test status
Simulation time 21698374484 ps
CPU time 185.23 seconds
Started Mar 21 02:36:21 PM PDT 24
Finished Mar 21 02:39:26 PM PDT 24
Peak memory 215860 kb
Host smart-73db068a-0141-41f0-8f66-dceea7366d92
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115486481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1115486481
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1604612269
Short name T866
Test name
Test status
Simulation time 67170178032 ps
CPU time 156.54 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:40:09 PM PDT 24
Peak memory 215556 kb
Host smart-5acc5f2b-e5af-4dd8-b6c8-5dcf5c4e5131
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604612269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1604612269
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3582722516
Short name T888
Test name
Test status
Simulation time 338729600 ps
CPU time 8.17 seconds
Started Mar 21 02:36:27 PM PDT 24
Finished Mar 21 02:36:36 PM PDT 24
Peak memory 211384 kb
Host smart-333d506d-1447-4c1f-81af-c41f7f98470f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582722516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3582722516
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.390275833
Short name T71
Test name
Test status
Simulation time 2783724720 ps
CPU time 26.01 seconds
Started Mar 21 01:37:32 PM PDT 24
Finished Mar 21 01:37:58 PM PDT 24
Peak memory 211984 kb
Host smart-4c842cad-70cd-499d-ab1e-3609f805e0ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390275833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.390275833
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1064575444
Short name T703
Test name
Test status
Simulation time 21283147823 ps
CPU time 30.2 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:36:50 PM PDT 24
Peak memory 218840 kb
Host smart-8197a144-8244-465a-8baf-8da432b13809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064575444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1064575444
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3600935697
Short name T856
Test name
Test status
Simulation time 6097647069 ps
CPU time 30.06 seconds
Started Mar 21 01:37:30 PM PDT 24
Finished Mar 21 01:38:01 PM PDT 24
Peak memory 217884 kb
Host smart-02cf4335-0c03-47d7-bc36-6618b2b98831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600935697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3600935697
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3463085439
Short name T116
Test name
Test status
Simulation time 3828046045 ps
CPU time 101.02 seconds
Started Mar 21 02:36:20 PM PDT 24
Finished Mar 21 02:38:01 PM PDT 24
Peak memory 213708 kb
Host smart-dc69f364-3e2a-4146-8c4b-8178c00306ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463085439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3463085439
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3863576017
Short name T921
Test name
Test status
Simulation time 466889603 ps
CPU time 80.86 seconds
Started Mar 21 01:37:31 PM PDT 24
Finished Mar 21 01:38:52 PM PDT 24
Peak memory 212668 kb
Host smart-1b881e44-593c-48ac-97db-9d2bf87c3511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863576017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3863576017
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1724539319
Short name T487
Test name
Test status
Simulation time 2006016433 ps
CPU time 10.83 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:20:59 PM PDT 24
Peak memory 210900 kb
Host smart-a4726b73-7931-4836-8bf5-da2ba1d0a6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724539319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1724539319
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.533013476
Short name T658
Test name
Test status
Simulation time 174962343 ps
CPU time 4.6 seconds
Started Mar 21 01:35:45 PM PDT 24
Finished Mar 21 01:35:50 PM PDT 24
Peak memory 210768 kb
Host smart-79461aa2-631c-49f9-bf87-8c63729e1a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533013476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.533013476
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.156662939
Short name T471
Test name
Test status
Simulation time 1305156754 ps
CPU time 83.96 seconds
Started Mar 21 01:35:36 PM PDT 24
Finished Mar 21 01:37:05 PM PDT 24
Peak memory 229492 kb
Host smart-6d0de005-095e-4018-9967-f1b7594210f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156662939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.156662939
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3678030882
Short name T466
Test name
Test status
Simulation time 23904731651 ps
CPU time 234.42 seconds
Started Mar 21 03:20:50 PM PDT 24
Finished Mar 21 03:24:45 PM PDT 24
Peak memory 236540 kb
Host smart-cf00d4c0-5aaf-4737-980f-41c69abda781
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678030882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3678030882
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.233000331
Short name T485
Test name
Test status
Simulation time 3527018781 ps
CPU time 13.31 seconds
Started Mar 21 01:35:33 PM PDT 24
Finished Mar 21 01:35:46 PM PDT 24
Peak memory 211428 kb
Host smart-fedaf2c7-9018-4d03-90c3-145a660048da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233000331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.233000331
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.450731087
Short name T529
Test name
Test status
Simulation time 304576720 ps
CPU time 5.33 seconds
Started Mar 21 03:20:52 PM PDT 24
Finished Mar 21 03:20:57 PM PDT 24
Peak memory 210856 kb
Host smart-04de786c-97b8-49cf-ab09-324d5f83ed13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450731087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.450731087
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.704828076
Short name T225
Test name
Test status
Simulation time 1835367907 ps
CPU time 14.72 seconds
Started Mar 21 01:35:46 PM PDT 24
Finished Mar 21 01:36:01 PM PDT 24
Peak memory 210776 kb
Host smart-9bf3fd55-0984-497b-ad6c-60dfad28ca4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704828076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.704828076
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.626309321
Short name T41
Test name
Test status
Simulation time 11217601553 ps
CPU time 63.55 seconds
Started Mar 21 01:35:43 PM PDT 24
Finished Mar 21 01:36:46 PM PDT 24
Peak memory 233388 kb
Host smart-7c8286a9-0883-4cbd-8c56-2bc0d13f54dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626309321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.626309321
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1456000314
Short name T262
Test name
Test status
Simulation time 2112740635 ps
CPU time 21.99 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:21:10 PM PDT 24
Peak memory 213228 kb
Host smart-13b4e0a1-f32e-4ba0-921a-9c08f8f5c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456000314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1456000314
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2579412684
Short name T425
Test name
Test status
Simulation time 2703184654 ps
CPU time 19.75 seconds
Started Mar 21 01:35:35 PM PDT 24
Finished Mar 21 01:35:56 PM PDT 24
Peak memory 211556 kb
Host smart-4650d05b-6590-4bff-b61a-3531cc2a4b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579412684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2579412684
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1838401617
Short name T579
Test name
Test status
Simulation time 3436026969 ps
CPU time 45.9 seconds
Started Mar 21 03:20:50 PM PDT 24
Finished Mar 21 03:21:36 PM PDT 24
Peak memory 215888 kb
Host smart-98728d9b-9316-481b-84f1-e24728112ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838401617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1838401617
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4111641654
Short name T680
Test name
Test status
Simulation time 12514373566 ps
CPU time 73.71 seconds
Started Mar 21 01:35:37 PM PDT 24
Finished Mar 21 01:36:51 PM PDT 24
Peak memory 216684 kb
Host smart-78126a76-1191-493d-9a31-71946210ad0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111641654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4111641654
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3478400371
Short name T625
Test name
Test status
Simulation time 63781351517 ps
CPU time 2358.48 seconds
Started Mar 21 01:35:41 PM PDT 24
Finished Mar 21 02:15:01 PM PDT 24
Peak memory 238392 kb
Host smart-ea86ffa1-2386-4339-9553-565bb7ba9f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478400371 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3478400371
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4014673993
Short name T526
Test name
Test status
Simulation time 13517284108 ps
CPU time 535.1 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:29:43 PM PDT 24
Peak memory 227424 kb
Host smart-20f613e1-9e6d-417e-9182-d25e64b842b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014673993 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4014673993
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2868529319
Short name T206
Test name
Test status
Simulation time 168342566 ps
CPU time 4.1 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:20:53 PM PDT 24
Peak memory 210864 kb
Host smart-73613665-4681-4aae-a5cc-2e8b1fc0e903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868529319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2868529319
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4170512040
Short name T467
Test name
Test status
Simulation time 813492479 ps
CPU time 9.43 seconds
Started Mar 21 01:35:50 PM PDT 24
Finished Mar 21 01:36:00 PM PDT 24
Peak memory 210672 kb
Host smart-c7b80a7e-7662-4416-b98c-51c62edb3f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170512040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4170512040
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1628524055
Short name T266
Test name
Test status
Simulation time 10272651021 ps
CPU time 85.42 seconds
Started Mar 21 01:35:50 PM PDT 24
Finished Mar 21 01:37:16 PM PDT 24
Peak memory 229300 kb
Host smart-361f5965-dbac-4394-b811-161c0668da4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628524055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1628524055
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.718963801
Short name T204
Test name
Test status
Simulation time 60379483787 ps
CPU time 279.84 seconds
Started Mar 21 03:20:53 PM PDT 24
Finished Mar 21 03:25:33 PM PDT 24
Peak memory 220272 kb
Host smart-81b6f055-f041-471e-ae34-c92109e7a258
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718963801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.718963801
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2833967566
Short name T414
Test name
Test status
Simulation time 175446113 ps
CPU time 9.45 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:20:58 PM PDT 24
Peak memory 211612 kb
Host smart-b65f9d8c-ac82-4969-833c-397e824f8766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833967566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2833967566
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1703622340
Short name T551
Test name
Test status
Simulation time 1007436624 ps
CPU time 11.4 seconds
Started Mar 21 03:20:50 PM PDT 24
Finished Mar 21 03:21:02 PM PDT 24
Peak memory 211140 kb
Host smart-0bf8041d-7e05-402f-8cee-751c6075633a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703622340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1703622340
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2073909963
Short name T221
Test name
Test status
Simulation time 1106182259 ps
CPU time 11.41 seconds
Started Mar 21 01:35:44 PM PDT 24
Finished Mar 21 01:35:57 PM PDT 24
Peak memory 210772 kb
Host smart-179b0e3f-8055-4b0b-8083-b426462939ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073909963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2073909963
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.709067983
Short name T29
Test name
Test status
Simulation time 807104699 ps
CPU time 101.75 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:22:30 PM PDT 24
Peak memory 233428 kb
Host smart-6321f9b9-b6f7-40bd-998d-33218e3092e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709067983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.709067983
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.787084440
Short name T35
Test name
Test status
Simulation time 3900366182 ps
CPU time 103.47 seconds
Started Mar 21 01:35:50 PM PDT 24
Finished Mar 21 01:37:33 PM PDT 24
Peak memory 229888 kb
Host smart-f21114a2-fc3f-48b9-818e-66bb5d850de7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787084440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.787084440
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4107381270
Short name T470
Test name
Test status
Simulation time 713931237 ps
CPU time 9.85 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:20:59 PM PDT 24
Peak memory 219132 kb
Host smart-60e61020-006b-42c1-a54c-46a7a80da015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107381270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4107381270
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.900834768
Short name T541
Test name
Test status
Simulation time 1943204192 ps
CPU time 22.02 seconds
Started Mar 21 01:35:51 PM PDT 24
Finished Mar 21 01:36:13 PM PDT 24
Peak memory 212500 kb
Host smart-ffafd6fb-a77b-4fdc-9512-ac1e646cda7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900834768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.900834768
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1456215609
Short name T677
Test name
Test status
Simulation time 30273990380 ps
CPU time 59.19 seconds
Started Mar 21 03:20:47 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 217276 kb
Host smart-02d2a1d1-76de-4db8-85d6-5d6bc26a6210
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456215609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1456215609
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2583343454
Short name T354
Test name
Test status
Simulation time 26430161183 ps
CPU time 93.91 seconds
Started Mar 21 01:35:36 PM PDT 24
Finished Mar 21 01:37:10 PM PDT 24
Peak memory 219016 kb
Host smart-ad5c720b-ac01-4f6f-a51d-66565ed39fca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583343454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2583343454
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2727143410
Short name T113
Test name
Test status
Simulation time 20970700124 ps
CPU time 403.65 seconds
Started Mar 21 01:35:46 PM PDT 24
Finished Mar 21 01:42:30 PM PDT 24
Peak memory 223380 kb
Host smart-da302284-1023-4aef-a11c-1615a2811dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727143410 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2727143410
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2003371043
Short name T285
Test name
Test status
Simulation time 5264094179 ps
CPU time 12.58 seconds
Started Mar 21 01:36:01 PM PDT 24
Finished Mar 21 01:36:14 PM PDT 24
Peak memory 210900 kb
Host smart-e52ce56e-7568-47e3-9544-2125aeb9f1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003371043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2003371043
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3221016484
Short name T183
Test name
Test status
Simulation time 333896822 ps
CPU time 4.1 seconds
Started Mar 21 03:21:22 PM PDT 24
Finished Mar 21 03:21:26 PM PDT 24
Peak memory 210888 kb
Host smart-aded850c-494d-4d52-bd3f-b72d79a506bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221016484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3221016484
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1617464290
Short name T164
Test name
Test status
Simulation time 106761366068 ps
CPU time 264.73 seconds
Started Mar 21 03:21:06 PM PDT 24
Finished Mar 21 03:25:31 PM PDT 24
Peak memory 229288 kb
Host smart-a2fcfa50-d3b8-47ea-81db-6cc1057a82a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617464290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1617464290
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3550304879
Short name T593
Test name
Test status
Simulation time 97539624027 ps
CPU time 261.95 seconds
Started Mar 21 01:36:04 PM PDT 24
Finished Mar 21 01:40:28 PM PDT 24
Peak memory 236388 kb
Host smart-5caad17c-b688-49cd-97bd-b0e7d1c38d21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550304879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3550304879
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2401612207
Short name T362
Test name
Test status
Simulation time 6912202857 ps
CPU time 31.12 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:36:34 PM PDT 24
Peak memory 211696 kb
Host smart-860fb3fe-c1f5-4072-b7ac-7a40787c81d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401612207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2401612207
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.561914131
Short name T611
Test name
Test status
Simulation time 15376323482 ps
CPU time 32.12 seconds
Started Mar 21 03:21:19 PM PDT 24
Finished Mar 21 03:21:51 PM PDT 24
Peak memory 211844 kb
Host smart-36256fa8-fab5-4338-b005-d8cebe0fa670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561914131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.561914131
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1192925851
Short name T451
Test name
Test status
Simulation time 2233412975 ps
CPU time 12.24 seconds
Started Mar 21 03:21:06 PM PDT 24
Finished Mar 21 03:21:19 PM PDT 24
Peak memory 210896 kb
Host smart-e2e5833c-f1a5-40d2-a713-60c07537b3cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192925851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1192925851
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3815115470
Short name T640
Test name
Test status
Simulation time 735389667 ps
CPU time 6.84 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:36:13 PM PDT 24
Peak memory 210736 kb
Host smart-b3bdf9eb-6a20-42eb-8a10-fd352db4080c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815115470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3815115470
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3678183399
Short name T578
Test name
Test status
Simulation time 348730204 ps
CPU time 9.77 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:18 PM PDT 24
Peak memory 218956 kb
Host smart-036a7445-7ad2-4350-845c-8458165a5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678183399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3678183399
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4061142967
Short name T351
Test name
Test status
Simulation time 2470403283 ps
CPU time 11.99 seconds
Started Mar 21 03:21:04 PM PDT 24
Finished Mar 21 03:21:17 PM PDT 24
Peak memory 212728 kb
Host smart-19d36def-233f-41cb-a7f5-b7e6be6fd33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061142967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4061142967
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3020146610
Short name T562
Test name
Test status
Simulation time 4636501939 ps
CPU time 41.63 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:36:38 PM PDT 24
Peak memory 218988 kb
Host smart-6588297c-9dcb-4d4b-b5c7-21dde01e0f5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020146610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3020146610
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.375253935
Short name T96
Test name
Test status
Simulation time 564090523 ps
CPU time 26.49 seconds
Started Mar 21 03:21:09 PM PDT 24
Finished Mar 21 03:21:36 PM PDT 24
Peak memory 215928 kb
Host smart-5be0adf2-ef9c-421f-a2a0-5fd9bf2847a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375253935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.375253935
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1464392461
Short name T194
Test name
Test status
Simulation time 158626013359 ps
CPU time 2705.04 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 02:21:03 PM PDT 24
Peak memory 232212 kb
Host smart-ee4d2cfb-ab94-481d-8185-cdffe1628cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464392461 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1464392461
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1886702301
Short name T192
Test name
Test status
Simulation time 5610044196 ps
CPU time 12.2 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:36:24 PM PDT 24
Peak memory 210804 kb
Host smart-2a1d583b-ec86-4d1d-96fb-afd0de662d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886702301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1886702301
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.728970103
Short name T678
Test name
Test status
Simulation time 2975786366 ps
CPU time 13.83 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:21:45 PM PDT 24
Peak memory 210920 kb
Host smart-b001fb01-d2da-4fc1-b1e3-90c256757a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728970103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.728970103
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1198589012
Short name T374
Test name
Test status
Simulation time 33994590676 ps
CPU time 354.95 seconds
Started Mar 21 03:21:20 PM PDT 24
Finished Mar 21 03:27:16 PM PDT 24
Peak memory 224524 kb
Host smart-fcd70716-bbf1-480b-9201-1a9212b28528
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198589012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1198589012
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3693400666
Short name T608
Test name
Test status
Simulation time 43728062163 ps
CPU time 464.33 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:43:50 PM PDT 24
Peak memory 234976 kb
Host smart-c408805a-3d74-471a-bc9e-3fdbaabf91ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693400666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3693400666
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3150382444
Short name T403
Test name
Test status
Simulation time 23832398721 ps
CPU time 25.54 seconds
Started Mar 21 03:21:19 PM PDT 24
Finished Mar 21 03:21:46 PM PDT 24
Peak memory 211876 kb
Host smart-164c4469-d292-49f1-bbb1-9753d91d9da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150382444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3150382444
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3322056482
Short name T635
Test name
Test status
Simulation time 24171991906 ps
CPU time 34.15 seconds
Started Mar 21 01:36:06 PM PDT 24
Finished Mar 21 01:36:41 PM PDT 24
Peak memory 210920 kb
Host smart-4bc1ef63-c0c5-44f7-a7e1-bde4a10de102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322056482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3322056482
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2428319358
Short name T453
Test name
Test status
Simulation time 3136790835 ps
CPU time 14.63 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:36:11 PM PDT 24
Peak memory 210844 kb
Host smart-6edd4cd6-fbc9-4d81-be24-ceede927aa8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428319358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2428319358
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3814724566
Short name T486
Test name
Test status
Simulation time 740889280 ps
CPU time 9.89 seconds
Started Mar 21 03:21:19 PM PDT 24
Finished Mar 21 03:21:29 PM PDT 24
Peak memory 210884 kb
Host smart-4ae19a5b-9bb8-4b40-a334-1a9ee75db0f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814724566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3814724566
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1065312316
Short name T523
Test name
Test status
Simulation time 8932080914 ps
CPU time 30.17 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:40 PM PDT 24
Peak memory 213432 kb
Host smart-37464c51-809c-4621-ac21-72e614407409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065312316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1065312316
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2144641263
Short name T199
Test name
Test status
Simulation time 397706857 ps
CPU time 9.94 seconds
Started Mar 21 03:21:19 PM PDT 24
Finished Mar 21 03:21:30 PM PDT 24
Peak memory 212636 kb
Host smart-3e1a7722-5d2f-443d-9259-ce5ca1a86d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144641263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2144641263
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.119010947
Short name T220
Test name
Test status
Simulation time 200765453 ps
CPU time 13.21 seconds
Started Mar 21 01:36:04 PM PDT 24
Finished Mar 21 01:36:19 PM PDT 24
Peak memory 218868 kb
Host smart-fa29be05-9043-45f6-93c4-e2287e97beb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119010947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.119010947
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1789093241
Short name T421
Test name
Test status
Simulation time 10681393250 ps
CPU time 26.24 seconds
Started Mar 21 03:21:19 PM PDT 24
Finished Mar 21 03:21:45 PM PDT 24
Peak memory 213472 kb
Host smart-3e8b9938-d11d-4e17-b183-c9055a9a265e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789093241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1789093241
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3610126316
Short name T167
Test name
Test status
Simulation time 377742037 ps
CPU time 4.35 seconds
Started Mar 21 01:36:02 PM PDT 24
Finished Mar 21 01:36:07 PM PDT 24
Peak memory 210832 kb
Host smart-5e34721f-5c5e-4e38-805a-97fd41c5c075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610126316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3610126316
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4282975224
Short name T247
Test name
Test status
Simulation time 3914927983 ps
CPU time 15.76 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 210944 kb
Host smart-44fa66ae-4c2c-4174-bc5c-89e8bfbb5df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282975224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4282975224
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3529556680
Short name T454
Test name
Test status
Simulation time 45008896730 ps
CPU time 396.77 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 224812 kb
Host smart-46ab17ef-a49a-460e-b1bd-5c3ecf6704a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529556680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3529556680
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.385449554
Short name T601
Test name
Test status
Simulation time 6540254577 ps
CPU time 139.53 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:38:26 PM PDT 24
Peak memory 212200 kb
Host smart-feb4e8c4-9540-436a-a3eb-58aff758d62b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385449554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.385449554
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1380501655
Short name T307
Test name
Test status
Simulation time 7859389796 ps
CPU time 20.9 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 01:36:15 PM PDT 24
Peak memory 212560 kb
Host smart-ae11b573-5a8b-41e3-8eee-ff64ce0b4e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380501655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1380501655
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2850978013
Short name T240
Test name
Test status
Simulation time 2054807000 ps
CPU time 22.52 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 03:21:51 PM PDT 24
Peak memory 211376 kb
Host smart-72a66627-80d8-4a05-bfb0-e29da1a71ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850978013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2850978013
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2677646242
Short name T647
Test name
Test status
Simulation time 2808516329 ps
CPU time 7.81 seconds
Started Mar 21 01:36:12 PM PDT 24
Finished Mar 21 01:36:20 PM PDT 24
Peak memory 210848 kb
Host smart-b11b6abc-3c9a-4b7e-bb18-721ddb16b24a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677646242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2677646242
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.752017827
Short name T197
Test name
Test status
Simulation time 649313188 ps
CPU time 5.35 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 03:21:35 PM PDT 24
Peak memory 210812 kb
Host smart-717ca891-eb5c-41d2-ad39-d3e512125fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=752017827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.752017827
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2422894357
Short name T542
Test name
Test status
Simulation time 10451490645 ps
CPU time 28.37 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 01:36:27 PM PDT 24
Peak memory 213448 kb
Host smart-c6c4c05e-7e14-4b5c-ac55-87c8a244068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422894357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2422894357
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2728263997
Short name T249
Test name
Test status
Simulation time 6950580495 ps
CPU time 43.2 seconds
Started Mar 21 03:21:28 PM PDT 24
Finished Mar 21 03:22:12 PM PDT 24
Peak memory 213060 kb
Host smart-be2e70d3-5f98-43c6-a740-97e15ecf2e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728263997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2728263997
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1732986791
Short name T648
Test name
Test status
Simulation time 18113573026 ps
CPU time 49.35 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:36:55 PM PDT 24
Peak memory 217240 kb
Host smart-0cfc3fb4-d94d-450f-bdcb-dbea7bb80149
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732986791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1732986791
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2576296505
Short name T310
Test name
Test status
Simulation time 1534477062 ps
CPU time 22.71 seconds
Started Mar 21 03:21:34 PM PDT 24
Finished Mar 21 03:21:57 PM PDT 24
Peak memory 213888 kb
Host smart-73e739aa-b5f9-4a90-bd18-f9c61539a652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576296505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2576296505
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2751016575
Short name T114
Test name
Test status
Simulation time 132794729879 ps
CPU time 1481.74 seconds
Started Mar 21 03:21:30 PM PDT 24
Finished Mar 21 03:46:12 PM PDT 24
Peak memory 235580 kb
Host smart-a0a721b7-61d4-43c7-8f5e-469f14e8ca54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751016575 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2751016575
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.906796887
Short name T56
Test name
Test status
Simulation time 85163006166 ps
CPU time 3071.5 seconds
Started Mar 21 01:36:07 PM PDT 24
Finished Mar 21 02:27:19 PM PDT 24
Peak memory 227384 kb
Host smart-217e9de9-815a-4d59-99c9-e86ba54f8883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906796887 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.906796887
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.758914369
Short name T455
Test name
Test status
Simulation time 5469861553 ps
CPU time 11.18 seconds
Started Mar 21 03:21:30 PM PDT 24
Finished Mar 21 03:21:41 PM PDT 24
Peak memory 210960 kb
Host smart-4d6c65e8-da36-45ac-b425-126b30c161bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758914369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.758914369
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1918025316
Short name T432
Test name
Test status
Simulation time 87203563919 ps
CPU time 220.17 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:39:43 PM PDT 24
Peak memory 212128 kb
Host smart-537e56b6-d029-4d81-8f39-c30e19dd98d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918025316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1918025316
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4119225841
Short name T132
Test name
Test status
Simulation time 15358749037 ps
CPU time 180.55 seconds
Started Mar 21 03:21:32 PM PDT 24
Finished Mar 21 03:24:33 PM PDT 24
Peak memory 228552 kb
Host smart-670656a9-76f2-42b2-91ed-33108c00e876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119225841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4119225841
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1784672057
Short name T17
Test name
Test status
Simulation time 168460432 ps
CPU time 9.59 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:21:41 PM PDT 24
Peak memory 211632 kb
Host smart-8baee559-112a-4d52-8ced-3fe85451e2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784672057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1784672057
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2720250911
Short name T571
Test name
Test status
Simulation time 3874647439 ps
CPU time 14.59 seconds
Started Mar 21 01:36:00 PM PDT 24
Finished Mar 21 01:36:14 PM PDT 24
Peak memory 211520 kb
Host smart-1c78c223-5969-4a79-833d-a8ca0eff03c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720250911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2720250911
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.195938032
Short name T499
Test name
Test status
Simulation time 2114547944 ps
CPU time 11.93 seconds
Started Mar 21 03:21:32 PM PDT 24
Finished Mar 21 03:21:44 PM PDT 24
Peak memory 210784 kb
Host smart-fbcc3d27-22d0-43a5-ad2d-b1c62909aad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195938032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.195938032
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3031586417
Short name T649
Test name
Test status
Simulation time 596685466 ps
CPU time 9.54 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:18 PM PDT 24
Peak memory 210776 kb
Host smart-3953bd08-e7c1-4a00-8e82-c40961aa3bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031586417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3031586417
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1748222607
Short name T108
Test name
Test status
Simulation time 4395123610 ps
CPU time 22.02 seconds
Started Mar 21 03:21:30 PM PDT 24
Finished Mar 21 03:21:52 PM PDT 24
Peak memory 212136 kb
Host smart-92507455-0675-4683-88fa-751a445eb130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748222607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1748222607
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.578120740
Short name T80
Test name
Test status
Simulation time 2951135601 ps
CPU time 32.75 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 01:36:31 PM PDT 24
Peak memory 218904 kb
Host smart-c17d868d-c710-4bd1-ae07-d03cd3a4a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578120740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.578120740
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1847660605
Short name T102
Test name
Test status
Simulation time 4301578548 ps
CPU time 35.9 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:22:07 PM PDT 24
Peak memory 213232 kb
Host smart-5a8c8db7-c629-4b95-bae6-5d6e0e5d93cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847660605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1847660605
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.39292672
Short name T477
Test name
Test status
Simulation time 10988113082 ps
CPU time 36.56 seconds
Started Mar 21 01:36:04 PM PDT 24
Finished Mar 21 01:36:43 PM PDT 24
Peak memory 219016 kb
Host smart-f7776343-7e59-4d73-923a-0bac4f85134a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39292672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.rom_ctrl_stress_all.39292672
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1524453304
Short name T418
Test name
Test status
Simulation time 79377960767 ps
CPU time 1531.45 seconds
Started Mar 21 03:21:34 PM PDT 24
Finished Mar 21 03:47:06 PM PDT 24
Peak memory 234652 kb
Host smart-9088646f-66b5-4719-b0a9-a521adc84895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524453304 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1524453304
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3203222408
Short name T205
Test name
Test status
Simulation time 743848869 ps
CPU time 6.84 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 03:21:36 PM PDT 24
Peak memory 210876 kb
Host smart-a0a0876c-ba66-4cb8-a9d3-fcf67e0d17fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203222408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3203222408
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.524076436
Short name T615
Test name
Test status
Simulation time 3545609208 ps
CPU time 12.8 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:36:18 PM PDT 24
Peak memory 210808 kb
Host smart-54ca8ee7-df53-4a7f-9cc9-d546d45e5ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524076436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.524076436
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1369874091
Short name T510
Test name
Test status
Simulation time 1575903332 ps
CPU time 87.38 seconds
Started Mar 21 03:21:28 PM PDT 24
Finished Mar 21 03:22:55 PM PDT 24
Peak memory 212172 kb
Host smart-11ecc238-cc02-4455-9fc3-4095ad4cf3d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369874091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1369874091
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2752536813
Short name T415
Test name
Test status
Simulation time 22542480838 ps
CPU time 268.95 seconds
Started Mar 21 01:36:01 PM PDT 24
Finished Mar 21 01:40:30 PM PDT 24
Peak memory 220004 kb
Host smart-8713ab5d-7d15-44d8-8ce8-91653a21a397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752536813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2752536813
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1135536692
Short name T135
Test name
Test status
Simulation time 1179991572 ps
CPU time 13.83 seconds
Started Mar 21 01:35:55 PM PDT 24
Finished Mar 21 01:36:09 PM PDT 24
Peak memory 210828 kb
Host smart-332a4927-6d9a-4167-ba86-60f3f4536268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135536692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1135536692
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.444836980
Short name T184
Test name
Test status
Simulation time 4100444416 ps
CPU time 32.01 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 03:22:02 PM PDT 24
Peak memory 219104 kb
Host smart-6a9331d3-e516-4f78-b6a3-a0d767c6df73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444836980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.444836980
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3701464976
Short name T306
Test name
Test status
Simulation time 379440664 ps
CPU time 5.53 seconds
Started Mar 21 03:21:33 PM PDT 24
Finished Mar 21 03:21:38 PM PDT 24
Peak memory 210844 kb
Host smart-0e5113aa-1244-40d5-a14e-db9b1a2a97d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701464976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3701464976
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.524621939
Short name T280
Test name
Test status
Simulation time 7967596212 ps
CPU time 14.63 seconds
Started Mar 21 01:35:59 PM PDT 24
Finished Mar 21 01:36:14 PM PDT 24
Peak memory 210852 kb
Host smart-387caa55-d443-437f-b401-ca03f4e1a2ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524621939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.524621939
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2280565139
Short name T324
Test name
Test status
Simulation time 1566298032 ps
CPU time 19.81 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:36:16 PM PDT 24
Peak memory 218940 kb
Host smart-cd5ffc33-753d-413f-bd3f-940909c2926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280565139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2280565139
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2793673298
Short name T156
Test name
Test status
Simulation time 3637319801 ps
CPU time 22.88 seconds
Started Mar 21 03:21:33 PM PDT 24
Finished Mar 21 03:21:56 PM PDT 24
Peak memory 219080 kb
Host smart-7f27e3ad-9672-4c8c-8846-6e2eff083156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793673298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2793673298
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1536246709
Short name T6
Test name
Test status
Simulation time 3956194039 ps
CPU time 21.54 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:32 PM PDT 24
Peak memory 211204 kb
Host smart-b0e6c72f-2a03-49fd-ab78-0ebd2c6b9be1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536246709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1536246709
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4132781294
Short name T219
Test name
Test status
Simulation time 16995019424 ps
CPU time 73.05 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:22:45 PM PDT 24
Peak memory 219084 kb
Host smart-98a4dc8a-ea54-46bb-9bf3-ca7bcd9d8503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132781294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4132781294
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1658919471
Short name T304
Test name
Test status
Simulation time 478778922 ps
CPU time 5.04 seconds
Started Mar 21 01:35:57 PM PDT 24
Finished Mar 21 01:36:02 PM PDT 24
Peak memory 210776 kb
Host smart-17a10ac2-c52e-46ba-97b6-a673c6995c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658919471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1658919471
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.274783534
Short name T235
Test name
Test status
Simulation time 85675040 ps
CPU time 4.28 seconds
Started Mar 21 03:21:28 PM PDT 24
Finished Mar 21 03:21:33 PM PDT 24
Peak memory 210860 kb
Host smart-338a36b8-ba19-4d86-940e-9bb86c3bc0ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274783534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.274783534
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2597135098
Short name T158
Test name
Test status
Simulation time 20604404078 ps
CPU time 239.41 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:40:06 PM PDT 24
Peak memory 233324 kb
Host smart-af46e0e3-2867-4c3b-a39c-9a426af09fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597135098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2597135098
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4280206544
Short name T46
Test name
Test status
Simulation time 6149727759 ps
CPU time 18.88 seconds
Started Mar 21 01:36:01 PM PDT 24
Finished Mar 21 01:36:19 PM PDT 24
Peak memory 211072 kb
Host smart-fc9c70ae-ee29-4e9c-9f50-9f33e7255467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280206544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4280206544
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.848292845
Short name T267
Test name
Test status
Simulation time 1187630267 ps
CPU time 9.42 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 03:21:38 PM PDT 24
Peak memory 211380 kb
Host smart-64ae529e-8dd9-4445-9c18-b7e7e4030403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848292845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.848292845
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.126727238
Short name T595
Test name
Test status
Simulation time 7433848960 ps
CPU time 17.37 seconds
Started Mar 21 03:21:30 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 210864 kb
Host smart-7bb4b42a-2601-4f2c-b03d-65e0c5aef06e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126727238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.126727238
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2127835741
Short name T602
Test name
Test status
Simulation time 18804985153 ps
CPU time 16.04 seconds
Started Mar 21 01:35:59 PM PDT 24
Finished Mar 21 01:36:15 PM PDT 24
Peak memory 210756 kb
Host smart-dd6966b7-6f8b-4958-9d0f-a0218c39aa13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127835741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2127835741
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1073883422
Short name T263
Test name
Test status
Simulation time 185765760 ps
CPU time 9.91 seconds
Started Mar 21 03:21:28 PM PDT 24
Finished Mar 21 03:21:38 PM PDT 24
Peak memory 213216 kb
Host smart-804d6992-416f-45a9-9eaf-2d8d5377f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073883422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1073883422
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1777421079
Short name T472
Test name
Test status
Simulation time 183017614 ps
CPU time 10.19 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:36:16 PM PDT 24
Peak memory 218940 kb
Host smart-b3087802-091e-4781-b4f8-fca123edd330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777421079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1777421079
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2159686800
Short name T598
Test name
Test status
Simulation time 10778230512 ps
CPU time 22.06 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:36:32 PM PDT 24
Peak memory 211840 kb
Host smart-d22bd9c3-b6cd-454f-8816-eac802d16546
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159686800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2159686800
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1260219674
Short name T367
Test name
Test status
Simulation time 631654719 ps
CPU time 8.33 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 03:21:38 PM PDT 24
Peak memory 210908 kb
Host smart-1c92ef6e-5175-477f-80a7-f8eede092e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260219674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1260219674
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.901629819
Short name T333
Test name
Test status
Simulation time 10943369563 ps
CPU time 10.48 seconds
Started Mar 21 01:35:52 PM PDT 24
Finished Mar 21 01:36:02 PM PDT 24
Peak memory 210796 kb
Host smart-11e02f47-9b99-4f19-9287-6abb515d69c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901629819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.901629819
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.233935419
Short name T193
Test name
Test status
Simulation time 36848748972 ps
CPU time 284.58 seconds
Started Mar 21 03:21:28 PM PDT 24
Finished Mar 21 03:26:13 PM PDT 24
Peak memory 237656 kb
Host smart-074dab5b-3808-41e9-b456-b6947b1b19f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233935419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.233935419
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3636084816
Short name T25
Test name
Test status
Simulation time 64850181067 ps
CPU time 329.74 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 01:41:28 PM PDT 24
Peak memory 233436 kb
Host smart-7a159bed-5b87-4831-be7a-cf77348534cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636084816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3636084816
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1962847281
Short name T402
Test name
Test status
Simulation time 2232072162 ps
CPU time 22.45 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:21:54 PM PDT 24
Peak memory 211520 kb
Host smart-390afb16-8976-4fcd-81ed-e9fcfc8ea7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962847281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1962847281
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3953482452
Short name T154
Test name
Test status
Simulation time 12355245623 ps
CPU time 18.09 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:36:14 PM PDT 24
Peak memory 211732 kb
Host smart-efc9d2ca-259c-4c88-bd6c-9181c21a6bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953482452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3953482452
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.246909158
Short name T610
Test name
Test status
Simulation time 2092949637 ps
CPU time 17.2 seconds
Started Mar 21 03:21:31 PM PDT 24
Finished Mar 21 03:21:48 PM PDT 24
Peak memory 210844 kb
Host smart-2dc2edc2-221d-4733-8e04-3326b59c95d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246909158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.246909158
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3063778346
Short name T319
Test name
Test status
Simulation time 3181906432 ps
CPU time 14.52 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 01:36:13 PM PDT 24
Peak memory 210756 kb
Host smart-d583568d-8e9d-4841-b30f-47482b13262d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063778346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3063778346
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1619900017
Short name T667
Test name
Test status
Simulation time 50860919553 ps
CPU time 32.78 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:22:13 PM PDT 24
Peak memory 219068 kb
Host smart-e6c1e3b1-fc25-4dba-9bfc-c412b04feb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619900017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1619900017
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3707195124
Short name T172
Test name
Test status
Simulation time 1370746580 ps
CPU time 12.38 seconds
Started Mar 21 01:36:06 PM PDT 24
Finished Mar 21 01:36:20 PM PDT 24
Peak memory 213440 kb
Host smart-c0fe0307-020c-4e29-927c-18b8359e141a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707195124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3707195124
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1969396667
Short name T160
Test name
Test status
Simulation time 26083748391 ps
CPU time 70.25 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:37:16 PM PDT 24
Peak memory 219068 kb
Host smart-241935bb-9e61-4152-a53f-c32414dd53d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969396667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1969396667
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.308673355
Short name T8
Test name
Test status
Simulation time 145540039 ps
CPU time 13.19 seconds
Started Mar 21 03:21:30 PM PDT 24
Finished Mar 21 03:21:44 PM PDT 24
Peak memory 210860 kb
Host smart-63857b01-80eb-4983-aae2-3471cab35eb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308673355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.308673355
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3913905509
Short name T54
Test name
Test status
Simulation time 38069270879 ps
CPU time 2941.51 seconds
Started Mar 21 03:21:29 PM PDT 24
Finished Mar 21 04:10:31 PM PDT 24
Peak memory 228684 kb
Host smart-90f948ab-fa36-4457-8a0d-616d5b408155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913905509 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3913905509
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2755881645
Short name T474
Test name
Test status
Simulation time 1452565659 ps
CPU time 6.38 seconds
Started Mar 21 01:36:01 PM PDT 24
Finished Mar 21 01:36:07 PM PDT 24
Peak memory 210776 kb
Host smart-ad386b96-9344-4a5e-9083-fc193ae17386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755881645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2755881645
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.870448002
Short name T586
Test name
Test status
Simulation time 2464436303 ps
CPU time 11.75 seconds
Started Mar 21 03:21:38 PM PDT 24
Finished Mar 21 03:21:50 PM PDT 24
Peak memory 210944 kb
Host smart-39f138d5-b0f9-4431-886c-433c5a139af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870448002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.870448002
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2522031993
Short name T634
Test name
Test status
Simulation time 3598497383 ps
CPU time 157.93 seconds
Started Mar 21 01:36:00 PM PDT 24
Finished Mar 21 01:38:39 PM PDT 24
Peak memory 234780 kb
Host smart-b06955a5-d177-4b00-be30-f7d363f239e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522031993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2522031993
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.567292032
Short name T607
Test name
Test status
Simulation time 1634434289 ps
CPU time 93.7 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:23:14 PM PDT 24
Peak memory 226020 kb
Host smart-88338fd3-8b23-45bd-b119-3ad2abdf602a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567292032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.567292032
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2781637907
Short name T504
Test name
Test status
Simulation time 5999975722 ps
CPU time 26.3 seconds
Started Mar 21 03:21:41 PM PDT 24
Finished Mar 21 03:22:08 PM PDT 24
Peak memory 211884 kb
Host smart-bc88a3f8-fc62-451f-bee0-e877b5afc7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781637907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2781637907
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2821513878
Short name T251
Test name
Test status
Simulation time 4416149927 ps
CPU time 33.99 seconds
Started Mar 21 01:36:07 PM PDT 24
Finished Mar 21 01:36:42 PM PDT 24
Peak memory 212264 kb
Host smart-66b625b7-20bf-48e7-9b98-0e1d7fe28c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821513878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2821513878
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3287095787
Short name T387
Test name
Test status
Simulation time 1805165241 ps
CPU time 5.41 seconds
Started Mar 21 03:21:42 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 210828 kb
Host smart-ca288fc5-2410-4509-be89-75a23ed8741e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287095787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3287095787
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3595302918
Short name T544
Test name
Test status
Simulation time 6148817575 ps
CPU time 14.24 seconds
Started Mar 21 01:36:04 PM PDT 24
Finished Mar 21 01:36:20 PM PDT 24
Peak memory 210884 kb
Host smart-4a3e44b6-0878-4151-9148-04e1b9ede8d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595302918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3595302918
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1402059431
Short name T42
Test name
Test status
Simulation time 7046688727 ps
CPU time 30.79 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:22:11 PM PDT 24
Peak memory 214184 kb
Host smart-5ad94005-abee-474a-b517-51956332aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402059431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1402059431
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.341159061
Short name T568
Test name
Test status
Simulation time 2949239207 ps
CPU time 10.3 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:36:16 PM PDT 24
Peak memory 219004 kb
Host smart-92a4e311-4e70-49d3-8ba4-bafaa0b2cad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341159061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.341159061
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.131625149
Short name T452
Test name
Test status
Simulation time 6609638291 ps
CPU time 72.51 seconds
Started Mar 21 03:21:41 PM PDT 24
Finished Mar 21 03:22:53 PM PDT 24
Peak memory 219048 kb
Host smart-941ac110-7d9a-448a-b7db-a67a74acd399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131625149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.131625149
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1661038577
Short name T302
Test name
Test status
Simulation time 114435423708 ps
CPU time 89.41 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 01:37:27 PM PDT 24
Peak memory 218944 kb
Host smart-98eab8b0-5dce-4e46-9391-6de30aaef389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661038577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1661038577
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2006151745
Short name T57
Test name
Test status
Simulation time 167038324379 ps
CPU time 531.93 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:44:48 PM PDT 24
Peak memory 228188 kb
Host smart-2915b3eb-3b9f-4a31-8dbe-b8784dafae16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006151745 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2006151745
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1013341856
Short name T618
Test name
Test status
Simulation time 9383482888 ps
CPU time 12.21 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:21:52 PM PDT 24
Peak memory 210948 kb
Host smart-9286e9e2-9265-4903-892d-3966f9be5768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013341856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1013341856
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2501850022
Short name T203
Test name
Test status
Simulation time 1030282102 ps
CPU time 10.58 seconds
Started Mar 21 01:36:07 PM PDT 24
Finished Mar 21 01:36:18 PM PDT 24
Peak memory 210764 kb
Host smart-9751aaf7-18d1-4529-b550-c9bca0b31a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501850022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2501850022
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1335314820
Short name T51
Test name
Test status
Simulation time 24350766250 ps
CPU time 209.46 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:39:36 PM PDT 24
Peak memory 230356 kb
Host smart-ac8f9048-de0e-4572-b72c-a537d1f4ea3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335314820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1335314820
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.989108812
Short name T283
Test name
Test status
Simulation time 3197114388 ps
CPU time 116.06 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:23:37 PM PDT 24
Peak memory 212240 kb
Host smart-0e49f5b2-cf5f-435d-b25e-34a47d4f93f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989108812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.989108812
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3544460366
Short name T223
Test name
Test status
Simulation time 19098338135 ps
CPU time 26.58 seconds
Started Mar 21 03:21:38 PM PDT 24
Finished Mar 21 03:22:05 PM PDT 24
Peak memory 219128 kb
Host smart-0b8eb958-609e-4e32-a548-6087eeeb20c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544460366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3544460366
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.704832319
Short name T641
Test name
Test status
Simulation time 347862413 ps
CPU time 9.54 seconds
Started Mar 21 01:36:07 PM PDT 24
Finished Mar 21 01:36:18 PM PDT 24
Peak memory 211316 kb
Host smart-48301bf7-3fc3-4787-9d4f-5f711420ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704832319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.704832319
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.580603244
Short name T295
Test name
Test status
Simulation time 641392324 ps
CPU time 9.31 seconds
Started Mar 21 03:21:38 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 210844 kb
Host smart-9a28fd0c-4414-4b8f-aaa6-db57389c12ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580603244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.580603244
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.979545426
Short name T426
Test name
Test status
Simulation time 2560719711 ps
CPU time 7.58 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:36:14 PM PDT 24
Peak memory 210868 kb
Host smart-74532b55-2f64-4249-a086-f7a3b1879368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979545426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.979545426
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1776259779
Short name T254
Test name
Test status
Simulation time 21343451623 ps
CPU time 23.46 seconds
Started Mar 21 01:36:02 PM PDT 24
Finished Mar 21 01:36:26 PM PDT 24
Peak memory 219052 kb
Host smart-fe270bd1-a100-4fbc-bbf9-8cf27c3b107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776259779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1776259779
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2336729022
Short name T103
Test name
Test status
Simulation time 184850650 ps
CPU time 10.27 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:21:50 PM PDT 24
Peak memory 212984 kb
Host smart-fe9c1b8f-b2f5-4acc-b480-f2523a14c46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336729022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2336729022
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.484491571
Short name T353
Test name
Test status
Simulation time 24611331145 ps
CPU time 86.68 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:37:35 PM PDT 24
Peak memory 219016 kb
Host smart-daf79103-e071-47e3-accf-b50adfa2dce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484491571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.484491571
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.707973776
Short name T259
Test name
Test status
Simulation time 4281665904 ps
CPU time 37.97 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:22:18 PM PDT 24
Peak memory 212972 kb
Host smart-81d1ca86-f981-4c11-a672-7550930ed08a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707973776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.707973776
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2247030523
Short name T191
Test name
Test status
Simulation time 165357673282 ps
CPU time 686.88 seconds
Started Mar 21 03:21:39 PM PDT 24
Finished Mar 21 03:33:06 PM PDT 24
Peak memory 229740 kb
Host smart-ee65e90a-e2de-4215-9708-4c5d0df8658f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247030523 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2247030523
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1596319777
Short name T322
Test name
Test status
Simulation time 11443485413 ps
CPU time 17.21 seconds
Started Mar 21 01:36:04 PM PDT 24
Finished Mar 21 01:36:24 PM PDT 24
Peak memory 210904 kb
Host smart-e2605202-9331-4e68-a537-fc6eb9303129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596319777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1596319777
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2839363997
Short name T653
Test name
Test status
Simulation time 1721263000 ps
CPU time 7.35 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 210904 kb
Host smart-d49c9656-de60-4eda-adb5-d2bd1bfb5134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839363997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2839363997
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3066804160
Short name T395
Test name
Test status
Simulation time 4858589517 ps
CPU time 89.63 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:37:35 PM PDT 24
Peak memory 228368 kb
Host smart-f8e1413c-409a-4e33-b8cb-96c37ffd6a0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066804160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3066804160
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1812305248
Short name T260
Test name
Test status
Simulation time 1522372203 ps
CPU time 12.2 seconds
Started Mar 21 03:21:38 PM PDT 24
Finished Mar 21 03:21:51 PM PDT 24
Peak memory 211432 kb
Host smart-d6e10516-a0f6-4a37-acd4-f9ef88f67a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812305248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1812305248
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3181126888
Short name T101
Test name
Test status
Simulation time 175817487 ps
CPU time 9.25 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:36:15 PM PDT 24
Peak memory 211484 kb
Host smart-9176abd8-07a0-4509-91b3-15f30314bc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181126888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3181126888
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1660101922
Short name T152
Test name
Test status
Simulation time 347150637 ps
CPU time 7.66 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 210860 kb
Host smart-3e7e0288-2a48-4ff0-9d93-99afdf1ec88c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660101922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1660101922
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3312754197
Short name T492
Test name
Test status
Simulation time 1280589357 ps
CPU time 12.57 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:36:19 PM PDT 24
Peak memory 210800 kb
Host smart-f7d4fe38-dc6d-4f72-85ea-3266630f3c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312754197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3312754197
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3744990013
Short name T143
Test name
Test status
Simulation time 4239887497 ps
CPU time 41.09 seconds
Started Mar 21 01:36:04 PM PDT 24
Finished Mar 21 01:36:47 PM PDT 24
Peak memory 219004 kb
Host smart-250b5fcf-fcd8-4f78-ada9-ef45c6dfc683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744990013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3744990013
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.587007558
Short name T547
Test name
Test status
Simulation time 723008244 ps
CPU time 10.42 seconds
Started Mar 21 03:21:42 PM PDT 24
Finished Mar 21 03:21:52 PM PDT 24
Peak memory 213292 kb
Host smart-b4484cae-f3c6-4c96-9cef-d0ca070880f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587007558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.587007558
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1323607316
Short name T534
Test name
Test status
Simulation time 41664715895 ps
CPU time 62.74 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 01:37:01 PM PDT 24
Peak memory 219028 kb
Host smart-4d7a779a-9b7a-459f-8d13-4142e9d7ceb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323607316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1323607316
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2931172811
Short name T570
Test name
Test status
Simulation time 3676526201 ps
CPU time 18.39 seconds
Started Mar 21 03:21:39 PM PDT 24
Finished Mar 21 03:21:58 PM PDT 24
Peak memory 210860 kb
Host smart-28ce7f61-b2b0-4fd5-b0b8-800920022dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931172811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2931172811
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2646862308
Short name T355
Test name
Test status
Simulation time 1365218827 ps
CPU time 12.19 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:21:01 PM PDT 24
Peak memory 210880 kb
Host smart-e3409faf-cee4-4425-bbc7-402c3d5179fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646862308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2646862308
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2674933567
Short name T350
Test name
Test status
Simulation time 4614073561 ps
CPU time 12.91 seconds
Started Mar 21 01:35:42 PM PDT 24
Finished Mar 21 01:35:55 PM PDT 24
Peak memory 210888 kb
Host smart-e8b20ace-a549-40ef-aac5-92e4281fa3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674933567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2674933567
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2218327
Short name T531
Test name
Test status
Simulation time 1636061423 ps
CPU time 64.18 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:21:53 PM PDT 24
Peak memory 228388 kb
Host smart-00f0b98a-03a4-4146-a5a8-2d6579420190
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corr
upt_sig_fatal_chk.2218327
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3163621910
Short name T241
Test name
Test status
Simulation time 75126355538 ps
CPU time 380.06 seconds
Started Mar 21 01:35:57 PM PDT 24
Finished Mar 21 01:42:17 PM PDT 24
Peak memory 213236 kb
Host smart-163b26c0-13f5-41f0-bf1f-26f0a3e9c4c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163621910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3163621910
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3282358574
Short name T539
Test name
Test status
Simulation time 2856366323 ps
CPU time 26.7 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:21:15 PM PDT 24
Peak memory 211544 kb
Host smart-2f20cf64-76be-48cc-81d5-56e8a9698c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282358574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3282358574
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.404041899
Short name T232
Test name
Test status
Simulation time 3586429912 ps
CPU time 15.11 seconds
Started Mar 21 01:35:45 PM PDT 24
Finished Mar 21 01:36:01 PM PDT 24
Peak memory 211604 kb
Host smart-008b64df-54bd-4cc5-b0c0-6468c3c0f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404041899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.404041899
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1094947995
Short name T569
Test name
Test status
Simulation time 914045229 ps
CPU time 9.04 seconds
Started Mar 21 01:35:44 PM PDT 24
Finished Mar 21 01:35:54 PM PDT 24
Peak memory 210788 kb
Host smart-44ad5571-9fde-42da-84ba-33f51c112d40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094947995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1094947995
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2727328121
Short name T170
Test name
Test status
Simulation time 6872051526 ps
CPU time 12.71 seconds
Started Mar 21 03:20:52 PM PDT 24
Finished Mar 21 03:21:05 PM PDT 24
Peak memory 210916 kb
Host smart-f5db2633-8551-4b75-84c4-d931614d373f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727328121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2727328121
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1332921013
Short name T36
Test name
Test status
Simulation time 1770919287 ps
CPU time 54.22 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:36:51 PM PDT 24
Peak memory 230476 kb
Host smart-1f575095-a777-44e6-a737-430134d5754e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332921013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1332921013
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4187730621
Short name T38
Test name
Test status
Simulation time 1786293746 ps
CPU time 61.2 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:21:50 PM PDT 24
Peak memory 233200 kb
Host smart-522ece4f-53f5-441d-ab5b-80aba3f3d993
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187730621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4187730621
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2270583996
Short name T330
Test name
Test status
Simulation time 7489923217 ps
CPU time 21.83 seconds
Started Mar 21 01:35:55 PM PDT 24
Finished Mar 21 01:36:17 PM PDT 24
Peak memory 214048 kb
Host smart-abde71ea-7b64-43ec-82bd-0b67c7bfd091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270583996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2270583996
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.829142873
Short name T131
Test name
Test status
Simulation time 186259456 ps
CPU time 10.25 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:20:58 PM PDT 24
Peak memory 213112 kb
Host smart-12de9969-8ed5-4277-b5b7-7a5960d16a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829142873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.829142873
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.103248448
Short name T401
Test name
Test status
Simulation time 3620745121 ps
CPU time 17.89 seconds
Started Mar 21 01:35:44 PM PDT 24
Finished Mar 21 01:36:03 PM PDT 24
Peak memory 210756 kb
Host smart-f1f185df-589c-4183-a302-834fccf92c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103248448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.103248448
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2787938288
Short name T328
Test name
Test status
Simulation time 10816216431 ps
CPU time 27.94 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:21:17 PM PDT 24
Peak memory 219068 kb
Host smart-8b917976-737a-436e-b6d8-03cf235c67d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787938288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2787938288
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2936866074
Short name T639
Test name
Test status
Simulation time 1512897751 ps
CPU time 13.37 seconds
Started Mar 21 03:21:39 PM PDT 24
Finished Mar 21 03:21:53 PM PDT 24
Peak memory 210904 kb
Host smart-017ab086-f8b2-4ad2-b7cc-26a91198e592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936866074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2936866074
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4141304816
Short name T357
Test name
Test status
Simulation time 5323155839 ps
CPU time 12.38 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:21 PM PDT 24
Peak memory 210916 kb
Host smart-cb8a5e4b-7966-45a7-8e2a-414a4624a6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141304816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4141304816
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2702255874
Short name T202
Test name
Test status
Simulation time 14752792808 ps
CPU time 223.92 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:39:50 PM PDT 24
Peak memory 231456 kb
Host smart-bad4635a-fd50-4003-bd14-178a006f02fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702255874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2702255874
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2810396960
Short name T488
Test name
Test status
Simulation time 32634651840 ps
CPU time 289.72 seconds
Started Mar 21 03:21:39 PM PDT 24
Finished Mar 21 03:26:29 PM PDT 24
Peak memory 212212 kb
Host smart-8aecb581-d717-4a8c-b15a-7832a2595ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810396960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2810396960
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2627108642
Short name T332
Test name
Test status
Simulation time 1423517760 ps
CPU time 19.02 seconds
Started Mar 21 03:21:44 PM PDT 24
Finished Mar 21 03:22:03 PM PDT 24
Peak memory 211480 kb
Host smart-5e2879eb-a185-49be-8b32-2ee8467ff106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627108642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2627108642
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3516670490
Short name T619
Test name
Test status
Simulation time 6270999718 ps
CPU time 19.97 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:28 PM PDT 24
Peak memory 210908 kb
Host smart-ffca02fd-85cf-44c3-b547-18bfa3632d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516670490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3516670490
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.392833513
Short name T519
Test name
Test status
Simulation time 11569991726 ps
CPU time 9.2 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:21:49 PM PDT 24
Peak memory 210916 kb
Host smart-8f8bf664-eb4f-4cb4-8288-efae9deffc78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=392833513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.392833513
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.756933532
Short name T159
Test name
Test status
Simulation time 99663849 ps
CPU time 5.48 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:14 PM PDT 24
Peak memory 210808 kb
Host smart-2fef64b1-2677-4035-8024-f88b73f998b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=756933532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.756933532
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3234174107
Short name T77
Test name
Test status
Simulation time 3171682839 ps
CPU time 32.45 seconds
Started Mar 21 03:21:38 PM PDT 24
Finished Mar 21 03:22:11 PM PDT 24
Peak memory 212464 kb
Host smart-49e01b55-5bdc-4b2a-96dd-5af6df94ef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234174107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3234174107
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3469956564
Short name T377
Test name
Test status
Simulation time 7749968603 ps
CPU time 32.33 seconds
Started Mar 21 01:36:06 PM PDT 24
Finished Mar 21 01:36:39 PM PDT 24
Peak memory 214336 kb
Host smart-d511fadd-040b-4ec6-8994-b9affc6d0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469956564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3469956564
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2570851365
Short name T373
Test name
Test status
Simulation time 4613496226 ps
CPU time 27.99 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:22:08 PM PDT 24
Peak memory 219092 kb
Host smart-8725d79c-a7f7-4709-97b8-aa3f81ddf184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570851365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2570851365
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3723413532
Short name T443
Test name
Test status
Simulation time 2153169592 ps
CPU time 18.02 seconds
Started Mar 21 01:36:05 PM PDT 24
Finished Mar 21 01:36:25 PM PDT 24
Peak memory 211244 kb
Host smart-7bd144cb-ae0c-4036-a5da-fee6ae6d2816
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723413532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3723413532
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3789096907
Short name T506
Test name
Test status
Simulation time 4923397903 ps
CPU time 11.64 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:21:52 PM PDT 24
Peak memory 210960 kb
Host smart-21355a4f-3c6f-426b-869d-5c9d65428096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789096907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3789096907
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.427702262
Short name T463
Test name
Test status
Simulation time 2189628999 ps
CPU time 17.31 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:36:31 PM PDT 24
Peak memory 210952 kb
Host smart-b9e7d14c-148a-451f-b880-4f1e77e7556b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427702262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.427702262
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3826138935
Short name T278
Test name
Test status
Simulation time 53125613010 ps
CPU time 183.4 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:39:16 PM PDT 24
Peak memory 244784 kb
Host smart-8ae82cd5-86ba-4848-a0bf-8699c1d479ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826138935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3826138935
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.667576645
Short name T505
Test name
Test status
Simulation time 2105588690 ps
CPU time 137.39 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 230220 kb
Host smart-e54e00b8-d0c7-47c9-a470-4f3f55a46d4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667576645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.667576645
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2369654924
Short name T476
Test name
Test status
Simulation time 56894909691 ps
CPU time 28.52 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:36:41 PM PDT 24
Peak memory 212016 kb
Host smart-d6757314-1f7d-43f4-88ba-d73a6478d597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369654924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2369654924
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.366164474
Short name T186
Test name
Test status
Simulation time 3144016507 ps
CPU time 14.27 seconds
Started Mar 21 03:21:39 PM PDT 24
Finished Mar 21 03:21:53 PM PDT 24
Peak memory 211444 kb
Host smart-a3d60701-f46c-4640-94e0-4ed921a81275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366164474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.366164474
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4231135467
Short name T151
Test name
Test status
Simulation time 1472617761 ps
CPU time 13.76 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:21:54 PM PDT 24
Peak memory 210836 kb
Host smart-b44ce089-c871-4648-b4cb-6e9b50d71178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231135467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4231135467
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.605162101
Short name T420
Test name
Test status
Simulation time 3685408444 ps
CPU time 16.06 seconds
Started Mar 21 01:36:02 PM PDT 24
Finished Mar 21 01:36:19 PM PDT 24
Peak memory 210840 kb
Host smart-7fdd8551-ef89-47d0-8c5e-1410d9b2c70c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605162101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.605162101
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1410994212
Short name T652
Test name
Test status
Simulation time 51235011729 ps
CPU time 29.52 seconds
Started Mar 21 03:21:42 PM PDT 24
Finished Mar 21 03:22:11 PM PDT 24
Peak memory 213944 kb
Host smart-4adaaa04-e286-4f2b-a9f4-42c83829ceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410994212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1410994212
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3933000832
Short name T589
Test name
Test status
Simulation time 1692094153 ps
CPU time 20.3 seconds
Started Mar 21 01:35:55 PM PDT 24
Finished Mar 21 01:36:15 PM PDT 24
Peak memory 218940 kb
Host smart-4cd1a68d-d092-4f24-a0b2-12f4284b6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933000832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3933000832
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1666274538
Short name T410
Test name
Test status
Simulation time 8575055046 ps
CPU time 65.86 seconds
Started Mar 21 03:21:40 PM PDT 24
Finished Mar 21 03:22:46 PM PDT 24
Peak memory 217064 kb
Host smart-eb5e9437-1841-44d3-905e-158f7b598fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666274538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1666274538
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2446202432
Short name T605
Test name
Test status
Simulation time 1340895646 ps
CPU time 13.41 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:22 PM PDT 24
Peak memory 211260 kb
Host smart-f7bb2d51-9c74-4ed2-9a63-afba7a267ade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446202432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2446202432
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.743480188
Short name T300
Test name
Test status
Simulation time 1846383937 ps
CPU time 14.53 seconds
Started Mar 21 03:21:53 PM PDT 24
Finished Mar 21 03:22:08 PM PDT 24
Peak memory 210880 kb
Host smart-f699ee99-41f2-461a-8938-5d0d19d2d459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743480188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.743480188
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.9163261
Short name T490
Test name
Test status
Simulation time 2808624313 ps
CPU time 8.58 seconds
Started Mar 21 01:36:15 PM PDT 24
Finished Mar 21 01:36:25 PM PDT 24
Peak memory 210796 kb
Host smart-451c6167-6184-4940-8c3a-7e9919c60501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9163261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.9163261
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1208028164
Short name T663
Test name
Test status
Simulation time 202624143688 ps
CPU time 524.06 seconds
Started Mar 21 03:21:51 PM PDT 24
Finished Mar 21 03:30:36 PM PDT 24
Peak memory 240940 kb
Host smart-6d568089-150f-4528-9f89-279a0c717b81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208028164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1208028164
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1288257447
Short name T224
Test name
Test status
Simulation time 80430744355 ps
CPU time 325.69 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:41:38 PM PDT 24
Peak memory 224548 kb
Host smart-7cdb9c3a-4711-4579-b8fd-43d5d1c16c00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288257447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1288257447
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2583497586
Short name T382
Test name
Test status
Simulation time 1843212040 ps
CPU time 15.56 seconds
Started Mar 21 03:21:50 PM PDT 24
Finished Mar 21 03:22:06 PM PDT 24
Peak memory 211592 kb
Host smart-d679e18e-38cd-460e-b379-c94bff2768ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583497586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2583497586
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2674346070
Short name T134
Test name
Test status
Simulation time 2750375969 ps
CPU time 14 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:36:27 PM PDT 24
Peak memory 211828 kb
Host smart-31fe7149-eab6-4768-a0c0-4b2ef3b5d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674346070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2674346070
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2366051168
Short name T268
Test name
Test status
Simulation time 2222171040 ps
CPU time 17.67 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:26 PM PDT 24
Peak memory 210828 kb
Host smart-0a4ba90d-0993-4cee-bb27-ce767ac67d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366051168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2366051168
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.988881567
Short name T651
Test name
Test status
Simulation time 190548077 ps
CPU time 5.76 seconds
Started Mar 21 03:21:48 PM PDT 24
Finished Mar 21 03:21:54 PM PDT 24
Peak memory 210896 kb
Host smart-95a253f1-576b-425c-ba96-e3b1100d0e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988881567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.988881567
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2950150294
Short name T417
Test name
Test status
Simulation time 10261362328 ps
CPU time 32.55 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:36:42 PM PDT 24
Peak memory 213488 kb
Host smart-661208b4-1f95-41ce-a708-cac2c153d8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950150294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2950150294
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.478669462
Short name T153
Test name
Test status
Simulation time 785826029 ps
CPU time 15.67 seconds
Started Mar 21 03:21:39 PM PDT 24
Finished Mar 21 03:21:55 PM PDT 24
Peak memory 212776 kb
Host smart-e6d4c8ac-837b-4061-beb6-bbc43882901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478669462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.478669462
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1874213336
Short name T217
Test name
Test status
Simulation time 9393861881 ps
CPU time 39.52 seconds
Started Mar 21 03:21:56 PM PDT 24
Finished Mar 21 03:22:36 PM PDT 24
Peak memory 219056 kb
Host smart-501aa031-c4e0-4029-9291-50ff3a37dd9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874213336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1874213336
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2542028648
Short name T642
Test name
Test status
Simulation time 17114202312 ps
CPU time 139.75 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:38:29 PM PDT 24
Peak memory 219032 kb
Host smart-f91cbb1b-076d-46c6-a7e4-438bf80e85f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542028648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2542028648
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2217373706
Short name T331
Test name
Test status
Simulation time 412552711 ps
CPU time 5.61 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:36:17 PM PDT 24
Peak memory 210784 kb
Host smart-87fa3105-3839-4aab-8c86-d4e85997434e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217373706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2217373706
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3066967977
Short name T213
Test name
Test status
Simulation time 174885256 ps
CPU time 4.26 seconds
Started Mar 21 03:21:48 PM PDT 24
Finished Mar 21 03:21:53 PM PDT 24
Peak memory 210796 kb
Host smart-c45ce2c8-92d7-4e17-a4e6-77640c447f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066967977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3066967977
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1972744828
Short name T216
Test name
Test status
Simulation time 25036089118 ps
CPU time 94.94 seconds
Started Mar 21 03:21:53 PM PDT 24
Finished Mar 21 03:23:28 PM PDT 24
Peak memory 236592 kb
Host smart-b3ed285e-e7dc-496f-aa5c-bfc2b1c9f4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972744828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1972744828
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3444815269
Short name T345
Test name
Test status
Simulation time 89396494738 ps
CPU time 278.72 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:40:49 PM PDT 24
Peak memory 227984 kb
Host smart-54b64230-84d6-4580-a889-c94825423909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444815269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3444815269
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2920691101
Short name T475
Test name
Test status
Simulation time 667364025 ps
CPU time 9.32 seconds
Started Mar 21 03:21:53 PM PDT 24
Finished Mar 21 03:22:03 PM PDT 24
Peak memory 212244 kb
Host smart-3a46b650-840b-4df6-b981-26969bcc9f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920691101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2920691101
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2932622112
Short name T483
Test name
Test status
Simulation time 3219405077 ps
CPU time 27.69 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:44 PM PDT 24
Peak memory 211392 kb
Host smart-fd355c8c-bf74-48e7-bae3-2995f16d3b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932622112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2932622112
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3333480027
Short name T337
Test name
Test status
Simulation time 9483766183 ps
CPU time 9.33 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:36:19 PM PDT 24
Peak memory 210844 kb
Host smart-c320557e-3638-4f4c-977f-6d0573ffb89a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333480027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3333480027
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.447041665
Short name T461
Test name
Test status
Simulation time 393690485 ps
CPU time 5.84 seconds
Started Mar 21 03:21:50 PM PDT 24
Finished Mar 21 03:21:56 PM PDT 24
Peak memory 210872 kb
Host smart-85877489-67c1-48f3-877d-9e7e50918d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=447041665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.447041665
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2194697419
Short name T428
Test name
Test status
Simulation time 12042519803 ps
CPU time 27.22 seconds
Started Mar 21 03:21:54 PM PDT 24
Finished Mar 21 03:22:21 PM PDT 24
Peak memory 214036 kb
Host smart-e6b680e5-6e08-4f58-8c12-a291ea1544b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194697419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2194697419
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.869103406
Short name T196
Test name
Test status
Simulation time 6929883341 ps
CPU time 29.11 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:36:39 PM PDT 24
Peak memory 213932 kb
Host smart-b8953963-3b7d-4aca-b82c-54c8947a4873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869103406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.869103406
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3593421212
Short name T527
Test name
Test status
Simulation time 862123064 ps
CPU time 13.98 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:36:23 PM PDT 24
Peak memory 213552 kb
Host smart-fc504e8c-59a2-4d87-8e27-dc85fdb9a9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593421212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3593421212
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4201162225
Short name T281
Test name
Test status
Simulation time 141698712 ps
CPU time 10.91 seconds
Started Mar 21 03:21:50 PM PDT 24
Finished Mar 21 03:22:01 PM PDT 24
Peak memory 210840 kb
Host smart-de8542db-4968-4738-a899-7c7f0c55d912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201162225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4201162225
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2167987365
Short name T352
Test name
Test status
Simulation time 15630615889 ps
CPU time 471.56 seconds
Started Mar 21 03:21:52 PM PDT 24
Finished Mar 21 03:29:43 PM PDT 24
Peak memory 224036 kb
Host smart-81e46723-b3a5-4449-8bc7-401d7083ca57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167987365 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2167987365
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1283253104
Short name T389
Test name
Test status
Simulation time 19539296953 ps
CPU time 16.15 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:33 PM PDT 24
Peak memory 210792 kb
Host smart-145b11e8-1981-4906-a8ff-b9450e634363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283253104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1283253104
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1835243834
Short name T32
Test name
Test status
Simulation time 630197616 ps
CPU time 8.2 seconds
Started Mar 21 03:21:50 PM PDT 24
Finished Mar 21 03:21:58 PM PDT 24
Peak memory 210904 kb
Host smart-03b4150e-d646-4dd6-8dcb-61306e9e3b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835243834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1835243834
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.361331057
Short name T327
Test name
Test status
Simulation time 139159354368 ps
CPU time 393.18 seconds
Started Mar 21 03:21:55 PM PDT 24
Finished Mar 21 03:28:28 PM PDT 24
Peak memory 219328 kb
Host smart-045d59c1-f5b8-48b6-bf31-e826baa69834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361331057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.361331057
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1771779952
Short name T577
Test name
Test status
Simulation time 293597142 ps
CPU time 9.44 seconds
Started Mar 21 03:21:51 PM PDT 24
Finished Mar 21 03:22:00 PM PDT 24
Peak memory 211516 kb
Host smart-54420a99-6aa7-457b-ae67-205a62f5be23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771779952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1771779952
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.396868625
Short name T671
Test name
Test status
Simulation time 3591544930 ps
CPU time 29.26 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:36:41 PM PDT 24
Peak memory 211668 kb
Host smart-30b02788-bcbb-4d52-b3cb-9a76c2993644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396868625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.396868625
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1289091151
Short name T317
Test name
Test status
Simulation time 4476613787 ps
CPU time 11.88 seconds
Started Mar 21 03:21:51 PM PDT 24
Finished Mar 21 03:22:03 PM PDT 24
Peak memory 210896 kb
Host smart-7e8252ea-a87f-4871-87b5-162bf8c3ef9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289091151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1289091151
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3372383866
Short name T631
Test name
Test status
Simulation time 6704753893 ps
CPU time 12.45 seconds
Started Mar 21 01:36:08 PM PDT 24
Finished Mar 21 01:36:21 PM PDT 24
Peak memory 210836 kb
Host smart-365f723e-283b-4da7-8b51-028f074188b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372383866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3372383866
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1748657659
Short name T346
Test name
Test status
Simulation time 4724284853 ps
CPU time 32.83 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:36:45 PM PDT 24
Peak memory 213368 kb
Host smart-01bd0155-77be-4b47-8713-c8615e3f4010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748657659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1748657659
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3866289129
Short name T636
Test name
Test status
Simulation time 3282290031 ps
CPU time 32.66 seconds
Started Mar 21 03:21:55 PM PDT 24
Finished Mar 21 03:22:28 PM PDT 24
Peak memory 219060 kb
Host smart-c8fcab21-af58-44d2-94b2-1dcfeba4d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866289129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3866289129
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1998673280
Short name T326
Test name
Test status
Simulation time 28067499291 ps
CPU time 44.09 seconds
Started Mar 21 03:21:48 PM PDT 24
Finished Mar 21 03:22:32 PM PDT 24
Peak memory 214048 kb
Host smart-d0475e13-0291-411a-812d-6059066bdedb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998673280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1998673280
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.491821695
Short name T211
Test name
Test status
Simulation time 7200664231 ps
CPU time 19.63 seconds
Started Mar 21 01:36:07 PM PDT 24
Finished Mar 21 01:36:27 PM PDT 24
Peak memory 218984 kb
Host smart-435c516f-8662-44d1-b51e-96d6f18c03e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491821695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.491821695
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1777045434
Short name T347
Test name
Test status
Simulation time 351787982329 ps
CPU time 3378.89 seconds
Started Mar 21 03:21:56 PM PDT 24
Finished Mar 21 04:18:15 PM PDT 24
Peak memory 243784 kb
Host smart-ebb202a4-83d6-4223-a9cf-b8c8a319a939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777045434 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1777045434
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1240826210
Short name T644
Test name
Test status
Simulation time 1701927074 ps
CPU time 14.56 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:36:24 PM PDT 24
Peak memory 210760 kb
Host smart-e8889ba3-4a43-4adf-8a34-700830ee347b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240826210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1240826210
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.170188605
Short name T201
Test name
Test status
Simulation time 981910153 ps
CPU time 9.93 seconds
Started Mar 21 03:21:48 PM PDT 24
Finished Mar 21 03:21:58 PM PDT 24
Peak memory 210880 kb
Host smart-17efc06d-14bf-4ee8-96e8-519184b226f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170188605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.170188605
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1503527732
Short name T385
Test name
Test status
Simulation time 36553354578 ps
CPU time 344.79 seconds
Started Mar 21 03:21:56 PM PDT 24
Finished Mar 21 03:27:41 PM PDT 24
Peak memory 224652 kb
Host smart-342c0017-5c1d-491c-b559-8628dae90b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503527732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1503527732
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1528808073
Short name T381
Test name
Test status
Simulation time 51906458599 ps
CPU time 157.89 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:38:51 PM PDT 24
Peak memory 236392 kb
Host smart-616d66c0-1fcf-478a-9d6b-278f6c2aa997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528808073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1528808073
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2806321398
Short name T491
Test name
Test status
Simulation time 172341361 ps
CPU time 9.22 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:20 PM PDT 24
Peak memory 211692 kb
Host smart-54dd5337-d30f-41b9-ba6a-f8861925da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806321398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2806321398
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3542969619
Short name T98
Test name
Test status
Simulation time 598394701 ps
CPU time 13.2 seconds
Started Mar 21 03:21:50 PM PDT 24
Finished Mar 21 03:22:03 PM PDT 24
Peak memory 210924 kb
Host smart-51a4d577-d01c-48b6-93e8-44a149ff9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542969619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3542969619
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3799445437
Short name T276
Test name
Test status
Simulation time 11764961290 ps
CPU time 13.81 seconds
Started Mar 21 03:21:50 PM PDT 24
Finished Mar 21 03:22:04 PM PDT 24
Peak memory 210892 kb
Host smart-cd27b8e1-ee99-4bfe-adad-f3bc2522a7aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3799445437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3799445437
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.666393766
Short name T617
Test name
Test status
Simulation time 1272514190 ps
CPU time 8.9 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:19 PM PDT 24
Peak memory 210780 kb
Host smart-e84c711e-67ff-4104-aa84-a3ec7ce9d8f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666393766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.666393766
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1138412956
Short name T572
Test name
Test status
Simulation time 33976390019 ps
CPU time 30.24 seconds
Started Mar 21 03:21:49 PM PDT 24
Finished Mar 21 03:22:19 PM PDT 24
Peak memory 213732 kb
Host smart-81df40f6-12e4-456e-93de-00d40da7df58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138412956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1138412956
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1410886690
Short name T406
Test name
Test status
Simulation time 3852127489 ps
CPU time 38.5 seconds
Started Mar 21 01:36:14 PM PDT 24
Finished Mar 21 01:36:52 PM PDT 24
Peak memory 212620 kb
Host smart-dec5c7b5-6ed1-4956-a2e7-e990ab5a0b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410886690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1410886690
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1759689448
Short name T234
Test name
Test status
Simulation time 1445111011 ps
CPU time 10.26 seconds
Started Mar 21 03:21:52 PM PDT 24
Finished Mar 21 03:22:03 PM PDT 24
Peak memory 214232 kb
Host smart-a3d902ae-4161-40d9-b42e-453ad7004731
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759689448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1759689448
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2616436667
Short name T626
Test name
Test status
Simulation time 8849385904 ps
CPU time 56.55 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:37:13 PM PDT 24
Peak memory 218892 kb
Host smart-9d4662b9-0dee-4bea-b225-f946efea9569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616436667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2616436667
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2180955287
Short name T576
Test name
Test status
Simulation time 2145712435 ps
CPU time 8.16 seconds
Started Mar 21 03:21:58 PM PDT 24
Finished Mar 21 03:22:06 PM PDT 24
Peak memory 210904 kb
Host smart-b91943d3-f4aa-44e6-aea2-cb403e924032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180955287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2180955287
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2988627358
Short name T614
Test name
Test status
Simulation time 2113089087 ps
CPU time 16.1 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:27 PM PDT 24
Peak memory 210840 kb
Host smart-ff8effe5-c632-4463-9e11-9ef2ba8feaa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988627358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2988627358
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3261037363
Short name T253
Test name
Test status
Simulation time 27855571908 ps
CPU time 188.89 seconds
Started Mar 21 03:21:57 PM PDT 24
Finished Mar 21 03:25:07 PM PDT 24
Peak memory 212220 kb
Host smart-fa6f6161-7ca9-436f-90b1-0108682b7eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261037363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3261037363
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.553835609
Short name T274
Test name
Test status
Simulation time 34835961885 ps
CPU time 266.43 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:40:43 PM PDT 24
Peak memory 228164 kb
Host smart-2c2100ba-cae4-4fe0-9ed5-452c30d05c37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553835609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.553835609
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2072091650
Short name T500
Test name
Test status
Simulation time 8337651839 ps
CPU time 33.27 seconds
Started Mar 21 01:36:14 PM PDT 24
Finished Mar 21 01:36:48 PM PDT 24
Peak memory 212096 kb
Host smart-ed8fcfd2-570f-4c24-99eb-6efca80980b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072091650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2072091650
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4164423206
Short name T424
Test name
Test status
Simulation time 6425873551 ps
CPU time 21.86 seconds
Started Mar 21 03:21:59 PM PDT 24
Finished Mar 21 03:22:21 PM PDT 24
Peak memory 211900 kb
Host smart-80c3cb7c-0562-4f9b-a56f-24e0efa67601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164423206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4164423206
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.179355577
Short name T550
Test name
Test status
Simulation time 4299752234 ps
CPU time 11.39 seconds
Started Mar 21 03:21:57 PM PDT 24
Finished Mar 21 03:22:09 PM PDT 24
Peak memory 210920 kb
Host smart-d3604390-656b-4b40-b186-33b5be3d3a1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179355577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.179355577
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.346754691
Short name T511
Test name
Test status
Simulation time 1062175622 ps
CPU time 11.4 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:22 PM PDT 24
Peak memory 210784 kb
Host smart-1a3aa0bd-e4fc-4dbf-a99a-808693f8a8e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346754691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.346754691
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3899769755
Short name T370
Test name
Test status
Simulation time 3068560122 ps
CPU time 31.32 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:36:43 PM PDT 24
Peak memory 212860 kb
Host smart-513959ef-f9bc-4d29-a3a1-04d2397a601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899769755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3899769755
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.404380245
Short name T248
Test name
Test status
Simulation time 68781754212 ps
CPU time 31.19 seconds
Started Mar 21 03:21:59 PM PDT 24
Finished Mar 21 03:22:30 PM PDT 24
Peak memory 214128 kb
Host smart-0205b110-9736-40e0-b1ac-08f1087f11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404380245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.404380245
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2111529697
Short name T282
Test name
Test status
Simulation time 2858519729 ps
CPU time 16.36 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:36:30 PM PDT 24
Peak memory 210832 kb
Host smart-f8d329ba-68aa-45e7-bdbf-82e22c6d1a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111529697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2111529697
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3053139767
Short name T287
Test name
Test status
Simulation time 3142358764 ps
CPU time 40.68 seconds
Started Mar 21 03:22:03 PM PDT 24
Finished Mar 21 03:22:44 PM PDT 24
Peak memory 215588 kb
Host smart-23675d06-799b-4aa3-9390-f3bf42894a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053139767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3053139767
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1679478506
Short name T11
Test name
Test status
Simulation time 111664421407 ps
CPU time 4141.61 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 02:45:13 PM PDT 24
Peak memory 243732 kb
Host smart-7bd25957-fd52-49f4-b9cb-77fa11bb4ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679478506 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1679478506
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1987552351
Short name T574
Test name
Test status
Simulation time 43078863402 ps
CPU time 1739.87 seconds
Started Mar 21 03:21:59 PM PDT 24
Finished Mar 21 03:50:59 PM PDT 24
Peak memory 235544 kb
Host smart-6c698558-e6ea-4e1c-ab64-2711ebaf89d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987552351 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1987552351
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1326964287
Short name T391
Test name
Test status
Simulation time 292645559 ps
CPU time 6.59 seconds
Started Mar 21 01:36:09 PM PDT 24
Finished Mar 21 01:36:16 PM PDT 24
Peak memory 210832 kb
Host smart-228a9335-5489-4602-a44e-93937e53bf14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326964287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1326964287
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3007966220
Short name T187
Test name
Test status
Simulation time 19161159006 ps
CPU time 16.68 seconds
Started Mar 21 03:22:00 PM PDT 24
Finished Mar 21 03:22:17 PM PDT 24
Peak memory 210932 kb
Host smart-f8873723-47f9-473f-a909-c873502870d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007966220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3007966220
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2253446504
Short name T256
Test name
Test status
Simulation time 20265831395 ps
CPU time 147.4 seconds
Started Mar 21 03:21:58 PM PDT 24
Finished Mar 21 03:24:26 PM PDT 24
Peak memory 219336 kb
Host smart-6d2d390b-52ec-4292-8c7f-0475ada4f341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253446504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2253446504
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.503893086
Short name T26
Test name
Test status
Simulation time 14286305457 ps
CPU time 122.06 seconds
Started Mar 21 01:36:14 PM PDT 24
Finished Mar 21 01:38:16 PM PDT 24
Peak memory 211100 kb
Host smart-64e7e71e-0b85-40ce-965c-19d680a993cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503893086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.503893086
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2458698017
Short name T22
Test name
Test status
Simulation time 4390266655 ps
CPU time 34.2 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:45 PM PDT 24
Peak memory 211648 kb
Host smart-422629b7-e48a-487b-a0bc-bf5d180f4045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458698017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2458698017
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3007576667
Short name T209
Test name
Test status
Simulation time 2532981132 ps
CPU time 25.01 seconds
Started Mar 21 03:22:01 PM PDT 24
Finished Mar 21 03:22:26 PM PDT 24
Peak memory 211344 kb
Host smart-2f3ec394-38d8-4333-b84d-98a3eba6bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007576667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3007576667
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3296487686
Short name T645
Test name
Test status
Simulation time 7661567227 ps
CPU time 16.55 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:36:30 PM PDT 24
Peak memory 210832 kb
Host smart-7c0f12db-5be9-47a2-bbc2-7484d819c36b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296487686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3296487686
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.331846045
Short name T409
Test name
Test status
Simulation time 98697751 ps
CPU time 5.72 seconds
Started Mar 21 03:21:59 PM PDT 24
Finished Mar 21 03:22:05 PM PDT 24
Peak memory 210748 kb
Host smart-f1b06eb4-fb44-4d0d-bfb7-e34158b3e36e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331846045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.331846045
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.4223580441
Short name T620
Test name
Test status
Simulation time 7250502925 ps
CPU time 31.51 seconds
Started Mar 21 03:21:58 PM PDT 24
Finished Mar 21 03:22:30 PM PDT 24
Peak memory 219064 kb
Host smart-64087ada-6b55-4df3-a061-a0f1f4d4d118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223580441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.4223580441
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.444296901
Short name T363
Test name
Test status
Simulation time 183751719 ps
CPU time 10.55 seconds
Started Mar 21 01:36:12 PM PDT 24
Finished Mar 21 01:36:23 PM PDT 24
Peak memory 212916 kb
Host smart-ffcb1291-2dc4-494d-bf85-e960f8ccaf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444296901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.444296901
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.274183772
Short name T604
Test name
Test status
Simulation time 1022219578 ps
CPU time 21.03 seconds
Started Mar 21 03:21:57 PM PDT 24
Finished Mar 21 03:22:19 PM PDT 24
Peak memory 214660 kb
Host smart-1cc02315-3257-481a-b899-17e18e6b2535
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274183772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.274183772
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3093110723
Short name T561
Test name
Test status
Simulation time 3916633687 ps
CPU time 19.35 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:30 PM PDT 24
Peak memory 213284 kb
Host smart-c2860480-29ad-4c34-8004-613304d1677f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093110723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3093110723
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1790831470
Short name T553
Test name
Test status
Simulation time 24793061125 ps
CPU time 11.9 seconds
Started Mar 21 03:22:01 PM PDT 24
Finished Mar 21 03:22:13 PM PDT 24
Peak memory 210968 kb
Host smart-1ca9bca2-522d-4131-bdbf-c020072e4b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790831470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1790831470
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2373982257
Short name T537
Test name
Test status
Simulation time 1233238382 ps
CPU time 11.99 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:28 PM PDT 24
Peak memory 210832 kb
Host smart-66609dae-9e9c-40d8-a8d4-023682906bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373982257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2373982257
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4109335652
Short name T255
Test name
Test status
Simulation time 13166583731 ps
CPU time 218.28 seconds
Started Mar 21 03:21:57 PM PDT 24
Finished Mar 21 03:25:36 PM PDT 24
Peak memory 237532 kb
Host smart-6f7a14fd-7071-4716-bac9-83e51bb0ee86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109335652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4109335652
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.686019705
Short name T212
Test name
Test status
Simulation time 47840666409 ps
CPU time 209.12 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:39:43 PM PDT 24
Peak memory 237524 kb
Host smart-e2ee21b0-88f6-42f2-a085-61ea862ece97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686019705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.686019705
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1360100808
Short name T637
Test name
Test status
Simulation time 6083416858 ps
CPU time 19.88 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:36 PM PDT 24
Peak memory 211864 kb
Host smart-acdf76ac-33dc-44fc-8eb2-08ad8c937dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360100808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1360100808
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2222990207
Short name T289
Test name
Test status
Simulation time 27385398183 ps
CPU time 20.38 seconds
Started Mar 21 03:21:57 PM PDT 24
Finished Mar 21 03:22:17 PM PDT 24
Peak memory 211840 kb
Host smart-478b1728-ef3b-4a24-8474-1d6a6f259fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222990207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2222990207
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.117807212
Short name T137
Test name
Test status
Simulation time 4272505313 ps
CPU time 17.17 seconds
Started Mar 21 03:21:57 PM PDT 24
Finished Mar 21 03:22:15 PM PDT 24
Peak memory 210900 kb
Host smart-2861c167-6a4c-4a39-ae75-374d0fcde5a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117807212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.117807212
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1620476077
Short name T422
Test name
Test status
Simulation time 97837575 ps
CPU time 5.63 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:22 PM PDT 24
Peak memory 210780 kb
Host smart-6c22c9e3-4383-48c3-a8b6-192d63b1ceba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620476077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1620476077
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1134502767
Short name T318
Test name
Test status
Simulation time 5691599932 ps
CPU time 17.5 seconds
Started Mar 21 03:21:58 PM PDT 24
Finished Mar 21 03:22:16 PM PDT 24
Peak memory 219084 kb
Host smart-03709acf-4202-42bd-8773-bdfc309c6427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134502767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1134502767
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.998166648
Short name T628
Test name
Test status
Simulation time 727450708 ps
CPU time 10.21 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:20 PM PDT 24
Peak memory 218924 kb
Host smart-ccae78a5-7203-4631-93de-f77b48d80ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998166648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.998166648
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1262580394
Short name T559
Test name
Test status
Simulation time 464779432 ps
CPU time 22.14 seconds
Started Mar 21 01:36:14 PM PDT 24
Finished Mar 21 01:36:36 PM PDT 24
Peak memory 215408 kb
Host smart-88d2dbf5-999b-4452-a5f9-7ece63c473cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262580394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1262580394
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1716434454
Short name T208
Test name
Test status
Simulation time 14162213229 ps
CPU time 47.07 seconds
Started Mar 21 03:21:59 PM PDT 24
Finished Mar 21 03:22:46 PM PDT 24
Peak memory 219040 kb
Host smart-16a547a0-6128-402d-a0c1-f56f59b61f93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716434454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1716434454
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2162611526
Short name T157
Test name
Test status
Simulation time 3429377652 ps
CPU time 9.97 seconds
Started Mar 21 01:36:13 PM PDT 24
Finished Mar 21 01:36:23 PM PDT 24
Peak memory 210904 kb
Host smart-53aeb010-6484-4184-aa6a-b1cb6ce1f0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162611526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2162611526
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2538632217
Short name T392
Test name
Test status
Simulation time 12838617200 ps
CPU time 16.56 seconds
Started Mar 21 03:22:02 PM PDT 24
Finished Mar 21 03:22:19 PM PDT 24
Peak memory 210964 kb
Host smart-c2ee21f8-135d-47f4-8c09-02156ae3f2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538632217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2538632217
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2064726672
Short name T176
Test name
Test status
Simulation time 38182991782 ps
CPU time 347.23 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:41:58 PM PDT 24
Peak memory 231040 kb
Host smart-95303125-ee16-41c3-a7cb-1f2ac85e8c5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064726672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2064726672
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4282911782
Short name T679
Test name
Test status
Simulation time 22061970280 ps
CPU time 242.03 seconds
Started Mar 21 03:22:00 PM PDT 24
Finished Mar 21 03:26:02 PM PDT 24
Peak memory 241704 kb
Host smart-18278e6c-e80d-49b2-9ef2-66f36c9e01aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282911782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4282911782
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1413414617
Short name T457
Test name
Test status
Simulation time 3952852493 ps
CPU time 34.44 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:51 PM PDT 24
Peak memory 211520 kb
Host smart-d8cf7ac7-47b3-4ea7-afa0-dfb6671027fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413414617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1413414617
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4271718617
Short name T436
Test name
Test status
Simulation time 12875708974 ps
CPU time 16.13 seconds
Started Mar 21 03:21:59 PM PDT 24
Finished Mar 21 03:22:15 PM PDT 24
Peak memory 211864 kb
Host smart-c8a69862-a075-4de5-84f9-cae309278675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271718617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4271718617
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1112476125
Short name T5
Test name
Test status
Simulation time 403641571 ps
CPU time 5.66 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:22 PM PDT 24
Peak memory 210692 kb
Host smart-7c5b0dd7-71d4-4722-a7bb-0bbe5f5f72f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112476125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1112476125
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1496829214
Short name T405
Test name
Test status
Simulation time 1924992464 ps
CPU time 8.4 seconds
Started Mar 21 03:22:03 PM PDT 24
Finished Mar 21 03:22:12 PM PDT 24
Peak memory 210816 kb
Host smart-fce860c4-ab4b-4629-bc57-de8875ff5f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496829214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1496829214
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1071196342
Short name T685
Test name
Test status
Simulation time 3600140443 ps
CPU time 16.91 seconds
Started Mar 21 01:36:12 PM PDT 24
Finished Mar 21 01:36:29 PM PDT 24
Peak memory 213492 kb
Host smart-a6a19209-730a-4508-ade8-f3d5d949a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071196342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1071196342
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.593268396
Short name T411
Test name
Test status
Simulation time 361253355 ps
CPU time 9.63 seconds
Started Mar 21 03:22:01 PM PDT 24
Finished Mar 21 03:22:11 PM PDT 24
Peak memory 219012 kb
Host smart-c93cb351-08f1-47b6-95f3-b0848bcfd962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593268396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.593268396
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3633048079
Short name T673
Test name
Test status
Simulation time 11521251530 ps
CPU time 91.31 seconds
Started Mar 21 03:22:04 PM PDT 24
Finished Mar 21 03:23:35 PM PDT 24
Peak memory 216704 kb
Host smart-a8fc5533-8ea6-42f1-9e0f-21611e99a22f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633048079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3633048079
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.950091296
Short name T517
Test name
Test status
Simulation time 446572291 ps
CPU time 16.31 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:27 PM PDT 24
Peak memory 214572 kb
Host smart-b54b3e34-96d0-41fc-adb2-1855ec559b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950091296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.950091296
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4253461107
Short name T603
Test name
Test status
Simulation time 125956174263 ps
CPU time 7255.39 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 03:37:13 PM PDT 24
Peak memory 235516 kb
Host smart-160b00ff-0585-418b-800f-6c12abc440d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253461107 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.4253461107
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1215335511
Short name T616
Test name
Test status
Simulation time 4427969965 ps
CPU time 13.44 seconds
Started Mar 21 03:21:00 PM PDT 24
Finished Mar 21 03:21:14 PM PDT 24
Peak memory 211072 kb
Host smart-b6cb5c69-1618-4898-bd27-a8244e14eb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215335511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1215335511
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3109187600
Short name T495
Test name
Test status
Simulation time 11066165057 ps
CPU time 15.42 seconds
Started Mar 21 01:35:50 PM PDT 24
Finished Mar 21 01:36:06 PM PDT 24
Peak memory 210896 kb
Host smart-8b44e37d-0d34-49ef-a6b0-da4e25746510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109187600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3109187600
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.510328884
Short name T336
Test name
Test status
Simulation time 29010026854 ps
CPU time 122.31 seconds
Started Mar 21 01:35:58 PM PDT 24
Finished Mar 21 01:38:00 PM PDT 24
Peak memory 229568 kb
Host smart-5285cdc4-0afd-4d03-beab-65ef02d54043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510328884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.510328884
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1046749828
Short name T339
Test name
Test status
Simulation time 6166238932 ps
CPU time 27.23 seconds
Started Mar 21 03:20:57 PM PDT 24
Finished Mar 21 03:21:25 PM PDT 24
Peak memory 211812 kb
Host smart-3147112a-cb8b-4cc3-a138-ffa2076b5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046749828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1046749828
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.718385956
Short name T15
Test name
Test status
Simulation time 308976597 ps
CPU time 9.53 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 01:36:03 PM PDT 24
Peak memory 211316 kb
Host smart-9ef1eef0-4da0-4069-a5a8-c69d57f17730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718385956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.718385956
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1886781329
Short name T292
Test name
Test status
Simulation time 641168278 ps
CPU time 9.81 seconds
Started Mar 21 01:35:53 PM PDT 24
Finished Mar 21 01:36:03 PM PDT 24
Peak memory 210784 kb
Host smart-df767d74-f69d-4110-9b2f-1ae4bc92218a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886781329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1886781329
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1884115793
Short name T30
Test name
Test status
Simulation time 385507926 ps
CPU time 100.4 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 01:37:34 PM PDT 24
Peak memory 230412 kb
Host smart-9217adaf-272a-4cdf-aced-ceb4b9d5794b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884115793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1884115793
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.870555502
Short name T39
Test name
Test status
Simulation time 2089269271 ps
CPU time 56.76 seconds
Started Mar 21 03:20:57 PM PDT 24
Finished Mar 21 03:21:54 PM PDT 24
Peak memory 233220 kb
Host smart-1bf2ccb0-3c39-4d78-a487-fa188ae6c198
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870555502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.870555502
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1413496027
Short name T79
Test name
Test status
Simulation time 18404042311 ps
CPU time 37.4 seconds
Started Mar 21 01:35:48 PM PDT 24
Finished Mar 21 01:36:26 PM PDT 24
Peak memory 213652 kb
Host smart-af9f2866-922a-4b74-8781-8112ded89177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413496027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1413496027
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.577094633
Short name T303
Test name
Test status
Simulation time 34541274056 ps
CPU time 29.47 seconds
Started Mar 21 03:20:51 PM PDT 24
Finished Mar 21 03:21:20 PM PDT 24
Peak memory 219368 kb
Host smart-bbad206e-f8fc-4ead-b3a2-ee65240062f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577094633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.577094633
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3430436209
Short name T528
Test name
Test status
Simulation time 9512467897 ps
CPU time 29.81 seconds
Started Mar 21 03:20:51 PM PDT 24
Finished Mar 21 03:21:21 PM PDT 24
Peak memory 219352 kb
Host smart-9aa01903-c839-4e79-b3bf-0ad69c6d5300
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430436209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3430436209
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.456722177
Short name T438
Test name
Test status
Simulation time 13187796729 ps
CPU time 33.66 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 01:36:28 PM PDT 24
Peak memory 219024 kb
Host smart-01134b83-af7e-4a3f-9567-7b6519a69949
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456722177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.456722177
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2128375080
Short name T662
Test name
Test status
Simulation time 781244357 ps
CPU time 9.53 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:22:19 PM PDT 24
Peak memory 210888 kb
Host smart-d01f2f2a-3bc8-40a6-8968-5f806550fa02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128375080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2128375080
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3813178510
Short name T530
Test name
Test status
Simulation time 1658848399 ps
CPU time 4.33 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:21 PM PDT 24
Peak memory 210840 kb
Host smart-29a769db-9e59-4615-9f46-6b2ad498a66c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813178510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3813178510
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.166890767
Short name T277
Test name
Test status
Simulation time 636489369546 ps
CPU time 327.77 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:41:39 PM PDT 24
Peak memory 236468 kb
Host smart-950ca1cb-bdad-4626-8337-0ef461e13848
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166890767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.166890767
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2116166609
Short name T590
Test name
Test status
Simulation time 45707834446 ps
CPU time 411.54 seconds
Started Mar 21 03:22:01 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 228456 kb
Host smart-725294d5-97e7-41ab-987b-4370e0d57a4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116166609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2116166609
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.302852120
Short name T408
Test name
Test status
Simulation time 1976223644 ps
CPU time 20.69 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:31 PM PDT 24
Peak memory 211452 kb
Host smart-edf5bcee-0506-40bf-bd8c-723f0c928797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302852120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.302852120
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3717235683
Short name T412
Test name
Test status
Simulation time 4283505974 ps
CPU time 22.08 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:22:31 PM PDT 24
Peak memory 211584 kb
Host smart-3e03b62b-a5b0-4a04-b702-5f1341d7e6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717235683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3717235683
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3778341807
Short name T423
Test name
Test status
Simulation time 7247533462 ps
CPU time 15.25 seconds
Started Mar 21 01:36:18 PM PDT 24
Finished Mar 21 01:36:34 PM PDT 24
Peak memory 210852 kb
Host smart-38ffda3f-a7ee-4cee-9d93-341583b29035
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778341807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3778341807
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.885134605
Short name T97
Test name
Test status
Simulation time 4356179036 ps
CPU time 17.34 seconds
Started Mar 21 03:22:03 PM PDT 24
Finished Mar 21 03:22:20 PM PDT 24
Peak memory 210880 kb
Host smart-356f1534-0737-4de1-b4d2-76a637fac9fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885134605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.885134605
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2118323750
Short name T594
Test name
Test status
Simulation time 4120097234 ps
CPU time 22.99 seconds
Started Mar 21 03:21:57 PM PDT 24
Finished Mar 21 03:22:20 PM PDT 24
Peak memory 212932 kb
Host smart-83cf76e2-be2c-48d5-83f9-b5c2116dac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118323750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2118323750
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.494780468
Short name T546
Test name
Test status
Simulation time 8272552436 ps
CPU time 29.63 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:47 PM PDT 24
Peak memory 219004 kb
Host smart-cf355742-c773-448d-9e25-852d7fcd896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494780468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.494780468
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1331711080
Short name T238
Test name
Test status
Simulation time 372949270 ps
CPU time 19.59 seconds
Started Mar 21 03:21:59 PM PDT 24
Finished Mar 21 03:22:19 PM PDT 24
Peak memory 218976 kb
Host smart-97bb3421-5edc-4f40-969c-e35a3812632f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331711080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1331711080
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.381119344
Short name T459
Test name
Test status
Simulation time 321836136 ps
CPU time 8.34 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:25 PM PDT 24
Peak memory 210776 kb
Host smart-2e7713ae-042d-4e53-8abf-dcf9f7f64c86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381119344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.381119344
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2282211610
Short name T323
Test name
Test status
Simulation time 1714698255 ps
CPU time 14.43 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:22:23 PM PDT 24
Peak memory 210880 kb
Host smart-ae57401f-3410-4bd7-bf76-0dccd97733d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282211610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2282211610
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.930105050
Short name T585
Test name
Test status
Simulation time 332731836 ps
CPU time 4.29 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:21 PM PDT 24
Peak memory 210876 kb
Host smart-958c57a6-4a6a-4939-88db-f650db91191a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930105050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.930105050
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1688668414
Short name T484
Test name
Test status
Simulation time 45635667181 ps
CPU time 189.92 seconds
Started Mar 21 03:22:10 PM PDT 24
Finished Mar 21 03:25:20 PM PDT 24
Peak memory 229048 kb
Host smart-2a6f60cb-36e2-42a0-a8ec-65aca101d957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688668414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1688668414
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3598927090
Short name T384
Test name
Test status
Simulation time 85745203841 ps
CPU time 237.13 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:40:14 PM PDT 24
Peak memory 236908 kb
Host smart-9f7f4bab-76fd-4e6c-a874-2f79e788d098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598927090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3598927090
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.420698027
Short name T372
Test name
Test status
Simulation time 25398078279 ps
CPU time 26.26 seconds
Started Mar 21 03:22:10 PM PDT 24
Finished Mar 21 03:22:37 PM PDT 24
Peak memory 211764 kb
Host smart-03295555-172c-49dd-a4f0-4aa46b9a6bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420698027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.420698027
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.540557106
Short name T684
Test name
Test status
Simulation time 1350139954 ps
CPU time 18.29 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:35 PM PDT 24
Peak memory 211436 kb
Host smart-8186c466-9155-49b3-afa5-b5d07cfc1ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540557106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.540557106
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2963678756
Short name T379
Test name
Test status
Simulation time 2022863943 ps
CPU time 16.32 seconds
Started Mar 21 01:36:14 PM PDT 24
Finished Mar 21 01:36:30 PM PDT 24
Peak memory 210780 kb
Host smart-427eda5a-7416-4276-b734-92c60408f666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963678756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2963678756
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.806166421
Short name T657
Test name
Test status
Simulation time 1725152516 ps
CPU time 14.78 seconds
Started Mar 21 03:22:12 PM PDT 24
Finished Mar 21 03:22:27 PM PDT 24
Peak memory 210844 kb
Host smart-d68f7d8b-f43c-4410-b90d-b833aafcc334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806166421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.806166421
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.54973081
Short name T369
Test name
Test status
Simulation time 16554851283 ps
CPU time 18.22 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:22:28 PM PDT 24
Peak memory 219072 kb
Host smart-a76e40f1-819b-458c-86e2-7056d0a0959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54973081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.54973081
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.96170450
Short name T441
Test name
Test status
Simulation time 1325808635 ps
CPU time 17.92 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:35 PM PDT 24
Peak memory 218944 kb
Host smart-f7cf7237-3ac0-48cf-8314-f43d4d639aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96170450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.96170450
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1600361353
Short name T81
Test name
Test status
Simulation time 94418100572 ps
CPU time 59.49 seconds
Started Mar 21 01:36:15 PM PDT 24
Finished Mar 21 01:37:16 PM PDT 24
Peak memory 214916 kb
Host smart-b58ab9a4-e478-456c-bedd-500a8c10ec9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600361353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1600361353
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3786698099
Short name T375
Test name
Test status
Simulation time 5716456500 ps
CPU time 66.13 seconds
Started Mar 21 03:22:10 PM PDT 24
Finished Mar 21 03:23:16 PM PDT 24
Peak memory 216420 kb
Host smart-a72f12fa-cf60-4edd-9b74-689751a2f89d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786698099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3786698099
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.338980451
Short name T250
Test name
Test status
Simulation time 9969355029 ps
CPU time 17.66 seconds
Started Mar 21 03:22:11 PM PDT 24
Finished Mar 21 03:22:30 PM PDT 24
Peak memory 210952 kb
Host smart-2fc67994-2aa1-4238-8209-b28f7b2b6405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338980451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.338980451
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.975318982
Short name T445
Test name
Test status
Simulation time 162273742 ps
CPU time 4.43 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:22 PM PDT 24
Peak memory 210772 kb
Host smart-7798fe92-05d3-420a-ba3d-43cf6073f496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975318982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.975318982
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1911632099
Short name T599
Test name
Test status
Simulation time 9703628404 ps
CPU time 71.12 seconds
Started Mar 21 03:22:11 PM PDT 24
Finished Mar 21 03:23:22 PM PDT 24
Peak memory 227548 kb
Host smart-75128803-b753-4cc2-b279-d6865e2eb1dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911632099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1911632099
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2719736331
Short name T311
Test name
Test status
Simulation time 14219915148 ps
CPU time 211.53 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:39:48 PM PDT 24
Peak memory 228900 kb
Host smart-2e679939-6ae0-4c22-8c24-5358e45a64dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719736331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2719736331
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1151833229
Short name T448
Test name
Test status
Simulation time 5894036968 ps
CPU time 26.35 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:22:35 PM PDT 24
Peak memory 211852 kb
Host smart-40555cbe-bcaa-4191-838a-70da8625acc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151833229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1151833229
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.942691439
Short name T596
Test name
Test status
Simulation time 3674317269 ps
CPU time 31.18 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:49 PM PDT 24
Peak memory 209280 kb
Host smart-1b808b61-08fd-47db-84f0-7e3337d236ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942691439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.942691439
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2463427692
Short name T233
Test name
Test status
Simulation time 7918867336 ps
CPU time 16.58 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:34 PM PDT 24
Peak memory 210900 kb
Host smart-fce78b74-ceea-4e3d-a018-f2c8fc3f4149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463427692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2463427692
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3198028601
Short name T344
Test name
Test status
Simulation time 371881831 ps
CPU time 5.23 seconds
Started Mar 21 03:22:07 PM PDT 24
Finished Mar 21 03:22:12 PM PDT 24
Peak memory 210832 kb
Host smart-31d14a8d-bcf1-4049-941c-9e5812fc1501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198028601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3198028601
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1196877361
Short name T437
Test name
Test status
Simulation time 530986367 ps
CPU time 11.4 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:28 PM PDT 24
Peak memory 212488 kb
Host smart-3c5e8143-80aa-47e1-8e14-fb672f93aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196877361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1196877361
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3000560017
Short name T668
Test name
Test status
Simulation time 2851154762 ps
CPU time 28.08 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:22:37 PM PDT 24
Peak memory 219092 kb
Host smart-f4f9312d-a590-4f42-ac3d-4c2a59dc0f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000560017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3000560017
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3487233838
Short name T162
Test name
Test status
Simulation time 363028434 ps
CPU time 9.73 seconds
Started Mar 21 03:22:12 PM PDT 24
Finished Mar 21 03:22:22 PM PDT 24
Peak memory 210820 kb
Host smart-257a268a-bab7-4813-8204-5613d6b153c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487233838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3487233838
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3762326392
Short name T390
Test name
Test status
Simulation time 1077929635 ps
CPU time 23.48 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:40 PM PDT 24
Peak memory 219000 kb
Host smart-134ecce9-e269-40bc-ba91-e205653cc156
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762326392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3762326392
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2860684031
Short name T185
Test name
Test status
Simulation time 252405294 ps
CPU time 5.07 seconds
Started Mar 21 03:22:22 PM PDT 24
Finished Mar 21 03:22:27 PM PDT 24
Peak memory 210840 kb
Host smart-ce4d0748-a9d5-4038-96bb-9d28e3e95c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860684031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2860684031
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.823044111
Short name T575
Test name
Test status
Simulation time 516609635 ps
CPU time 5.15 seconds
Started Mar 21 01:36:18 PM PDT 24
Finished Mar 21 01:36:23 PM PDT 24
Peak memory 210840 kb
Host smart-ed78a25d-4698-489d-9987-e38b9f081e71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823044111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.823044111
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2373516999
Short name T383
Test name
Test status
Simulation time 135711762235 ps
CPU time 324.36 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:27:33 PM PDT 24
Peak memory 218584 kb
Host smart-542aecbd-e236-42c9-bff0-114ad461783f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373516999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2373516999
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.768535181
Short name T365
Test name
Test status
Simulation time 81281936443 ps
CPU time 391.11 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:42:48 PM PDT 24
Peak memory 220464 kb
Host smart-c2f814ff-6521-4b44-a640-d9d4355cd8d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768535181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.768535181
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1099088028
Short name T368
Test name
Test status
Simulation time 1510211776 ps
CPU time 9.48 seconds
Started Mar 21 03:22:09 PM PDT 24
Finished Mar 21 03:22:19 PM PDT 24
Peak memory 211456 kb
Host smart-a60c0348-ce9e-4fdf-968e-25a5a133ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099088028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1099088028
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3301439894
Short name T270
Test name
Test status
Simulation time 8173024027 ps
CPU time 20.98 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:39 PM PDT 24
Peak memory 209488 kb
Host smart-f18323db-2db3-4d92-823e-62531376a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301439894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3301439894
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1924900892
Short name T338
Test name
Test status
Simulation time 6389852910 ps
CPU time 13.72 seconds
Started Mar 21 03:22:07 PM PDT 24
Finished Mar 21 03:22:21 PM PDT 24
Peak memory 210920 kb
Host smart-6a48f009-bae2-4e2c-ba4c-d4da6e45dcce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924900892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1924900892
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2058387501
Short name T329
Test name
Test status
Simulation time 95807993 ps
CPU time 5.67 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:23 PM PDT 24
Peak memory 210720 kb
Host smart-ad222c1b-b869-449b-b24a-b40454e6a1e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058387501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2058387501
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.367141990
Short name T469
Test name
Test status
Simulation time 354174967 ps
CPU time 9.93 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:26 PM PDT 24
Peak memory 218948 kb
Host smart-8cece82a-c326-4d7e-bebb-9af7c33cede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367141990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.367141990
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.60336870
Short name T178
Test name
Test status
Simulation time 2227675636 ps
CPU time 24.57 seconds
Started Mar 21 03:22:11 PM PDT 24
Finished Mar 21 03:22:36 PM PDT 24
Peak memory 219068 kb
Host smart-10aebe0f-a6c1-410e-b6c2-07c38b420f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60336870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.60336870
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1208132791
Short name T265
Test name
Test status
Simulation time 3257774093 ps
CPU time 40.41 seconds
Started Mar 21 03:22:08 PM PDT 24
Finished Mar 21 03:22:48 PM PDT 24
Peak memory 213268 kb
Host smart-758688f8-63a5-4618-9aa0-05ddb0e5f6f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208132791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1208132791
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4118890344
Short name T257
Test name
Test status
Simulation time 19560453898 ps
CPU time 42.35 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:37:00 PM PDT 24
Peak memory 219008 kb
Host smart-13370d39-f14e-4e02-9bb8-560d2902cf66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118890344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4118890344
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2425654006
Short name T501
Test name
Test status
Simulation time 374144773884 ps
CPU time 2595.56 seconds
Started Mar 21 03:22:24 PM PDT 24
Finished Mar 21 04:05:40 PM PDT 24
Peak memory 248096 kb
Host smart-bd078f21-6443-4d5d-a675-aa4aa949fdbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425654006 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2425654006
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.176246381
Short name T688
Test name
Test status
Simulation time 4078018746 ps
CPU time 11.04 seconds
Started Mar 21 03:22:26 PM PDT 24
Finished Mar 21 03:22:37 PM PDT 24
Peak memory 210968 kb
Host smart-1e46f54b-d141-4fba-b1c0-eaa4f0727cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176246381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.176246381
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.78557564
Short name T34
Test name
Test status
Simulation time 5681635352 ps
CPU time 11.59 seconds
Started Mar 21 01:36:15 PM PDT 24
Finished Mar 21 01:36:28 PM PDT 24
Peak memory 210792 kb
Host smart-9a4714cb-3167-40a8-9fe8-2adde963b2ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78557564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.78557564
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1273277344
Short name T261
Test name
Test status
Simulation time 161006045768 ps
CPU time 462.6 seconds
Started Mar 21 01:36:18 PM PDT 24
Finished Mar 21 01:44:01 PM PDT 24
Peak memory 240872 kb
Host smart-052aea70-7d33-41b3-8055-ff06e2116075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273277344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1273277344
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3622451094
Short name T313
Test name
Test status
Simulation time 102855926554 ps
CPU time 362.69 seconds
Started Mar 21 03:22:20 PM PDT 24
Finished Mar 21 03:28:23 PM PDT 24
Peak memory 220004 kb
Host smart-03fcdbca-7c33-4d2a-aa86-e830b4a97f64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622451094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3622451094
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3032825757
Short name T399
Test name
Test status
Simulation time 4433179058 ps
CPU time 16.77 seconds
Started Mar 21 03:22:23 PM PDT 24
Finished Mar 21 03:22:40 PM PDT 24
Peak memory 211708 kb
Host smart-fbb5ff6e-c80b-4516-b62a-1996c1da9d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032825757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3032825757
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.781279030
Short name T431
Test name
Test status
Simulation time 370633273 ps
CPU time 9.69 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:26 PM PDT 24
Peak memory 211268 kb
Host smart-86d5e2eb-7382-4207-a164-1e726adc1d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781279030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.781279030
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1198196961
Short name T489
Test name
Test status
Simulation time 3132256951 ps
CPU time 15.26 seconds
Started Mar 21 03:22:23 PM PDT 24
Finished Mar 21 03:22:39 PM PDT 24
Peak memory 210676 kb
Host smart-2244de74-2bd4-4d83-ace5-fa95b6b78b38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198196961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1198196961
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.480384578
Short name T655
Test name
Test status
Simulation time 706734002 ps
CPU time 7.57 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:24 PM PDT 24
Peak memory 210792 kb
Host smart-b5cc567f-a4bf-4385-b3b5-2be26ad449c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480384578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.480384578
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1421499052
Short name T521
Test name
Test status
Simulation time 599063532 ps
CPU time 14.05 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:22:35 PM PDT 24
Peak memory 212512 kb
Host smart-20227506-0701-4d34-be7a-547da3411f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421499052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1421499052
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.679247848
Short name T181
Test name
Test status
Simulation time 15792355746 ps
CPU time 36.2 seconds
Started Mar 21 01:36:18 PM PDT 24
Finished Mar 21 01:36:54 PM PDT 24
Peak memory 219000 kb
Host smart-b66357c7-2335-48ac-bee2-e5ae9b03c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679247848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.679247848
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.819800887
Short name T496
Test name
Test status
Simulation time 2351686512 ps
CPU time 24.2 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:22:46 PM PDT 24
Peak memory 215504 kb
Host smart-ccd21b84-d6c0-4677-9e92-77d973730c99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819800887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.819800887
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.86522339
Short name T565
Test name
Test status
Simulation time 370802211 ps
CPU time 16.52 seconds
Started Mar 21 01:36:17 PM PDT 24
Finished Mar 21 01:36:34 PM PDT 24
Peak memory 218940 kb
Host smart-c15da148-e682-4095-830b-909f5cecd024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86522339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.rom_ctrl_stress_all.86522339
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3978637096
Short name T446
Test name
Test status
Simulation time 14716366559 ps
CPU time 275.83 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:40:46 PM PDT 24
Peak memory 222608 kb
Host smart-ec8da6b4-2e36-4aff-9690-b8473916eb72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978637096 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3978637096
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2272355536
Short name T674
Test name
Test status
Simulation time 2628312780 ps
CPU time 12.31 seconds
Started Mar 21 01:36:14 PM PDT 24
Finished Mar 21 01:36:27 PM PDT 24
Peak memory 210832 kb
Host smart-37f805f8-1568-445a-b68c-31fb301930d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272355536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2272355536
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2386760325
Short name T656
Test name
Test status
Simulation time 169286099 ps
CPU time 5.36 seconds
Started Mar 21 03:22:22 PM PDT 24
Finished Mar 21 03:22:27 PM PDT 24
Peak memory 210884 kb
Host smart-a00b6288-08fc-41e4-a8f1-e8a03180a353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386760325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2386760325
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2062397753
Short name T171
Test name
Test status
Simulation time 14074558446 ps
CPU time 180.58 seconds
Started Mar 21 01:36:12 PM PDT 24
Finished Mar 21 01:39:13 PM PDT 24
Peak memory 220108 kb
Host smart-a57382c2-56a1-4ecc-96af-41eecd046c59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062397753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2062397753
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4160992592
Short name T301
Test name
Test status
Simulation time 2967543143 ps
CPU time 86.23 seconds
Started Mar 21 03:22:20 PM PDT 24
Finished Mar 21 03:23:47 PM PDT 24
Peak memory 212212 kb
Host smart-9ab88840-1231-4deb-a19e-21fec6d6daef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160992592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4160992592
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1890876537
Short name T664
Test name
Test status
Simulation time 6809140488 ps
CPU time 20.21 seconds
Started Mar 21 03:22:22 PM PDT 24
Finished Mar 21 03:22:42 PM PDT 24
Peak memory 211728 kb
Host smart-21438cd2-b277-40c4-8eb4-56f12e63cfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890876537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1890876537
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.446884191
Short name T592
Test name
Test status
Simulation time 177762993 ps
CPU time 9.41 seconds
Started Mar 21 01:36:10 PM PDT 24
Finished Mar 21 01:36:20 PM PDT 24
Peak memory 212020 kb
Host smart-40fa6557-d80c-4d76-87c4-833fad67a632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446884191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.446884191
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.271041731
Short name T279
Test name
Test status
Simulation time 2067722608 ps
CPU time 11.79 seconds
Started Mar 21 03:22:23 PM PDT 24
Finished Mar 21 03:22:35 PM PDT 24
Peak memory 210864 kb
Host smart-5c6627ad-9b20-4c61-a240-292000501cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271041731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.271041731
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4279196725
Short name T165
Test name
Test status
Simulation time 195186864 ps
CPU time 5.96 seconds
Started Mar 21 01:36:18 PM PDT 24
Finished Mar 21 01:36:24 PM PDT 24
Peak memory 210768 kb
Host smart-509ddc93-828c-44f1-9d01-762cd391ecfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279196725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4279196725
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4235826891
Short name T252
Test name
Test status
Simulation time 1684062757 ps
CPU time 20.09 seconds
Started Mar 21 01:36:18 PM PDT 24
Finished Mar 21 01:36:38 PM PDT 24
Peak memory 212652 kb
Host smart-791121fa-d723-4690-bfcf-bb132e383366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235826891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4235826891
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.468734172
Short name T222
Test name
Test status
Simulation time 529969299 ps
CPU time 14.46 seconds
Started Mar 21 03:22:25 PM PDT 24
Finished Mar 21 03:22:41 PM PDT 24
Peak memory 218808 kb
Host smart-e98a5199-2ce2-48e1-a77e-1d02b666145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468734172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.468734172
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2811266517
Short name T226
Test name
Test status
Simulation time 672664905 ps
CPU time 30.17 seconds
Started Mar 21 01:36:16 PM PDT 24
Finished Mar 21 01:36:47 PM PDT 24
Peak memory 214852 kb
Host smart-a0797b2d-5a00-4ea4-b981-9fdc276120b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811266517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2811266517
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.719895917
Short name T291
Test name
Test status
Simulation time 481481239 ps
CPU time 24.12 seconds
Started Mar 21 03:22:23 PM PDT 24
Finished Mar 21 03:22:47 PM PDT 24
Peak memory 215004 kb
Host smart-1f9d9849-6431-48b8-b85c-67a54a007486
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719895917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.719895917
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3418913721
Short name T629
Test name
Test status
Simulation time 332825160 ps
CPU time 4.36 seconds
Started Mar 21 03:22:24 PM PDT 24
Finished Mar 21 03:22:28 PM PDT 24
Peak memory 210888 kb
Host smart-3da14128-b9d5-4593-868e-5cbe4bae1cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418913721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3418913721
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3424753314
Short name T366
Test name
Test status
Simulation time 379238325 ps
CPU time 4.2 seconds
Started Mar 21 01:36:36 PM PDT 24
Finished Mar 21 01:36:40 PM PDT 24
Peak memory 210840 kb
Host smart-bcee0837-fc0f-46a0-b127-e673faf7c577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424753314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3424753314
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1893469441
Short name T378
Test name
Test status
Simulation time 2647513529 ps
CPU time 114.18 seconds
Started Mar 21 01:36:36 PM PDT 24
Finished Mar 21 01:38:31 PM PDT 24
Peak memory 218280 kb
Host smart-c7c0ac9f-1c6b-4c7c-bddd-f1ad98e7aa51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893469441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1893469441
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.541109162
Short name T600
Test name
Test status
Simulation time 54609272975 ps
CPU time 169.23 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:25:10 PM PDT 24
Peak memory 229696 kb
Host smart-985d6189-8228-4921-aa77-de9091ce42fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541109162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.541109162
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1485763540
Short name T99
Test name
Test status
Simulation time 5688516434 ps
CPU time 18.74 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:36:46 PM PDT 24
Peak memory 211828 kb
Host smart-e0f30204-fd37-48d3-97ce-f0cdc9a4c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485763540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1485763540
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1825651229
Short name T532
Test name
Test status
Simulation time 5456117668 ps
CPU time 18.2 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:22:39 PM PDT 24
Peak memory 211860 kb
Host smart-c58de29d-23ef-4760-9454-4d008dedcdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825651229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1825651229
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1513874183
Short name T376
Test name
Test status
Simulation time 4752514591 ps
CPU time 10.07 seconds
Started Mar 21 01:36:30 PM PDT 24
Finished Mar 21 01:36:41 PM PDT 24
Peak memory 210844 kb
Host smart-7a70ad08-9ac4-4248-a59c-5f7c4b39d049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513874183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1513874183
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.216699819
Short name T482
Test name
Test status
Simulation time 8364493925 ps
CPU time 17.77 seconds
Started Mar 21 03:22:20 PM PDT 24
Finished Mar 21 03:22:38 PM PDT 24
Peak memory 210916 kb
Host smart-32ae821c-c57a-4082-b16c-bf377067b0e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216699819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.216699819
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1866167222
Short name T290
Test name
Test status
Simulation time 10463835915 ps
CPU time 23.51 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:22:45 PM PDT 24
Peak memory 214068 kb
Host smart-d5b83ae6-7302-4d1b-93c7-6f1f1b721c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866167222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1866167222
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4120765957
Short name T360
Test name
Test status
Simulation time 1290428530 ps
CPU time 21.72 seconds
Started Mar 21 01:36:12 PM PDT 24
Finished Mar 21 01:36:34 PM PDT 24
Peak memory 213020 kb
Host smart-33b96db0-6771-4d06-8038-5183d5435cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120765957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4120765957
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2279491144
Short name T681
Test name
Test status
Simulation time 1416982537 ps
CPU time 24.06 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:22:46 PM PDT 24
Peak memory 214260 kb
Host smart-5742a371-253b-43f5-b094-0e5660328e02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279491144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2279491144
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.480653350
Short name T133
Test name
Test status
Simulation time 35707256193 ps
CPU time 76.08 seconds
Started Mar 21 01:36:11 PM PDT 24
Finished Mar 21 01:37:28 PM PDT 24
Peak memory 218968 kb
Host smart-9550cdc0-9044-4c79-8cd6-ee64d4e140f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480653350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.480653350
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1966832434
Short name T155
Test name
Test status
Simulation time 8021161567 ps
CPU time 15.89 seconds
Started Mar 21 03:22:22 PM PDT 24
Finished Mar 21 03:22:38 PM PDT 24
Peak memory 210948 kb
Host smart-21d5dfe9-8e6d-4e97-beea-ccaadfd40526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966832434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1966832434
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2901852361
Short name T588
Test name
Test status
Simulation time 3739338996 ps
CPU time 9.86 seconds
Started Mar 21 01:36:30 PM PDT 24
Finished Mar 21 01:36:41 PM PDT 24
Peak memory 210896 kb
Host smart-eadcb3ed-323f-4fcc-958a-6ca0cde88532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901852361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2901852361
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2327778879
Short name T269
Test name
Test status
Simulation time 90170797090 ps
CPU time 229.1 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:40:16 PM PDT 24
Peak memory 228076 kb
Host smart-8202bc3f-cb13-4523-b249-f3921a44556f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327778879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2327778879
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2891218752
Short name T429
Test name
Test status
Simulation time 547542329055 ps
CPU time 334.94 seconds
Started Mar 21 03:22:23 PM PDT 24
Finished Mar 21 03:27:58 PM PDT 24
Peak memory 236560 kb
Host smart-55c13f11-9af9-43af-95f8-14878c0e97d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891218752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2891218752
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1746725049
Short name T23
Test name
Test status
Simulation time 14477317315 ps
CPU time 30.06 seconds
Started Mar 21 01:36:28 PM PDT 24
Finished Mar 21 01:36:58 PM PDT 24
Peak memory 211680 kb
Host smart-0eae1cdb-bf94-4fda-84dc-3feb42607976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746725049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1746725049
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2708680595
Short name T573
Test name
Test status
Simulation time 1246243705 ps
CPU time 11.11 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:22:32 PM PDT 24
Peak memory 211480 kb
Host smart-11b3c86c-6137-4934-901d-80bf0d263c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708680595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2708680595
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2685228501
Short name T479
Test name
Test status
Simulation time 306036289 ps
CPU time 5.52 seconds
Started Mar 21 03:22:20 PM PDT 24
Finished Mar 21 03:22:26 PM PDT 24
Peak memory 210872 kb
Host smart-ce1c0290-e605-4fbc-a547-a7b695ff51e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685228501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2685228501
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.755487980
Short name T9
Test name
Test status
Simulation time 1292253819 ps
CPU time 12.58 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 01:36:41 PM PDT 24
Peak memory 210740 kb
Host smart-c48b50e0-ca7a-4ebc-89b0-5229bbc89a51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755487980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.755487980
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2407080867
Short name T394
Test name
Test status
Simulation time 2397148902 ps
CPU time 24.64 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:36:51 PM PDT 24
Peak memory 218996 kb
Host smart-fd90d7ed-5011-4b89-bee4-25e25e6ec300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407080867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2407080867
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3041722527
Short name T612
Test name
Test status
Simulation time 3946517124 ps
CPU time 36.34 seconds
Started Mar 21 03:22:21 PM PDT 24
Finished Mar 21 03:22:57 PM PDT 24
Peak memory 219076 kb
Host smart-5474d249-4865-46dd-81ce-8cc70e52442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041722527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3041722527
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1690268332
Short name T498
Test name
Test status
Simulation time 9461394966 ps
CPU time 19.43 seconds
Started Mar 21 03:22:22 PM PDT 24
Finished Mar 21 03:22:42 PM PDT 24
Peak memory 211884 kb
Host smart-497abde2-7d15-4540-ad94-41fd8eff3049
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690268332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1690268332
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1772963500
Short name T427
Test name
Test status
Simulation time 26496426414 ps
CPU time 72.65 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:37:40 PM PDT 24
Peak memory 219020 kb
Host smart-2e1f7d9a-5db8-4972-8b2e-0cf5cb5b5fa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772963500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1772963500
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3789451996
Short name T334
Test name
Test status
Simulation time 56637744570 ps
CPU time 4903.52 seconds
Started Mar 21 01:36:28 PM PDT 24
Finished Mar 21 02:58:12 PM PDT 24
Peak memory 228276 kb
Host smart-6202fd93-5e7c-4d35-8810-a99889189b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789451996 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3789451996
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4202941183
Short name T55
Test name
Test status
Simulation time 80683784364 ps
CPU time 5871.28 seconds
Started Mar 21 03:22:22 PM PDT 24
Finished Mar 21 05:00:14 PM PDT 24
Peak memory 229300 kb
Host smart-063032d9-0567-425b-b3bb-6c618f9f3d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202941183 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.4202941183
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3140357918
Short name T298
Test name
Test status
Simulation time 85883403 ps
CPU time 4.29 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:37 PM PDT 24
Peak memory 210952 kb
Host smart-e3e6a610-c8cf-4c37-8f9c-67f63fadd8f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140357918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3140357918
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3511027664
Short name T244
Test name
Test status
Simulation time 4645311313 ps
CPU time 10.8 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:37 PM PDT 24
Peak memory 210900 kb
Host smart-0710d190-4ca3-46a1-98f8-fd1417f129b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511027664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3511027664
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1239213476
Short name T627
Test name
Test status
Simulation time 2767474264 ps
CPU time 110.46 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:24:22 PM PDT 24
Peak memory 232424 kb
Host smart-4a6fb67d-1aea-49b2-9eb0-66007361163e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239213476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1239213476
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2018861883
Short name T556
Test name
Test status
Simulation time 154833317786 ps
CPU time 376.3 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:42:43 PM PDT 24
Peak memory 219292 kb
Host smart-1ff98eb3-bebd-40e1-8150-023e35aac995
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018861883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2018861883
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1214097002
Short name T621
Test name
Test status
Simulation time 10358246071 ps
CPU time 25.31 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:36:58 PM PDT 24
Peak memory 212148 kb
Host smart-e31cef14-eabc-41d9-af67-dede7c69dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214097002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1214097002
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3816032160
Short name T549
Test name
Test status
Simulation time 7128794447 ps
CPU time 15.87 seconds
Started Mar 21 03:22:30 PM PDT 24
Finished Mar 21 03:22:46 PM PDT 24
Peak memory 211888 kb
Host smart-6aa9a37c-d3f9-46c6-933b-d63c0438b59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816032160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3816032160
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1833714101
Short name T198
Test name
Test status
Simulation time 843389138 ps
CPU time 10.97 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:22:42 PM PDT 24
Peak memory 210836 kb
Host smart-42aa4f44-0ec5-4917-8321-461433e1b8e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833714101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1833714101
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2769509357
Short name T335
Test name
Test status
Simulation time 1841734795 ps
CPU time 13.6 seconds
Started Mar 21 01:36:28 PM PDT 24
Finished Mar 21 01:36:41 PM PDT 24
Peak memory 210788 kb
Host smart-8c76faed-0d97-4bf0-81ca-936b02eefe0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769509357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2769509357
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2299205167
Short name T513
Test name
Test status
Simulation time 184686204 ps
CPU time 10.24 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:36 PM PDT 24
Peak memory 213136 kb
Host smart-3d5580ba-61db-46aa-b42e-c58b12a4c423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299205167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2299205167
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4274210987
Short name T687
Test name
Test status
Simulation time 10229762808 ps
CPU time 28.13 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 219056 kb
Host smart-088fbbf3-0aa7-40bd-a753-86905c2e30e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274210987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4274210987
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1063292981
Short name T200
Test name
Test status
Simulation time 10708664984 ps
CPU time 85.74 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 216796 kb
Host smart-e884733f-9d38-4c0e-8ce6-a7376c575a5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063292981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1063292981
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3857752206
Short name T229
Test name
Test status
Simulation time 3852382693 ps
CPU time 41.29 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:37:08 PM PDT 24
Peak memory 219124 kb
Host smart-96592712-11fd-47f6-ad4d-a9ce5dd9a2a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857752206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3857752206
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3476311125
Short name T545
Test name
Test status
Simulation time 141312620406 ps
CPU time 2097.56 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 02:11:29 PM PDT 24
Peak memory 236692 kb
Host smart-ccb91666-3d2b-4ab6-9a9f-b8cd82e655d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476311125 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3476311125
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3640284673
Short name T473
Test name
Test status
Simulation time 153922709624 ps
CPU time 3075.5 seconds
Started Mar 21 03:22:30 PM PDT 24
Finished Mar 21 04:13:46 PM PDT 24
Peak memory 243788 kb
Host smart-5805bd6e-7a8e-4f4e-b316-fbd1a8f5d439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640284673 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3640284673
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1297071684
Short name T356
Test name
Test status
Simulation time 8514693482 ps
CPU time 17.26 seconds
Started Mar 21 01:36:25 PM PDT 24
Finished Mar 21 01:36:43 PM PDT 24
Peak memory 210860 kb
Host smart-56427ec8-0073-4cd2-975f-a2e15e9a190a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297071684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1297071684
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4133006562
Short name T195
Test name
Test status
Simulation time 86236307 ps
CPU time 4.42 seconds
Started Mar 21 03:22:34 PM PDT 24
Finished Mar 21 03:22:39 PM PDT 24
Peak memory 210856 kb
Host smart-55dff5cc-6d5b-4ed6-892e-3b62c5749c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133006562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4133006562
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2123461844
Short name T27
Test name
Test status
Simulation time 4842423615 ps
CPU time 68.6 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:23:40 PM PDT 24
Peak memory 212248 kb
Host smart-9cd48328-fdab-4712-8c07-fc0faeb4c703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123461844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2123461844
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2223087408
Short name T52
Test name
Test status
Simulation time 56800510331 ps
CPU time 162.24 seconds
Started Mar 21 01:36:32 PM PDT 24
Finished Mar 21 01:39:15 PM PDT 24
Peak memory 220204 kb
Host smart-afc3be96-7923-44be-8fec-949c7f721012
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223087408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2223087408
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1084997906
Short name T514
Test name
Test status
Simulation time 4275126858 ps
CPU time 34.39 seconds
Started Mar 21 03:22:33 PM PDT 24
Finished Mar 21 03:23:08 PM PDT 24
Peak memory 211424 kb
Host smart-783b6fe6-a995-46ef-94da-3f97f41fe055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084997906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1084997906
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1835743202
Short name T21
Test name
Test status
Simulation time 2626474131 ps
CPU time 24.5 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 01:36:55 PM PDT 24
Peak memory 211408 kb
Host smart-4fc3ef9c-ef6c-4f0e-8523-92a5682c4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835743202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1835743202
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3048125620
Short name T43
Test name
Test status
Simulation time 198490277 ps
CPU time 5.65 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:22:37 PM PDT 24
Peak memory 210812 kb
Host smart-0a023044-8d3b-43ac-b316-70927afcc3c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048125620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3048125620
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3416265337
Short name T397
Test name
Test status
Simulation time 959454360 ps
CPU time 9.25 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:35 PM PDT 24
Peak memory 210684 kb
Host smart-883d324c-8227-425c-b24a-572d1b14a0bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416265337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3416265337
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.100963114
Short name T538
Test name
Test status
Simulation time 2869056943 ps
CPU time 32.49 seconds
Started Mar 21 01:36:38 PM PDT 24
Finished Mar 21 01:37:11 PM PDT 24
Peak memory 218996 kb
Host smart-182ae776-8d0d-4420-bc31-7f428770003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100963114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.100963114
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2094165767
Short name T404
Test name
Test status
Simulation time 3813523321 ps
CPU time 35.25 seconds
Started Mar 21 03:22:33 PM PDT 24
Finished Mar 21 03:23:09 PM PDT 24
Peak memory 212956 kb
Host smart-aa5b9bf4-09e7-4462-a266-d8bd79aae66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094165767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2094165767
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3504757787
Short name T371
Test name
Test status
Simulation time 428626948 ps
CPU time 12.12 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:44 PM PDT 24
Peak memory 213000 kb
Host smart-0cbc9983-1c59-4024-b5f6-fc86013db297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504757787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3504757787
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3703248770
Short name T139
Test name
Test status
Simulation time 12906278115 ps
CPU time 64.83 seconds
Started Mar 21 01:36:32 PM PDT 24
Finished Mar 21 01:37:37 PM PDT 24
Peak memory 219084 kb
Host smart-6f8c085c-cfd5-4ceb-8b14-2e0a2a79b271
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703248770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3703248770
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2520092674
Short name T145
Test name
Test status
Simulation time 830557287 ps
CPU time 4.39 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 01:35:59 PM PDT 24
Peak memory 210888 kb
Host smart-64a5d27e-5861-4505-ad79-fe83f877f18f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520092674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2520092674
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3656536589
Short name T361
Test name
Test status
Simulation time 2262781862 ps
CPU time 8.86 seconds
Started Mar 21 03:21:01 PM PDT 24
Finished Mar 21 03:21:10 PM PDT 24
Peak memory 211072 kb
Host smart-3118122a-ec27-4bbd-88c5-0266198b7310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656536589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3656536589
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2905772654
Short name T147
Test name
Test status
Simulation time 13641820186 ps
CPU time 126.25 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:38:03 PM PDT 24
Peak memory 213084 kb
Host smart-685078f1-e63b-4974-b335-a6246caadd94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905772654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2905772654
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3380072802
Short name T348
Test name
Test status
Simulation time 8569659699 ps
CPU time 145.96 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:23:25 PM PDT 24
Peak memory 228268 kb
Host smart-551a1ca5-49ce-4936-aa7e-96dbf464a011
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380072802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3380072802
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.198935287
Short name T493
Test name
Test status
Simulation time 11638150899 ps
CPU time 25.15 seconds
Started Mar 21 03:21:07 PM PDT 24
Finished Mar 21 03:21:33 PM PDT 24
Peak memory 211924 kb
Host smart-a90a710d-8e83-42aa-9de0-7dbba66e6f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198935287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.198935287
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.291601616
Short name T609
Test name
Test status
Simulation time 1466484828 ps
CPU time 18.37 seconds
Started Mar 21 01:35:51 PM PDT 24
Finished Mar 21 01:36:10 PM PDT 24
Peak memory 211372 kb
Host smart-f138f217-d99e-40bb-9d73-f16d7c758ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291601616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.291601616
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.146278527
Short name T166
Test name
Test status
Simulation time 182644657 ps
CPU time 5.61 seconds
Started Mar 21 01:35:43 PM PDT 24
Finished Mar 21 01:35:51 PM PDT 24
Peak memory 210680 kb
Host smart-9bd17404-d9b3-4228-9f67-97c2733f50a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146278527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.146278527
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2487220803
Short name T552
Test name
Test status
Simulation time 1816105264 ps
CPU time 15.75 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:21:15 PM PDT 24
Peak memory 210852 kb
Host smart-ff8edca4-d7d1-4bce-9ac1-74e68c29c479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487220803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2487220803
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2177389068
Short name T37
Test name
Test status
Simulation time 11947396144 ps
CPU time 64.44 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:22:04 PM PDT 24
Peak memory 230404 kb
Host smart-0cf12877-1460-4b1d-b6f2-2890d1c56d28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177389068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2177389068
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2197334944
Short name T31
Test name
Test status
Simulation time 5064477754 ps
CPU time 105.61 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:37:42 PM PDT 24
Peak memory 230624 kb
Host smart-2d7ca648-277c-41d0-a632-04b3e94e6d80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197334944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2197334944
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2559830325
Short name T130
Test name
Test status
Simulation time 4937121651 ps
CPU time 17.63 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 01:36:12 PM PDT 24
Peak memory 213320 kb
Host smart-99346335-0f42-4260-89f6-385af19a4ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559830325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2559830325
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.688547714
Short name T632
Test name
Test status
Simulation time 3595125653 ps
CPU time 39.56 seconds
Started Mar 21 03:21:00 PM PDT 24
Finished Mar 21 03:21:40 PM PDT 24
Peak memory 213096 kb
Host smart-165bed22-673b-499c-829f-f6145eaa917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688547714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.688547714
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3045749742
Short name T67
Test name
Test status
Simulation time 1043983348 ps
CPU time 17.25 seconds
Started Mar 21 01:35:57 PM PDT 24
Finished Mar 21 01:36:15 PM PDT 24
Peak memory 213084 kb
Host smart-d688ac93-0be2-40d7-9d90-25000ec39f41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045749742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3045749742
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.416743427
Short name T533
Test name
Test status
Simulation time 726319897 ps
CPU time 19.52 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:21:19 PM PDT 24
Peak memory 219008 kb
Host smart-7a0afb98-15d1-4da5-9fe5-3db14a51457d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416743427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.416743427
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2578587518
Short name T321
Test name
Test status
Simulation time 43354879616 ps
CPU time 5401.62 seconds
Started Mar 21 01:35:48 PM PDT 24
Finished Mar 21 03:05:50 PM PDT 24
Peak memory 233840 kb
Host smart-bce1a640-b561-49b4-b83c-a105bad2d754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578587518 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2578587518
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3557984193
Short name T502
Test name
Test status
Simulation time 91924557312 ps
CPU time 2520.4 seconds
Started Mar 21 03:21:02 PM PDT 24
Finished Mar 21 04:03:03 PM PDT 24
Peak memory 237636 kb
Host smart-6428b94f-f813-4113-8256-0af0b7ea5364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557984193 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3557984193
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3473784118
Short name T543
Test name
Test status
Simulation time 1507389511 ps
CPU time 10.82 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:43 PM PDT 24
Peak memory 210888 kb
Host smart-bdb288e6-3a3b-4c30-b2a5-6da32ad39849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473784118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3473784118
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.880712377
Short name T66
Test name
Test status
Simulation time 377704369 ps
CPU time 4.39 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:31 PM PDT 24
Peak memory 210824 kb
Host smart-763a07fa-19bb-40c7-973e-7a0c1a8e0601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880712377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.880712377
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2146227264
Short name T686
Test name
Test status
Simulation time 48830554018 ps
CPU time 288.67 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:41:22 PM PDT 24
Peak memory 236768 kb
Host smart-79ba8f8a-6992-4878-98e5-b68fded56be9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146227264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2146227264
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2739683245
Short name T315
Test name
Test status
Simulation time 77664801753 ps
CPU time 131.13 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:24:43 PM PDT 24
Peak memory 233784 kb
Host smart-c0617702-a74c-4241-bf6f-24520a55d4d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739683245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2739683245
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2755742293
Short name T447
Test name
Test status
Simulation time 1033403112 ps
CPU time 16.26 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:36:43 PM PDT 24
Peak memory 211392 kb
Host smart-e777042f-fcc1-482f-a6cc-33ea71ae3c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755742293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2755742293
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.862178762
Short name T141
Test name
Test status
Simulation time 10727533406 ps
CPU time 21.3 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:54 PM PDT 24
Peak memory 211908 kb
Host smart-5f28955e-db1c-4fca-9afa-ebd9b8f95e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862178762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.862178762
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1902637295
Short name T150
Test name
Test status
Simulation time 3078326545 ps
CPU time 8.48 seconds
Started Mar 21 01:36:30 PM PDT 24
Finished Mar 21 01:36:39 PM PDT 24
Peak memory 210852 kb
Host smart-ddd46bb5-e90b-4052-9e1d-e52e5ee41fce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902637295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1902637295
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2822455723
Short name T512
Test name
Test status
Simulation time 11924610386 ps
CPU time 14.65 seconds
Started Mar 21 03:22:35 PM PDT 24
Finished Mar 21 03:22:50 PM PDT 24
Peak memory 210908 kb
Host smart-149068f6-21e4-41c8-b5bf-8adefb27312a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822455723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2822455723
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1906598531
Short name T416
Test name
Test status
Simulation time 5865135717 ps
CPU time 19.37 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 213380 kb
Host smart-c602b1c4-3556-46b4-af15-b2ba11c3fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906598531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1906598531
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2954772469
Short name T584
Test name
Test status
Simulation time 9874291635 ps
CPU time 25.43 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 01:36:56 PM PDT 24
Peak memory 213332 kb
Host smart-bd3a6b30-5851-4380-8c37-505a03b93ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954772469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2954772469
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.157077783
Short name T149
Test name
Test status
Simulation time 855102037 ps
CPU time 25.21 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:22:56 PM PDT 24
Peak memory 218972 kb
Host smart-1c0ba9b8-2dc4-422f-ac28-fa78d9452767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157077783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.157077783
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1968817281
Short name T100
Test name
Test status
Simulation time 13077831445 ps
CPU time 43.04 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:37:10 PM PDT 24
Peak memory 218960 kb
Host smart-8adc536e-1c24-4c5b-84de-3da0fe5a065e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968817281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1968817281
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1128162365
Short name T666
Test name
Test status
Simulation time 591132986 ps
CPU time 8.24 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:41 PM PDT 24
Peak memory 210916 kb
Host smart-287d5beb-bfd9-4239-b983-d751ce51f798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128162365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1128162365
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.317657657
Short name T33
Test name
Test status
Simulation time 6387374907 ps
CPU time 13.67 seconds
Started Mar 21 01:36:35 PM PDT 24
Finished Mar 21 01:36:49 PM PDT 24
Peak memory 210880 kb
Host smart-900ee1a3-73c9-4a9e-b1a6-ff581fd9e360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317657657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.317657657
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2954971017
Short name T516
Test name
Test status
Simulation time 1459316621 ps
CPU time 104.67 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:38:17 PM PDT 24
Peak memory 232440 kb
Host smart-b6ab6cb5-ab41-4464-8088-6ec68428b1ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954971017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2954971017
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.555448878
Short name T264
Test name
Test status
Simulation time 35686850283 ps
CPU time 325.81 seconds
Started Mar 21 03:22:33 PM PDT 24
Finished Mar 21 03:27:59 PM PDT 24
Peak memory 236612 kb
Host smart-ebe79fe2-6b11-40d7-98ed-6a878ecee82f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555448878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.555448878
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1298670543
Short name T246
Test name
Test status
Simulation time 1325263908 ps
CPU time 17.81 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:50 PM PDT 24
Peak memory 211600 kb
Host smart-5298022e-df6d-4ee5-a0bd-ea423f3785cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298670543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1298670543
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3974811823
Short name T359
Test name
Test status
Simulation time 665761246 ps
CPU time 9.23 seconds
Started Mar 21 01:36:28 PM PDT 24
Finished Mar 21 01:36:37 PM PDT 24
Peak memory 211488 kb
Host smart-d24eafa6-7084-4116-b86d-a33fc1104886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974811823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3974811823
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.100213629
Short name T218
Test name
Test status
Simulation time 789016572 ps
CPU time 10.07 seconds
Started Mar 21 03:22:34 PM PDT 24
Finished Mar 21 03:22:44 PM PDT 24
Peak memory 210860 kb
Host smart-02720920-5b9f-4e75-8039-ca9d82ea8c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100213629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.100213629
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4054718970
Short name T231
Test name
Test status
Simulation time 378703496 ps
CPU time 5.56 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 01:36:34 PM PDT 24
Peak memory 210792 kb
Host smart-bfbae6a0-41c4-4df6-8fe1-f9de5d73afc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054718970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4054718970
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2123030851
Short name T646
Test name
Test status
Simulation time 1209604493 ps
CPU time 17.04 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:36:44 PM PDT 24
Peak memory 218956 kb
Host smart-d400fd42-c280-4fa2-8658-65f902f69ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123030851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2123030851
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.340234291
Short name T144
Test name
Test status
Simulation time 4971686552 ps
CPU time 27.92 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:22:59 PM PDT 24
Peak memory 219076 kb
Host smart-14d0bfc6-403f-4d32-92c4-4d3ea2bfc0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340234291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.340234291
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1566676985
Short name T169
Test name
Test status
Simulation time 6107614282 ps
CPU time 22.04 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:54 PM PDT 24
Peak memory 214088 kb
Host smart-5aadd89f-d381-4afd-8354-747c72f98a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566676985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1566676985
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3162963640
Short name T140
Test name
Test status
Simulation time 2486391227 ps
CPU time 24.49 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:36:58 PM PDT 24
Peak memory 218996 kb
Host smart-07ddc061-bb77-4aa1-88e3-f2e1a2787318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162963640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3162963640
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1157343013
Short name T342
Test name
Test status
Simulation time 62428835718 ps
CPU time 608.05 seconds
Started Mar 21 03:22:33 PM PDT 24
Finished Mar 21 03:32:41 PM PDT 24
Peak memory 227944 kb
Host smart-145afbf9-dc63-4519-b6df-229bac904763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157343013 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1157343013
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2453792684
Short name T314
Test name
Test status
Simulation time 2131867423 ps
CPU time 17.4 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:43 PM PDT 24
Peak memory 210840 kb
Host smart-28493941-b4d0-4919-9682-a447304e2a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453792684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2453792684
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.789146964
Short name T47
Test name
Test status
Simulation time 8417359109 ps
CPU time 15.77 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:49 PM PDT 24
Peak memory 210964 kb
Host smart-7dd0095e-c28b-4a7e-bfdd-6d70aae9ff57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789146964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.789146964
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1554044734
Short name T161
Test name
Test status
Simulation time 76861375436 ps
CPU time 179.6 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:39:32 PM PDT 24
Peak memory 223724 kb
Host smart-fc0ef0f5-0db3-4ebf-9018-172be50a2eb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554044734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1554044734
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3277413756
Short name T480
Test name
Test status
Simulation time 8918550300 ps
CPU time 127.67 seconds
Started Mar 21 03:22:33 PM PDT 24
Finished Mar 21 03:24:41 PM PDT 24
Peak memory 230392 kb
Host smart-bb6b57a9-1936-4f0f-893b-a04159884a94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277413756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3277413756
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2757656775
Short name T630
Test name
Test status
Simulation time 1544151339 ps
CPU time 19.03 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 211564 kb
Host smart-2f02da04-7990-4d2e-9844-d4f415565f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757656775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2757656775
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.745405014
Short name T683
Test name
Test status
Simulation time 1269967894 ps
CPU time 17.82 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:44 PM PDT 24
Peak memory 211668 kb
Host smart-768492f7-c766-4e04-ac0e-818e80b42170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745405014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.745405014
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1464945197
Short name T207
Test name
Test status
Simulation time 1860891168 ps
CPU time 10.52 seconds
Started Mar 21 03:22:33 PM PDT 24
Finished Mar 21 03:22:44 PM PDT 24
Peak memory 210744 kb
Host smart-c0088a94-44ac-4f38-86d8-7992b19ee9c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464945197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1464945197
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.608859444
Short name T558
Test name
Test status
Simulation time 367487610 ps
CPU time 5.25 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:36:39 PM PDT 24
Peak memory 210784 kb
Host smart-0a348000-c748-4125-9b73-ec05d95d06b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=608859444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.608859444
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2354589477
Short name T14
Test name
Test status
Simulation time 382161238 ps
CPU time 9.84 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:22:42 PM PDT 24
Peak memory 213284 kb
Host smart-f02cd6aa-06fa-40ed-9132-bdd05f101328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354589477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2354589477
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4077042638
Short name T564
Test name
Test status
Simulation time 3934452688 ps
CPU time 40.31 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:37:07 PM PDT 24
Peak memory 212676 kb
Host smart-619764d2-a283-43d0-b289-f98580ccaa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077042638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4077042638
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2425717608
Short name T462
Test name
Test status
Simulation time 1134941136 ps
CPU time 30.09 seconds
Started Mar 21 03:22:31 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 215080 kb
Host smart-71cce99f-d804-47be-b08a-b7b5f1b8e9ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425717608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2425717608
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3095835410
Short name T400
Test name
Test status
Simulation time 3794975644 ps
CPU time 19.21 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:45 PM PDT 24
Peak memory 214260 kb
Host smart-0ba41429-0e89-41fb-b37a-666b8a7006ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095835410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3095835410
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1703268811
Short name T633
Test name
Test status
Simulation time 4829102226 ps
CPU time 11.44 seconds
Started Mar 21 03:22:49 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 210860 kb
Host smart-b0d90c63-37b7-4191-a69b-0923e93aec0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703268811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1703268811
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1719452335
Short name T341
Test name
Test status
Simulation time 1475943462 ps
CPU time 12.99 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:36:46 PM PDT 24
Peak memory 210840 kb
Host smart-f53b7067-a28d-4390-8f78-58f3f94526a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719452335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1719452335
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3256614313
Short name T48
Test name
Test status
Simulation time 4606028804 ps
CPU time 144 seconds
Started Mar 21 03:22:34 PM PDT 24
Finished Mar 21 03:24:58 PM PDT 24
Peak memory 224888 kb
Host smart-0fbd45bd-b5fb-44eb-b7e2-76a8488c5c33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256614313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3256614313
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3725226895
Short name T180
Test name
Test status
Simulation time 56724780315 ps
CPU time 348.22 seconds
Started Mar 21 01:36:33 PM PDT 24
Finished Mar 21 01:42:22 PM PDT 24
Peak memory 231384 kb
Host smart-c90bdae2-a2fb-41d1-b43f-08e8e2300a5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725226895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3725226895
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2595464253
Short name T168
Test name
Test status
Simulation time 16336517898 ps
CPU time 22.93 seconds
Started Mar 21 03:22:33 PM PDT 24
Finished Mar 21 03:22:56 PM PDT 24
Peak memory 210932 kb
Host smart-7a98199d-2d61-41cc-b961-3c1394684b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595464253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2595464253
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3652693554
Short name T676
Test name
Test status
Simulation time 3588180398 ps
CPU time 25.61 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 01:36:54 PM PDT 24
Peak memory 211468 kb
Host smart-80339de5-50e7-4dc0-a0c9-255835b83638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652693554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3652693554
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1848137974
Short name T624
Test name
Test status
Simulation time 3524990178 ps
CPU time 9.76 seconds
Started Mar 21 03:22:35 PM PDT 24
Finished Mar 21 03:22:45 PM PDT 24
Peak memory 210908 kb
Host smart-f4732c91-6277-4c16-bdf8-df36f5747c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848137974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1848137974
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.286962304
Short name T456
Test name
Test status
Simulation time 1938527427 ps
CPU time 16.52 seconds
Started Mar 21 01:36:35 PM PDT 24
Finished Mar 21 01:36:51 PM PDT 24
Peak memory 210796 kb
Host smart-b52541d5-4450-4e8b-8b74-28368f988b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286962304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.286962304
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4242834954
Short name T522
Test name
Test status
Simulation time 16364834456 ps
CPU time 41.26 seconds
Started Mar 21 03:22:34 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 213912 kb
Host smart-5992e213-7f20-4d07-bd18-19e9dfa9b77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242834954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4242834954
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.744283385
Short name T407
Test name
Test status
Simulation time 2840993589 ps
CPU time 25.72 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 01:36:54 PM PDT 24
Peak memory 218924 kb
Host smart-56334cb2-8282-4f96-bab5-1e4dd2aaef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744283385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.744283385
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1741532771
Short name T654
Test name
Test status
Simulation time 8787595398 ps
CPU time 48.18 seconds
Started Mar 21 03:22:32 PM PDT 24
Finished Mar 21 03:23:20 PM PDT 24
Peak memory 219072 kb
Host smart-64a0c95b-3428-4118-9d4e-cd87831b8273
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741532771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1741532771
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2416010729
Short name T591
Test name
Test status
Simulation time 381318637 ps
CPU time 19.76 seconds
Started Mar 21 01:36:32 PM PDT 24
Finished Mar 21 01:36:52 PM PDT 24
Peak memory 213220 kb
Host smart-2ff8369e-e81e-4cd9-ab37-b380497ea349
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416010729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2416010729
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1757022280
Short name T271
Test name
Test status
Simulation time 761928711 ps
CPU time 9 seconds
Started Mar 21 01:36:37 PM PDT 24
Finished Mar 21 01:36:46 PM PDT 24
Peak memory 210824 kb
Host smart-b3b964bb-c062-472b-af06-9c022a83b517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757022280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1757022280
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4108842736
Short name T386
Test name
Test status
Simulation time 3097802548 ps
CPU time 9.03 seconds
Started Mar 21 03:22:45 PM PDT 24
Finished Mar 21 03:22:54 PM PDT 24
Peak memory 210980 kb
Host smart-dce8527a-7e2a-478e-8995-c235c45fcaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108842736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4108842736
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2571223933
Short name T661
Test name
Test status
Simulation time 7544935486 ps
CPU time 124.03 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:24:51 PM PDT 24
Peak memory 219360 kb
Host smart-5b6050b7-e988-4c65-abbf-b19cfc70d01b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571223933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2571223933
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3773251122
Short name T494
Test name
Test status
Simulation time 6213538150 ps
CPU time 148.94 seconds
Started Mar 21 01:36:36 PM PDT 24
Finished Mar 21 01:39:05 PM PDT 24
Peak memory 237476 kb
Host smart-194139d0-62af-498c-ada0-f54bd4a3efe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773251122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3773251122
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1687561601
Short name T525
Test name
Test status
Simulation time 2354252267 ps
CPU time 22.62 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:23:09 PM PDT 24
Peak memory 211528 kb
Host smart-dabd1f44-0d06-4b3f-b491-f7994310260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687561601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1687561601
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3614887146
Short name T388
Test name
Test status
Simulation time 3601865009 ps
CPU time 29.65 seconds
Started Mar 21 01:36:25 PM PDT 24
Finished Mar 21 01:36:55 PM PDT 24
Peak memory 211728 kb
Host smart-b294731c-f786-434b-9527-1d87bcf39f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614887146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3614887146
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1751720481
Short name T597
Test name
Test status
Simulation time 344975225 ps
CPU time 7.24 seconds
Started Mar 21 01:36:37 PM PDT 24
Finished Mar 21 01:36:45 PM PDT 24
Peak memory 210772 kb
Host smart-16459979-2ec2-43d8-920c-a4b1ef4b46ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751720481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1751720481
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.586412812
Short name T245
Test name
Test status
Simulation time 7435769088 ps
CPU time 16.13 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 210916 kb
Host smart-438e83fb-b5f1-4712-bdef-b23cf19620a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586412812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.586412812
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.248830438
Short name T243
Test name
Test status
Simulation time 1542959406 ps
CPU time 15.16 seconds
Started Mar 21 01:36:37 PM PDT 24
Finished Mar 21 01:36:52 PM PDT 24
Peak memory 212992 kb
Host smart-9904f957-74e9-4149-a4ed-e79d5cbab80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248830438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.248830438
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2784070731
Short name T364
Test name
Test status
Simulation time 15861412648 ps
CPU time 31.42 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:23:18 PM PDT 24
Peak memory 219056 kb
Host smart-1ee2c914-163c-4516-9234-0bc0cb23ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784070731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2784070731
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1033098253
Short name T78
Test name
Test status
Simulation time 5896735098 ps
CPU time 37.47 seconds
Started Mar 21 01:36:36 PM PDT 24
Finished Mar 21 01:37:14 PM PDT 24
Peak memory 219008 kb
Host smart-670f3b5f-7e3a-4563-9bba-d4c031934754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033098253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1033098253
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3292196298
Short name T497
Test name
Test status
Simulation time 10035037851 ps
CPU time 51.46 seconds
Started Mar 21 03:22:45 PM PDT 24
Finished Mar 21 03:23:37 PM PDT 24
Peak memory 219132 kb
Host smart-552a91dd-9991-43c2-860c-d5ee5429d9ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292196298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3292196298
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2495958533
Short name T64
Test name
Test status
Simulation time 1496854813 ps
CPU time 9.05 seconds
Started Mar 21 01:36:36 PM PDT 24
Finished Mar 21 01:36:45 PM PDT 24
Peak memory 210852 kb
Host smart-12d9df1c-7bf1-4b22-ac07-d0f6792d8556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495958533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2495958533
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.704152178
Short name T148
Test name
Test status
Simulation time 1174250794 ps
CPU time 8.08 seconds
Started Mar 21 03:22:45 PM PDT 24
Finished Mar 21 03:22:53 PM PDT 24
Peak memory 210912 kb
Host smart-3b4edba8-9fa8-493c-9135-541e0fbf8f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704152178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.704152178
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2551405654
Short name T670
Test name
Test status
Simulation time 2322953048 ps
CPU time 147.07 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:25:14 PM PDT 24
Peak memory 228192 kb
Host smart-7dee640c-c4d6-47a0-b3d2-d5978cfcde10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551405654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2551405654
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3290019646
Short name T174
Test name
Test status
Simulation time 1800646250 ps
CPU time 108.5 seconds
Started Mar 21 01:36:36 PM PDT 24
Finished Mar 21 01:38:24 PM PDT 24
Peak memory 221140 kb
Host smart-4546e6d2-2fee-48dd-955e-d140f091e699
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290019646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3290019646
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1794761068
Short name T535
Test name
Test status
Simulation time 16036830732 ps
CPU time 32.33 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:23:18 PM PDT 24
Peak memory 211808 kb
Host smart-27e8f538-266a-4876-bbe3-f69ae6f63d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794761068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1794761068
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3670679849
Short name T230
Test name
Test status
Simulation time 2286760115 ps
CPU time 22.82 seconds
Started Mar 21 01:36:28 PM PDT 24
Finished Mar 21 01:36:51 PM PDT 24
Peak memory 211420 kb
Host smart-da7ded75-cbb6-4781-b8e4-66a7afb64689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670679849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3670679849
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1951916165
Short name T566
Test name
Test status
Simulation time 100151773 ps
CPU time 5.35 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 210840 kb
Host smart-65e6597a-9d8f-4f65-a453-2e44963e9f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951916165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1951916165
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2664116358
Short name T110
Test name
Test status
Simulation time 101295251 ps
CPU time 5.47 seconds
Started Mar 21 01:36:34 PM PDT 24
Finished Mar 21 01:36:40 PM PDT 24
Peak memory 210800 kb
Host smart-ff896f24-f936-4f06-b3ed-3be22efbca57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664116358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2664116358
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.429627759
Short name T380
Test name
Test status
Simulation time 13126146595 ps
CPU time 34.31 seconds
Started Mar 21 03:22:45 PM PDT 24
Finished Mar 21 03:23:20 PM PDT 24
Peak memory 219076 kb
Host smart-99f8d6c8-7a16-40a7-bf8b-a922dc31e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429627759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.429627759
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.815961749
Short name T660
Test name
Test status
Simulation time 4145732382 ps
CPU time 18.98 seconds
Started Mar 21 01:36:35 PM PDT 24
Finished Mar 21 01:36:55 PM PDT 24
Peak memory 219020 kb
Host smart-b96b5424-2bba-4646-83ba-c9eba8f848b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815961749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.815961749
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1270972779
Short name T665
Test name
Test status
Simulation time 431666894 ps
CPU time 7.24 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:22:53 PM PDT 24
Peak memory 210896 kb
Host smart-cd7a2c88-dc2d-415a-b614-58fcb1c2a8cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270972779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1270972779
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.901384412
Short name T435
Test name
Test status
Simulation time 34447036393 ps
CPU time 86.31 seconds
Started Mar 21 01:36:35 PM PDT 24
Finished Mar 21 01:38:02 PM PDT 24
Peak memory 219040 kb
Host smart-081507f1-acf0-4a50-accf-4f764b43abf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901384412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.901384412
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3834756562
Short name T182
Test name
Test status
Simulation time 10314099423 ps
CPU time 1222.31 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:43:08 PM PDT 24
Peak memory 223776 kb
Host smart-cd280835-8aa9-4af8-8a77-6ce6751d791e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834756562 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3834756562
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1422944746
Short name T460
Test name
Test status
Simulation time 3566107648 ps
CPU time 9.32 seconds
Started Mar 21 01:36:31 PM PDT 24
Finished Mar 21 01:36:40 PM PDT 24
Peak memory 210868 kb
Host smart-3d2293c4-4642-4bc8-9ca9-1a7150a85136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422944746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1422944746
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.21302079
Short name T398
Test name
Test status
Simulation time 175331143 ps
CPU time 4.2 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 210900 kb
Host smart-cf62b879-8f67-48fc-aeef-e91cd500f254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21302079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.21302079
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1061811624
Short name T557
Test name
Test status
Simulation time 11079390520 ps
CPU time 264.75 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:27:11 PM PDT 24
Peak memory 230204 kb
Host smart-36e3b5c2-0fcc-4320-874a-c6b15d238d1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061811624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1061811624
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1822790565
Short name T320
Test name
Test status
Simulation time 3721604593 ps
CPU time 97.48 seconds
Started Mar 21 01:36:32 PM PDT 24
Finished Mar 21 01:38:10 PM PDT 24
Peak memory 232584 kb
Host smart-196e6489-9a1e-423b-896a-057de6084fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822790565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1822790565
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1525653372
Short name T481
Test name
Test status
Simulation time 168729165 ps
CPU time 9.18 seconds
Started Mar 21 01:36:26 PM PDT 24
Finished Mar 21 01:36:35 PM PDT 24
Peak memory 211352 kb
Host smart-bcee069b-3cdf-4735-96b9-c6ed5d921534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525653372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1525653372
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1727456064
Short name T413
Test name
Test status
Simulation time 6124293857 ps
CPU time 24.73 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:23:11 PM PDT 24
Peak memory 210956 kb
Host smart-74803b0b-365a-4443-9b08-eb156f2f52d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727456064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1727456064
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2369830098
Short name T508
Test name
Test status
Simulation time 213670046 ps
CPU time 6.08 seconds
Started Mar 21 03:22:48 PM PDT 24
Finished Mar 21 03:22:54 PM PDT 24
Peak memory 210844 kb
Host smart-a54acbcf-a9c4-4214-b304-eda417a1dfa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369830098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2369830098
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.990825989
Short name T288
Test name
Test status
Simulation time 1634280285 ps
CPU time 7.18 seconds
Started Mar 21 01:36:36 PM PDT 24
Finished Mar 21 01:36:43 PM PDT 24
Peak memory 210804 kb
Host smart-7806f655-9e23-44fc-b9a7-0ee1ffdc0f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990825989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.990825989
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2634380777
Short name T582
Test name
Test status
Simulation time 4642515194 ps
CPU time 44.15 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 212928 kb
Host smart-7fbe0397-6b87-46bc-92ba-797e050a9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634380777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2634380777
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2782121527
Short name T296
Test name
Test status
Simulation time 997311694 ps
CPU time 9.99 seconds
Started Mar 21 01:36:35 PM PDT 24
Finished Mar 21 01:36:45 PM PDT 24
Peak memory 218968 kb
Host smart-9dffb73c-d297-4259-8931-125e11e3fbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782121527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2782121527
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1806734394
Short name T109
Test name
Test status
Simulation time 1877964913 ps
CPU time 46 seconds
Started Mar 21 01:36:37 PM PDT 24
Finished Mar 21 01:37:23 PM PDT 24
Peak memory 215904 kb
Host smart-6d5f4a9d-0102-4b32-900f-7708768a848d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806734394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1806734394
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3999810686
Short name T638
Test name
Test status
Simulation time 413340164 ps
CPU time 22.39 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:23:09 PM PDT 24
Peak memory 214744 kb
Host smart-bcf5f120-9388-46aa-8cb1-7b2838a1f4bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999810686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3999810686
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2839973670
Short name T520
Test name
Test status
Simulation time 8146305192 ps
CPU time 16.15 seconds
Started Mar 21 01:36:39 PM PDT 24
Finished Mar 21 01:36:56 PM PDT 24
Peak memory 210896 kb
Host smart-fc0475af-0c26-4755-a55a-e2f62d79dacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839973670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2839973670
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3192147193
Short name T689
Test name
Test status
Simulation time 1941791688 ps
CPU time 14.67 seconds
Started Mar 21 03:22:48 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 210904 kb
Host smart-03731aa5-d3f5-4f93-b552-8e8c50fb860c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192147193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3192147193
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1043944956
Short name T540
Test name
Test status
Simulation time 19032789158 ps
CPU time 217.88 seconds
Started Mar 21 03:22:45 PM PDT 24
Finished Mar 21 03:26:23 PM PDT 24
Peak memory 236288 kb
Host smart-c60b19a4-6c1b-4b70-af7c-0dd594e6abcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043944956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1043944956
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.377542740
Short name T449
Test name
Test status
Simulation time 109354211653 ps
CPU time 520.84 seconds
Started Mar 21 01:36:31 PM PDT 24
Finished Mar 21 01:45:12 PM PDT 24
Peak memory 233540 kb
Host smart-0e3499fb-d0fa-4d6b-86f8-8bd11fcfb052
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377542740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.377542740
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.289998658
Short name T581
Test name
Test status
Simulation time 2398575200 ps
CPU time 13.77 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:23:01 PM PDT 24
Peak memory 211528 kb
Host smart-af16ae8d-399e-4829-a622-76f4290fac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289998658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.289998658
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4083999503
Short name T434
Test name
Test status
Simulation time 11921883830 ps
CPU time 24.87 seconds
Started Mar 21 01:36:27 PM PDT 24
Finished Mar 21 01:36:52 PM PDT 24
Peak memory 212256 kb
Host smart-7756deea-d4f8-4e11-8efb-e4080a19ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083999503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4083999503
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.997032649
Short name T308
Test name
Test status
Simulation time 235010964 ps
CPU time 6.32 seconds
Started Mar 21 01:36:29 PM PDT 24
Finished Mar 21 01:36:37 PM PDT 24
Peak memory 210788 kb
Host smart-e24ef068-273e-4179-8cfd-d5260f94a0e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997032649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.997032649
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.999421562
Short name T440
Test name
Test status
Simulation time 376488571 ps
CPU time 5.66 seconds
Started Mar 21 03:22:48 PM PDT 24
Finished Mar 21 03:22:54 PM PDT 24
Peak memory 210860 kb
Host smart-cc5bf36d-b741-4320-8556-4a9dd48227be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999421562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.999421562
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1259236571
Short name T433
Test name
Test status
Simulation time 3226381247 ps
CPU time 28.86 seconds
Started Mar 21 01:36:31 PM PDT 24
Finished Mar 21 01:37:00 PM PDT 24
Peak memory 213080 kb
Host smart-6e6190ea-589c-4924-91de-5af0e71d36dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259236571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1259236571
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.750878774
Short name T146
Test name
Test status
Simulation time 16033982459 ps
CPU time 38.38 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:23:26 PM PDT 24
Peak memory 219052 kb
Host smart-89d5b6d8-0171-4123-96c6-f5b474eea340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750878774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.750878774
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1986602798
Short name T18
Test name
Test status
Simulation time 2809709581 ps
CPU time 26.19 seconds
Started Mar 21 01:36:31 PM PDT 24
Finished Mar 21 01:36:57 PM PDT 24
Peak memory 213848 kb
Host smart-bd0a4b6f-f38f-40f3-a763-2ffebc49bdf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986602798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1986602798
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4161183986
Short name T396
Test name
Test status
Simulation time 564936153 ps
CPU time 24.47 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:23:11 PM PDT 24
Peak memory 219004 kb
Host smart-1e7ecf93-14bb-4331-9cc1-b9c5ad47faf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161183986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4161183986
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1770030749
Short name T13
Test name
Test status
Simulation time 37345344553 ps
CPU time 1454.49 seconds
Started Mar 21 03:22:48 PM PDT 24
Finished Mar 21 03:47:02 PM PDT 24
Peak memory 235580 kb
Host smart-58a3980a-7720-4c21-83d5-39ad72e387a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770030749 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1770030749
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3994457789
Short name T299
Test name
Test status
Simulation time 1551618792 ps
CPU time 13.6 seconds
Started Mar 21 01:36:40 PM PDT 24
Finished Mar 21 01:36:54 PM PDT 24
Peak memory 210828 kb
Host smart-4ffee45e-57b7-44e3-8058-baf5a3fa0886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994457789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3994457789
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4155646254
Short name T468
Test name
Test status
Simulation time 9720837151 ps
CPU time 16.13 seconds
Started Mar 21 03:22:47 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 210964 kb
Host smart-d4d064a6-8bc6-4fe9-b63e-43070c938a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155646254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4155646254
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1537508818
Short name T669
Test name
Test status
Simulation time 25902290321 ps
CPU time 268.48 seconds
Started Mar 21 01:36:43 PM PDT 24
Finished Mar 21 01:41:12 PM PDT 24
Peak memory 218296 kb
Host smart-00d9289f-d718-43db-8bfd-143d698654ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537508818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1537508818
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.712632373
Short name T309
Test name
Test status
Simulation time 72240899084 ps
CPU time 170.94 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:25:38 PM PDT 24
Peak memory 228528 kb
Host smart-9e874302-c634-4e4d-834a-43a68e33e193
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712632373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.712632373
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2891050196
Short name T444
Test name
Test status
Simulation time 31606275253 ps
CPU time 23.03 seconds
Started Mar 21 01:36:45 PM PDT 24
Finished Mar 21 01:37:08 PM PDT 24
Peak memory 211972 kb
Host smart-c3cb48f7-e476-416c-8478-622683d50140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891050196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2891050196
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3341264134
Short name T554
Test name
Test status
Simulation time 2425337829 ps
CPU time 23.74 seconds
Started Mar 21 03:22:45 PM PDT 24
Finished Mar 21 03:23:09 PM PDT 24
Peak memory 211664 kb
Host smart-41acbb85-cef6-4d38-883d-36295d0d79d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341264134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3341264134
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1810436870
Short name T442
Test name
Test status
Simulation time 1029655758 ps
CPU time 11.58 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:22:58 PM PDT 24
Peak memory 210820 kb
Host smart-4062d81f-ce5c-4712-af2b-0e09f70daeaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810436870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1810436870
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3340777703
Short name T650
Test name
Test status
Simulation time 5672074860 ps
CPU time 15.46 seconds
Started Mar 21 01:36:39 PM PDT 24
Finished Mar 21 01:36:55 PM PDT 24
Peak memory 210852 kb
Host smart-29ef0b92-d656-49e9-8c83-dc9943033b6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340777703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3340777703
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1666052956
Short name T623
Test name
Test status
Simulation time 3935709907 ps
CPU time 35.82 seconds
Started Mar 21 03:22:49 PM PDT 24
Finished Mar 21 03:23:25 PM PDT 24
Peak memory 211816 kb
Host smart-88b861d3-085d-4667-9f79-5a22b3e4b22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666052956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1666052956
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4032134469
Short name T312
Test name
Test status
Simulation time 2263623591 ps
CPU time 14.19 seconds
Started Mar 21 01:36:39 PM PDT 24
Finished Mar 21 01:36:53 PM PDT 24
Peak memory 219052 kb
Host smart-8cfa658d-d61c-4e91-830f-0f80ab13d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032134469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4032134469
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.168233772
Short name T509
Test name
Test status
Simulation time 28936800976 ps
CPU time 105.42 seconds
Started Mar 21 01:36:38 PM PDT 24
Finished Mar 21 01:38:23 PM PDT 24
Peak memory 218960 kb
Host smart-8cf95d2c-aed8-4494-949b-683207cdb03e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168233772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.168233772
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.447074488
Short name T242
Test name
Test status
Simulation time 79941698451 ps
CPU time 62.48 seconds
Started Mar 21 03:22:50 PM PDT 24
Finished Mar 21 03:23:53 PM PDT 24
Peak memory 218984 kb
Host smart-7ec70011-92ef-4e91-aadf-af981e119b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447074488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.447074488
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.466569076
Short name T53
Test name
Test status
Simulation time 27321436812 ps
CPU time 884.36 seconds
Started Mar 21 03:22:48 PM PDT 24
Finished Mar 21 03:37:33 PM PDT 24
Peak memory 235592 kb
Host smart-495e29dc-e781-4e69-9929-46dab1108fcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466569076 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.466569076
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2457545531
Short name T138
Test name
Test status
Simulation time 4065246979 ps
CPU time 16.31 seconds
Started Mar 21 01:36:38 PM PDT 24
Finished Mar 21 01:36:55 PM PDT 24
Peak memory 210824 kb
Host smart-9d38a75b-e1b2-4479-9c45-404db45f6492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457545531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2457545531
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.593161419
Short name T177
Test name
Test status
Simulation time 3662618439 ps
CPU time 9.05 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:09 PM PDT 24
Peak memory 210968 kb
Host smart-0cbe307d-7ac2-4535-bb53-f1a5b0a1ce98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593161419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.593161419
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3394682219
Short name T28
Test name
Test status
Simulation time 179508353375 ps
CPU time 325.31 seconds
Started Mar 21 03:23:01 PM PDT 24
Finished Mar 21 03:28:27 PM PDT 24
Peak memory 228304 kb
Host smart-32867d4a-5b30-4063-90b3-3fd42e0c8797
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394682219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3394682219
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3938173768
Short name T297
Test name
Test status
Simulation time 56604506410 ps
CPU time 120.27 seconds
Started Mar 21 01:36:39 PM PDT 24
Finished Mar 21 01:38:40 PM PDT 24
Peak memory 237568 kb
Host smart-da9eee4c-c97d-4d6d-976f-c67b6e924eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938173768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3938173768
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.280645350
Short name T439
Test name
Test status
Simulation time 23661796561 ps
CPU time 36.01 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:39 PM PDT 24
Peak memory 211852 kb
Host smart-53c3c588-a251-4b4a-af0c-6fd1a8d34a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280645350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.280645350
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.976915358
Short name T613
Test name
Test status
Simulation time 2559519874 ps
CPU time 25.4 seconds
Started Mar 21 01:36:40 PM PDT 24
Finished Mar 21 01:37:05 PM PDT 24
Peak memory 211536 kb
Host smart-a1647dcd-2480-4f81-bd32-da1741416bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976915358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.976915358
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1852889207
Short name T430
Test name
Test status
Simulation time 1522698408 ps
CPU time 14.6 seconds
Started Mar 21 01:36:40 PM PDT 24
Finished Mar 21 01:36:55 PM PDT 24
Peak memory 210772 kb
Host smart-5c535dc0-e655-4da0-8f37-f569943f85d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852889207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1852889207
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3165760965
Short name T563
Test name
Test status
Simulation time 1275257140 ps
CPU time 12.8 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:12 PM PDT 24
Peak memory 210884 kb
Host smart-44519f8b-9aeb-4cc4-b16e-303da22a800e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165760965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3165760965
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2222812593
Short name T228
Test name
Test status
Simulation time 15489559080 ps
CPU time 36.72 seconds
Started Mar 21 01:36:39 PM PDT 24
Finished Mar 21 01:37:16 PM PDT 24
Peak memory 219004 kb
Host smart-12661c1f-c35e-47e0-b170-2e81bf5d1326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222812593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2222812593
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4292089682
Short name T188
Test name
Test status
Simulation time 13832688705 ps
CPU time 31.05 seconds
Started Mar 21 03:22:46 PM PDT 24
Finished Mar 21 03:23:17 PM PDT 24
Peak memory 213244 kb
Host smart-85006a0d-8a72-4161-b5ee-cf759fc8045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292089682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4292089682
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1593926381
Short name T622
Test name
Test status
Simulation time 2519087142 ps
CPU time 26.81 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:27 PM PDT 24
Peak memory 214148 kb
Host smart-1514b804-e408-467f-95bf-04c7b0953e35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593926381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1593926381
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2718888291
Short name T316
Test name
Test status
Simulation time 8223245142 ps
CPU time 18.38 seconds
Started Mar 21 01:36:39 PM PDT 24
Finished Mar 21 01:36:58 PM PDT 24
Peak memory 211976 kb
Host smart-2ff2d819-027a-4f3b-b5c3-acda104eda3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718888291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2718888291
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.506542962
Short name T518
Test name
Test status
Simulation time 2978186606 ps
CPU time 13.5 seconds
Started Mar 21 01:35:55 PM PDT 24
Finished Mar 21 01:36:09 PM PDT 24
Peak memory 210880 kb
Host smart-34338f43-6716-44c7-84e9-82df1cd056ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506542962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.506542962
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.65068681
Short name T515
Test name
Test status
Simulation time 1387816646 ps
CPU time 8.84 seconds
Started Mar 21 03:20:58 PM PDT 24
Finished Mar 21 03:21:07 PM PDT 24
Peak memory 210896 kb
Host smart-4f385600-730d-4856-b730-7aff67f0a7af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65068681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.65068681
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1116519439
Short name T580
Test name
Test status
Simulation time 1543460586 ps
CPU time 93.34 seconds
Started Mar 21 01:35:44 PM PDT 24
Finished Mar 21 01:37:19 PM PDT 24
Peak memory 227388 kb
Host smart-29697210-6f89-4107-a26e-a7d38c5e86a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116519439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1116519439
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2008350818
Short name T189
Test name
Test status
Simulation time 184260924101 ps
CPU time 483.37 seconds
Started Mar 21 03:21:00 PM PDT 24
Finished Mar 21 03:29:03 PM PDT 24
Peak memory 224400 kb
Host smart-c2568451-2bf8-49e9-bc2c-f18ce7253da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008350818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2008350818
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.130641048
Short name T503
Test name
Test status
Simulation time 6388099389 ps
CPU time 19.36 seconds
Started Mar 21 01:35:49 PM PDT 24
Finished Mar 21 01:36:09 PM PDT 24
Peak memory 210896 kb
Host smart-b044fa39-ed95-4657-ae45-3b432bbd6569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130641048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.130641048
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2861280019
Short name T175
Test name
Test status
Simulation time 10231358043 ps
CPU time 24.58 seconds
Started Mar 21 03:20:58 PM PDT 24
Finished Mar 21 03:21:23 PM PDT 24
Peak memory 211792 kb
Host smart-12345e61-2eda-4422-94d6-0ca0c807f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861280019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2861280019
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3831370772
Short name T190
Test name
Test status
Simulation time 2870747059 ps
CPU time 10.2 seconds
Started Mar 21 03:21:07 PM PDT 24
Finished Mar 21 03:21:18 PM PDT 24
Peak memory 210908 kb
Host smart-c2f25302-320c-407e-95f0-6b2f1b09a7c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831370772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3831370772
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.491425797
Short name T258
Test name
Test status
Simulation time 1468059607 ps
CPU time 9.75 seconds
Started Mar 21 01:35:44 PM PDT 24
Finished Mar 21 01:35:55 PM PDT 24
Peak memory 210756 kb
Host smart-f35b5885-0169-46f8-9dd1-0a1e1ac47f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491425797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.491425797
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3545996141
Short name T4
Test name
Test status
Simulation time 7596738001 ps
CPU time 25.34 seconds
Started Mar 21 03:21:00 PM PDT 24
Finished Mar 21 03:21:26 PM PDT 24
Peak memory 214492 kb
Host smart-d3372fdf-1ce3-4a88-8774-80a85694c75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545996141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3545996141
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3957337622
Short name T560
Test name
Test status
Simulation time 16036063977 ps
CPU time 32.92 seconds
Started Mar 21 01:35:43 PM PDT 24
Finished Mar 21 01:36:18 PM PDT 24
Peak memory 219012 kb
Host smart-304d4973-4f29-4515-81cc-6e60fb4373cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957337622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3957337622
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1323100550
Short name T458
Test name
Test status
Simulation time 15185294631 ps
CPU time 45.32 seconds
Started Mar 21 01:35:44 PM PDT 24
Finished Mar 21 01:36:31 PM PDT 24
Peak memory 219004 kb
Host smart-45e153cb-4d1e-4e3b-bdf2-327496112560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323100550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1323100550
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.889570719
Short name T606
Test name
Test status
Simulation time 9060308339 ps
CPU time 44.35 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:21:43 PM PDT 24
Peak memory 219068 kb
Host smart-dfc8c76c-c14b-42a8-89e4-a275c1ddd190
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889570719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.889570719
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2701387761
Short name T548
Test name
Test status
Simulation time 29819406828 ps
CPU time 1209.68 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:41:09 PM PDT 24
Peak memory 235272 kb
Host smart-6f5f35dc-f107-437d-b9e1-a9dd87c50d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701387761 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2701387761
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1518041477
Short name T173
Test name
Test status
Simulation time 917341269 ps
CPU time 9.31 seconds
Started Mar 21 03:21:01 PM PDT 24
Finished Mar 21 03:21:11 PM PDT 24
Peak memory 210884 kb
Host smart-2d187e6e-1b99-41fe-82b5-7abc598484c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518041477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1518041477
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2799747967
Short name T587
Test name
Test status
Simulation time 3906409308 ps
CPU time 10.69 seconds
Started Mar 21 01:35:45 PM PDT 24
Finished Mar 21 01:35:56 PM PDT 24
Peak memory 210888 kb
Host smart-4bab4c2f-2b27-42d0-9b72-ed5fb9c75ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799747967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2799747967
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1044900826
Short name T239
Test name
Test status
Simulation time 33887090622 ps
CPU time 171.99 seconds
Started Mar 21 01:35:51 PM PDT 24
Finished Mar 21 01:38:43 PM PDT 24
Peak memory 220552 kb
Host smart-447d36b8-56da-41d6-9e29-d045b128317b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044900826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1044900826
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4105005302
Short name T286
Test name
Test status
Simulation time 14670600780 ps
CPU time 137.34 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:23:16 PM PDT 24
Peak memory 229356 kb
Host smart-d8667102-9278-4655-8edd-8027ac12d946
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105005302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4105005302
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2301104480
Short name T275
Test name
Test status
Simulation time 2124805319 ps
CPU time 21.55 seconds
Started Mar 21 01:35:49 PM PDT 24
Finished Mar 21 01:36:11 PM PDT 24
Peak memory 211624 kb
Host smart-66a931e3-0dcb-4ca5-89fc-a8b6451e5c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301104480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2301104480
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3235848927
Short name T524
Test name
Test status
Simulation time 7523468322 ps
CPU time 21.4 seconds
Started Mar 21 03:20:58 PM PDT 24
Finished Mar 21 03:21:20 PM PDT 24
Peak memory 212076 kb
Host smart-f350ae66-ed9c-4600-8592-05dd479834a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235848927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3235848927
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.141290255
Short name T340
Test name
Test status
Simulation time 4204335533 ps
CPU time 17.98 seconds
Started Mar 21 01:35:45 PM PDT 24
Finished Mar 21 01:36:03 PM PDT 24
Peak memory 210832 kb
Host smart-07daa069-d15c-4c72-83cc-4d1be3949f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141290255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.141290255
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4244194761
Short name T49
Test name
Test status
Simulation time 2180789576 ps
CPU time 9.08 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:21:08 PM PDT 24
Peak memory 210916 kb
Host smart-5da02bab-ad6c-4892-a1c7-4496289d0ab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244194761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4244194761
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1811407911
Short name T450
Test name
Test status
Simulation time 49656898929 ps
CPU time 29.03 seconds
Started Mar 21 03:21:07 PM PDT 24
Finished Mar 21 03:21:37 PM PDT 24
Peak memory 219064 kb
Host smart-5d7982cf-44be-44c1-9546-4bf7a90b3b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811407911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1811407911
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2797435238
Short name T20
Test name
Test status
Simulation time 2704563350 ps
CPU time 25.6 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 01:36:20 PM PDT 24
Peak memory 219004 kb
Host smart-bc83bbd5-c643-422c-ba12-039f8244a2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797435238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2797435238
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.440993419
Short name T294
Test name
Test status
Simulation time 7041426179 ps
CPU time 36.09 seconds
Started Mar 21 01:35:45 PM PDT 24
Finished Mar 21 01:36:21 PM PDT 24
Peak memory 213372 kb
Host smart-c5dc6f84-ec23-4e2f-90ed-25a16515010e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440993419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.440993419
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.338269964
Short name T236
Test name
Test status
Simulation time 3973281922 ps
CPU time 12.45 seconds
Started Mar 21 03:20:58 PM PDT 24
Finished Mar 21 03:21:11 PM PDT 24
Peak memory 210952 kb
Host smart-bb74e8eb-7a7b-459e-8cff-488bc28e52bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338269964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.338269964
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.555996993
Short name T214
Test name
Test status
Simulation time 89234722 ps
CPU time 4.24 seconds
Started Mar 21 01:35:46 PM PDT 24
Finished Mar 21 01:35:50 PM PDT 24
Peak memory 210740 kb
Host smart-53716a5f-ea81-4757-85df-93951ce4dd37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555996993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.555996993
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2063594066
Short name T24
Test name
Test status
Simulation time 19675394633 ps
CPU time 229.44 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 221144 kb
Host smart-7cc7d1ba-9738-4ad3-86eb-5ade0c753305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063594066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2063594066
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3427707424
Short name T44
Test name
Test status
Simulation time 5118683549 ps
CPU time 81.63 seconds
Started Mar 21 01:35:44 PM PDT 24
Finished Mar 21 01:37:07 PM PDT 24
Peak memory 228412 kb
Host smart-8d1d9e67-0362-46d5-8946-872f59456c6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427707424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3427707424
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4140915909
Short name T419
Test name
Test status
Simulation time 17644912362 ps
CPU time 23.92 seconds
Started Mar 21 03:21:08 PM PDT 24
Finished Mar 21 03:21:33 PM PDT 24
Peak memory 212100 kb
Host smart-ed71199a-df1a-43e5-ba11-c69ee0a04c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140915909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4140915909
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.556606196
Short name T305
Test name
Test status
Simulation time 1980275799 ps
CPU time 21.03 seconds
Started Mar 21 01:35:51 PM PDT 24
Finished Mar 21 01:36:12 PM PDT 24
Peak memory 210828 kb
Host smart-1ba09564-38af-4cf2-837f-ce1227b97ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556606196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.556606196
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1390192318
Short name T111
Test name
Test status
Simulation time 8621379043 ps
CPU time 16.71 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:36:12 PM PDT 24
Peak memory 210836 kb
Host smart-d697bef3-6d0c-46a4-a5c4-4764e03fbd0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390192318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1390192318
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1957487633
Short name T464
Test name
Test status
Simulation time 1564444828 ps
CPU time 13.92 seconds
Started Mar 21 03:21:00 PM PDT 24
Finished Mar 21 03:21:15 PM PDT 24
Peak memory 211140 kb
Host smart-236a9513-3bfa-4415-a282-45edff488898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957487633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1957487633
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2652607427
Short name T45
Test name
Test status
Simulation time 838634563 ps
CPU time 15.47 seconds
Started Mar 21 03:20:58 PM PDT 24
Finished Mar 21 03:21:14 PM PDT 24
Peak memory 218976 kb
Host smart-0b124471-1a60-4648-9407-602db2ca4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652607427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2652607427
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.320968423
Short name T3
Test name
Test status
Simulation time 184702217 ps
CPU time 10.31 seconds
Started Mar 21 01:35:53 PM PDT 24
Finished Mar 21 01:36:04 PM PDT 24
Peak memory 212824 kb
Host smart-ce263a48-9987-4990-9bdd-0a84ced7e94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320968423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.320968423
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2462060586
Short name T136
Test name
Test status
Simulation time 971586853 ps
CPU time 11.27 seconds
Started Mar 21 03:21:08 PM PDT 24
Finished Mar 21 03:21:19 PM PDT 24
Peak memory 210784 kb
Host smart-3c77c6ef-1dfe-4421-a488-26c887b8424f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462060586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2462060586
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3156204979
Short name T675
Test name
Test status
Simulation time 8266980916 ps
CPU time 43.05 seconds
Started Mar 21 01:35:47 PM PDT 24
Finished Mar 21 01:36:30 PM PDT 24
Peak memory 218996 kb
Host smart-f5389239-5052-4514-a048-000368936337
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156204979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3156204979
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.273691365
Short name T1
Test name
Test status
Simulation time 14181949175 ps
CPU time 3289.09 seconds
Started Mar 21 01:35:54 PM PDT 24
Finished Mar 21 02:30:43 PM PDT 24
Peak memory 224164 kb
Host smart-63e0d086-761c-4c8d-96d3-28919c759e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273691365 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.273691365
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3911592557
Short name T95
Test name
Test status
Simulation time 82172646217 ps
CPU time 5189.36 seconds
Started Mar 21 03:20:59 PM PDT 24
Finished Mar 21 04:47:29 PM PDT 24
Peak memory 235576 kb
Host smart-a81b1277-4f38-491a-995a-183ffe33772c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911592557 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3911592557
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1870224085
Short name T478
Test name
Test status
Simulation time 1684717612 ps
CPU time 14.71 seconds
Started Mar 21 03:21:05 PM PDT 24
Finished Mar 21 03:21:20 PM PDT 24
Peak memory 210880 kb
Host smart-de4586b8-51fa-47cd-b27b-11535b9ffea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870224085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1870224085
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3621917301
Short name T293
Test name
Test status
Simulation time 1950275698 ps
CPU time 16.05 seconds
Started Mar 21 01:36:03 PM PDT 24
Finished Mar 21 01:36:19 PM PDT 24
Peak memory 210772 kb
Host smart-1e5c1ebf-3e02-4eed-b672-a7261633d753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621917301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3621917301
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3430854904
Short name T536
Test name
Test status
Simulation time 29086698927 ps
CPU time 316.13 seconds
Started Mar 21 03:21:07 PM PDT 24
Finished Mar 21 03:26:24 PM PDT 24
Peak memory 229312 kb
Host smart-68675a0a-0023-438e-a0de-2007ae3e785d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430854904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3430854904
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3817574158
Short name T465
Test name
Test status
Simulation time 63435425954 ps
CPU time 184.8 seconds
Started Mar 21 01:35:47 PM PDT 24
Finished Mar 21 01:38:52 PM PDT 24
Peak memory 218244 kb
Host smart-b5e74a61-6a5a-4c65-9f90-89a9eed8c8d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817574158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3817574158
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1659704526
Short name T343
Test name
Test status
Simulation time 680555810 ps
CPU time 13.95 seconds
Started Mar 21 01:35:55 PM PDT 24
Finished Mar 21 01:36:09 PM PDT 24
Peak memory 211492 kb
Host smart-4d9ebf22-ffa0-4759-a646-f7166a406292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659704526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1659704526
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1877572774
Short name T393
Test name
Test status
Simulation time 4110648780 ps
CPU time 16.56 seconds
Started Mar 21 03:21:06 PM PDT 24
Finished Mar 21 03:21:24 PM PDT 24
Peak memory 211504 kb
Host smart-c1f4ecb5-ba69-4b94-8cd7-a9f4ffbb66a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877572774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1877572774
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2623410032
Short name T349
Test name
Test status
Simulation time 4224876490 ps
CPU time 17.55 seconds
Started Mar 21 03:21:06 PM PDT 24
Finished Mar 21 03:21:25 PM PDT 24
Peak memory 210908 kb
Host smart-fed9e656-35eb-4419-abb7-e5c27615ab7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623410032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2623410032
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2838590001
Short name T142
Test name
Test status
Simulation time 4163953976 ps
CPU time 12.16 seconds
Started Mar 21 01:35:49 PM PDT 24
Finished Mar 21 01:36:02 PM PDT 24
Peak memory 210872 kb
Host smart-5a2a46fb-8736-468c-801e-5a310e3f6c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838590001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2838590001
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1974250323
Short name T643
Test name
Test status
Simulation time 764811392 ps
CPU time 10.56 seconds
Started Mar 21 03:21:00 PM PDT 24
Finished Mar 21 03:21:11 PM PDT 24
Peak memory 212824 kb
Host smart-742f74b8-a59e-41db-b547-d7179952a24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974250323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1974250323
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.842319169
Short name T210
Test name
Test status
Simulation time 3294211301 ps
CPU time 23.13 seconds
Started Mar 21 01:35:51 PM PDT 24
Finished Mar 21 01:36:15 PM PDT 24
Peak memory 212992 kb
Host smart-fc200f8e-b2e0-417e-8042-cc381c201b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842319169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.842319169
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1674035606
Short name T567
Test name
Test status
Simulation time 4700591973 ps
CPU time 50.21 seconds
Started Mar 21 01:35:49 PM PDT 24
Finished Mar 21 01:36:40 PM PDT 24
Peak memory 216796 kb
Host smart-73fe9718-9958-410c-9046-707d94ef10df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674035606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1674035606
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3740394693
Short name T284
Test name
Test status
Simulation time 17056169872 ps
CPU time 37.78 seconds
Started Mar 21 03:21:08 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 214092 kb
Host smart-d10d8139-5904-4d93-a317-7f97e0bc15b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740394693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3740394693
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.634829479
Short name T325
Test name
Test status
Simulation time 46457374128 ps
CPU time 1769.69 seconds
Started Mar 21 01:35:57 PM PDT 24
Finished Mar 21 02:05:27 PM PDT 24
Peak memory 232620 kb
Host smart-1bec4e11-b69a-470c-b4c7-7b7164557a54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634829479 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.634829479
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1036338904
Short name T659
Test name
Test status
Simulation time 1039026758 ps
CPU time 9.83 seconds
Started Mar 21 01:36:06 PM PDT 24
Finished Mar 21 01:36:17 PM PDT 24
Peak memory 210716 kb
Host smart-2bcfd14e-83eb-4c93-b040-21de84a28874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036338904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1036338904
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3508988572
Short name T237
Test name
Test status
Simulation time 3731532392 ps
CPU time 10.43 seconds
Started Mar 21 03:21:06 PM PDT 24
Finished Mar 21 03:21:17 PM PDT 24
Peak memory 210892 kb
Host smart-44f75855-ffce-495d-a629-48be3de169c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508988572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3508988572
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2540581871
Short name T179
Test name
Test status
Simulation time 20495690791 ps
CPU time 205.69 seconds
Started Mar 21 01:35:56 PM PDT 24
Finished Mar 21 01:39:21 PM PDT 24
Peak memory 228592 kb
Host smart-94056959-db2d-4f6d-8024-294bdbd4f796
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540581871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2540581871
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4167670805
Short name T555
Test name
Test status
Simulation time 405089007712 ps
CPU time 378.69 seconds
Started Mar 21 03:21:06 PM PDT 24
Finished Mar 21 03:27:24 PM PDT 24
Peak memory 233424 kb
Host smart-14c269ce-d666-4ac1-9de1-7fc36d0b69b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167670805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4167670805
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1068268423
Short name T16
Test name
Test status
Simulation time 793118423 ps
CPU time 9.46 seconds
Started Mar 21 03:21:08 PM PDT 24
Finished Mar 21 03:21:18 PM PDT 24
Peak memory 211580 kb
Host smart-92a2c361-5827-4a8f-9efa-7f1a7447e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068268423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1068268423
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.784280842
Short name T583
Test name
Test status
Simulation time 1371944356 ps
CPU time 12.17 seconds
Started Mar 21 01:36:01 PM PDT 24
Finished Mar 21 01:36:13 PM PDT 24
Peak memory 211268 kb
Host smart-1e1685a4-6b6e-4722-90b5-8473683e3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784280842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.784280842
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1234826141
Short name T672
Test name
Test status
Simulation time 418189691 ps
CPU time 5.81 seconds
Started Mar 21 01:35:57 PM PDT 24
Finished Mar 21 01:36:03 PM PDT 24
Peak memory 210776 kb
Host smart-c4c7dc3d-289d-4045-a913-0f8ef057e87a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234826141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1234826141
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.669445899
Short name T682
Test name
Test status
Simulation time 1713306851 ps
CPU time 14.92 seconds
Started Mar 21 03:21:08 PM PDT 24
Finished Mar 21 03:21:25 PM PDT 24
Peak memory 210848 kb
Host smart-dad0aa13-d8fd-4065-a45c-b7b30fd95bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669445899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.669445899
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3376628918
Short name T507
Test name
Test status
Simulation time 2462099616 ps
CPU time 14.94 seconds
Started Mar 21 03:21:06 PM PDT 24
Finished Mar 21 03:21:21 PM PDT 24
Peak memory 219120 kb
Host smart-9f058c7e-ffcb-4bcc-87f0-697cac0153db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376628918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3376628918
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3894302369
Short name T358
Test name
Test status
Simulation time 11321970611 ps
CPU time 26.44 seconds
Started Mar 21 01:36:06 PM PDT 24
Finished Mar 21 01:36:33 PM PDT 24
Peak memory 219056 kb
Host smart-be94ebb9-685c-4104-81df-3a01fd8f4e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894302369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3894302369
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1812384591
Short name T227
Test name
Test status
Simulation time 48237643564 ps
CPU time 49.08 seconds
Started Mar 21 03:21:07 PM PDT 24
Finished Mar 21 03:21:57 PM PDT 24
Peak memory 215964 kb
Host smart-d3c284b6-9165-4919-853b-ebf68f1cd729
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812384591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1812384591
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.46112673
Short name T273
Test name
Test status
Simulation time 20149015702 ps
CPU time 83.09 seconds
Started Mar 21 01:35:53 PM PDT 24
Finished Mar 21 01:37:16 PM PDT 24
Peak memory 219084 kb
Host smart-f9f7f3b2-e7a3-48a4-8fac-7fafbea0a853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46112673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.rom_ctrl_stress_all.46112673
Directory /workspace/9.rom_ctrl_stress_all/latest
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