Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	107157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2127010

1

T1

11

T2

15

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	599932	1			T1	137		T2	151		T3	286
values[0x0]	802261	1			T16	8927		T17	24482		T18	17705
values[0x1]	831974	1			T16	9127		T17	25186		T18	18372

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53810	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2180357

1

T1

89

T2

89

T3

161

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7807	1			T1	1		T3	2		T4	1
valid_sources[0x01]	8871	1			T1	1		T2	1		T12	1
valid_sources[0x02]	6820	1			T3	1		T14	1		T16	110
valid_sources[0x03]	10194	1			T2	4		T3	1		T4	1
valid_sources[0x04]	8848	1			T3	1		T14	3		T16	93
valid_sources[0x05]	9271	1			T1	2		T2	1		T4	1
valid_sources[0x06]	8480	1			T2	4		T3	1		T9	10
valid_sources[0x07]	9114	1			T4	2		T16	99		T70	1
valid_sources[0x08]	7576	1			T14	2		T11	6		T16	108
valid_sources[0x09]	8951	1			T3	1		T16	102		T71	2
valid_sources[0x0a]	10525	1			T1	1		T2	1		T3	1
valid_sources[0x0b]	5732	1			T14	1		T16	98		T17	242
valid_sources[0x0c]	10101	1			T3	1		T4	1		T5	2
valid_sources[0x0d]	9880	1			T3	1		T14	2		T16	119
valid_sources[0x0e]	7667	1			T2	3		T3	1		T9	3
valid_sources[0x0f]	9874	1			T4	2		T5	1		T12	1
valid_sources[0x10]	7630	1			T2	4		T3	2		T12	2
valid_sources[0x11]	9414	1			T12	3		T11	1		T16	107
valid_sources[0x12]	7760	1			T14	1		T16	99		T71	1
valid_sources[0x13]	9812	1			T3	2		T4	1		T13	1
valid_sources[0x14]	7570	1			T3	1		T16	90		T17	223
valid_sources[0x15]	9908	1			T1	1		T2	2		T3	1
valid_sources[0x16]	7728	1			T3	2		T4	1		T12	1
valid_sources[0x17]	10090	1			T2	4		T3	1		T12	2
valid_sources[0x18]	8622	1			T1	2		T2	2		T3	2
valid_sources[0x19]	8656	1			T4	4		T5	1		T14	1
valid_sources[0x1a]	6972	1			T1	1		T3	1		T13	1
valid_sources[0x1b]	13071	1			T2	2		T3	2		T13	1
valid_sources[0x1c]	9140	1			T1	1		T12	3		T11	7
valid_sources[0x1d]	11814	1			T1	1		T3	2		T12	4
valid_sources[0x1e]	9291	1			T1	1		T4	2		T12	2
valid_sources[0x1f]	9764	1			T3	2		T4	2		T14	1
valid_sources[0x20]	8010	1			T1	1		T2	1		T3	2
valid_sources[0x21]	10224	1			T3	2		T4	2		T12	2
valid_sources[0x22]	9290	1			T2	1		T4	1		T12	1
valid_sources[0x23]	9064	1			T1	1		T3	4		T13	1
valid_sources[0x24]	8639	1			T3	1		T4	1		T12	1
valid_sources[0x25]	9074	1			T3	1		T12	3		T16	98
valid_sources[0x26]	7901	1			T13	1		T14	2		T16	95
valid_sources[0x27]	7582	1			T4	1		T12	2		T14	1
valid_sources[0x28]	8619	1			T3	1		T16	84		T71	3
valid_sources[0x29]	8771	1			T12	1		T13	1		T16	109
valid_sources[0x2a]	8587	1			T1	4		T3	2		T4	3
valid_sources[0x2b]	8533	1			T3	1		T4	1		T14	2
valid_sources[0x2c]	9917	1			T3	1		T4	2		T12	4
valid_sources[0x2d]	8776	1			T4	1		T12	1		T14	1
valid_sources[0x2e]	7255	1			T12	1		T14	2		T16	117
valid_sources[0x2f]	11602	1			T3	2		T4	1		T16	104
valid_sources[0x30]	8631	1			T3	1		T5	5		T12	1
valid_sources[0x31]	9187	1			T3	2		T12	1		T16	87
valid_sources[0x32]	7832	1			T3	1		T4	1		T16	100
valid_sources[0x33]	9421	1			T3	1		T16	104		T17	401
valid_sources[0x34]	9616	1			T1	1		T3	1		T4	1
valid_sources[0x35]	7984	1			T3	3		T12	1		T16	96
valid_sources[0x36]	9043	1			T4	1		T14	2		T16	118
valid_sources[0x37]	9933	1			T3	2		T12	1		T16	114
valid_sources[0x38]	6755	1			T3	3		T4	2		T16	82
valid_sources[0x39]	8471	1			T4	3		T12	1		T14	2
valid_sources[0x3a]	8064	1			T4	2		T16	88		T71	1
valid_sources[0x3b]	8507	1			T3	3		T16	94		T17	328
valid_sources[0x3c]	7545	1			T1	1		T3	1		T9	4
valid_sources[0x3d]	8338	1			T1	1		T14	1		T16	79
valid_sources[0x3e]	7222	1			T1	1		T3	4		T14	1
valid_sources[0x3f]	9222	1			T1	1		T4	1		T14	2
valid_sources[0x40]	8976	1			T4	1		T12	2		T13	1
valid_sources[0x41]	10118	1			T1	3		T3	1		T12	6
valid_sources[0x42]	8001	1			T2	7		T4	1		T16	88
valid_sources[0x43]	8133	1			T3	3		T4	3		T16	87
valid_sources[0x44]	12056	1			T3	2		T12	1		T14	2
valid_sources[0x45]	9015	1			T3	2		T5	1		T14	1
valid_sources[0x46]	7136	1			T3	1		T14	1		T16	82
valid_sources[0x47]	9157	1			T3	3		T4	1		T16	95
valid_sources[0x48]	8347	1			T3	2		T16	86		T17	373
valid_sources[0x49]	6943	1			T1	1		T4	1		T12	2
valid_sources[0x4a]	9628	1			T3	2		T4	1		T5	1
valid_sources[0x4b]	10339	1			T4	1		T16	94		T71	2
valid_sources[0x4c]	7771	1			T1	1		T3	1		T12	1
valid_sources[0x4d]	9791	1			T4	1		T16	78		T69	5
valid_sources[0x4e]	8783	1			T3	3		T4	1		T12	1
valid_sources[0x4f]	7112	1			T4	1		T5	2		T16	89
valid_sources[0x50]	8322	1			T2	5		T3	2		T4	1
valid_sources[0x51]	8066	1			T3	3		T12	1		T11	1
valid_sources[0x52]	8594	1			T3	2		T4	1		T14	1
valid_sources[0x53]	7070	1			T4	1		T5	2		T14	1
valid_sources[0x54]	11514	1			T4	3		T16	91		T70	1
valid_sources[0x55]	10537	1			T3	1		T4	1		T12	2
valid_sources[0x56]	10905	1			T3	1		T4	2		T13	2
valid_sources[0x57]	8519	1			T3	2		T12	1		T14	1
valid_sources[0x58]	9532	1			T3	3		T4	2		T14	1
valid_sources[0x59]	7098	1			T4	4		T16	90		T17	175
valid_sources[0x5a]	10497	1			T1	4		T3	1		T5	1
valid_sources[0x5b]	10032	1			T1	1		T3	2		T13	2
valid_sources[0x5c]	7024	1			T3	2		T4	1		T12	1
valid_sources[0x5d]	7768	1			T1	3		T2	6		T3	1
valid_sources[0x5e]	5813	1			T4	2		T12	2		T13	1
valid_sources[0x5f]	8663	1			T1	1		T3	1		T4	1
valid_sources[0x60]	11503	1			T3	2		T12	1		T14	1
valid_sources[0x61]	8077	1			T1	4		T3	2		T4	1
valid_sources[0x62]	8733	1			T4	1		T16	92		T17	358
valid_sources[0x63]	6180	1			T1	1		T4	4		T13	1
valid_sources[0x64]	8233	1			T3	4		T12	1		T14	1
valid_sources[0x65]	10602	1			T3	2		T4	1		T14	1
valid_sources[0x66]	8737	1			T1	1		T3	2		T16	76
valid_sources[0x67]	7806	1			T1	1		T4	1		T9	6
valid_sources[0x68]	6997	1			T3	2		T5	7		T12	5
valid_sources[0x69]	8752	1			T4	1		T14	1		T16	100
valid_sources[0x6a]	8155	1			T3	5		T5	1		T14	1
valid_sources[0x6b]	7360	1			T2	2		T3	2		T4	4
valid_sources[0x6c]	11236	1			T3	1		T4	3		T14	1
valid_sources[0x6d]	10161	1			T4	1		T16	96		T69	2
valid_sources[0x6e]	9264	1			T3	2		T16	105		T71	1
valid_sources[0x6f]	9732	1			T3	4		T4	1		T16	91
valid_sources[0x70]	7685	1			T3	2		T4	2		T12	3
valid_sources[0x71]	8121	1			T11	6		T16	106		T71	1
valid_sources[0x72]	10233	1			T1	2		T12	1		T16	93
valid_sources[0x73]	10784	1			T3	1		T13	1		T16	93
valid_sources[0x74]	7482	1			T1	2		T3	2		T5	2
valid_sources[0x75]	8728	1			T3	3		T12	1		T14	2
valid_sources[0x76]	8937	1			T2	2		T3	4		T4	1
valid_sources[0x77]	8008	1			T1	1		T4	2		T12	1
valid_sources[0x78]	10525	1			T3	1		T12	5		T14	1
valid_sources[0x79]	7640	1			T4	4		T13	1		T16	96
valid_sources[0x7a]	7049	1			T1	1		T4	4		T12	2
valid_sources[0x7b]	8439	1			T1	1		T3	2		T16	99
valid_sources[0x7c]	8724	1			T1	1		T4	4		T12	1
valid_sources[0x7d]	9362	1			T1	1		T3	1		T5	3
valid_sources[0x7e]	10009	1			T2	3		T3	1		T4	4
valid_sources[0x7f]	8884	1			T1	6		T2	3		T3	2
valid_sources[0x80]	7325	1			T3	2		T16	120		T69	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

536082

1

T1

11

T2

15

T3

30

values[0x0]

all_enables

biggest_size

795258

1

T16

8856

T17

24275

T18

17547

values[0x1]

all_enables

biggest_size

795670

1

T16

8717

T17

24175

T18

17532

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	166067	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1647893

1

T1

38

T3

58

T5

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	458049	1			T1	64		T3	128		T5	32
values[0x0]	627803	1			T37	3		T16	6372		T17	18546
values[0x1]	728108	1			T7	2		T37	1		T16	7322

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	76621	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1737339

1

T1

41

T3

73

T5

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6922	1			T1	1		T8	1		T16	60
valid_sources[0x01]	6958	1			T9	3		T11	1		T16	51
valid_sources[0x02]	7002	1			T3	1		T29	1		T16	94
valid_sources[0x03]	6982	1			T16	37		T30	1		T17	182
valid_sources[0x04]	7721	1			T3	1		T5	3		T9	1
valid_sources[0x05]	7661	1			T12	1		T16	34		T30	1
valid_sources[0x06]	7029	1			T16	57		T17	216		T18	118
valid_sources[0x07]	7011	1			T11	4		T16	89		T30	1
valid_sources[0x08]	7467	1			T16	61		T17	205		T18	142
valid_sources[0x09]	7216	1			T11	8		T16	114		T17	193
valid_sources[0x0a]	6605	1			T3	1		T16	6		T17	191
valid_sources[0x0b]	7411	1			T1	4		T13	1		T16	30
valid_sources[0x0c]	7254	1			T11	4		T16	63		T58	2
valid_sources[0x0d]	7291	1			T16	41		T17	194		T18	135
valid_sources[0x0e]	6775	1			T3	1		T16	95		T17	190
valid_sources[0x0f]	6979	1			T1	3		T3	1		T12	2
valid_sources[0x10]	7297	1			T5	1		T11	3		T37	1
valid_sources[0x11]	7480	1			T16	140		T71	1		T17	207
valid_sources[0x12]	7095	1			T3	1		T9	1		T12	4
valid_sources[0x13]	6710	1			T16	81		T17	212		T18	159
valid_sources[0x14]	6506	1			T5	4		T16	36		T17	187
valid_sources[0x15]	6883	1			T16	120		T17	202		T18	165
valid_sources[0x16]	6998	1			T3	2		T16	82		T17	217
valid_sources[0x17]	6772	1			T12	2		T16	67		T17	223
valid_sources[0x18]	7085	1			T3	1		T16	94		T17	206
valid_sources[0x19]	7058	1			T5	2		T12	1		T16	68
valid_sources[0x1a]	7037	1			T3	3		T12	2		T16	94
valid_sources[0x1b]	7217	1			T16	50		T17	194		T18	119
valid_sources[0x1c]	7222	1			T16	77		T71	3		T17	195
valid_sources[0x1d]	6893	1			T5	1		T16	76		T17	196
valid_sources[0x1e]	6884	1			T12	1		T16	25		T17	190
valid_sources[0x1f]	7597	1			T3	1		T9	1		T16	89
valid_sources[0x20]	7365	1			T16	92		T58	1		T17	179
valid_sources[0x21]	7058	1			T16	27		T58	2		T17	212
valid_sources[0x22]	6955	1			T3	1		T5	1		T11	2
valid_sources[0x23]	6945	1			T5	1		T16	49		T17	218
valid_sources[0x24]	7246	1			T3	1		T11	9		T16	131
valid_sources[0x25]	6977	1			T16	105		T17	212		T18	123
valid_sources[0x26]	7095	1			T3	1		T9	1		T37	1
valid_sources[0x27]	6869	1			T12	1		T16	50		T17	223
valid_sources[0x28]	7149	1			T3	1		T16	104		T58	1
valid_sources[0x29]	6973	1			T3	1		T12	1		T16	128
valid_sources[0x2a]	6757	1			T3	1		T16	37		T17	200
valid_sources[0x2b]	7352	1			T3	1		T16	9		T17	218
valid_sources[0x2c]	7274	1			T16	30		T17	216		T38	1
valid_sources[0x2d]	7604	1			T16	165		T17	230		T18	121
valid_sources[0x2e]	6927	1			T16	95		T71	5		T30	1
valid_sources[0x2f]	6931	1			T3	1		T5	2		T16	62
valid_sources[0x30]	7147	1			T16	103		T30	1		T17	200
valid_sources[0x31]	6895	1			T12	1		T16	132		T17	204
valid_sources[0x32]	7215	1			T5	1		T16	80		T17	198
valid_sources[0x33]	6798	1			T16	28		T17	192		T18	148
valid_sources[0x34]	6762	1			T12	2		T16	44		T17	209
valid_sources[0x35]	6848	1			T3	2		T9	1		T12	1
valid_sources[0x36]	6880	1			T3	1		T9	1		T16	88
valid_sources[0x37]	7159	1			T3	1		T16	91		T17	203
valid_sources[0x38]	7020	1			T16	39		T17	198		T18	182
valid_sources[0x39]	7032	1			T3	1		T16	49		T17	209
valid_sources[0x3a]	7553	1			T3	1		T5	1		T16	40
valid_sources[0x3b]	6921	1			T3	2		T5	1		T16	61
valid_sources[0x3c]	7369	1			T3	1		T16	82		T17	183
valid_sources[0x3d]	7187	1			T3	3		T16	35		T17	249
valid_sources[0x3e]	7535	1			T9	1		T12	3		T16	97
valid_sources[0x3f]	7094	1			T1	1		T12	2		T16	79
valid_sources[0x40]	6638	1			T16	50		T71	8		T17	212
valid_sources[0x41]	7421	1			T16	180		T17	244		T18	134
valid_sources[0x42]	7271	1			T12	4		T16	42		T71	7
valid_sources[0x43]	6989	1			T3	1		T5	1		T16	118
valid_sources[0x44]	7268	1			T1	7		T9	1		T13	1
valid_sources[0x45]	7594	1			T9	2		T12	1		T16	61
valid_sources[0x46]	6941	1			T16	64		T17	219		T18	117
valid_sources[0x47]	6799	1			T12	1		T16	137		T17	196
valid_sources[0x48]	6975	1			T16	142		T17	202		T18	129
valid_sources[0x49]	7355	1			T16	80		T17	193		T18	201
valid_sources[0x4a]	7633	1			T13	1		T11	3		T16	123
valid_sources[0x4b]	7002	1			T3	1		T5	2		T16	11
valid_sources[0x4c]	7189	1			T3	1		T12	3		T16	111
valid_sources[0x4d]	6953	1			T3	1		T16	84		T17	200
valid_sources[0x4e]	7193	1			T16	121		T17	216		T18	116
valid_sources[0x4f]	7281	1			T5	1		T16	24		T17	232
valid_sources[0x50]	6786	1			T12	1		T16	29		T17	228
valid_sources[0x51]	7097	1			T3	2		T16	41		T30	1
valid_sources[0x52]	7060	1			T12	1		T16	27		T30	1
valid_sources[0x53]	6857	1			T1	3		T16	54		T70	32
valid_sources[0x54]	6933	1			T5	1		T9	1		T16	82
valid_sources[0x55]	7320	1			T5	1		T16	86		T17	231
valid_sources[0x56]	6830	1			T3	1		T16	142		T17	207
valid_sources[0x57]	7658	1			T3	1		T16	43		T30	1
valid_sources[0x58]	7048	1			T16	112		T30	1		T17	220
valid_sources[0x59]	6979	1			T7	2		T12	1		T16	32
valid_sources[0x5a]	7309	1			T3	2		T16	49		T17	203
valid_sources[0x5b]	6823	1			T9	1		T16	64		T32	38
valid_sources[0x5c]	7459	1			T3	1		T16	25		T17	219
valid_sources[0x5d]	7084	1			T13	1		T16	93		T22	1
valid_sources[0x5e]	6653	1			T16	21		T17	206		T18	118
valid_sources[0x5f]	7292	1			T3	1		T11	1		T16	111
valid_sources[0x60]	7429	1			T3	2		T16	128		T17	216
valid_sources[0x61]	7331	1			T1	3		T16	32		T17	220
valid_sources[0x62]	7217	1			T3	1		T16	59		T17	216
valid_sources[0x63]	7355	1			T12	1		T16	36		T58	2
valid_sources[0x64]	7207	1			T11	3		T16	76		T58	2
valid_sources[0x65]	6992	1			T12	2		T16	24		T17	208
valid_sources[0x66]	7075	1			T1	2		T3	1		T16	166
valid_sources[0x67]	6854	1			T3	1		T12	2		T16	58
valid_sources[0x68]	7144	1			T3	1		T16	53		T71	4
valid_sources[0x69]	7766	1			T1	1		T3	1		T12	3
valid_sources[0x6a]	6711	1			T11	1		T16	66		T30	1
valid_sources[0x6b]	7129	1			T9	1		T16	27		T71	3
valid_sources[0x6c]	7389	1			T16	100		T17	215		T18	146
valid_sources[0x6d]	8086	1			T16	61		T17	196		T38	1
valid_sources[0x6e]	7448	1			T16	158		T58	1		T17	200
valid_sources[0x6f]	7607	1			T16	73		T17	202		T18	91
valid_sources[0x70]	7086	1			T3	1		T16	135		T17	253
valid_sources[0x71]	6962	1			T3	1		T16	84		T17	180
valid_sources[0x72]	7075	1			T3	1		T16	71		T71	1
valid_sources[0x73]	7142	1			T16	77		T17	204		T18	157
valid_sources[0x74]	7209	1			T1	2		T16	57		T17	192
valid_sources[0x75]	7437	1			T16	115		T58	1		T17	224
valid_sources[0x76]	7339	1			T9	1		T11	3		T16	75
valid_sources[0x77]	7453	1			T16	120		T30	1		T17	195
valid_sources[0x78]	7057	1			T3	1		T16	14		T17	182
valid_sources[0x79]	7448	1			T9	1		T12	1		T13	1
valid_sources[0x7a]	6951	1			T3	1		T16	48		T17	222
valid_sources[0x7b]	7301	1			T1	10		T16	104		T17	247
valid_sources[0x7c]	7059	1			T16	139		T58	1		T17	230
valid_sources[0x7d]	7082	1			T3	2		T16	81		T17	240
valid_sources[0x7e]	7283	1			T16	151		T17	225		T18	156
valid_sources[0x7f]	6811	1			T16	38		T17	225		T18	125
valid_sources[0x80]	6665	1			T3	2		T16	91		T17	230

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

416937

1

T1

38

T3

58

T5

11

values[0x0]

all_enables

biggest_size

614390

1

T37

1

T16

6237

T17

18209

values[0x1]

all_enables

biggest_size

616566

1

T16

6174

T17

18600

T18

13321