Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3867448

1

T1

126

T2

136

T3

256

full_word

2479630

1

T1

11

T2

15

T3

30

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6346428	1			T1	137		T2	151		T3	286
auto[TlIntgErrCmd]	216	1			T72	2		T73	5		T74	4
auto[TlIntgErrData]	219	1			T72	6		T73	1		T74	8
auto[TlIntgErrBoth]	215	1			T72	2		T73	4		T74	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027502

1

T1

137

T2

151

T3

286

auto[1]

5319576

1

T16

57182

T17

160952

T18

118502

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	440014	1			T1	126		T2	136		T3	256
auto[TlIntgErrNone]	partial	auto[1]	3426837	1			T16	36359		T17	103324		T18	76820
auto[TlIntgErrNone]	full_word	auto[0]	587184	1			T1	11		T2	15		T3	30
auto[TlIntgErrNone]	full_word	auto[1]	1892393	1			T16	20823		T17	57628		T18	41682
auto[TlIntgErrCmd]	partial	auto[0]	81	1			T73	1		T74	2		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	118	1			T72	2		T73	3		T74	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T122	2		T129	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T73	1		T131	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	107	1			T72	2		T73	1		T74	6
auto[TlIntgErrData]	partial	auto[1]	95	1			T72	4		T74	2		T126	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T126	1		T132	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T123	1		T130	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	88	1			T72	1		T74	1		T122	5
auto[TlIntgErrBoth]	partial	auto[1]	108	1			T73	3		T74	7		T122	3
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T72	1		T73	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T135	1		T123	1		T130	1