| T552 |
/workspace/coverage/default/27.rom_ctrl_stress_all.570373548 |
|
|
Mar 24 12:58:00 PM PDT 24 |
Mar 24 12:58:24 PM PDT 24 |
2948233711 ps |
| T553 |
/workspace/coverage/default/35.rom_ctrl_stress_all.3533835091 |
|
|
Mar 24 12:58:10 PM PDT 24 |
Mar 24 12:58:27 PM PDT 24 |
6082452691 ps |
| T554 |
/workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1079422780 |
|
|
Mar 24 01:09:07 PM PDT 24 |
Mar 24 01:09:20 PM PDT 24 |
5182155685 ps |
| T555 |
/workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3116725832 |
|
|
Mar 24 12:58:15 PM PDT 24 |
Mar 24 12:58:31 PM PDT 24 |
4043669320 ps |
| T556 |
/workspace/coverage/default/7.rom_ctrl_stress_all.2374384672 |
|
|
Mar 24 01:08:05 PM PDT 24 |
Mar 24 01:08:37 PM PDT 24 |
586490046 ps |
| T557 |
/workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2918791488 |
|
|
Mar 24 01:08:19 PM PDT 24 |
Mar 24 01:11:32 PM PDT 24 |
57388105114 ps |
| T558 |
/workspace/coverage/default/30.rom_ctrl_stress_all.1321482700 |
|
|
Mar 24 01:08:35 PM PDT 24 |
Mar 24 01:09:18 PM PDT 24 |
6707873559 ps |
| T559 |
/workspace/coverage/default/38.rom_ctrl_stress_all.727609804 |
|
|
Mar 24 01:08:42 PM PDT 24 |
Mar 24 01:09:23 PM PDT 24 |
5237650361 ps |
| T560 |
/workspace/coverage/default/42.rom_ctrl_stress_all.2735407047 |
|
|
Mar 24 12:58:27 PM PDT 24 |
Mar 24 12:59:46 PM PDT 24 |
6958394676 ps |
| T561 |
/workspace/coverage/default/33.rom_ctrl_kmac_err_chk.37155365 |
|
|
Mar 24 01:08:32 PM PDT 24 |
Mar 24 01:09:00 PM PDT 24 |
2928494235 ps |
| T562 |
/workspace/coverage/default/29.rom_ctrl_smoke.2984236853 |
|
|
Mar 24 01:08:35 PM PDT 24 |
Mar 24 01:08:58 PM PDT 24 |
4820057451 ps |
| T563 |
/workspace/coverage/default/8.rom_ctrl_max_throughput_chk.533437919 |
|
|
Mar 24 12:57:10 PM PDT 24 |
Mar 24 12:57:15 PM PDT 24 |
383786670 ps |
| T564 |
/workspace/coverage/default/11.rom_ctrl_alert_test.2289499269 |
|
|
Mar 24 01:08:14 PM PDT 24 |
Mar 24 01:08:18 PM PDT 24 |
378388291 ps |
| T565 |
/workspace/coverage/default/10.rom_ctrl_smoke.2662413509 |
|
|
Mar 24 01:08:09 PM PDT 24 |
Mar 24 01:08:25 PM PDT 24 |
2329946433 ps |
| T566 |
/workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.271248366 |
|
|
Mar 24 01:09:12 PM PDT 24 |
Mar 24 01:10:31 PM PDT 24 |
5802427905 ps |
| T567 |
/workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3085251639 |
|
|
Mar 24 12:57:28 PM PDT 24 |
Mar 24 01:00:56 PM PDT 24 |
58901746525 ps |
| T568 |
/workspace/coverage/default/0.rom_ctrl_smoke.3290787183 |
|
|
Mar 24 12:56:55 PM PDT 24 |
Mar 24 12:57:14 PM PDT 24 |
8786561551 ps |
| T569 |
/workspace/coverage/default/30.rom_ctrl_smoke.3425501044 |
|
|
Mar 24 01:08:38 PM PDT 24 |
Mar 24 01:08:48 PM PDT 24 |
2529764866 ps |
| T570 |
/workspace/coverage/default/10.rom_ctrl_stress_all.3562546057 |
|
|
Mar 24 12:57:14 PM PDT 24 |
Mar 24 12:58:16 PM PDT 24 |
92442427550 ps |
| T571 |
/workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1701089613 |
|
|
Mar 24 01:08:15 PM PDT 24 |
Mar 24 01:08:26 PM PDT 24 |
1074616043 ps |
| T572 |
/workspace/coverage/default/38.rom_ctrl_alert_test.1976023993 |
|
|
Mar 24 12:58:16 PM PDT 24 |
Mar 24 12:58:31 PM PDT 24 |
8402709524 ps |
| T573 |
/workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3108885067 |
|
|
Mar 24 12:57:30 PM PDT 24 |
Mar 24 12:57:48 PM PDT 24 |
2629546295 ps |
| T574 |
/workspace/coverage/default/18.rom_ctrl_stress_all.3675627015 |
|
|
Mar 24 12:57:25 PM PDT 24 |
Mar 24 12:57:40 PM PDT 24 |
1065105095 ps |
| T575 |
/workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1944126397 |
|
|
Mar 24 01:08:00 PM PDT 24 |
Mar 24 01:21:34 PM PDT 24 |
21508706432 ps |
| T576 |
/workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2197127102 |
|
|
Mar 24 12:57:12 PM PDT 24 |
Mar 24 12:57:44 PM PDT 24 |
57116529059 ps |
| T577 |
/workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1670395481 |
|
|
Mar 24 01:08:31 PM PDT 24 |
Mar 24 01:08:41 PM PDT 24 |
693982657 ps |
| T578 |
/workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.214473254 |
|
|
Mar 24 12:58:31 PM PDT 24 |
Mar 24 01:00:23 PM PDT 24 |
27772325574 ps |
| T579 |
/workspace/coverage/default/31.rom_ctrl_alert_test.754065964 |
|
|
Mar 24 12:58:08 PM PDT 24 |
Mar 24 12:58:20 PM PDT 24 |
1126748012 ps |
| T580 |
/workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4032183504 |
|
|
Mar 24 01:08:06 PM PDT 24 |
Mar 24 01:08:23 PM PDT 24 |
3963187745 ps |
| T581 |
/workspace/coverage/default/29.rom_ctrl_alert_test.65622796 |
|
|
Mar 24 01:08:27 PM PDT 24 |
Mar 24 01:08:41 PM PDT 24 |
3973714144 ps |
| T582 |
/workspace/coverage/default/45.rom_ctrl_kmac_err_chk.568661700 |
|
|
Mar 24 12:58:32 PM PDT 24 |
Mar 24 12:59:06 PM PDT 24 |
15708434311 ps |
| T583 |
/workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1452196257 |
|
|
Mar 24 01:09:03 PM PDT 24 |
Mar 24 01:09:15 PM PDT 24 |
845343476 ps |
| T584 |
/workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4164258886 |
|
|
Mar 24 12:58:15 PM PDT 24 |
Mar 24 12:58:41 PM PDT 24 |
11243166291 ps |
| T585 |
/workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1470457026 |
|
|
Mar 24 12:57:26 PM PDT 24 |
Mar 24 12:59:39 PM PDT 24 |
4004298397 ps |
| T586 |
/workspace/coverage/default/30.rom_ctrl_alert_test.1030683499 |
|
|
Mar 24 12:58:06 PM PDT 24 |
Mar 24 12:58:23 PM PDT 24 |
2197478327 ps |
| T587 |
/workspace/coverage/default/19.rom_ctrl_max_throughput_chk.769002549 |
|
|
Mar 24 12:57:31 PM PDT 24 |
Mar 24 12:57:48 PM PDT 24 |
9521809529 ps |
| T588 |
/workspace/coverage/default/28.rom_ctrl_stress_all.3395052817 |
|
|
Mar 24 12:57:55 PM PDT 24 |
Mar 24 12:58:39 PM PDT 24 |
38986573652 ps |
| T589 |
/workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3211049766 |
|
|
Mar 24 12:58:01 PM PDT 24 |
Mar 24 12:58:18 PM PDT 24 |
7779258423 ps |
| T590 |
/workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1515925934 |
|
|
Mar 24 12:57:23 PM PDT 24 |
Mar 24 12:57:29 PM PDT 24 |
191042112 ps |
| T591 |
/workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3242977693 |
|
|
Mar 24 01:08:22 PM PDT 24 |
Mar 24 01:08:34 PM PDT 24 |
1978806453 ps |
| T592 |
/workspace/coverage/default/31.rom_ctrl_smoke.3698055363 |
|
|
Mar 24 01:08:28 PM PDT 24 |
Mar 24 01:09:09 PM PDT 24 |
19296227429 ps |
| T593 |
/workspace/coverage/default/27.rom_ctrl_alert_test.2083980240 |
|
|
Mar 24 12:57:56 PM PDT 24 |
Mar 24 12:58:02 PM PDT 24 |
173233848 ps |
| T594 |
/workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3114058730 |
|
|
Mar 24 12:58:15 PM PDT 24 |
Mar 24 12:58:49 PM PDT 24 |
20862082279 ps |
| T595 |
/workspace/coverage/default/26.rom_ctrl_stress_all.424538620 |
|
|
Mar 24 01:08:21 PM PDT 24 |
Mar 24 01:09:00 PM PDT 24 |
15656755169 ps |
| T596 |
/workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3026051233 |
|
|
Mar 24 12:56:59 PM PDT 24 |
Mar 24 12:57:21 PM PDT 24 |
8864857916 ps |
| T597 |
/workspace/coverage/default/36.rom_ctrl_alert_test.3807192760 |
|
|
Mar 24 12:58:15 PM PDT 24 |
Mar 24 12:58:26 PM PDT 24 |
3162031818 ps |
| T598 |
/workspace/coverage/default/37.rom_ctrl_alert_test.999092824 |
|
|
Mar 24 12:58:14 PM PDT 24 |
Mar 24 12:58:22 PM PDT 24 |
643405482 ps |
| T599 |
/workspace/coverage/default/15.rom_ctrl_kmac_err_chk.156990856 |
|
|
Mar 24 01:08:15 PM PDT 24 |
Mar 24 01:08:25 PM PDT 24 |
2072060841 ps |
| T600 |
/workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3398101107 |
|
|
Mar 24 12:57:25 PM PDT 24 |
Mar 24 12:57:38 PM PDT 24 |
1040887257 ps |
| T601 |
/workspace/coverage/default/28.rom_ctrl_alert_test.2120758681 |
|
|
Mar 24 12:58:01 PM PDT 24 |
Mar 24 12:58:07 PM PDT 24 |
167464796 ps |
| T602 |
/workspace/coverage/default/2.rom_ctrl_kmac_err_chk.584968457 |
|
|
Mar 24 12:57:04 PM PDT 24 |
Mar 24 12:57:30 PM PDT 24 |
19925185182 ps |
| T603 |
/workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2423525002 |
|
|
Mar 24 12:57:14 PM PDT 24 |
Mar 24 12:57:19 PM PDT 24 |
117093095 ps |
| T604 |
/workspace/coverage/default/45.rom_ctrl_alert_test.819700324 |
|
|
Mar 24 01:09:11 PM PDT 24 |
Mar 24 01:09:18 PM PDT 24 |
493351311 ps |
| T605 |
/workspace/coverage/default/41.rom_ctrl_stress_all.233724179 |
|
|
Mar 24 01:08:54 PM PDT 24 |
Mar 24 01:10:16 PM PDT 24 |
41100936352 ps |
| T606 |
/workspace/coverage/default/31.rom_ctrl_kmac_err_chk.125013475 |
|
|
Mar 24 12:58:10 PM PDT 24 |
Mar 24 12:58:37 PM PDT 24 |
2968683671 ps |
| T43 |
/workspace/coverage/default/0.rom_ctrl_sec_cm.2540735747 |
|
|
Mar 24 01:08:00 PM PDT 24 |
Mar 24 01:08:52 PM PDT 24 |
721261698 ps |
| T607 |
/workspace/coverage/default/47.rom_ctrl_kmac_err_chk.938335540 |
|
|
Mar 24 01:09:05 PM PDT 24 |
Mar 24 01:09:33 PM PDT 24 |
6058405247 ps |
| T608 |
/workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2964485327 |
|
|
Mar 24 01:07:53 PM PDT 24 |
Mar 24 01:08:24 PM PDT 24 |
6784868003 ps |
| T609 |
/workspace/coverage/default/14.rom_ctrl_kmac_err_chk.216514916 |
|
|
Mar 24 12:57:19 PM PDT 24 |
Mar 24 12:57:43 PM PDT 24 |
4807585622 ps |
| T610 |
/workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2507917386 |
|
|
Mar 24 01:07:55 PM PDT 24 |
Mar 24 01:08:06 PM PDT 24 |
863267302 ps |
| T611 |
/workspace/coverage/default/36.rom_ctrl_smoke.363915727 |
|
|
Mar 24 01:08:39 PM PDT 24 |
Mar 24 01:09:07 PM PDT 24 |
7979876828 ps |
| T612 |
/workspace/coverage/default/23.rom_ctrl_stress_all.3931079596 |
|
|
Mar 24 01:08:25 PM PDT 24 |
Mar 24 01:10:03 PM PDT 24 |
18820629527 ps |
| T613 |
/workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3518547113 |
|
|
Mar 24 01:08:42 PM PDT 24 |
Mar 24 01:08:48 PM PDT 24 |
99702066 ps |
| T614 |
/workspace/coverage/default/40.rom_ctrl_alert_test.4037305827 |
|
|
Mar 24 01:08:54 PM PDT 24 |
Mar 24 01:09:00 PM PDT 24 |
574556513 ps |
| T615 |
/workspace/coverage/default/36.rom_ctrl_stress_all.330646226 |
|
|
Mar 24 01:08:35 PM PDT 24 |
Mar 24 01:09:09 PM PDT 24 |
3146139083 ps |
| T616 |
/workspace/coverage/default/12.rom_ctrl_kmac_err_chk.984423906 |
|
|
Mar 24 01:08:14 PM PDT 24 |
Mar 24 01:08:28 PM PDT 24 |
2740613031 ps |
| T617 |
/workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3905920402 |
|
|
Mar 24 01:08:15 PM PDT 24 |
Mar 24 01:09:07 PM PDT 24 |
1570282690 ps |
| T618 |
/workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2851540001 |
|
|
Mar 24 12:58:16 PM PDT 24 |
Mar 24 01:02:39 PM PDT 24 |
157312098035 ps |
| T619 |
/workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4065850994 |
|
|
Mar 24 01:08:36 PM PDT 24 |
Mar 24 01:08:45 PM PDT 24 |
175354879 ps |
| T620 |
/workspace/coverage/default/25.rom_ctrl_alert_test.2191677698 |
|
|
Mar 24 01:08:30 PM PDT 24 |
Mar 24 01:08:37 PM PDT 24 |
614102115 ps |
| T621 |
/workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2573537756 |
|
|
Mar 24 12:57:09 PM PDT 24 |
Mar 24 12:57:21 PM PDT 24 |
1140627237 ps |
| T622 |
/workspace/coverage/default/4.rom_ctrl_smoke.1341014142 |
|
|
Mar 24 01:08:01 PM PDT 24 |
Mar 24 01:08:29 PM PDT 24 |
10318920939 ps |
| T623 |
/workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1533420411 |
|
|
Mar 24 12:57:40 PM PDT 24 |
Mar 24 12:58:09 PM PDT 24 |
11773697847 ps |
| T624 |
/workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1382048855 |
|
|
Mar 24 01:09:07 PM PDT 24 |
Mar 24 01:09:24 PM PDT 24 |
2113582638 ps |
| T625 |
/workspace/coverage/default/25.rom_ctrl_smoke.3670406711 |
|
|
Mar 24 12:57:47 PM PDT 24 |
Mar 24 12:57:57 PM PDT 24 |
381398850 ps |
| T626 |
/workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1614612131 |
|
|
Mar 24 12:57:55 PM PDT 24 |
Mar 24 01:02:17 PM PDT 24 |
27383932170 ps |
| T627 |
/workspace/coverage/default/23.rom_ctrl_alert_test.1699273480 |
|
|
Mar 24 01:08:22 PM PDT 24 |
Mar 24 01:08:33 PM PDT 24 |
3771602731 ps |
| T628 |
/workspace/coverage/default/11.rom_ctrl_alert_test.2778086919 |
|
|
Mar 24 12:57:17 PM PDT 24 |
Mar 24 12:57:31 PM PDT 24 |
1737468260 ps |
| T629 |
/workspace/coverage/default/23.rom_ctrl_smoke.2078703355 |
|
|
Mar 24 12:57:42 PM PDT 24 |
Mar 24 12:57:53 PM PDT 24 |
190965055 ps |
| T630 |
/workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3899851315 |
|
|
Mar 24 01:08:22 PM PDT 24 |
Mar 24 01:08:31 PM PDT 24 |
692655585 ps |
| T631 |
/workspace/coverage/default/16.rom_ctrl_smoke.3681760017 |
|
|
Mar 24 12:57:19 PM PDT 24 |
Mar 24 12:57:59 PM PDT 24 |
12430403879 ps |
| T632 |
/workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4187070090 |
|
|
Mar 24 01:08:05 PM PDT 24 |
Mar 24 01:10:19 PM PDT 24 |
6344027478 ps |
| T633 |
/workspace/coverage/default/49.rom_ctrl_stress_all.2255763977 |
|
|
Mar 24 12:58:40 PM PDT 24 |
Mar 24 12:59:40 PM PDT 24 |
50576717377 ps |
| T634 |
/workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3490289429 |
|
|
Mar 24 01:08:30 PM PDT 24 |
Mar 24 01:10:20 PM PDT 24 |
2178986754 ps |
| T635 |
/workspace/coverage/default/5.rom_ctrl_alert_test.4179666196 |
|
|
Mar 24 01:08:01 PM PDT 24 |
Mar 24 01:08:05 PM PDT 24 |
321345218 ps |
| T636 |
/workspace/coverage/default/18.rom_ctrl_smoke.1715649008 |
|
|
Mar 24 12:57:27 PM PDT 24 |
Mar 24 12:57:42 PM PDT 24 |
1878571590 ps |
| T637 |
/workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1466551987 |
|
|
Mar 24 01:08:28 PM PDT 24 |
Mar 24 01:08:46 PM PDT 24 |
1276907963 ps |
| T638 |
/workspace/coverage/default/40.rom_ctrl_smoke.3047241195 |
|
|
Mar 24 12:58:22 PM PDT 24 |
Mar 24 12:58:54 PM PDT 24 |
14527129065 ps |
| T639 |
/workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3629442480 |
|
|
Mar 24 12:58:24 PM PDT 24 |
Mar 24 12:58:38 PM PDT 24 |
1547942013 ps |
| T640 |
/workspace/coverage/default/36.rom_ctrl_alert_test.2354919320 |
|
|
Mar 24 01:08:38 PM PDT 24 |
Mar 24 01:08:45 PM PDT 24 |
1613059956 ps |
| T641 |
/workspace/coverage/default/47.rom_ctrl_stress_all.4237636924 |
|
|
Mar 24 01:09:08 PM PDT 24 |
Mar 24 01:09:39 PM PDT 24 |
12661399849 ps |
| T642 |
/workspace/coverage/default/35.rom_ctrl_smoke.223551590 |
|
|
Mar 24 01:08:31 PM PDT 24 |
Mar 24 01:09:06 PM PDT 24 |
19259745739 ps |
| T643 |
/workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2440109681 |
|
|
Mar 24 12:57:02 PM PDT 24 |
Mar 24 12:57:18 PM PDT 24 |
1901821695 ps |
| T644 |
/workspace/coverage/default/45.rom_ctrl_alert_test.340570864 |
|
|
Mar 24 12:58:35 PM PDT 24 |
Mar 24 12:58:50 PM PDT 24 |
1822465058 ps |
| T44 |
/workspace/coverage/default/2.rom_ctrl_sec_cm.2252233464 |
|
|
Mar 24 01:07:53 PM PDT 24 |
Mar 24 01:08:47 PM PDT 24 |
4306139200 ps |
| T645 |
/workspace/coverage/default/12.rom_ctrl_stress_all.385569128 |
|
|
Mar 24 12:57:15 PM PDT 24 |
Mar 24 12:57:53 PM PDT 24 |
9011640738 ps |
| T646 |
/workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3010062579 |
|
|
Mar 24 01:08:10 PM PDT 24 |
Mar 24 01:08:16 PM PDT 24 |
197154326 ps |
| T647 |
/workspace/coverage/default/41.rom_ctrl_smoke.1361076180 |
|
|
Mar 24 01:08:55 PM PDT 24 |
Mar 24 01:09:20 PM PDT 24 |
2834901734 ps |
| T20 |
/workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1389299415 |
|
|
Mar 24 01:08:43 PM PDT 24 |
Mar 24 02:07:21 PM PDT 24 |
46228936931 ps |
| T648 |
/workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2251208469 |
|
|
Mar 24 12:58:40 PM PDT 24 |
Mar 24 01:00:47 PM PDT 24 |
18811962079 ps |
| T649 |
/workspace/coverage/default/13.rom_ctrl_stress_all.4044802705 |
|
|
Mar 24 12:57:18 PM PDT 24 |
Mar 24 12:58:25 PM PDT 24 |
76197902943 ps |
| T650 |
/workspace/coverage/default/35.rom_ctrl_max_throughput_chk.987525873 |
|
|
Mar 24 01:08:32 PM PDT 24 |
Mar 24 01:08:46 PM PDT 24 |
5669124596 ps |
| T651 |
/workspace/coverage/default/25.rom_ctrl_kmac_err_chk.521818824 |
|
|
Mar 24 01:08:28 PM PDT 24 |
Mar 24 01:08:46 PM PDT 24 |
5127821316 ps |
| T652 |
/workspace/coverage/default/39.rom_ctrl_kmac_err_chk.89626655 |
|
|
Mar 24 01:08:53 PM PDT 24 |
Mar 24 01:09:26 PM PDT 24 |
19703914027 ps |
| T653 |
/workspace/coverage/default/43.rom_ctrl_smoke.4185990967 |
|
|
Mar 24 01:09:00 PM PDT 24 |
Mar 24 01:09:19 PM PDT 24 |
4016627723 ps |
| T654 |
/workspace/coverage/default/49.rom_ctrl_alert_test.983521555 |
|
|
Mar 24 01:09:15 PM PDT 24 |
Mar 24 01:09:25 PM PDT 24 |
3379867704 ps |
| T655 |
/workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3372130617 |
|
|
Mar 24 12:57:23 PM PDT 24 |
Mar 24 01:04:06 PM PDT 24 |
165818815872 ps |
| T656 |
/workspace/coverage/default/32.rom_ctrl_max_throughput_chk.663886602 |
|
|
Mar 24 12:58:06 PM PDT 24 |
Mar 24 12:58:13 PM PDT 24 |
469281667 ps |
| T657 |
/workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2402891816 |
|
|
Mar 24 12:57:23 PM PDT 24 |
Mar 24 01:01:07 PM PDT 24 |
9270147728 ps |
| T658 |
/workspace/coverage/default/17.rom_ctrl_stress_all.1205242819 |
|
|
Mar 24 01:08:17 PM PDT 24 |
Mar 24 01:09:02 PM PDT 24 |
11870442620 ps |
| T659 |
/workspace/coverage/default/44.rom_ctrl_smoke.2373369825 |
|
|
Mar 24 01:09:00 PM PDT 24 |
Mar 24 01:09:10 PM PDT 24 |
354555385 ps |
| T660 |
/workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1562147332 |
|
|
Mar 24 01:09:09 PM PDT 24 |
Mar 24 01:09:21 PM PDT 24 |
1138897528 ps |
| T661 |
/workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3937647877 |
|
|
Mar 24 01:08:22 PM PDT 24 |
Mar 24 01:08:54 PM PDT 24 |
7035608414 ps |
| T45 |
/workspace/coverage/default/4.rom_ctrl_sec_cm.967808453 |
|
|
Mar 24 12:57:05 PM PDT 24 |
Mar 24 12:58:01 PM PDT 24 |
669611797 ps |
| T662 |
/workspace/coverage/default/44.rom_ctrl_kmac_err_chk.245790241 |
|
|
Mar 24 12:58:27 PM PDT 24 |
Mar 24 12:58:51 PM PDT 24 |
2849311460 ps |
| T663 |
/workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3670916902 |
|
|
Mar 24 01:09:09 PM PDT 24 |
Mar 24 01:09:23 PM PDT 24 |
2826996301 ps |
| T664 |
/workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2607145 |
|
|
Mar 24 01:08:32 PM PDT 24 |
Mar 24 01:08:50 PM PDT 24 |
1865981195 ps |
| T665 |
/workspace/coverage/default/11.rom_ctrl_stress_all.293275073 |
|
|
Mar 24 01:08:14 PM PDT 24 |
Mar 24 01:08:42 PM PDT 24 |
913881200 ps |
| T666 |
/workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2042809198 |
|
|
Mar 24 01:08:59 PM PDT 24 |
Mar 24 01:09:25 PM PDT 24 |
2544182226 ps |
| T667 |
/workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2366247703 |
|
|
Mar 24 01:09:05 PM PDT 24 |
Mar 24 01:09:27 PM PDT 24 |
1859287652 ps |
| T668 |
/workspace/coverage/default/28.rom_ctrl_kmac_err_chk.632904713 |
|
|
Mar 24 12:57:57 PM PDT 24 |
Mar 24 12:58:09 PM PDT 24 |
1381317394 ps |
| T669 |
/workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.116705234 |
|
|
Mar 24 12:58:35 PM PDT 24 |
Mar 24 01:00:31 PM PDT 24 |
23779976129 ps |
| T670 |
/workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4069970582 |
|
|
Mar 24 01:08:46 PM PDT 24 |
Mar 24 02:08:18 PM PDT 24 |
95683303949 ps |
| T671 |
/workspace/coverage/default/10.rom_ctrl_stress_all.1768088538 |
|
|
Mar 24 01:08:10 PM PDT 24 |
Mar 24 01:08:59 PM PDT 24 |
7181754139 ps |
| T672 |
/workspace/coverage/default/0.rom_ctrl_kmac_err_chk.277866857 |
|
|
Mar 24 01:07:53 PM PDT 24 |
Mar 24 01:08:03 PM PDT 24 |
665101372 ps |
| T673 |
/workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1463887041 |
|
|
Mar 24 12:58:29 PM PDT 24 |
Mar 24 01:05:19 PM PDT 24 |
39923112455 ps |
| T674 |
/workspace/coverage/default/5.rom_ctrl_smoke.71872240 |
|
|
Mar 24 12:57:07 PM PDT 24 |
Mar 24 12:57:35 PM PDT 24 |
11724974257 ps |
| T675 |
/workspace/coverage/default/22.rom_ctrl_alert_test.124052651 |
|
|
Mar 24 12:57:43 PM PDT 24 |
Mar 24 12:57:54 PM PDT 24 |
1251809505 ps |
| T676 |
/workspace/coverage/default/8.rom_ctrl_stress_all.598641848 |
|
|
Mar 24 12:57:09 PM PDT 24 |
Mar 24 12:57:34 PM PDT 24 |
1472299317 ps |
| T677 |
/workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.674409994 |
|
|
Mar 24 12:58:21 PM PDT 24 |
Mar 24 01:02:20 PM PDT 24 |
83448649249 ps |
| T678 |
/workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4178332080 |
|
|
Mar 24 12:57:40 PM PDT 24 |
Mar 24 01:01:36 PM PDT 24 |
43590789019 ps |
| T679 |
/workspace/coverage/default/1.rom_ctrl_stress_all.360416692 |
|
|
Mar 24 01:07:53 PM PDT 24 |
Mar 24 01:08:09 PM PDT 24 |
4580094149 ps |
| T72 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.605493878 |
|
|
Mar 24 12:48:33 PM PDT 24 |
Mar 24 12:49:21 PM PDT 24 |
2314611065 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2741916405 |
|
|
Mar 24 12:47:55 PM PDT 24 |
Mar 24 12:48:06 PM PDT 24 |
2008397829 ps |
| T76 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1063577635 |
|
|
Mar 24 12:48:21 PM PDT 24 |
Mar 24 12:48:25 PM PDT 24 |
439153288 ps |
| T680 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4238733873 |
|
|
Mar 24 12:48:32 PM PDT 24 |
Mar 24 12:48:50 PM PDT 24 |
3285093243 ps |
| T109 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2394885831 |
|
|
Mar 24 12:48:15 PM PDT 24 |
Mar 24 12:48:23 PM PDT 24 |
630630125 ps |
| T110 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.651750349 |
|
|
Mar 24 12:47:47 PM PDT 24 |
Mar 24 12:48:14 PM PDT 24 |
558773851 ps |
| T681 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2963867973 |
|
|
Mar 24 12:47:56 PM PDT 24 |
Mar 24 12:48:11 PM PDT 24 |
3779697354 ps |
| T682 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4284032 |
|
|
Mar 24 12:48:15 PM PDT 24 |
Mar 24 12:48:22 PM PDT 24 |
372426169 ps |
| T683 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1907612740 |
|
|
Mar 24 12:48:15 PM PDT 24 |
Mar 24 12:48:24 PM PDT 24 |
206641634 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3218907456 |
|
|
Mar 24 12:47:48 PM PDT 24 |
Mar 24 12:48:34 PM PDT 24 |
1895322341 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3470415335 |
|
|
Mar 24 12:47:55 PM PDT 24 |
Mar 24 12:49:13 PM PDT 24 |
7170395106 ps |
| T79 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3094209076 |
|
|
Mar 24 12:47:48 PM PDT 24 |
Mar 24 12:47:52 PM PDT 24 |
175429346 ps |
| T684 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.157378800 |
|
|
Mar 24 12:47:48 PM PDT 24 |
Mar 24 12:47:56 PM PDT 24 |
567914859 ps |
| T116 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4056271215 |
|
|
Mar 24 12:48:23 PM PDT 24 |
Mar 24 12:48:31 PM PDT 24 |
1515732677 ps |
| T111 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4089132738 |
|
|
Mar 24 12:47:44 PM PDT 24 |
Mar 24 12:47:48 PM PDT 24 |
1657662460 ps |
| T117 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4166968560 |
|
|
Mar 24 12:47:44 PM PDT 24 |
Mar 24 12:47:51 PM PDT 24 |
565794753 ps |
| T118 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2383726789 |
|
|
Mar 24 12:48:34 PM PDT 24 |
Mar 24 12:48:39 PM PDT 24 |
251509323 ps |
| T122 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1436532716 |
|
|
Mar 24 12:48:02 PM PDT 24 |
Mar 24 12:49:17 PM PDT 24 |
3046078625 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3603593177 |
|
|
Mar 24 12:47:39 PM PDT 24 |
Mar 24 12:47:50 PM PDT 24 |
10224746547 ps |
| T685 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.653717780 |
|
|
Mar 24 12:48:15 PM PDT 24 |
Mar 24 12:48:29 PM PDT 24 |
5119145374 ps |
| T686 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3301174945 |
|
|
Mar 24 12:48:15 PM PDT 24 |
Mar 24 12:48:30 PM PDT 24 |
1831073250 ps |
| T112 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.448717974 |
|
|
Mar 24 12:48:15 PM PDT 24 |
Mar 24 12:48:20 PM PDT 24 |
89012083 ps |
| T81 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.441021274 |
|
|
Mar 24 12:47:55 PM PDT 24 |
Mar 24 12:49:26 PM PDT 24 |
193291343482 ps |
| T113 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2512652632 |
|
|
Mar 24 12:47:51 PM PDT 24 |
Mar 24 12:48:04 PM PDT 24 |
2190935911 ps |
| T687 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2311787275 |
|
|
Mar 24 12:47:47 PM PDT 24 |
Mar 24 12:47:57 PM PDT 24 |
200492265 ps |
| T688 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4267923392 |
|
|
Mar 24 12:47:50 PM PDT 24 |
Mar 24 12:47:58 PM PDT 24 |
663241786 ps |
| T82 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.933500230 |
|
|
Mar 24 12:47:51 PM PDT 24 |
Mar 24 12:48:10 PM PDT 24 |
380661454 ps |
| T83 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.447399667 |
|
|
Mar 24 12:48:17 PM PDT 24 |
Mar 24 12:49:23 PM PDT 24 |
17533132431 ps |
| T126 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4234886023 |
|
|
Mar 24 12:47:51 PM PDT 24 |
Mar 24 12:48:30 PM PDT 24 |
1050872718 ps |
| T689 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3139916524 |
|
|
Mar 24 12:47:51 PM PDT 24 |
Mar 24 12:48:02 PM PDT 24 |
416225478 ps |
| T690 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3879126130 |
|
|
Mar 24 12:48:10 PM PDT 24 |
Mar 24 12:48:21 PM PDT 24 |
4641686809 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3085719285 |
|
|
Mar 24 12:47:38 PM PDT 24 |
Mar 24 12:48:57 PM PDT 24 |
2242666144 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3460594501 |
|
|
Mar 24 12:48:16 PM PDT 24 |
Mar 24 12:49:35 PM PDT 24 |
9435211158 ps |
| T691 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2744562232 |
|
|
Mar 24 12:47:44 PM PDT 24 |
Mar 24 12:47:54 PM PDT 24 |
899634730 ps |
| T692 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3158633283 |
|
|
Mar 24 12:48:06 PM PDT 24 |
Mar 24 12:48:16 PM PDT 24 |
4110941010 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2410545054 |
|
|
Mar 24 12:47:41 PM PDT 24 |
Mar 24 12:48:58 PM PDT 24 |
4591045902 ps |
| T693 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3225140918 |
|
|
Mar 24 12:48:20 PM PDT 24 |
Mar 24 12:49:01 PM PDT 24 |
4858570905 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1878041056 |
|
|
Mar 24 12:48:16 PM PDT 24 |
Mar 24 12:48:21 PM PDT 24 |
396340018 ps |
| T694 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1071955062 |
|
|
Mar 24 12:47:57 PM PDT 24 |
Mar 24 12:48:12 PM PDT 24 |
6220195190 ps |
| T695 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.92679291 |
|
|
Mar 24 12:48:04 PM PDT 24 |
Mar 24 12:49:01 PM PDT 24 |
17855962692 ps |
| T696 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3404542567 |
|
|
Mar 24 12:48:16 PM PDT 24 |
Mar 24 12:48:21 PM PDT 24 |
142904362 ps |
| T697 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.894834379 |
|
|
Mar 24 12:48:11 PM PDT 24 |
Mar 24 12:48:27 PM PDT 24 |
5262008286 ps |
| T698 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.390576302 |
|
|
Mar 24 12:47:42 PM PDT 24 |
Mar 24 12:47:59 PM PDT 24 |
3053626745 ps |
| T699 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.875393823 |
|
|
Mar 24 12:48:17 PM PDT 24 |
Mar 24 12:48:24 PM PDT 24 |
1617746475 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.780741827 |
|
|
Mar 24 12:48:16 PM PDT 24 |
Mar 24 12:48:30 PM PDT 24 |
7238198352 ps |
| T84 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1508282172 |
|
|
Mar 24 12:47:51 PM PDT 24 |
Mar 24 12:47:59 PM PDT 24 |
649393915 ps |
| T85 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3386480047 |
|
|
Mar 24 12:48:23 PM PDT 24 |
Mar 24 12:48:31 PM PDT 24 |
689880409 ps |
| T700 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3356864555 |
|
|
Mar 24 12:47:54 PM PDT 24 |
Mar 24 12:48:05 PM PDT 24 |
10633440901 ps |
| T86 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.253891510 |
|
|
Mar 24 12:48:01 PM PDT 24 |
Mar 24 12:48:09 PM PDT 24 |
1894125844 ps |
| T701 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.301310602 |
|
|
Mar 24 12:47:57 PM PDT 24 |
Mar 24 12:48:04 PM PDT 24 |
708159085 ps |
| T702 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3541913591 |
|
|
Mar 24 12:48:28 PM PDT 24 |
Mar 24 12:48:33 PM PDT 24 |
1088505857 ps |
| T703 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2758490121 |
|
|
Mar 24 12:47:37 PM PDT 24 |
Mar 24 12:47:54 PM PDT 24 |
6192419401 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1277686021 |
|
|
Mar 24 12:48:09 PM PDT 24 |
Mar 24 12:48:23 PM PDT 24 |
1635651748 ps |
| T132 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.389893634 |
|
|
Mar 24 12:48:04 PM PDT 24 |
Mar 24 12:49:16 PM PDT 24 |
1961261706 ps |
| T90 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1452850663 |
|
|
Mar 24 12:47:39 PM PDT 24 |
Mar 24 12:48:44 PM PDT 24 |
54129417435 ps |
| T704 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.338295187 |
|
|
Mar 24 12:48:27 PM PDT 24 |
Mar 24 12:49:24 PM PDT 24 |
62699119678 ps |
| T705 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2719855734 |
|
|
Mar 24 12:48:16 PM PDT 24 |
Mar 24 12:48:25 PM PDT 24 |
5668918094 ps |
| T91 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2194936296 |
|
|
Mar 24 12:47:42 PM PDT 24 |
Mar 24 12:47:47 PM PDT 24 |
332885944 ps |
| T706 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2263872573 |
|
|
Mar 24 12:48:12 PM PDT 24 |
Mar 24 12:48:32 PM PDT 24 |
10348759922 ps |
| T123 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3405168126 |
|
|
Mar 24 12:48:31 PM PDT 24 |
Mar 24 12:49:50 PM PDT 24 |
2321117572 ps |
| T707 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.330831953 |
|
|
Mar 24 12:47:44 PM PDT 24 |
Mar 24 12:47:51 PM PDT 24 |
1317012966 ps |
| T708 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2255127295 |
|
|
Mar 24 12:48:03 PM PDT 24 |
Mar 24 12:48:14 PM PDT 24 |
710355756 ps |
| T709 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.572153893 |
|
|
Mar 24 12:47:50 PM PDT 24 |
Mar 24 12:47:58 PM PDT 24 |
333066744 ps |
| T710 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.323625951 |
|
|
Mar 24 12:48:10 PM PDT 24 |
Mar 24 12:48:19 PM PDT 24 |
209297142 ps |
| T711 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1635868155 |
|
|
Mar 24 12:47:43 PM PDT 24 |
Mar 24 12:49:01 PM PDT 24 |
1904094943 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4148827263 |
|
|
Mar 24 12:48:01 PM PDT 24 |
Mar 24 12:48:45 PM PDT 24 |
10446468497 ps |
| T712 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.402592461 |
|
|
Mar 24 12:48:09 PM PDT 24 |
Mar 24 12:48:21 PM PDT 24 |
9079051946 ps |
| T713 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2013629557 |
|
|
Mar 24 12:47:42 PM PDT 24 |
Mar 24 12:47:47 PM PDT 24 |
509720816 ps |
| T714 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2512208054 |
|
|
Mar 24 12:47:56 PM PDT 24 |
Mar 24 12:48:12 PM PDT 24 |
3906261595 ps |
| T715 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1211134786 |
|
|
Mar 24 12:47:45 PM PDT 24 |
Mar 24 12:47:58 PM PDT 24 |
1316553753 ps |
| T716 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.24590151 |
|
|
Mar 24 12:47:47 PM PDT 24 |
Mar 24 12:47:55 PM PDT 24 |
492686879 ps |
| T717 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3151875006 |
|
|
Mar 24 12:47:40 PM PDT 24 |
Mar 24 12:47:56 PM PDT 24 |
7791897677 ps |
| T718 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1366841825 |
|
|
Mar 24 12:48:09 PM PDT 24 |
Mar 24 12:48:23 PM PDT 24 |
1433205570 ps |
| T719 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.886610218 |
|
|
Mar 24 12:48:18 PM PDT 24 |
Mar 24 12:48:26 PM PDT 24 |
434436070 ps |
| T720 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2447560295 |
|
|
Mar 24 12:48:30 PM PDT 24 |
Mar 24 12:48:41 PM PDT 24 |
4237432391 ps |
| T721 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.760863360 |
|
|
Mar 24 12:48:02 PM PDT 24 |
Mar 24 12:48:16 PM PDT 24 |
6006676516 ps |
| T722 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3719069215 |
|
|
Mar 24 12:47:38 PM PDT 24 |
Mar 24 12:47:45 PM PDT 24 |
175480198 ps |
| T723 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1728737665 |
|
|
Mar 24 12:48:14 PM PDT 24 |
Mar 24 12:48:23 PM PDT 24 |
5089831013 ps |
| T724 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2571486231 |
|
|
Mar 24 12:48:17 PM PDT 24 |
Mar 24 12:48:21 PM PDT 24 |
555084755 ps |
| T133 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1479511430 |
|
|
Mar 24 12:47:55 PM PDT 24 |
Mar 24 12:48:37 PM PDT 24 |
1229399402 ps |
| T129 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.838287495 |
|
|
Mar 24 12:48:32 PM PDT 24 |
Mar 24 12:49:49 PM PDT 24 |
3347084006 ps |
| T725 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.110579614 |
|
|
Mar 24 12:47:50 PM PDT 24 |
Mar 24 12:48:06 PM PDT 24 |
1858926256 ps |
| T726 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4207641377 |
|
|
Mar 24 12:48:34 PM PDT 24 |
Mar 24 12:49:14 PM PDT 24 |
588834228 ps |
| T727 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.440295913 |
|
|
Mar 24 12:48:06 PM PDT 24 |
Mar 24 12:49:09 PM PDT 24 |
7918033391 ps |
| T728 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1834179537 |
|
|
Mar 24 12:48:32 PM PDT 24 |
Mar 24 12:48:49 PM PDT 24 |
1521562793 ps |
| T729 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.527580452 |
|
|
Mar 24 12:48:25 PM PDT 24 |
Mar 24 12:48:35 PM PDT 24 |
1896342947 ps |
| T730 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3164443065 |
|
|
Mar 24 12:47:46 PM PDT 24 |
Mar 24 12:48:03 PM PDT 24 |
15473112275 ps |
| T731 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.905587652 |
|
|
Mar 24 12:47:53 PM PDT 24 |
Mar 24 12:47:57 PM PDT 24 |
91066906 ps |
| T732 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2982216897 |
|
|
Mar 24 12:47:43 PM PDT 24 |
Mar 24 12:49:14 PM PDT 24 |
56312625264 ps |
| T733 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.628325212 |
|
|
Mar 24 12:48:13 PM PDT 24 |
Mar 24 12:48:18 PM PDT 24 |
1382890193 ps |
| T130 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2653182596 |
|
|
Mar 24 12:47:59 PM PDT 24 |
Mar 24 12:49:19 PM PDT 24 |
2158572011 ps |
| T734 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.528058766 |
|
|
Mar 24 12:47:44 PM PDT 24 |
Mar 24 12:47:53 PM PDT 24 |
756193975 ps |
| T735 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1939398308 |
|
|
Mar 24 12:48:32 PM PDT 24 |
Mar 24 12:48:37 PM PDT 24 |
164784912 ps |
| T736 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3084420963 |
|
|
Mar 24 12:48:25 PM PDT 24 |
Mar 24 12:48:33 PM PDT 24 |
2296265502 ps |
| T737 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3159956973 |
|
|
Mar 24 12:48:25 PM PDT 24 |
Mar 24 12:48:30 PM PDT 24 |
259252157 ps |
| T93 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2582583335 |
|
|
Mar 24 12:48:02 PM PDT 24 |
Mar 24 12:49:12 PM PDT 24 |
11125598946 ps |
| T738 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2745670961 |
|
|
Mar 24 12:47:37 PM PDT 24 |
Mar 24 12:47:49 PM PDT 24 |
1110700224 ps |
| T739 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.942799945 |
|
|
Mar 24 12:47:38 PM PDT 24 |
Mar 24 12:47:52 PM PDT 24 |
3493240667 ps |
| T740 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3528937079 |
|
|
Mar 24 12:47:39 PM PDT 24 |
Mar 24 12:47:51 PM PDT 24 |
9087837776 ps |
| T741 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.95168098 |
|
|
Mar 24 12:48:15 PM PDT 24 |
Mar 24 12:48:25 PM PDT 24 |
3922167102 ps |
| T742 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1049375119 |
|
|
Mar 24 12:47:52 PM PDT 24 |
Mar 24 12:48:06 PM PDT 24 |
7272088673 ps |
| T743 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3980004342 |
|
|
Mar 24 12:48:09 PM PDT 24 |
Mar 24 12:48:25 PM PDT 24 |
8496240547 ps |
| T744 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1472748083 |
|
|
Mar 24 12:48:21 PM PDT 24 |
Mar 24 12:48:37 PM PDT 24 |
8964480462 ps |
| T745 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.324998798 |
|
|
Mar 24 12:48:25 PM PDT 24 |
Mar 24 12:48:32 PM PDT 24 |
319951769 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3703688328 |
|
|
Mar 24 12:47:44 PM PDT 24 |
Mar 24 12:48:12 PM PDT 24 |
1105560782 ps |
| T746 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1512907939 |
|
|
Mar 24 12:48:04 PM PDT 24 |
Mar 24 12:48:46 PM PDT 24 |
1972844935 ps |
| T747 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1669096228 |
|
|
Mar 24 12:47:44 PM PDT 24 |
Mar 24 12:47:49 PM PDT 24 |
347609955 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1570437975 |
|
|
Mar 24 12:48:11 PM PDT 24 |
Mar 24 12:49:44 PM PDT 24 |
12097244010 ps |
| T748 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3107641654 |
|
|
Mar 24 12:47:55 PM PDT 24 |
Mar 24 12:48:13 PM PDT 24 |
6340746243 ps |
| T749 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2104801293 |
|
|
Mar 24 12:48:30 PM PDT 24 |
Mar 24 12:48:45 PM PDT 24 |
3406998496 ps |
| T750 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1579958920 |
|
|
Mar 24 12:47:37 PM PDT 24 |
Mar 24 12:47:53 PM PDT 24 |
1970644183 ps |
| T751 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3934066005 |
|
|
Mar 24 12:47:42 PM PDT 24 |
Mar 24 12:47:55 PM PDT 24 |
3172260097 ps |
| T752 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3225462587 |
|
|
Mar 24 12:48:32 PM PDT 24 |
Mar 24 12:48:38 PM PDT 24 |
97162179 ps |
| T753 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.156393601 |
|
|
Mar 24 12:48:31 PM PDT 24 |
Mar 24 12:48:44 PM PDT 24 |
1061286471 ps |
| T754 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1470703994 |
|
|
Mar 24 12:47:58 PM PDT 24 |
Mar 24 12:48:10 PM PDT 24 |
4416250394 ps |
| T131 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.545533926 |
|
|
Mar 24 12:48:16 PM PDT 24 |
Mar 24 12:49:33 PM PDT 24 |
1752725568 ps |
| T755 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.37460169 |
|
|
Mar 24 12:48:10 PM PDT 24 |
Mar 24 12:48:25 PM PDT 24 |
8226761940 ps |
| T756 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.954290825 |
|
|
Mar 24 12:48:11 PM PDT 24 |
Mar 24 12:48:49 PM PDT 24 |
10138265479 ps |