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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 96.96 93.25 97.88 100.00 99.01 98.04 99.07


Total test records in report: 922
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T757 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.950933016 Mar 24 12:48:20 PM PDT 24 Mar 24 12:49:28 PM PDT 24 934049196 ps
T758 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1245068623 Mar 24 12:48:13 PM PDT 24 Mar 24 12:48:19 PM PDT 24 273349262 ps
T759 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3584207986 Mar 24 12:48:04 PM PDT 24 Mar 24 12:48:14 PM PDT 24 868305790 ps
T96 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1665762312 Mar 24 12:48:27 PM PDT 24 Mar 24 12:48:54 PM PDT 24 2380396839 ps
T760 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1043108191 Mar 24 12:48:10 PM PDT 24 Mar 24 12:48:26 PM PDT 24 9352500425 ps
T761 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.963812494 Mar 24 12:47:37 PM PDT 24 Mar 24 12:47:51 PM PDT 24 1182881232 ps
T762 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3063798017 Mar 24 12:47:42 PM PDT 24 Mar 24 12:47:55 PM PDT 24 1352250719 ps
T763 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3016005786 Mar 24 12:48:31 PM PDT 24 Mar 24 12:48:59 PM PDT 24 2229893217 ps
T124 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2093363743 Mar 24 12:48:28 PM PDT 24 Mar 24 12:49:45 PM PDT 24 8087495442 ps
T764 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3421727217 Mar 24 12:48:19 PM PDT 24 Mar 24 12:48:32 PM PDT 24 2967951765 ps
T765 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.564894578 Mar 24 12:47:57 PM PDT 24 Mar 24 12:48:42 PM PDT 24 15533537055 ps
T766 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4010294567 Mar 24 12:48:16 PM PDT 24 Mar 24 12:49:32 PM PDT 24 3257336759 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3077819959 Mar 24 12:48:11 PM PDT 24 Mar 24 12:48:25 PM PDT 24 4590954092 ps
T767 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3827565435 Mar 24 12:48:17 PM PDT 24 Mar 24 12:49:05 PM PDT 24 19166989179 ps
T768 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.838404176 Mar 24 12:48:32 PM PDT 24 Mar 24 12:48:37 PM PDT 24 90943966 ps
T769 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2351966964 Mar 24 12:48:32 PM PDT 24 Mar 24 12:49:57 PM PDT 24 9499483665 ps
T770 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1433847123 Mar 24 12:48:28 PM PDT 24 Mar 24 12:48:42 PM PDT 24 4431611848 ps
T771 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3534886065 Mar 24 12:47:51 PM PDT 24 Mar 24 12:48:03 PM PDT 24 1203392872 ps
T772 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2329682544 Mar 24 12:47:57 PM PDT 24 Mar 24 12:49:13 PM PDT 24 5841071859 ps
T125 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1814827129 Mar 24 12:48:16 PM PDT 24 Mar 24 12:48:58 PM PDT 24 985333911 ps
T773 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1423911888 Mar 24 12:48:27 PM PDT 24 Mar 24 12:49:37 PM PDT 24 655355395 ps
T774 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2519746007 Mar 24 12:48:02 PM PDT 24 Mar 24 12:48:10 PM PDT 24 1100225854 ps
T775 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1661026613 Mar 24 12:48:04 PM PDT 24 Mar 24 12:48:08 PM PDT 24 94707293 ps
T776 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2515115214 Mar 24 12:47:56 PM PDT 24 Mar 24 12:48:07 PM PDT 24 1207662085 ps
T777 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3445492205 Mar 24 12:48:10 PM PDT 24 Mar 24 12:48:26 PM PDT 24 37712802233 ps
T778 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1642353896 Mar 24 12:48:32 PM PDT 24 Mar 24 12:49:13 PM PDT 24 7549559938 ps
T779 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2252759692 Mar 24 12:48:12 PM PDT 24 Mar 24 12:48:25 PM PDT 24 1121471876 ps
T780 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.80008929 Mar 24 12:48:03 PM PDT 24 Mar 24 12:49:20 PM PDT 24 1169336337 ps
T781 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1055503721 Mar 24 12:48:22 PM PDT 24 Mar 24 12:50:08 PM PDT 24 51241707138 ps
T782 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.98659454 Mar 24 12:48:04 PM PDT 24 Mar 24 12:48:20 PM PDT 24 1892677454 ps
T783 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.79101876 Mar 24 12:48:21 PM PDT 24 Mar 24 12:49:04 PM PDT 24 5137154781 ps
T784 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.955944592 Mar 24 12:48:28 PM PDT 24 Mar 24 12:48:41 PM PDT 24 12325355696 ps
T785 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2109253624 Mar 24 12:47:42 PM PDT 24 Mar 24 12:47:57 PM PDT 24 18551878326 ps
T786 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2965797789 Mar 24 12:47:52 PM PDT 24 Mar 24 12:49:25 PM PDT 24 46255219488 ps
T787 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.921748583 Mar 24 12:47:55 PM PDT 24 Mar 24 12:48:11 PM PDT 24 5286414968 ps
T788 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2763758771 Mar 24 12:48:09 PM PDT 24 Mar 24 12:48:20 PM PDT 24 1258351632 ps
T789 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1606711462 Mar 24 12:47:45 PM PDT 24 Mar 24 12:47:49 PM PDT 24 89093178 ps
T790 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.684536893 Mar 24 12:48:04 PM PDT 24 Mar 24 12:48:09 PM PDT 24 86493763 ps
T791 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4244797135 Mar 24 12:47:55 PM PDT 24 Mar 24 12:48:11 PM PDT 24 29599293129 ps
T98 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.905454698 Mar 24 12:48:01 PM PDT 24 Mar 24 12:48:47 PM PDT 24 25285569641 ps
T134 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3068084770 Mar 24 12:47:41 PM PDT 24 Mar 24 12:49:00 PM PDT 24 4404933209 ps
T792 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.201522497 Mar 24 12:47:51 PM PDT 24 Mar 24 12:47:55 PM PDT 24 86516284 ps
T793 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2298120150 Mar 24 12:48:17 PM PDT 24 Mar 24 12:48:24 PM PDT 24 347543086 ps
T794 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1854113286 Mar 24 12:48:29 PM PDT 24 Mar 24 12:48:33 PM PDT 24 85713369 ps
T795 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.108988008 Mar 24 12:47:50 PM PDT 24 Mar 24 12:47:57 PM PDT 24 508854782 ps
T796 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1878381476 Mar 24 12:47:42 PM PDT 24 Mar 24 12:48:48 PM PDT 24 12134684825 ps
T797 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2575185321 Mar 24 12:47:55 PM PDT 24 Mar 24 12:47:59 PM PDT 24 168093583 ps
T798 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.672071681 Mar 24 12:47:43 PM PDT 24 Mar 24 12:47:51 PM PDT 24 533952291 ps
T799 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2549560533 Mar 24 12:48:03 PM PDT 24 Mar 24 12:48:20 PM PDT 24 1909836327 ps
T800 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.793314995 Mar 24 12:47:49 PM PDT 24 Mar 24 12:47:55 PM PDT 24 342120080 ps
T801 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2947332006 Mar 24 12:48:32 PM PDT 24 Mar 24 12:48:41 PM PDT 24 2854134751 ps
T802 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2559444103 Mar 24 12:48:25 PM PDT 24 Mar 24 12:48:35 PM PDT 24 554839161 ps
T803 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4248184387 Mar 24 12:47:55 PM PDT 24 Mar 24 12:48:02 PM PDT 24 85748013 ps
T804 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1796534385 Mar 24 12:47:48 PM PDT 24 Mar 24 12:47:54 PM PDT 24 452275815 ps
T805 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2090749737 Mar 24 12:48:19 PM PDT 24 Mar 24 12:48:27 PM PDT 24 167202643 ps
T806 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3747428412 Mar 24 12:47:54 PM PDT 24 Mar 24 12:48:09 PM PDT 24 1744191945 ps
T807 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1221534592 Mar 24 12:47:57 PM PDT 24 Mar 24 12:48:07 PM PDT 24 5110242830 ps
T808 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3517803491 Mar 24 12:47:57 PM PDT 24 Mar 24 12:48:11 PM PDT 24 1597495029 ps
T809 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.676777707 Mar 24 12:48:09 PM PDT 24 Mar 24 12:48:13 PM PDT 24 89007936 ps
T810 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3871937286 Mar 24 12:47:54 PM PDT 24 Mar 24 12:48:13 PM PDT 24 13444054813 ps
T811 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1914782274 Mar 24 12:47:50 PM PDT 24 Mar 24 12:47:54 PM PDT 24 637439449 ps
T812 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1053369142 Mar 24 12:48:32 PM PDT 24 Mar 24 12:48:46 PM PDT 24 16255308022 ps
T813 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3064313345 Mar 24 12:48:30 PM PDT 24 Mar 24 12:48:58 PM PDT 24 2224018275 ps
T814 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3000587383 Mar 24 12:48:19 PM PDT 24 Mar 24 12:48:56 PM PDT 24 252266246 ps
T815 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.87687488 Mar 24 12:48:32 PM PDT 24 Mar 24 12:48:39 PM PDT 24 1807015864 ps
T816 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1202156199 Mar 24 12:48:16 PM PDT 24 Mar 24 12:48:25 PM PDT 24 721381671 ps
T817 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1588351200 Mar 24 12:48:02 PM PDT 24 Mar 24 12:48:07 PM PDT 24 332608025 ps
T818 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4083550085 Mar 24 12:48:31 PM PDT 24 Mar 24 12:49:46 PM PDT 24 1438937834 ps
T819 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3587908424 Mar 24 12:48:16 PM PDT 24 Mar 24 12:49:15 PM PDT 24 6965064460 ps
T820 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.190554884 Mar 24 12:47:41 PM PDT 24 Mar 24 12:47:53 PM PDT 24 1014105584 ps
T821 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3522660433 Mar 24 12:48:32 PM PDT 24 Mar 24 12:49:40 PM PDT 24 27699822046 ps
T822 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4121758549 Mar 24 12:48:10 PM PDT 24 Mar 24 12:48:52 PM PDT 24 8096547716 ps
T823 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3501322795 Mar 24 12:47:41 PM PDT 24 Mar 24 12:47:45 PM PDT 24 346413417 ps
T824 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3269116924 Mar 24 12:48:04 PM PDT 24 Mar 24 12:48:12 PM PDT 24 95988268 ps
T825 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1872323154 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:45 PM PDT 24 173357246 ps
T826 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2646349427 Mar 24 12:47:50 PM PDT 24 Mar 24 12:47:58 PM PDT 24 109930320 ps
T827 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3879809642 Mar 24 12:47:57 PM PDT 24 Mar 24 12:48:05 PM PDT 24 568015576 ps
T828 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1381695345 Mar 24 12:47:37 PM PDT 24 Mar 24 12:47:48 PM PDT 24 2100049165 ps
T829 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1616597664 Mar 24 12:47:56 PM PDT 24 Mar 24 12:48:02 PM PDT 24 346759859 ps
T830 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2436803382 Mar 24 12:48:30 PM PDT 24 Mar 24 12:48:35 PM PDT 24 88865963 ps
T831 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2683341141 Mar 24 12:48:15 PM PDT 24 Mar 24 12:49:31 PM PDT 24 17904028839 ps
T832 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.191265472 Mar 24 12:48:32 PM PDT 24 Mar 24 12:48:46 PM PDT 24 17324436592 ps
T833 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4113707444 Mar 24 12:48:08 PM PDT 24 Mar 24 12:48:12 PM PDT 24 90860802 ps
T834 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1896066972 Mar 24 12:48:15 PM PDT 24 Mar 24 12:49:25 PM PDT 24 1995665260 ps
T835 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3238910258 Mar 24 12:48:28 PM PDT 24 Mar 24 12:48:39 PM PDT 24 7099351797 ps
T836 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3552051210 Mar 24 12:48:03 PM PDT 24 Mar 24 12:48:17 PM PDT 24 1492050157 ps
T837 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1076780987 Mar 24 12:48:02 PM PDT 24 Mar 24 12:48:09 PM PDT 24 291769294 ps
T838 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3799369234 Mar 24 12:47:55 PM PDT 24 Mar 24 12:48:13 PM PDT 24 4500737462 ps
T839 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2997794005 Mar 24 12:48:01 PM PDT 24 Mar 24 12:48:16 PM PDT 24 1892652493 ps
T840 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2880107688 Mar 24 12:48:14 PM PDT 24 Mar 24 12:48:28 PM PDT 24 1834277302 ps
T841 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.673552460 Mar 24 12:48:12 PM PDT 24 Mar 24 12:48:25 PM PDT 24 1008656167 ps
T842 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3490674112 Mar 24 12:47:42 PM PDT 24 Mar 24 12:47:56 PM PDT 24 1259529379 ps
T843 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3843390157 Mar 24 12:48:03 PM PDT 24 Mar 24 12:49:38 PM PDT 24 11854575044 ps
T844 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1739117423 Mar 24 12:48:10 PM PDT 24 Mar 24 12:49:04 PM PDT 24 26330034010 ps
T845 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2242100926 Mar 24 12:48:14 PM PDT 24 Mar 24 12:49:31 PM PDT 24 34678994841 ps
T846 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3874043002 Mar 24 12:48:26 PM PDT 24 Mar 24 12:48:41 PM PDT 24 3132385758 ps
T847 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.909970160 Mar 24 12:48:20 PM PDT 24 Mar 24 12:48:24 PM PDT 24 157073037 ps
T848 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3478773015 Mar 24 12:48:11 PM PDT 24 Mar 24 12:48:16 PM PDT 24 171959876 ps
T849 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2176134262 Mar 24 12:47:42 PM PDT 24 Mar 24 12:47:50 PM PDT 24 964422733 ps
T850 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.321767649 Mar 24 12:48:02 PM PDT 24 Mar 24 12:48:13 PM PDT 24 4249616478 ps
T851 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2350818656 Mar 24 12:47:54 PM PDT 24 Mar 24 12:49:14 PM PDT 24 2274276472 ps
T852 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3571629568 Mar 24 12:48:05 PM PDT 24 Mar 24 12:49:17 PM PDT 24 7345371430 ps
T853 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3431767386 Mar 24 12:48:03 PM PDT 24 Mar 24 12:48:49 PM PDT 24 2043623464 ps
T854 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.217581661 Mar 24 12:48:05 PM PDT 24 Mar 24 12:48:17 PM PDT 24 675646891 ps
T855 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2431990660 Mar 24 12:48:16 PM PDT 24 Mar 24 12:48:33 PM PDT 24 4304276580 ps
T856 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.585275162 Mar 24 12:47:55 PM PDT 24 Mar 24 12:48:11 PM PDT 24 7943467717 ps
T857 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2725813959 Mar 24 12:47:57 PM PDT 24 Mar 24 12:48:05 PM PDT 24 2464669796 ps
T858 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.209690739 Mar 24 12:47:38 PM PDT 24 Mar 24 12:47:50 PM PDT 24 2770573517 ps
T859 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1170455474 Mar 24 12:48:00 PM PDT 24 Mar 24 12:48:38 PM PDT 24 5124880114 ps
T860 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4047150832 Mar 24 12:47:40 PM PDT 24 Mar 24 12:47:45 PM PDT 24 172599651 ps
T861 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.151774605 Mar 24 12:47:39 PM PDT 24 Mar 24 12:47:52 PM PDT 24 2966179131 ps
T862 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1820557444 Mar 24 12:47:36 PM PDT 24 Mar 24 12:47:40 PM PDT 24 87511003 ps
T863 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2537718023 Mar 24 12:47:49 PM PDT 24 Mar 24 12:48:51 PM PDT 24 7578101573 ps
T864 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2302368447 Mar 24 12:48:01 PM PDT 24 Mar 24 12:48:12 PM PDT 24 3065905970 ps
T865 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.675301778 Mar 24 12:48:13 PM PDT 24 Mar 24 12:48:21 PM PDT 24 346716818 ps
T866 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2960344567 Mar 24 12:47:48 PM PDT 24 Mar 24 12:47:57 PM PDT 24 842650814 ps
T867 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2595406810 Mar 24 12:47:38 PM PDT 24 Mar 24 12:47:57 PM PDT 24 379845327 ps
T868 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3558492105 Mar 24 12:48:31 PM PDT 24 Mar 24 12:48:44 PM PDT 24 1884841655 ps
T869 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3155590605 Mar 24 12:48:28 PM PDT 24 Mar 24 12:48:32 PM PDT 24 85485226 ps
T870 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1866029009 Mar 24 12:48:03 PM PDT 24 Mar 24 12:48:44 PM PDT 24 869329102 ps
T871 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2385984580 Mar 24 12:48:09 PM PDT 24 Mar 24 12:48:25 PM PDT 24 2023341866 ps
T872 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3056628974 Mar 24 12:48:03 PM PDT 24 Mar 24 12:48:08 PM PDT 24 87341762 ps
T873 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1154194816 Mar 24 12:48:18 PM PDT 24 Mar 24 12:48:32 PM PDT 24 4743873188 ps
T874 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1902047714 Mar 24 12:48:06 PM PDT 24 Mar 24 12:48:13 PM PDT 24 433666841 ps
T875 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1642460833 Mar 24 12:48:10 PM PDT 24 Mar 24 12:48:23 PM PDT 24 1502874224 ps
T876 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1018182269 Mar 24 12:48:12 PM PDT 24 Mar 24 12:48:24 PM PDT 24 1269700510 ps
T877 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2174810978 Mar 24 12:47:56 PM PDT 24 Mar 24 12:49:12 PM PDT 24 6343147621 ps
T878 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1082378013 Mar 24 12:47:45 PM PDT 24 Mar 24 12:47:59 PM PDT 24 19980932072 ps
T879 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2405244665 Mar 24 12:47:58 PM PDT 24 Mar 24 12:48:08 PM PDT 24 3760396706 ps
T880 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1590094538 Mar 24 12:48:03 PM PDT 24 Mar 24 12:48:24 PM PDT 24 2096366706 ps
T881 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2310532575 Mar 24 12:47:45 PM PDT 24 Mar 24 12:47:54 PM PDT 24 692647713 ps
T882 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2124310458 Mar 24 12:48:01 PM PDT 24 Mar 24 12:48:46 PM PDT 24 18537353285 ps
T883 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3990504093 Mar 24 12:48:24 PM PDT 24 Mar 24 12:49:07 PM PDT 24 2592241430 ps
T884 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1918082011 Mar 24 12:48:09 PM PDT 24 Mar 24 12:48:25 PM PDT 24 9136356476 ps
T885 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2769242578 Mar 24 12:47:42 PM PDT 24 Mar 24 12:48:20 PM PDT 24 4012197715 ps
T886 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2615828144 Mar 24 12:47:39 PM PDT 24 Mar 24 12:48:17 PM PDT 24 317595484 ps
T887 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3219620254 Mar 24 12:48:09 PM PDT 24 Mar 24 12:48:16 PM PDT 24 231635341 ps
T888 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4106918308 Mar 24 12:48:22 PM PDT 24 Mar 24 12:48:37 PM PDT 24 16001426774 ps
T889 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1698442086 Mar 24 12:48:02 PM PDT 24 Mar 24 12:48:19 PM PDT 24 7572239583 ps
T890 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3672881523 Mar 24 12:48:19 PM PDT 24 Mar 24 12:48:23 PM PDT 24 167912489 ps
T891 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1569671346 Mar 24 12:47:48 PM PDT 24 Mar 24 12:48:04 PM PDT 24 8847615230 ps
T892 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2666134572 Mar 24 12:48:12 PM PDT 24 Mar 24 12:48:17 PM PDT 24 520323984 ps
T893 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.923469757 Mar 24 12:47:49 PM PDT 24 Mar 24 12:47:57 PM PDT 24 5447356038 ps
T894 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2877922367 Mar 24 12:48:09 PM PDT 24 Mar 24 12:48:22 PM PDT 24 1689992037 ps
T895 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.373667688 Mar 24 12:47:55 PM PDT 24 Mar 24 12:48:01 PM PDT 24 215806460 ps
T896 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1407612391 Mar 24 12:47:59 PM PDT 24 Mar 24 12:48:04 PM PDT 24 89306169 ps
T897 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1449402148 Mar 24 12:48:20 PM PDT 24 Mar 24 12:48:39 PM PDT 24 1495463168 ps
T898 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3356891249 Mar 24 12:47:52 PM PDT 24 Mar 24 12:47:58 PM PDT 24 98546811 ps
T899 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1928083504 Mar 24 12:47:57 PM PDT 24 Mar 24 12:48:58 PM PDT 24 11844924215 ps
T900 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1722773656 Mar 24 12:48:03 PM PDT 24 Mar 24 12:48:18 PM PDT 24 6937826892 ps
T901 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3144496360 Mar 24 12:48:35 PM PDT 24 Mar 24 12:48:44 PM PDT 24 1672116766 ps
T902 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2247220246 Mar 24 12:47:45 PM PDT 24 Mar 24 12:48:02 PM PDT 24 5298308947 ps
T903 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.723238707 Mar 24 12:47:42 PM PDT 24 Mar 24 12:47:58 PM PDT 24 10980879364 ps
T904 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2914101883 Mar 24 12:48:28 PM PDT 24 Mar 24 12:48:42 PM PDT 24 6174128706 ps
T905 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2987951373 Mar 24 12:48:24 PM PDT 24 Mar 24 12:48:38 PM PDT 24 5613094530 ps
T906 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1407174703 Mar 24 12:47:40 PM PDT 24 Mar 24 12:47:44 PM PDT 24 592129034 ps
T907 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2155497824 Mar 24 12:47:39 PM PDT 24 Mar 24 12:47:52 PM PDT 24 2697807136 ps
T908 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3779103373 Mar 24 12:48:16 PM PDT 24 Mar 24 12:48:44 PM PDT 24 2255628060 ps
T909 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.61833496 Mar 24 12:48:16 PM PDT 24 Mar 24 12:48:30 PM PDT 24 1625784665 ps
T910 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2307425911 Mar 24 12:47:57 PM PDT 24 Mar 24 12:49:27 PM PDT 24 41505940049 ps
T911 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2229088487 Mar 24 12:47:36 PM PDT 24 Mar 24 12:47:43 PM PDT 24 475044067 ps
T912 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2476717933 Mar 24 12:47:54 PM PDT 24 Mar 24 12:48:08 PM PDT 24 1100579796 ps
T913 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.430476805 Mar 24 12:48:15 PM PDT 24 Mar 24 12:48:29 PM PDT 24 1601386467 ps
T914 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3967709315 Mar 24 12:48:32 PM PDT 24 Mar 24 12:48:38 PM PDT 24 1351567204 ps
T915 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1313940051 Mar 24 12:48:30 PM PDT 24 Mar 24 12:48:43 PM PDT 24 513163333 ps
T916 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2585746753 Mar 24 12:47:51 PM PDT 24 Mar 24 12:49:03 PM PDT 24 361971597 ps
T917 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3733158734 Mar 24 12:47:49 PM PDT 24 Mar 24 12:48:35 PM PDT 24 1947391749 ps
T918 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1809669708 Mar 24 12:48:06 PM PDT 24 Mar 24 12:48:15 PM PDT 24 124697986 ps
T919 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2591299181 Mar 24 12:48:17 PM PDT 24 Mar 24 12:48:27 PM PDT 24 1858750144 ps
T920 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.202793340 Mar 24 12:47:43 PM PDT 24 Mar 24 12:48:01 PM PDT 24 4256997472 ps
T921 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2903952363 Mar 24 12:48:16 PM PDT 24 Mar 24 12:48:27 PM PDT 24 8518274729 ps
T922 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.772522554 Mar 24 12:48:08 PM PDT 24 Mar 24 12:48:21 PM PDT 24 19001137062 ps

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.783298216
Short name T3
Test name
Test status
Simulation time 29316396635 ps
CPU time 66.98 seconds
Started Mar 24 12:56:55 PM PDT 24
Finished Mar 24 12:58:02 PM PDT 24
Peak memory 218104 kb
Host smart-491a010d-50de-4641-849e-8fb478f0d486
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783298216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.783298216
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2115883578
Short name T16
Test name
Test status
Simulation time 67605567028 ps
CPU time 870.68 seconds
Started Mar 24 01:08:06 PM PDT 24
Finished Mar 24 01:22:37 PM PDT 24
Peak memory 235868 kb
Host smart-ee973875-bd3c-4a75-89f2-b874bfcd1df7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115883578 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2115883578
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.227987803
Short name T30
Test name
Test status
Simulation time 45415394090 ps
CPU time 185.74 seconds
Started Mar 24 01:07:57 PM PDT 24
Finished Mar 24 01:11:03 PM PDT 24
Peak memory 237244 kb
Host smart-e9f1cecd-c98d-4e90-8556-9ccfed8f02d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227987803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.227987803
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3997856418
Short name T25
Test name
Test status
Simulation time 72587699690 ps
CPU time 209.89 seconds
Started Mar 24 01:08:15 PM PDT 24
Finished Mar 24 01:11:45 PM PDT 24
Peak memory 238700 kb
Host smart-ecf63231-f9ba-4b83-8307-4860d66ee7cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997856418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3997856418
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3085719285
Short name T127
Test name
Test status
Simulation time 2242666144 ps
CPU time 78.59 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 12:48:57 PM PDT 24
Peak memory 219532 kb
Host smart-3f0f0592-8595-47e9-a0e6-9161173e111a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085719285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3085719285
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4066711998
Short name T34
Test name
Test status
Simulation time 2689839290 ps
CPU time 58.62 seconds
Started Mar 24 01:07:54 PM PDT 24
Finished Mar 24 01:08:53 PM PDT 24
Peak memory 233304 kb
Host smart-a70b0680-7a4c-4f81-b3a5-4833bf719c32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066711998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4066711998
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.441021274
Short name T81
Test name
Test status
Simulation time 193291343482 ps
CPU time 90.08 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:49:26 PM PDT 24
Peak memory 211420 kb
Host smart-cbde47a7-a4c1-4f67-a055-bb5c4aeadd99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441021274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.441021274
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.80008929
Short name T780
Test name
Test status
Simulation time 1169336337 ps
CPU time 77.01 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:49:20 PM PDT 24
Peak memory 219456 kb
Host smart-fff20535-64c4-4b3d-9ec4-89494e10918c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80008929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg
_err.80008929
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2002495065
Short name T21
Test name
Test status
Simulation time 72035015210 ps
CPU time 474.18 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 235812 kb
Host smart-2ddd0d30-bbee-42f7-b5d3-94686c77f1d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002495065 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2002495065
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.341399430
Short name T7
Test name
Test status
Simulation time 3422203588 ps
CPU time 9.56 seconds
Started Mar 24 12:58:21 PM PDT 24
Finished Mar 24 12:58:31 PM PDT 24
Peak memory 211320 kb
Host smart-508253fd-21a5-44e1-bf5b-c48fe754c5b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341399430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.341399430
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2000231348
Short name T58
Test name
Test status
Simulation time 287607131 ps
CPU time 10 seconds
Started Mar 24 12:58:32 PM PDT 24
Finished Mar 24 12:58:43 PM PDT 24
Peak memory 213288 kb
Host smart-842d7f34-460f-480b-b8eb-bfb2e101ce91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000231348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2000231348
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2670510902
Short name T10
Test name
Test status
Simulation time 362493784 ps
CPU time 9.3 seconds
Started Mar 24 01:08:26 PM PDT 24
Finished Mar 24 01:08:36 PM PDT 24
Peak memory 211660 kb
Host smart-9cff8df2-60c0-449c-8fea-daed4811b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670510902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2670510902
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3470415335
Short name T74
Test name
Test status
Simulation time 7170395106 ps
CPU time 77.7 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 211392 kb
Host smart-ea9f98dd-114c-465d-97f7-1d37867834f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470415335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3470415335
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.88138473
Short name T28
Test name
Test status
Simulation time 5097551055 ps
CPU time 19.71 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:35 PM PDT 24
Peak memory 211292 kb
Host smart-8c7c2e78-a213-4c89-9735-00b0ea6e1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88138473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.88138473
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4029784500
Short name T62
Test name
Test status
Simulation time 11329538788 ps
CPU time 22.17 seconds
Started Mar 24 01:08:16 PM PDT 24
Finished Mar 24 01:08:38 PM PDT 24
Peak memory 212276 kb
Host smart-b349606f-97ed-4184-8d95-c356c76b49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029784500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4029784500
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2653182596
Short name T130
Test name
Test status
Simulation time 2158572011 ps
CPU time 80.2 seconds
Started Mar 24 12:47:59 PM PDT 24
Finished Mar 24 12:49:19 PM PDT 24
Peak memory 212236 kb
Host smart-08d31bdd-0f0e-4b9c-89a0-5665ebf47750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653182596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2653182596
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2135718598
Short name T63
Test name
Test status
Simulation time 7402430714 ps
CPU time 143.15 seconds
Started Mar 24 12:57:50 PM PDT 24
Finished Mar 24 01:00:14 PM PDT 24
Peak memory 219464 kb
Host smart-0cfb164d-1151-4c9f-9547-0fc132e60c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135718598 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2135718598
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.651750349
Short name T110
Test name
Test status
Simulation time 558773851 ps
CPU time 27.4 seconds
Started Mar 24 12:47:47 PM PDT 24
Finished Mar 24 12:48:14 PM PDT 24
Peak memory 211180 kb
Host smart-d2851b24-6c3d-4f29-8179-5f9fc9dc0a47
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651750349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.651750349
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3458177149
Short name T99
Test name
Test status
Simulation time 4290405949 ps
CPU time 33.47 seconds
Started Mar 24 01:08:29 PM PDT 24
Finished Mar 24 01:09:03 PM PDT 24
Peak memory 219424 kb
Host smart-62e749f8-5478-4c68-9d97-c39f73c06729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458177149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3458177149
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.209690739
Short name T858
Test name
Test status
Simulation time 2770573517 ps
CPU time 12.12 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 12:47:50 PM PDT 24
Peak memory 211340 kb
Host smart-21b533ae-3406-4a94-87c2-ca9dd8882c61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209690739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.209690739
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3552051210
Short name T836
Test name
Test status
Simulation time 1492050157 ps
CPU time 13.22 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:17 PM PDT 24
Peak memory 211232 kb
Host smart-5f8bff48-6783-4591-89bc-82f2b5761413
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552051210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3552051210
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1669096228
Short name T747
Test name
Test status
Simulation time 347609955 ps
CPU time 4.43 seconds
Started Mar 24 12:47:44 PM PDT 24
Finished Mar 24 12:47:49 PM PDT 24
Peak memory 211308 kb
Host smart-ea54b372-0336-4996-8acc-8225e10ddbf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669096228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1669096228
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3980004342
Short name T743
Test name
Test status
Simulation time 8496240547 ps
CPU time 16.11 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211348 kb
Host smart-45495653-1e6f-4090-8e26-4e0bff8951d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980004342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3980004342
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2109253624
Short name T785
Test name
Test status
Simulation time 18551878326 ps
CPU time 14.98 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:57 PM PDT 24
Peak memory 211404 kb
Host smart-81663ee2-378a-4a35-a411-5078fd4d7836
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109253624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2109253624
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3269116924
Short name T824
Test name
Test status
Simulation time 95988268 ps
CPU time 7.2 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:48:12 PM PDT 24
Peak memory 211224 kb
Host smart-beb2898d-9fc0-41fa-a2c3-6e8cbebce262
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269116924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3269116924
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2302368447
Short name T864
Test name
Test status
Simulation time 3065905970 ps
CPU time 9.56 seconds
Started Mar 24 12:48:01 PM PDT 24
Finished Mar 24 12:48:12 PM PDT 24
Peak memory 219580 kb
Host smart-9875670c-67aa-4d37-9813-42b78db5f151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302368447 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2302368447
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.923469757
Short name T893
Test name
Test status
Simulation time 5447356038 ps
CPU time 8 seconds
Started Mar 24 12:47:49 PM PDT 24
Finished Mar 24 12:47:57 PM PDT 24
Peak memory 219456 kb
Host smart-8a674f65-eac2-4af9-8aab-1face09c7d86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923469757 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.923469757
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1722773656
Short name T900
Test name
Test status
Simulation time 6937826892 ps
CPU time 14.34 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:18 PM PDT 24
Peak memory 211324 kb
Host smart-aae96d0f-6c9e-4eca-83dc-24adc05ed79f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722773656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1722773656
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3528937079
Short name T740
Test name
Test status
Simulation time 9087837776 ps
CPU time 11.93 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:51 PM PDT 24
Peak memory 211348 kb
Host smart-b35a511a-8865-4eb5-9895-6131f0d4a511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528937079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3528937079
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1569671346
Short name T891
Test name
Test status
Simulation time 8847615230 ps
CPU time 15.81 seconds
Started Mar 24 12:47:48 PM PDT 24
Finished Mar 24 12:48:04 PM PDT 24
Peak memory 211056 kb
Host smart-d5ed44ec-7493-4afa-bf11-dd27a3022b24
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569671346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1569671346
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.684536893
Short name T790
Test name
Test status
Simulation time 86493763 ps
CPU time 4.12 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 211032 kb
Host smart-29baea35-1765-4f31-b893-685b03d40a68
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684536893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.684536893
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1820557444
Short name T862
Test name
Test status
Simulation time 87511003 ps
CPU time 4.17 seconds
Started Mar 24 12:47:36 PM PDT 24
Finished Mar 24 12:47:40 PM PDT 24
Peak memory 211284 kb
Host smart-672b9ea1-4017-41a5-bcbf-ed6910d3eebf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820557444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1820557444
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.98659454
Short name T782
Test name
Test status
Simulation time 1892677454 ps
CPU time 15.56 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:48:20 PM PDT 24
Peak memory 211240 kb
Host smart-3b34bfff-2eac-4262-9250-3f3b212cf3bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98659454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.98659454
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.92679291
Short name T695
Test name
Test status
Simulation time 17855962692 ps
CPU time 56.42 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 211700 kb
Host smart-0b93df7a-da9c-4a59-9c0d-1a1f74d2040e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92679291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pass
thru_mem_tl_intg_err.92679291
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.321767649
Short name T850
Test name
Test status
Simulation time 4249616478 ps
CPU time 10.37 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 211360 kb
Host smart-ec81a40c-692d-42f3-b6c7-29f203c068cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321767649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.321767649
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3501322795
Short name T823
Test name
Test status
Simulation time 346413417 ps
CPU time 4.27 seconds
Started Mar 24 12:47:41 PM PDT 24
Finished Mar 24 12:47:45 PM PDT 24
Peak memory 211268 kb
Host smart-2c6b060e-9dab-4543-ae0a-98af811a6140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501322795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3501322795
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1590094538
Short name T880
Test name
Test status
Simulation time 2096366706 ps
CPU time 19.83 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:24 PM PDT 24
Peak memory 219536 kb
Host smart-5b6c68a4-d57f-4b9d-ba5a-b9d0b7e1abb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590094538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1590094538
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2758490121
Short name T703
Test name
Test status
Simulation time 6192419401 ps
CPU time 16.73 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:54 PM PDT 24
Peak memory 219612 kb
Host smart-04e672a7-4fa4-44db-8128-f7e10879c101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758490121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2758490121
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.402592461
Short name T712
Test name
Test status
Simulation time 9079051946 ps
CPU time 12.5 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:21 PM PDT 24
Peak memory 211388 kb
Host smart-08120b95-8e7a-476b-8f2d-25ae43dbf76b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402592461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.402592461
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4047150832
Short name T860
Test name
Test status
Simulation time 172599651 ps
CPU time 5.35 seconds
Started Mar 24 12:47:40 PM PDT 24
Finished Mar 24 12:47:45 PM PDT 24
Peak memory 211316 kb
Host smart-8e64e7ba-49c6-4a41-b228-8d56591c9c6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047150832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4047150832
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1277686021
Short name T87
Test name
Test status
Simulation time 1635651748 ps
CPU time 14.18 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 211272 kb
Host smart-7f4652e7-e3ec-4a4a-abe3-bbba07e71ec9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277686021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1277686021
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2744562232
Short name T691
Test name
Test status
Simulation time 899634730 ps
CPU time 9.94 seconds
Started Mar 24 12:47:44 PM PDT 24
Finished Mar 24 12:47:54 PM PDT 24
Peak memory 211340 kb
Host smart-483b6cf7-deaf-4c87-b1fd-75b04547dcac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744562232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2744562232
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2155497824
Short name T907
Test name
Test status
Simulation time 2697807136 ps
CPU time 13.49 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:52 PM PDT 24
Peak memory 211360 kb
Host smart-06540e45-22b3-4aa1-880b-ed419ba547ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155497824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2155497824
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2252759692
Short name T779
Test name
Test status
Simulation time 1121471876 ps
CPU time 12.4 seconds
Started Mar 24 12:48:12 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211244 kb
Host smart-f2c9879f-7de4-47bc-a601-225c11b41ac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252759692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2252759692
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3151875006
Short name T717
Test name
Test status
Simulation time 7791897677 ps
CPU time 16.06 seconds
Started Mar 24 12:47:40 PM PDT 24
Finished Mar 24 12:47:56 PM PDT 24
Peak memory 219608 kb
Host smart-2da2c494-701e-45d9-9b38-d2f8fc6a3934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151875006 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3151875006
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.61833496
Short name T909
Test name
Test status
Simulation time 1625784665 ps
CPU time 13.94 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:30 PM PDT 24
Peak memory 219540 kb
Host smart-bfc81cf3-634f-47d7-bc3b-0dea9b2b154b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61833496 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.61833496
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2763758771
Short name T788
Test name
Test status
Simulation time 1258351632 ps
CPU time 11.57 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:20 PM PDT 24
Peak memory 211324 kb
Host smart-d317485e-c6be-4ef6-b3a0-d82b5bfe3e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763758771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2763758771
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.942799945
Short name T739
Test name
Test status
Simulation time 3493240667 ps
CPU time 13.74 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 12:47:52 PM PDT 24
Peak memory 211324 kb
Host smart-7064a66d-0407-4400-9a88-c47e47fcb4ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942799945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.942799945
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1796534385
Short name T804
Test name
Test status
Simulation time 452275815 ps
CPU time 5.48 seconds
Started Mar 24 12:47:48 PM PDT 24
Finished Mar 24 12:47:54 PM PDT 24
Peak memory 211024 kb
Host smart-022388ef-05f2-4826-9893-a5c867f3643a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796534385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1796534385
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4113707444
Short name T833
Test name
Test status
Simulation time 90860802 ps
CPU time 4.18 seconds
Started Mar 24 12:48:08 PM PDT 24
Finished Mar 24 12:48:12 PM PDT 24
Peak memory 211108 kb
Host smart-3052b485-0a94-46e4-9584-27e7f0a012ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113707444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4113707444
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1579958920
Short name T750
Test name
Test status
Simulation time 1970644183 ps
CPU time 15.07 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:53 PM PDT 24
Peak memory 211132 kb
Host smart-226e8d55-fb35-4ae2-9411-5e3063a521fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579958920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1579958920
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3584207986
Short name T759
Test name
Test status
Simulation time 868305790 ps
CPU time 9.05 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:48:14 PM PDT 24
Peak memory 211256 kb
Host smart-429a612d-5d7f-45a4-b9cc-ce8b65664911
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584207986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3584207986
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2595406810
Short name T867
Test name
Test status
Simulation time 379845327 ps
CPU time 18.85 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 12:47:57 PM PDT 24
Peak memory 211336 kb
Host smart-5b5c30c5-9436-4b40-8830-d77b6da3d426
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595406810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2595406810
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3843390157
Short name T843
Test name
Test status
Simulation time 11854575044 ps
CPU time 94.27 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:49:38 PM PDT 24
Peak memory 211316 kb
Host smart-a37db068-261a-4532-ba32-b6de9316e6a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843390157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3843390157
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2385984580
Short name T871
Test name
Test status
Simulation time 2023341866 ps
CPU time 15.61 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211280 kb
Host smart-4bef4f95-cf74-4949-bca1-7df7a0f05ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385984580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2385984580
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2960344567
Short name T866
Test name
Test status
Simulation time 842650814 ps
CPU time 9.52 seconds
Started Mar 24 12:47:48 PM PDT 24
Finished Mar 24 12:47:57 PM PDT 24
Peak memory 211156 kb
Host smart-fc43ab55-ca12-418e-80db-1b1f3252934c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960344567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2960344567
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.217581661
Short name T854
Test name
Test status
Simulation time 675646891 ps
CPU time 10.98 seconds
Started Mar 24 12:48:05 PM PDT 24
Finished Mar 24 12:48:17 PM PDT 24
Peak memory 219576 kb
Host smart-083750bd-5b6c-4469-894d-efce4962f95a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217581661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.217581661
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.963812494
Short name T761
Test name
Test status
Simulation time 1182881232 ps
CPU time 14.02 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:51 PM PDT 24
Peak memory 219580 kb
Host smart-1c5708fd-a7a9-4a42-9983-f4834bf7cbf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963812494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.963812494
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1866029009
Short name T870
Test name
Test status
Simulation time 869329102 ps
CPU time 40.83 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 212212 kb
Host smart-ebaa8c7b-75a9-4ea8-8bef-0932c1b0ee17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866029009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1866029009
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2615828144
Short name T886
Test name
Test status
Simulation time 317595484 ps
CPU time 37.32 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:48:17 PM PDT 24
Peak memory 212176 kb
Host smart-b85d0da5-0998-47c0-8428-1b43f3874300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615828144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2615828144
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3517803491
Short name T808
Test name
Test status
Simulation time 1597495029 ps
CPU time 13.9 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:11 PM PDT 24
Peak memory 218900 kb
Host smart-1059732b-5995-4715-9dd5-447f516dbb8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517803491 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3517803491
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.909970160
Short name T847
Test name
Test status
Simulation time 157073037 ps
CPU time 4.67 seconds
Started Mar 24 12:48:20 PM PDT 24
Finished Mar 24 12:48:24 PM PDT 24
Peak memory 213444 kb
Host smart-edb8ebf0-a955-4810-9271-19f34504220e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909970160 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.909970160
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3672881523
Short name T890
Test name
Test status
Simulation time 167912489 ps
CPU time 4.22 seconds
Started Mar 24 12:48:19 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 211300 kb
Host smart-4b455a98-1ffe-40e4-b24c-b3425cdd729e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672881523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3672881523
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3799369234
Short name T838
Test name
Test status
Simulation time 4500737462 ps
CPU time 16.93 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 211380 kb
Host smart-0f5af19e-df74-46af-b42e-dcf5d241490a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799369234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3799369234
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.79101876
Short name T783
Test name
Test status
Simulation time 5137154781 ps
CPU time 43.29 seconds
Started Mar 24 12:48:21 PM PDT 24
Finished Mar 24 12:49:04 PM PDT 24
Peak memory 211632 kb
Host smart-fcf58958-3816-445b-b26c-9aa8ce1d2dd1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79101876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pas
sthru_mem_tl_intg_err.79101876
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1221534592
Short name T807
Test name
Test status
Simulation time 5110242830 ps
CPU time 9.22 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:07 PM PDT 24
Peak memory 211248 kb
Host smart-74f6ab82-ad41-4dd7-885c-bb357b06befe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221534592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1221534592
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3421727217
Short name T764
Test name
Test status
Simulation time 2967951765 ps
CPU time 12.63 seconds
Started Mar 24 12:48:19 PM PDT 24
Finished Mar 24 12:48:32 PM PDT 24
Peak memory 211220 kb
Host smart-abf609fa-9747-4bd1-9ec8-d842bdb34ff6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421727217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3421727217
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2090749737
Short name T805
Test name
Test status
Simulation time 167202643 ps
CPU time 7.9 seconds
Started Mar 24 12:48:19 PM PDT 24
Finished Mar 24 12:48:27 PM PDT 24
Peak memory 219448 kb
Host smart-d465e2ff-39af-4542-badd-4b44457a8599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090749737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2090749737
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.921748583
Short name T787
Test name
Test status
Simulation time 5286414968 ps
CPU time 14.88 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:11 PM PDT 24
Peak memory 219644 kb
Host smart-8b8e48c8-57d2-4c4b-a177-2efd829185fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921748583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.921748583
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.950933016
Short name T757
Test name
Test status
Simulation time 934049196 ps
CPU time 67.77 seconds
Started Mar 24 12:48:20 PM PDT 24
Finished Mar 24 12:49:28 PM PDT 24
Peak memory 211324 kb
Host smart-753a4000-e011-4ee7-bada-6412e8a8ab04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950933016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.950933016
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2963867973
Short name T681
Test name
Test status
Simulation time 3779697354 ps
CPU time 14.6 seconds
Started Mar 24 12:47:56 PM PDT 24
Finished Mar 24 12:48:11 PM PDT 24
Peak memory 219616 kb
Host smart-d543f0cf-7d59-4385-b07c-f093ed87c434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963867973 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2963867973
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2987951373
Short name T905
Test name
Test status
Simulation time 5613094530 ps
CPU time 14.09 seconds
Started Mar 24 12:48:24 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 219600 kb
Host smart-28dd65a4-a40c-4ab4-8137-76ba7cca559c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987951373 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2987951373
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2575185321
Short name T797
Test name
Test status
Simulation time 168093583 ps
CPU time 4.16 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:47:59 PM PDT 24
Peak memory 211284 kb
Host smart-04dcb072-0b23-4501-aaa1-99b59a07a7d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575185321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2575185321
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.527580452
Short name T729
Test name
Test status
Simulation time 1896342947 ps
CPU time 9.62 seconds
Started Mar 24 12:48:25 PM PDT 24
Finished Mar 24 12:48:35 PM PDT 24
Peak memory 211304 kb
Host smart-1160ca82-57a1-4552-a879-50c7f8c13168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527580452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.527580452
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1449402148
Short name T897
Test name
Test status
Simulation time 1495463168 ps
CPU time 18.7 seconds
Started Mar 24 12:48:20 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 211376 kb
Host smart-76408907-3144-4230-a4e9-aea8b6ac0d02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449402148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1449402148
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4148827263
Short name T92
Test name
Test status
Simulation time 10446468497 ps
CPU time 42.64 seconds
Started Mar 24 12:48:01 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 211388 kb
Host smart-d22e2b8c-ea9b-4fa6-99f1-a9d42bd58b9f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148827263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4148827263
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1407612391
Short name T896
Test name
Test status
Simulation time 89306169 ps
CPU time 4.43 seconds
Started Mar 24 12:47:59 PM PDT 24
Finished Mar 24 12:48:04 PM PDT 24
Peak memory 211324 kb
Host smart-312ebe0f-364f-4729-b2f6-4e82a4aa498e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407612391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1407612391
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3159956973
Short name T737
Test name
Test status
Simulation time 259252157 ps
CPU time 5.31 seconds
Started Mar 24 12:48:25 PM PDT 24
Finished Mar 24 12:48:30 PM PDT 24
Peak memory 211300 kb
Host smart-a7b14352-5655-4f7b-bfb8-e8913798ed64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159956973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3159956973
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1154194816
Short name T873
Test name
Test status
Simulation time 4743873188 ps
CPU time 13.91 seconds
Started Mar 24 12:48:18 PM PDT 24
Finished Mar 24 12:48:32 PM PDT 24
Peak memory 219644 kb
Host smart-43588740-f0e3-4e9e-adf6-6d7d8cb2d4b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154194816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1154194816
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3107641654
Short name T748
Test name
Test status
Simulation time 6340746243 ps
CPU time 17.37 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 219612 kb
Host smart-f1a41887-07aa-4ed3-981b-ed01a329120e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107641654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3107641654
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2174810978
Short name T877
Test name
Test status
Simulation time 6343147621 ps
CPU time 74.93 seconds
Started Mar 24 12:47:56 PM PDT 24
Finished Mar 24 12:49:12 PM PDT 24
Peak memory 211400 kb
Host smart-8401f76f-70f0-467c-87f8-02bbfa2734ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174810978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2174810978
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3000587383
Short name T814
Test name
Test status
Simulation time 252266246 ps
CPU time 37.59 seconds
Started Mar 24 12:48:19 PM PDT 24
Finished Mar 24 12:48:56 PM PDT 24
Peak memory 212292 kb
Host smart-9f934716-a2a1-40d3-8da1-8adc91b14482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000587383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3000587383
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4106918308
Short name T888
Test name
Test status
Simulation time 16001426774 ps
CPU time 15.15 seconds
Started Mar 24 12:48:22 PM PDT 24
Finished Mar 24 12:48:37 PM PDT 24
Peak memory 212988 kb
Host smart-01253754-eda0-4cc9-a623-29cd77b00d75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106918308 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4106918308
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4244797135
Short name T791
Test name
Test status
Simulation time 29599293129 ps
CPU time 15.54 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:11 PM PDT 24
Peak memory 219540 kb
Host smart-01fee81d-8850-4431-b065-e904f9525881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244797135 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4244797135
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1071955062
Short name T694
Test name
Test status
Simulation time 6220195190 ps
CPU time 13.45 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:12 PM PDT 24
Peak memory 211340 kb
Host smart-d54c33b4-ee8f-4f8c-aac0-2cd8a530a496
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071955062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1071955062
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3386480047
Short name T85
Test name
Test status
Simulation time 689880409 ps
CPU time 8.31 seconds
Started Mar 24 12:48:23 PM PDT 24
Finished Mar 24 12:48:31 PM PDT 24
Peak memory 211152 kb
Host smart-6b95591b-5fa4-4ad0-b9e9-2f2241893da9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386480047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3386480047
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1055503721
Short name T781
Test name
Test status
Simulation time 51241707138 ps
CPU time 105.21 seconds
Started Mar 24 12:48:22 PM PDT 24
Finished Mar 24 12:50:08 PM PDT 24
Peak memory 211408 kb
Host smart-7aafc72f-2b61-43ff-9216-4adc7c43f612
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055503721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1055503721
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2124310458
Short name T882
Test name
Test status
Simulation time 18537353285 ps
CPU time 44.15 seconds
Started Mar 24 12:48:01 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 211360 kb
Host smart-f914d327-20c1-4312-826c-e236c9d70827
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124310458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2124310458
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1433847123
Short name T770
Test name
Test status
Simulation time 4431611848 ps
CPU time 13.88 seconds
Started Mar 24 12:48:28 PM PDT 24
Finished Mar 24 12:48:42 PM PDT 24
Peak memory 211204 kb
Host smart-0efd452f-0f9b-4035-8f25-6b66febf6dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433847123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1433847123
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1616597664
Short name T829
Test name
Test status
Simulation time 346759859 ps
CPU time 4.16 seconds
Started Mar 24 12:47:56 PM PDT 24
Finished Mar 24 12:48:02 PM PDT 24
Peak memory 211288 kb
Host smart-cfde4cec-fc57-4c65-b970-50ec1ad1020d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616597664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1616597664
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2559444103
Short name T802
Test name
Test status
Simulation time 554839161 ps
CPU time 9.77 seconds
Started Mar 24 12:48:25 PM PDT 24
Finished Mar 24 12:48:35 PM PDT 24
Peak memory 214616 kb
Host smart-d81a39d2-d27e-4c08-acb7-243d998dd98d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559444103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2559444103
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.585275162
Short name T856
Test name
Test status
Simulation time 7943467717 ps
CPU time 15.29 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:11 PM PDT 24
Peak memory 219568 kb
Host smart-c94d80b8-2034-4c44-87db-79cc79ab53d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585275162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.585275162
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1423911888
Short name T773
Test name
Test status
Simulation time 655355395 ps
CPU time 70.1 seconds
Started Mar 24 12:48:27 PM PDT 24
Finished Mar 24 12:49:37 PM PDT 24
Peak memory 212400 kb
Host smart-1ae5b116-54dc-4e66-b64e-c3a17014a0ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423911888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1423911888
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2329682544
Short name T772
Test name
Test status
Simulation time 5841071859 ps
CPU time 75.33 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 212636 kb
Host smart-8e09053c-7083-4e4f-b47d-08687343384a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329682544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2329682544
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3874043002
Short name T846
Test name
Test status
Simulation time 3132385758 ps
CPU time 13.98 seconds
Started Mar 24 12:48:26 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 219612 kb
Host smart-5a0f3c7a-56ce-4169-a893-f114c10908e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874043002 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3874043002
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3879809642
Short name T827
Test name
Test status
Simulation time 568015576 ps
CPU time 7.19 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:05 PM PDT 24
Peak memory 219508 kb
Host smart-6b47c0dd-d349-4eca-a7b1-aae49b4c4f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879809642 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3879809642
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3155590605
Short name T869
Test name
Test status
Simulation time 85485226 ps
CPU time 4.18 seconds
Started Mar 24 12:48:28 PM PDT 24
Finished Mar 24 12:48:32 PM PDT 24
Peak memory 211296 kb
Host smart-cffe948e-615f-4ce3-abf7-89daff45897c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155590605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3155590605
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.373667688
Short name T895
Test name
Test status
Simulation time 215806460 ps
CPU time 5.56 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:01 PM PDT 24
Peak memory 211296 kb
Host smart-e4b23e2d-f712-4401-ae3c-70a86e484f3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373667688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.373667688
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1170455474
Short name T859
Test name
Test status
Simulation time 5124880114 ps
CPU time 36.8 seconds
Started Mar 24 12:48:00 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 211428 kb
Host smart-754b7db2-c954-4a0f-b5bd-189c5a66bd2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170455474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1170455474
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.338295187
Short name T704
Test name
Test status
Simulation time 62699119678 ps
CPU time 57.48 seconds
Started Mar 24 12:48:27 PM PDT 24
Finished Mar 24 12:49:24 PM PDT 24
Peak memory 211428 kb
Host smart-84f10f48-a480-4aa8-8b0f-18992e13b71f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338295187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.338295187
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2515115214
Short name T776
Test name
Test status
Simulation time 1207662085 ps
CPU time 11.55 seconds
Started Mar 24 12:47:56 PM PDT 24
Finished Mar 24 12:48:07 PM PDT 24
Peak memory 211280 kb
Host smart-3f6ce044-2070-412e-ab5c-82ff44e775e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515115214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2515115214
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3084420963
Short name T736
Test name
Test status
Simulation time 2296265502 ps
CPU time 8.23 seconds
Started Mar 24 12:48:25 PM PDT 24
Finished Mar 24 12:48:33 PM PDT 24
Peak memory 211360 kb
Host smart-9ff0c558-365a-415a-b709-5f0cb31cd345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084420963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3084420963
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2476717933
Short name T912
Test name
Test status
Simulation time 1100579796 ps
CPU time 13.65 seconds
Started Mar 24 12:47:54 PM PDT 24
Finished Mar 24 12:48:08 PM PDT 24
Peak memory 219468 kb
Host smart-2f784c2c-b508-4146-a5a3-f0abc33e3192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476717933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2476717933
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.324998798
Short name T745
Test name
Test status
Simulation time 319951769 ps
CPU time 6.41 seconds
Started Mar 24 12:48:25 PM PDT 24
Finished Mar 24 12:48:32 PM PDT 24
Peak memory 219536 kb
Host smart-4a87b055-23bd-48a5-923b-42618cfa649a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324998798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.324998798
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1436532716
Short name T122
Test name
Test status
Simulation time 3046078625 ps
CPU time 74.53 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:49:17 PM PDT 24
Peak memory 211368 kb
Host smart-a339d401-d244-4bdc-88e4-91a44f05d544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436532716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1436532716
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2093363743
Short name T124
Test name
Test status
Simulation time 8087495442 ps
CPU time 76.67 seconds
Started Mar 24 12:48:28 PM PDT 24
Finished Mar 24 12:49:45 PM PDT 24
Peak memory 212352 kb
Host smart-b0992809-a33f-4bb6-98da-fc79dee1d3a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093363743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2093363743
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2741916405
Short name T75
Test name
Test status
Simulation time 2008397829 ps
CPU time 10.67 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:06 PM PDT 24
Peak memory 214020 kb
Host smart-0bfce5e9-bb18-479a-8bb1-ef53fef4d7cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741916405 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2741916405
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3541913591
Short name T702
Test name
Test status
Simulation time 1088505857 ps
CPU time 4.47 seconds
Started Mar 24 12:48:28 PM PDT 24
Finished Mar 24 12:48:33 PM PDT 24
Peak memory 212616 kb
Host smart-250cbc31-2d46-4dac-9d83-4c5fe46e3114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541913591 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3541913591
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.253891510
Short name T86
Test name
Test status
Simulation time 1894125844 ps
CPU time 7.26 seconds
Started Mar 24 12:48:01 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 211272 kb
Host smart-1fc3e5e5-746e-468a-9243-efefd845ec8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253891510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.253891510
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3238910258
Short name T835
Test name
Test status
Simulation time 7099351797 ps
CPU time 10.69 seconds
Started Mar 24 12:48:28 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 211368 kb
Host smart-5bb94f14-c95c-4b77-a93a-e06ee2072bdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238910258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3238910258
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1665762312
Short name T96
Test name
Test status
Simulation time 2380396839 ps
CPU time 27.12 seconds
Started Mar 24 12:48:27 PM PDT 24
Finished Mar 24 12:48:54 PM PDT 24
Peak memory 211424 kb
Host smart-dff2d90e-88c6-4590-89c1-50aaa54129f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665762312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1665762312
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2307425911
Short name T910
Test name
Test status
Simulation time 41505940049 ps
CPU time 89.08 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:49:27 PM PDT 24
Peak memory 211388 kb
Host smart-ea20214a-614e-43e7-9248-2f5fcdd9ce2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307425911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2307425911
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1470703994
Short name T754
Test name
Test status
Simulation time 4416250394 ps
CPU time 11.04 seconds
Started Mar 24 12:47:58 PM PDT 24
Finished Mar 24 12:48:10 PM PDT 24
Peak memory 211344 kb
Host smart-82e38fee-5a14-4862-b882-61d3cd0d4690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470703994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1470703994
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2914101883
Short name T904
Test name
Test status
Simulation time 6174128706 ps
CPU time 13.61 seconds
Started Mar 24 12:48:28 PM PDT 24
Finished Mar 24 12:48:42 PM PDT 24
Peak memory 211388 kb
Host smart-f770a120-fefb-422f-a2f2-3dda60bb948a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914101883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2914101883
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3356864555
Short name T700
Test name
Test status
Simulation time 10633440901 ps
CPU time 10.95 seconds
Started Mar 24 12:47:54 PM PDT 24
Finished Mar 24 12:48:05 PM PDT 24
Peak memory 219620 kb
Host smart-27cef8dd-eca0-4cd0-a389-4a5764b08399
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356864555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3356864555
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.955944592
Short name T784
Test name
Test status
Simulation time 12325355696 ps
CPU time 12.47 seconds
Started Mar 24 12:48:28 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 219664 kb
Host smart-c0c2e49d-b66a-47fc-8670-2edac661391e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955944592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.955944592
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3990504093
Short name T883
Test name
Test status
Simulation time 2592241430 ps
CPU time 42.75 seconds
Started Mar 24 12:48:24 PM PDT 24
Finished Mar 24 12:49:07 PM PDT 24
Peak memory 212204 kb
Host smart-77b0b0ac-74b4-4aa5-8a63-69c78d24e66a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990504093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3990504093
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.564894578
Short name T765
Test name
Test status
Simulation time 15533537055 ps
CPU time 45.48 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:42 PM PDT 24
Peak memory 211676 kb
Host smart-a258c660-7e7f-4684-a0b1-a8d7e7c6e8d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564894578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.564894578
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2436803382
Short name T830
Test name
Test status
Simulation time 88865963 ps
CPU time 4.32 seconds
Started Mar 24 12:48:30 PM PDT 24
Finished Mar 24 12:48:35 PM PDT 24
Peak memory 212488 kb
Host smart-1c532458-aca0-4655-860c-112c0f3ec7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436803382 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2436803382
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.301310602
Short name T701
Test name
Test status
Simulation time 708159085 ps
CPU time 6.3 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:04 PM PDT 24
Peak memory 213652 kb
Host smart-d439c1e3-4479-470f-bc00-446584f19dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301310602 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.301310602
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2725813959
Short name T857
Test name
Test status
Simulation time 2464669796 ps
CPU time 8.14 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:05 PM PDT 24
Peak memory 210604 kb
Host smart-0be7c5bc-acbd-41ca-aa41-fdded357c617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725813959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2725813959
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.87687488
Short name T815
Test name
Test status
Simulation time 1807015864 ps
CPU time 7.18 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 211324 kb
Host smart-d96c4958-b28b-40e8-a83c-d6695d0e4097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87687488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.87687488
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3016005786
Short name T763
Test name
Test status
Simulation time 2229893217 ps
CPU time 27.14 seconds
Started Mar 24 12:48:31 PM PDT 24
Finished Mar 24 12:48:59 PM PDT 24
Peak memory 211392 kb
Host smart-3063cd2b-2a70-4017-9077-c940bf2b740a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016005786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3016005786
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.905454698
Short name T98
Test name
Test status
Simulation time 25285569641 ps
CPU time 45.62 seconds
Started Mar 24 12:48:01 PM PDT 24
Finished Mar 24 12:48:47 PM PDT 24
Peak memory 211388 kb
Host smart-f012bb00-5752-42a6-82b8-e50d13151e1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905454698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.905454698
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.838404176
Short name T768
Test name
Test status
Simulation time 90943966 ps
CPU time 4.27 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:37 PM PDT 24
Peak memory 211336 kb
Host smart-d77a0220-05be-487b-91b9-d196e70970b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838404176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.838404176
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.905587652
Short name T731
Test name
Test status
Simulation time 91066906 ps
CPU time 4.22 seconds
Started Mar 24 12:47:53 PM PDT 24
Finished Mar 24 12:47:57 PM PDT 24
Peak memory 211296 kb
Host smart-7d834b28-7801-4ef3-ab96-a5155462450f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905587652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.905587652
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3871937286
Short name T810
Test name
Test status
Simulation time 13444054813 ps
CPU time 18.46 seconds
Started Mar 24 12:47:54 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 219604 kb
Host smart-af8ce4d2-87b9-419a-a4ee-4eb8eddd7658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871937286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3871937286
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4238733873
Short name T680
Test name
Test status
Simulation time 3285093243 ps
CPU time 17.54 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 219616 kb
Host smart-6563abc3-a50c-4a13-8de1-95118d879fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238733873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4238733873
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1479511430
Short name T133
Test name
Test status
Simulation time 1229399402 ps
CPU time 41.69 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:37 PM PDT 24
Peak memory 211796 kb
Host smart-b440fa09-23b4-4b73-882b-eff89be1d471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479511430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1479511430
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.838287495
Short name T129
Test name
Test status
Simulation time 3347084006 ps
CPU time 76.02 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:49:49 PM PDT 24
Peak memory 212380 kb
Host smart-5fdc8ffa-46c8-4c65-9437-fc05292dda47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838287495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.838287495
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2405244665
Short name T879
Test name
Test status
Simulation time 3760396706 ps
CPU time 10 seconds
Started Mar 24 12:47:58 PM PDT 24
Finished Mar 24 12:48:08 PM PDT 24
Peak memory 212496 kb
Host smart-f9cbe178-d223-40ad-beb5-a1625440dd58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405244665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2405244665
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3967709315
Short name T914
Test name
Test status
Simulation time 1351567204 ps
CPU time 4.93 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 219516 kb
Host smart-52b5ce7f-3012-49d0-bfcc-594fc32678ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967709315 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3967709315
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2512208054
Short name T714
Test name
Test status
Simulation time 3906261595 ps
CPU time 14.87 seconds
Started Mar 24 12:47:56 PM PDT 24
Finished Mar 24 12:48:12 PM PDT 24
Peak memory 211404 kb
Host smart-4d864a42-0649-4079-b048-67b6890de7a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512208054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2512208054
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3144496360
Short name T901
Test name
Test status
Simulation time 1672116766 ps
CPU time 9.18 seconds
Started Mar 24 12:48:35 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 211280 kb
Host smart-205780cf-bff9-4ba2-ae42-b71537f32a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144496360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3144496360
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1928083504
Short name T899
Test name
Test status
Simulation time 11844924215 ps
CPU time 61.22 seconds
Started Mar 24 12:47:57 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 211396 kb
Host smart-c7d9e06c-172a-45a6-8876-232a37004813
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928083504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1928083504
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2351966964
Short name T769
Test name
Test status
Simulation time 9499483665 ps
CPU time 84.89 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:49:57 PM PDT 24
Peak memory 211408 kb
Host smart-5b1f4fe1-8915-4b24-ace8-04809cf9292e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351966964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2351966964
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1939398308
Short name T735
Test name
Test status
Simulation time 164784912 ps
CPU time 4.39 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:37 PM PDT 24
Peak memory 211332 kb
Host smart-78dcca32-56dc-40d8-81c2-0467ed700fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939398308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1939398308
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2997794005
Short name T839
Test name
Test status
Simulation time 1892652493 ps
CPU time 14.44 seconds
Started Mar 24 12:48:01 PM PDT 24
Finished Mar 24 12:48:16 PM PDT 24
Peak memory 211300 kb
Host smart-a8570c08-e1d8-44c6-8700-2c5025ee05a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997794005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2997794005
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1313940051
Short name T915
Test name
Test status
Simulation time 513163333 ps
CPU time 12.35 seconds
Started Mar 24 12:48:30 PM PDT 24
Finished Mar 24 12:48:43 PM PDT 24
Peak memory 219472 kb
Host smart-9178b83a-e624-4cf6-91fd-f8ddf0a4a084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313940051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1313940051
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4248184387
Short name T803
Test name
Test status
Simulation time 85748013 ps
CPU time 6.32 seconds
Started Mar 24 12:47:55 PM PDT 24
Finished Mar 24 12:48:02 PM PDT 24
Peak memory 215684 kb
Host smart-d61a60e1-3347-45a4-8128-aef8d46e159b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248184387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4248184387
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.605493878
Short name T72
Test name
Test status
Simulation time 2314611065 ps
CPU time 47.84 seconds
Started Mar 24 12:48:33 PM PDT 24
Finished Mar 24 12:49:21 PM PDT 24
Peak memory 213148 kb
Host smart-e3faa82b-c4ca-49b1-8c70-81da1f2aa18b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605493878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.605493878
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2519746007
Short name T774
Test name
Test status
Simulation time 1100225854 ps
CPU time 7.84 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:48:10 PM PDT 24
Peak memory 213772 kb
Host smart-04313959-bd36-4e56-95ec-589f32b1965d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519746007 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2519746007
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3225462587
Short name T752
Test name
Test status
Simulation time 97162179 ps
CPU time 4.73 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 219556 kb
Host smart-e08556cc-5066-44b5-993e-ae569e0a33cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225462587 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3225462587
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2947332006
Short name T801
Test name
Test status
Simulation time 2854134751 ps
CPU time 8.18 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 211412 kb
Host smart-e65b6c0b-30d2-46ae-8153-c9b65949038c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947332006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2947332006
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.760863360
Short name T721
Test name
Test status
Simulation time 6006676516 ps
CPU time 13.23 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:48:16 PM PDT 24
Peak memory 211288 kb
Host smart-9f93682f-c38e-4570-9602-f4518c81b8b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760863360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.760863360
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3522660433
Short name T821
Test name
Test status
Simulation time 27699822046 ps
CPU time 67.45 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:49:40 PM PDT 24
Peak memory 211344 kb
Host smart-2abb1234-1511-40db-a2c5-24e22ba256b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522660433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3522660433
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.440295913
Short name T727
Test name
Test status
Simulation time 7918033391 ps
CPU time 63.25 seconds
Started Mar 24 12:48:06 PM PDT 24
Finished Mar 24 12:49:09 PM PDT 24
Peak memory 211632 kb
Host smart-c4c31ce9-7c30-4d6b-aa65-0bf65c8fae79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440295913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.440295913
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1053369142
Short name T812
Test name
Test status
Simulation time 16255308022 ps
CPU time 14.28 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 211320 kb
Host smart-0fe11bd0-f689-43c3-8452-e81a2d2f486d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053369142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1053369142
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1076780987
Short name T837
Test name
Test status
Simulation time 291769294 ps
CPU time 6.3 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 211300 kb
Host smart-46139474-0b4d-4163-b365-d33d54a7f704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076780987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1076780987
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1809669708
Short name T918
Test name
Test status
Simulation time 124697986 ps
CPU time 8.57 seconds
Started Mar 24 12:48:06 PM PDT 24
Finished Mar 24 12:48:15 PM PDT 24
Peak memory 219544 kb
Host smart-96c376ca-0f1f-4cf0-ac5c-95afffdc0b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809669708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1809669708
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1834179537
Short name T728
Test name
Test status
Simulation time 1521562793 ps
CPU time 16.49 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:49 PM PDT 24
Peak memory 219536 kb
Host smart-7e811137-27c4-49e1-b8ee-ef75b02619d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834179537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1834179537
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1512907939
Short name T746
Test name
Test status
Simulation time 1972844935 ps
CPU time 41.22 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 211840 kb
Host smart-7c0691fe-fed3-43ca-b9e2-c68b2ad4eabd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512907939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1512907939
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4083550085
Short name T818
Test name
Test status
Simulation time 1438937834 ps
CPU time 74.03 seconds
Started Mar 24 12:48:31 PM PDT 24
Finished Mar 24 12:49:46 PM PDT 24
Peak memory 212068 kb
Host smart-721a1310-5f3a-4d56-bc36-f5c270f83e46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083550085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4083550085
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1698442086
Short name T889
Test name
Test status
Simulation time 7572239583 ps
CPU time 16.78 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:48:19 PM PDT 24
Peak memory 219448 kb
Host smart-7c9f0e6b-290e-4a3a-89d0-a665b01fde7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698442086 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1698442086
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.191265472
Short name T832
Test name
Test status
Simulation time 17324436592 ps
CPU time 13.51 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 216116 kb
Host smart-1fbc9cd9-5caf-43b0-9b53-4eb22df238ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191265472 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.191265472
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1588351200
Short name T817
Test name
Test status
Simulation time 332608025 ps
CPU time 4.21 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:48:07 PM PDT 24
Peak memory 211340 kb
Host smart-aa678d3a-f6a6-4bdb-9f78-07bb0ed24893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588351200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1588351200
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2383726789
Short name T118
Test name
Test status
Simulation time 251509323 ps
CPU time 5.05 seconds
Started Mar 24 12:48:34 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 211300 kb
Host smart-29c95746-13b1-4c30-a0cf-d70e46f34a5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383726789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2383726789
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2582583335
Short name T93
Test name
Test status
Simulation time 11125598946 ps
CPU time 69.8 seconds
Started Mar 24 12:48:02 PM PDT 24
Finished Mar 24 12:49:12 PM PDT 24
Peak memory 211436 kb
Host smart-d8848813-dfd0-4ad2-82e0-c31bd739aab5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582583335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2582583335
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3064313345
Short name T813
Test name
Test status
Simulation time 2224018275 ps
CPU time 27.43 seconds
Started Mar 24 12:48:30 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 211312 kb
Host smart-3880db64-97aa-464b-b0a2-4496266ed737
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064313345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3064313345
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2104801293
Short name T749
Test name
Test status
Simulation time 3406998496 ps
CPU time 14.49 seconds
Started Mar 24 12:48:30 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 211372 kb
Host smart-86eeff97-7cf6-40ff-9347-1f0c429920e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104801293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2104801293
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3056628974
Short name T872
Test name
Test status
Simulation time 87341762 ps
CPU time 4.38 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:08 PM PDT 24
Peak memory 211296 kb
Host smart-1c02a921-c4eb-4ed1-bdc8-01ad06923245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056628974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3056628974
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.156393601
Short name T753
Test name
Test status
Simulation time 1061286471 ps
CPU time 12.76 seconds
Started Mar 24 12:48:31 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 219576 kb
Host smart-8a6d7f66-1c5b-4e09-bfaf-c60490f9cf0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156393601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.156393601
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3158633283
Short name T692
Test name
Test status
Simulation time 4110941010 ps
CPU time 10.08 seconds
Started Mar 24 12:48:06 PM PDT 24
Finished Mar 24 12:48:16 PM PDT 24
Peak memory 219640 kb
Host smart-834b443e-17cc-4ecf-a742-fc9eb1ed80c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158633283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3158633283
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3405168126
Short name T123
Test name
Test status
Simulation time 2321117572 ps
CPU time 78.13 seconds
Started Mar 24 12:48:31 PM PDT 24
Finished Mar 24 12:49:50 PM PDT 24
Peak memory 219556 kb
Host smart-19ea1c6e-d4ea-41a3-808d-622963e47cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405168126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3405168126
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3431767386
Short name T853
Test name
Test status
Simulation time 2043623464 ps
CPU time 46.42 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:49 PM PDT 24
Peak memory 212124 kb
Host smart-6896d8ec-746f-43ef-9e13-6e8f7b95c7de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431767386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3431767386
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1872323154
Short name T825
Test name
Test status
Simulation time 173357246 ps
CPU time 5.79 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 212500 kb
Host smart-762a0729-592c-4cc8-bda2-2ab975ab9b90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872323154 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1872323154
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1902047714
Short name T874
Test name
Test status
Simulation time 433666841 ps
CPU time 7.38 seconds
Started Mar 24 12:48:06 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 219520 kb
Host smart-9a645aa4-263d-4899-aa5d-3d66f6877dd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902047714 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1902047714
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1661026613
Short name T775
Test name
Test status
Simulation time 94707293 ps
CPU time 4.22 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:48:08 PM PDT 24
Peak memory 211312 kb
Host smart-b9ff0cfd-422c-4043-ae01-2ac243d7a08b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661026613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1661026613
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1854113286
Short name T794
Test name
Test status
Simulation time 85713369 ps
CPU time 4.15 seconds
Started Mar 24 12:48:29 PM PDT 24
Finished Mar 24 12:48:33 PM PDT 24
Peak memory 211252 kb
Host smart-ccdd48fc-887f-4ff6-9ed3-ba2d5609bb84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854113286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1854113286
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1642353896
Short name T778
Test name
Test status
Simulation time 7549559938 ps
CPU time 39.79 seconds
Started Mar 24 12:48:32 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 211348 kb
Host smart-e3b4d9e7-9050-439e-8f98-d75fd00027b1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642353896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1642353896
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3571629568
Short name T852
Test name
Test status
Simulation time 7345371430 ps
CPU time 71.81 seconds
Started Mar 24 12:48:05 PM PDT 24
Finished Mar 24 12:49:17 PM PDT 24
Peak memory 211412 kb
Host smart-bc7bda65-8ce6-4b3f-98ee-e591468e8185
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571629568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3571629568
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2447560295
Short name T720
Test name
Test status
Simulation time 4237432391 ps
CPU time 10.46 seconds
Started Mar 24 12:48:30 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 211212 kb
Host smart-718ecc66-abc5-4fa1-a192-c7686f9d50f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447560295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2447560295
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2549560533
Short name T799
Test name
Test status
Simulation time 1909836327 ps
CPU time 16.94 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:20 PM PDT 24
Peak memory 211324 kb
Host smart-0ad7be4a-2143-4891-9132-fe818e5496a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549560533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2549560533
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2255127295
Short name T708
Test name
Test status
Simulation time 710355756 ps
CPU time 11.08 seconds
Started Mar 24 12:48:03 PM PDT 24
Finished Mar 24 12:48:14 PM PDT 24
Peak memory 219572 kb
Host smart-0e1effdf-268a-4038-993e-4189d086b47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255127295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2255127295
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3558492105
Short name T868
Test name
Test status
Simulation time 1884841655 ps
CPU time 12.7 seconds
Started Mar 24 12:48:31 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 219440 kb
Host smart-15d47ab1-54a7-43e2-aa41-af1cbf83868d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558492105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3558492105
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.389893634
Short name T132
Test name
Test status
Simulation time 1961261706 ps
CPU time 71.33 seconds
Started Mar 24 12:48:04 PM PDT 24
Finished Mar 24 12:49:16 PM PDT 24
Peak memory 212240 kb
Host smart-23c5ced2-dc06-47e9-b3bf-57db7e259360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389893634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.389893634
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4207641377
Short name T726
Test name
Test status
Simulation time 588834228 ps
CPU time 39.54 seconds
Started Mar 24 12:48:34 PM PDT 24
Finished Mar 24 12:49:14 PM PDT 24
Peak memory 212016 kb
Host smart-38cddde4-97c5-4598-a77a-2dc3b10b30f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207641377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4207641377
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2229088487
Short name T911
Test name
Test status
Simulation time 475044067 ps
CPU time 7.22 seconds
Started Mar 24 12:47:36 PM PDT 24
Finished Mar 24 12:47:43 PM PDT 24
Peak memory 211300 kb
Host smart-0274f288-4e48-46c1-b577-9d67ce721e2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229088487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2229088487
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3478773015
Short name T848
Test name
Test status
Simulation time 171959876 ps
CPU time 4.27 seconds
Started Mar 24 12:48:11 PM PDT 24
Finished Mar 24 12:48:16 PM PDT 24
Peak memory 211304 kb
Host smart-5689558a-89b5-4a35-a2a9-694cd1bedb5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478773015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3478773015
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.151774605
Short name T861
Test name
Test status
Simulation time 2966179131 ps
CPU time 12.84 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:52 PM PDT 24
Peak memory 211316 kb
Host smart-fae0b0c9-80f5-4a94-9523-c19fbf892332
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151774605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.151774605
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4284032
Short name T682
Test name
Test status
Simulation time 372426169 ps
CPU time 6.81 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:22 PM PDT 24
Peak memory 211284 kb
Host smart-36bb6b9f-5fe6-4bca-9196-d6ca67a47a97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bas
h.4284032
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2877922367
Short name T894
Test name
Test status
Simulation time 1689992037 ps
CPU time 12.68 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:22 PM PDT 24
Peak memory 211324 kb
Host smart-631aa323-1f14-4a3c-b95d-df1da8086609
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877922367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2877922367
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.793314995
Short name T800
Test name
Test status
Simulation time 342120080 ps
CPU time 5.62 seconds
Started Mar 24 12:47:49 PM PDT 24
Finished Mar 24 12:47:55 PM PDT 24
Peak memory 211160 kb
Host smart-1a303aae-4af7-4c42-95d3-0c786d9fa65d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793314995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.793314995
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.190554884
Short name T820
Test name
Test status
Simulation time 1014105584 ps
CPU time 12.12 seconds
Started Mar 24 12:47:41 PM PDT 24
Finished Mar 24 12:47:53 PM PDT 24
Peak memory 219512 kb
Host smart-8312692a-87c4-442c-aa5d-ec8ff563eb2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190554884 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.190554884
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3219620254
Short name T887
Test name
Test status
Simulation time 231635341 ps
CPU time 6.07 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:16 PM PDT 24
Peak memory 219472 kb
Host smart-269fda15-445f-4433-8fed-bd67e4445fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219620254 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3219620254
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1245068623
Short name T758
Test name
Test status
Simulation time 273349262 ps
CPU time 5.69 seconds
Started Mar 24 12:48:13 PM PDT 24
Finished Mar 24 12:48:19 PM PDT 24
Peak memory 211276 kb
Host smart-328ef548-0261-49ac-aef7-79e00da10b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245068623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1245068623
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2745670961
Short name T738
Test name
Test status
Simulation time 1110700224 ps
CPU time 10.92 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:49 PM PDT 24
Peak memory 211320 kb
Host smart-bcb40f97-2e83-4890-8606-6b46b56223d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745670961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2745670961
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.330831953
Short name T707
Test name
Test status
Simulation time 1317012966 ps
CPU time 6.54 seconds
Started Mar 24 12:47:44 PM PDT 24
Finished Mar 24 12:47:51 PM PDT 24
Peak memory 211200 kb
Host smart-59220394-c9bd-4504-a69b-5df2fdcbfa89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330831953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.330831953
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.676777707
Short name T809
Test name
Test status
Simulation time 89007936 ps
CPU time 4.18 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:13 PM PDT 24
Peak memory 211124 kb
Host smart-b93fb2e1-cac3-43b5-8b23-6836ec3bc02e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676777707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.676777707
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1381695345
Short name T828
Test name
Test status
Simulation time 2100049165 ps
CPU time 11.77 seconds
Started Mar 24 12:47:37 PM PDT 24
Finished Mar 24 12:47:48 PM PDT 24
Peak memory 211204 kb
Host smart-9653ec22-4ec2-47e1-bd15-096f007e0636
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381695345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1381695345
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2431990660
Short name T855
Test name
Test status
Simulation time 4304276580 ps
CPU time 17.25 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:33 PM PDT 24
Peak memory 211272 kb
Host smart-0566e3b1-269b-4b46-9e49-ba68d6d79bf8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431990660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2431990660
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1452850663
Short name T90
Test name
Test status
Simulation time 54129417435 ps
CPU time 64.59 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 211384 kb
Host smart-b5278e8f-4a67-420c-bb93-d9bc20266803
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452850663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1452850663
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1570437975
Short name T95
Test name
Test status
Simulation time 12097244010 ps
CPU time 93.32 seconds
Started Mar 24 12:48:11 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 211248 kb
Host smart-54aab2e3-f979-40d4-b095-7c880d694d8b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570437975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1570437975
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3603593177
Short name T80
Test name
Test status
Simulation time 10224746547 ps
CPU time 11.39 seconds
Started Mar 24 12:47:39 PM PDT 24
Finished Mar 24 12:47:50 PM PDT 24
Peak memory 211432 kb
Host smart-0a473da1-fcd4-4a56-96e3-1db2a226bd8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603593177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3603593177
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.780741827
Short name T115
Test name
Test status
Simulation time 7238198352 ps
CPU time 13.64 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:30 PM PDT 24
Peak memory 211376 kb
Host smart-be2e4549-3039-4cf7-bbd6-2e82bf04a861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780741827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.780741827
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1366841825
Short name T718
Test name
Test status
Simulation time 1433205570 ps
CPU time 14.63 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 219576 kb
Host smart-940257b0-de85-42e7-8ebc-e607e73c1800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366841825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1366841825
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3719069215
Short name T722
Test name
Test status
Simulation time 175480198 ps
CPU time 7.57 seconds
Started Mar 24 12:47:38 PM PDT 24
Finished Mar 24 12:47:45 PM PDT 24
Peak memory 214556 kb
Host smart-7c0f6ecc-d75f-465c-8618-e224a2652254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719069215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3719069215
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1896066972
Short name T834
Test name
Test status
Simulation time 1995665260 ps
CPU time 69.99 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:49:25 PM PDT 24
Peak memory 211452 kb
Host smart-7d20c3fb-447d-4f67-8084-cacfa66b667d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896066972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1896066972
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2410545054
Short name T135
Test name
Test status
Simulation time 4591045902 ps
CPU time 77.31 seconds
Started Mar 24 12:47:41 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 219556 kb
Host smart-5f868b1f-e2ef-4bfc-9d00-3f04b51be8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410545054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2410545054
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1043108191
Short name T760
Test name
Test status
Simulation time 9352500425 ps
CPU time 16 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:48:26 PM PDT 24
Peak memory 211368 kb
Host smart-5f36797f-be4f-49ce-b018-c6d6fa74941c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043108191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1043108191
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3063798017
Short name T762
Test name
Test status
Simulation time 1352250719 ps
CPU time 12.87 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:55 PM PDT 24
Peak memory 211260 kb
Host smart-2c76f299-9202-475d-a508-c7fed3d36413
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063798017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3063798017
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1211134786
Short name T715
Test name
Test status
Simulation time 1316553753 ps
CPU time 12.55 seconds
Started Mar 24 12:47:45 PM PDT 24
Finished Mar 24 12:47:58 PM PDT 24
Peak memory 211304 kb
Host smart-01b70aee-33cc-4646-9d59-bcecef3a7b6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211134786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1211134786
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.894834379
Short name T697
Test name
Test status
Simulation time 5262008286 ps
CPU time 15.5 seconds
Started Mar 24 12:48:11 PM PDT 24
Finished Mar 24 12:48:27 PM PDT 24
Peak memory 211364 kb
Host smart-01ec50ee-afc0-43dd-939b-9f366e3ac407
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894834379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.894834379
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.202793340
Short name T920
Test name
Test status
Simulation time 4256997472 ps
CPU time 17.3 seconds
Started Mar 24 12:47:43 PM PDT 24
Finished Mar 24 12:48:01 PM PDT 24
Peak memory 211216 kb
Host smart-52bed111-491a-4fbf-a647-81cfcd83ddde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202793340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.202793340
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.673552460
Short name T841
Test name
Test status
Simulation time 1008656167 ps
CPU time 12.03 seconds
Started Mar 24 12:48:12 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211320 kb
Host smart-d7b91d92-d57e-47e1-9d18-f25f4ed07aad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673552460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.673552460
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2013629557
Short name T713
Test name
Test status
Simulation time 509720816 ps
CPU time 4.88 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:47 PM PDT 24
Peak memory 219576 kb
Host smart-e8fd89e2-4163-4bb7-b231-1d2c73aeeb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013629557 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2013629557
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.875393823
Short name T699
Test name
Test status
Simulation time 1617746475 ps
CPU time 7.83 seconds
Started Mar 24 12:48:17 PM PDT 24
Finished Mar 24 12:48:24 PM PDT 24
Peak memory 219520 kb
Host smart-78e3cddc-b57b-4952-86dd-7ca048d1a52b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875393823 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.875393823
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1018182269
Short name T876
Test name
Test status
Simulation time 1269700510 ps
CPU time 11.21 seconds
Started Mar 24 12:48:12 PM PDT 24
Finished Mar 24 12:48:24 PM PDT 24
Peak memory 211308 kb
Host smart-b62cbb3d-859e-49d3-a23f-eb3afd3df100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018182269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1018182269
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1082378013
Short name T878
Test name
Test status
Simulation time 19980932072 ps
CPU time 13.14 seconds
Started Mar 24 12:47:45 PM PDT 24
Finished Mar 24 12:47:59 PM PDT 24
Peak memory 211400 kb
Host smart-7b5e4b70-d50f-4495-9033-f297fc1a1081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082378013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1082378013
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1606711462
Short name T789
Test name
Test status
Simulation time 89093178 ps
CPU time 4.24 seconds
Started Mar 24 12:47:45 PM PDT 24
Finished Mar 24 12:47:49 PM PDT 24
Peak memory 211192 kb
Host smart-97bf616b-34b3-4067-b56a-b34fbdc9322a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606711462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1606711462
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2719855734
Short name T705
Test name
Test status
Simulation time 5668918094 ps
CPU time 8.74 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211208 kb
Host smart-92245d94-7c06-4a0f-bbb6-1f9fc35b675e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719855734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2719855734
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1407174703
Short name T906
Test name
Test status
Simulation time 592129034 ps
CPU time 4.07 seconds
Started Mar 24 12:47:40 PM PDT 24
Finished Mar 24 12:47:44 PM PDT 24
Peak memory 211268 kb
Host smart-45439c02-e31f-4e5f-bcb2-2a410cb7bd5a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407174703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1407174703
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1918082011
Short name T884
Test name
Test status
Simulation time 9136356476 ps
CPU time 15.47 seconds
Started Mar 24 12:48:09 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211336 kb
Host smart-740a7ba0-e93a-4b25-ad06-a944cd0322ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918082011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1918082011
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3703688328
Short name T94
Test name
Test status
Simulation time 1105560782 ps
CPU time 27.43 seconds
Started Mar 24 12:47:44 PM PDT 24
Finished Mar 24 12:48:12 PM PDT 24
Peak memory 211304 kb
Host smart-2229698f-1cfd-4b23-bdd9-f971f2aa469a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703688328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3703688328
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.954290825
Short name T756
Test name
Test status
Simulation time 10138265479 ps
CPU time 37.88 seconds
Started Mar 24 12:48:11 PM PDT 24
Finished Mar 24 12:48:49 PM PDT 24
Peak memory 211384 kb
Host smart-feb7e6c3-ae7f-41b7-b20b-f6da16aed20d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954290825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.954290825
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3490674112
Short name T842
Test name
Test status
Simulation time 1259529379 ps
CPU time 13.65 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:56 PM PDT 24
Peak memory 211288 kb
Host smart-678fdaff-1fc9-4d77-a473-e799527fbae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490674112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3490674112
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.628325212
Short name T733
Test name
Test status
Simulation time 1382890193 ps
CPU time 4.54 seconds
Started Mar 24 12:48:13 PM PDT 24
Finished Mar 24 12:48:18 PM PDT 24
Peak memory 211292 kb
Host smart-7e43ec70-dc4b-4060-9aa0-5640776bb5de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628325212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.628325212
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.323625951
Short name T710
Test name
Test status
Simulation time 209297142 ps
CPU time 8.49 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:48:19 PM PDT 24
Peak memory 219812 kb
Host smart-29280b06-ca10-43dc-b444-1744b67d0ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323625951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.323625951
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.390576302
Short name T698
Test name
Test status
Simulation time 3053626745 ps
CPU time 16.47 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:59 PM PDT 24
Peak memory 219628 kb
Host smart-7ad227a4-4e5b-4641-84db-28567d4767d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390576302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.390576302
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3218907456
Short name T73
Test name
Test status
Simulation time 1895322341 ps
CPU time 45.1 seconds
Started Mar 24 12:47:48 PM PDT 24
Finished Mar 24 12:48:34 PM PDT 24
Peak memory 212932 kb
Host smart-25ebfa49-eced-4a36-abe9-e99b854e781e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218907456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3218907456
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4010294567
Short name T766
Test name
Test status
Simulation time 3257336759 ps
CPU time 76.18 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:49:32 PM PDT 24
Peak memory 212384 kb
Host smart-9a2dbfff-8d5e-45da-b448-6dcf089ded0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010294567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4010294567
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2666134572
Short name T892
Test name
Test status
Simulation time 520323984 ps
CPU time 4.21 seconds
Started Mar 24 12:48:12 PM PDT 24
Finished Mar 24 12:48:17 PM PDT 24
Peak memory 211308 kb
Host smart-b5393c84-5c6b-4c3d-b0e0-d97b12c4a87a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666134572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2666134572
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.723238707
Short name T903
Test name
Test status
Simulation time 10980879364 ps
CPU time 16.1 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:58 PM PDT 24
Peak memory 211352 kb
Host smart-305f52a8-5307-4cbe-a084-208684c34313
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723238707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.723238707
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3934066005
Short name T751
Test name
Test status
Simulation time 3172260097 ps
CPU time 13.35 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:55 PM PDT 24
Peak memory 211184 kb
Host smart-ce502b2f-f560-40f6-80ff-c887be9975d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934066005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3934066005
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.430476805
Short name T913
Test name
Test status
Simulation time 1601386467 ps
CPU time 13.92 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:29 PM PDT 24
Peak memory 211308 kb
Host smart-0d9e16e6-5853-42b7-93e4-7929e4dd9714
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430476805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.430476805
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3077819959
Short name T97
Test name
Test status
Simulation time 4590954092 ps
CPU time 14.11 seconds
Started Mar 24 12:48:11 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211584 kb
Host smart-f0c8c34b-61a3-41b3-aaa6-d0d39764dffb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077819959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3077819959
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3164443065
Short name T730
Test name
Test status
Simulation time 15473112275 ps
CPU time 16.65 seconds
Started Mar 24 12:47:46 PM PDT 24
Finished Mar 24 12:48:03 PM PDT 24
Peak memory 211396 kb
Host smart-8f8eda99-af68-4b13-a0af-09ed00b94c50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164443065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3164443065
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1642460833
Short name T875
Test name
Test status
Simulation time 1502874224 ps
CPU time 12.94 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 219540 kb
Host smart-ee823a93-22ce-4112-8358-b3fb32540c17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642460833 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1642460833
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2310532575
Short name T881
Test name
Test status
Simulation time 692647713 ps
CPU time 8.39 seconds
Started Mar 24 12:47:45 PM PDT 24
Finished Mar 24 12:47:54 PM PDT 24
Peak memory 212800 kb
Host smart-658a2eb5-9aca-4257-ae5f-177d4ad4703b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310532575 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2310532575
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3879126130
Short name T690
Test name
Test status
Simulation time 4641686809 ps
CPU time 10.99 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:48:21 PM PDT 24
Peak memory 211596 kb
Host smart-96a03662-dc31-4874-8091-7a167dce062b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879126130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3879126130
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4166968560
Short name T117
Test name
Test status
Simulation time 565794753 ps
CPU time 6.19 seconds
Started Mar 24 12:47:44 PM PDT 24
Finished Mar 24 12:47:51 PM PDT 24
Peak memory 211196 kb
Host smart-afe5882b-42ed-4891-bd94-178e0a912729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166968560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4166968560
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.528058766
Short name T734
Test name
Test status
Simulation time 756193975 ps
CPU time 8.81 seconds
Started Mar 24 12:47:44 PM PDT 24
Finished Mar 24 12:47:53 PM PDT 24
Peak memory 211192 kb
Host smart-8d9ff150-0ce5-4ed5-89dd-86725568a81d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528058766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.528058766
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.95168098
Short name T741
Test name
Test status
Simulation time 3922167102 ps
CPU time 10.12 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 210524 kb
Host smart-e0dba83d-2722-489d-ab6e-f37fdf6f6dee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95168098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.95168098
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.672071681
Short name T798
Test name
Test status
Simulation time 533952291 ps
CPU time 7.7 seconds
Started Mar 24 12:47:43 PM PDT 24
Finished Mar 24 12:47:51 PM PDT 24
Peak memory 211252 kb
Host smart-ec208548-942d-4dba-8cdc-29dd7ebb6bb4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672071681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
672071681
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.772522554
Short name T922
Test name
Test status
Simulation time 19001137062 ps
CPU time 13.04 seconds
Started Mar 24 12:48:08 PM PDT 24
Finished Mar 24 12:48:21 PM PDT 24
Peak memory 211292 kb
Host smart-937e7bca-ad5d-43b4-87e4-bf471cd3e9d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772522554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
772522554
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1739117423
Short name T844
Test name
Test status
Simulation time 26330034010 ps
CPU time 53.28 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:49:04 PM PDT 24
Peak memory 211372 kb
Host smart-ba1a84ac-7af4-4c3f-a50e-ba97225ddf16
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739117423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1739117423
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1878381476
Short name T796
Test name
Test status
Simulation time 12134684825 ps
CPU time 65.04 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:48:48 PM PDT 24
Peak memory 211360 kb
Host smart-8c6aff07-df79-461c-9c5d-69250695e3a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878381476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1878381476
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3445492205
Short name T777
Test name
Test status
Simulation time 37712802233 ps
CPU time 15.68 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:48:26 PM PDT 24
Peak memory 211432 kb
Host smart-efbadc80-4e58-493f-9c37-c93b47e303b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445492205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3445492205
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4089132738
Short name T111
Test name
Test status
Simulation time 1657662460 ps
CPU time 4.19 seconds
Started Mar 24 12:47:44 PM PDT 24
Finished Mar 24 12:47:48 PM PDT 24
Peak memory 211256 kb
Host smart-a268fe4c-7a6a-4bf4-94e2-8689db14f6dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089132738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4089132738
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2311787275
Short name T687
Test name
Test status
Simulation time 200492265 ps
CPU time 10.16 seconds
Started Mar 24 12:47:47 PM PDT 24
Finished Mar 24 12:47:57 PM PDT 24
Peak memory 219560 kb
Host smart-5d5e1a67-c50f-4b64-9bab-ae41cfe3b73c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311787275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2311787275
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.675301778
Short name T865
Test name
Test status
Simulation time 346716818 ps
CPU time 7.6 seconds
Started Mar 24 12:48:13 PM PDT 24
Finished Mar 24 12:48:21 PM PDT 24
Peak memory 219568 kb
Host smart-0f162fcb-3710-4290-afb9-da4fb898afea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675301778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.675301778
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1814827129
Short name T125
Test name
Test status
Simulation time 985333911 ps
CPU time 41.77 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 211816 kb
Host smart-3a93033f-5c3d-4e07-bcc4-478c4013abcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814827129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1814827129
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3068084770
Short name T134
Test name
Test status
Simulation time 4404933209 ps
CPU time 78.52 seconds
Started Mar 24 12:47:41 PM PDT 24
Finished Mar 24 12:49:00 PM PDT 24
Peak memory 212636 kb
Host smart-b900b9a9-024e-4b3e-a0c4-a9694dea4116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068084770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3068084770
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2176134262
Short name T849
Test name
Test status
Simulation time 964422733 ps
CPU time 7.65 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:50 PM PDT 24
Peak memory 219564 kb
Host smart-a3919bc2-fd4e-4497-b094-181c74972b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176134262 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2176134262
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2591299181
Short name T919
Test name
Test status
Simulation time 1858750144 ps
CPU time 9.89 seconds
Started Mar 24 12:48:17 PM PDT 24
Finished Mar 24 12:48:27 PM PDT 24
Peak memory 219376 kb
Host smart-d4bf77a4-7b71-4e62-8e5a-93040c9810bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591299181 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2591299181
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2194936296
Short name T91
Test name
Test status
Simulation time 332885944 ps
CPU time 4.2 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:47:47 PM PDT 24
Peak memory 211272 kb
Host smart-86624e13-35c9-4e60-92ad-e0ed6f13d2ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194936296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2194936296
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.37460169
Short name T755
Test name
Test status
Simulation time 8226761940 ps
CPU time 14.25 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211412 kb
Host smart-603845c2-8b1c-4ea0-9c01-43ea1f87e0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.37460169
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2769242578
Short name T885
Test name
Test status
Simulation time 4012197715 ps
CPU time 37.27 seconds
Started Mar 24 12:47:42 PM PDT 24
Finished Mar 24 12:48:20 PM PDT 24
Peak memory 211412 kb
Host smart-574f3f79-af89-42e8-b13e-b1518c968a75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769242578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2769242578
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4121758549
Short name T822
Test name
Test status
Simulation time 8096547716 ps
CPU time 41.47 seconds
Started Mar 24 12:48:10 PM PDT 24
Finished Mar 24 12:48:52 PM PDT 24
Peak memory 211440 kb
Host smart-361e233e-10f7-413b-9552-b6301888c15d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121758549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4121758549
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1202156199
Short name T816
Test name
Test status
Simulation time 721381671 ps
CPU time 8.8 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211292 kb
Host smart-1be06548-3f48-4950-be76-b4fd7eae1f24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202156199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1202156199
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.24590151
Short name T716
Test name
Test status
Simulation time 492686879 ps
CPU time 7.56 seconds
Started Mar 24 12:47:47 PM PDT 24
Finished Mar 24 12:47:55 PM PDT 24
Peak memory 211312 kb
Host smart-a760b48b-a036-46bf-b384-b9448afc79dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctr
l_same_csr_outstanding.24590151
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2247220246
Short name T902
Test name
Test status
Simulation time 5298308947 ps
CPU time 16.61 seconds
Started Mar 24 12:47:45 PM PDT 24
Finished Mar 24 12:48:02 PM PDT 24
Peak memory 219632 kb
Host smart-2ff97a87-1d94-4488-9347-b4caf524d985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247220246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2247220246
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2263872573
Short name T706
Test name
Test status
Simulation time 10348759922 ps
CPU time 19.2 seconds
Started Mar 24 12:48:12 PM PDT 24
Finished Mar 24 12:48:32 PM PDT 24
Peak memory 219580 kb
Host smart-5aaa15b2-72fd-481e-a5d5-c792eabb9220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263872573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2263872573
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1635868155
Short name T711
Test name
Test status
Simulation time 1904094943 ps
CPU time 77.32 seconds
Started Mar 24 12:47:43 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 212276 kb
Host smart-cc2758be-1236-456b-85fb-ec96dc3bfceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635868155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1635868155
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3460594501
Short name T128
Test name
Test status
Simulation time 9435211158 ps
CPU time 78.92 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:49:35 PM PDT 24
Peak memory 212448 kb
Host smart-4c8b0ae2-64e1-4b95-98b9-793f635f8b35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460594501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3460594501
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1049375119
Short name T742
Test name
Test status
Simulation time 7272088673 ps
CPU time 13.84 seconds
Started Mar 24 12:47:52 PM PDT 24
Finished Mar 24 12:48:06 PM PDT 24
Peak memory 219624 kb
Host smart-834ab799-9ceb-45d0-8af1-34f1ce693e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049375119 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1049375119
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3301174945
Short name T686
Test name
Test status
Simulation time 1831073250 ps
CPU time 14.79 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:30 PM PDT 24
Peak memory 214260 kb
Host smart-79818bb2-c3ac-474f-b7d9-1cd80c7a7fa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301174945 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3301174945
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.201522497
Short name T792
Test name
Test status
Simulation time 86516284 ps
CPU time 4.12 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:47:55 PM PDT 24
Peak memory 211284 kb
Host smart-a308ef81-bb5d-41b9-ada6-0cddb305af0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201522497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.201522497
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2571486231
Short name T724
Test name
Test status
Simulation time 555084755 ps
CPU time 4.12 seconds
Started Mar 24 12:48:17 PM PDT 24
Finished Mar 24 12:48:21 PM PDT 24
Peak memory 211144 kb
Host smart-ad708a82-a264-4fea-a636-9a29b63523c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571486231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2571486231
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2982216897
Short name T732
Test name
Test status
Simulation time 56312625264 ps
CPU time 90.3 seconds
Started Mar 24 12:47:43 PM PDT 24
Finished Mar 24 12:49:14 PM PDT 24
Peak memory 211376 kb
Host smart-78c14b81-f70a-4ce3-83bc-732957bd1b5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982216897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2982216897
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3587908424
Short name T819
Test name
Test status
Simulation time 6965064460 ps
CPU time 58.74 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:49:15 PM PDT 24
Peak memory 211420 kb
Host smart-ba0ab351-6147-4ddb-be5f-a55c0f9885bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587908424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3587908424
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1878041056
Short name T114
Test name
Test status
Simulation time 396340018 ps
CPU time 4.26 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:21 PM PDT 24
Peak memory 211328 kb
Host smart-5647d6e1-7bcd-484c-a3ff-46e50731127c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878041056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1878041056
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3356891249
Short name T898
Test name
Test status
Simulation time 98546811 ps
CPU time 6.42 seconds
Started Mar 24 12:47:52 PM PDT 24
Finished Mar 24 12:47:58 PM PDT 24
Peak memory 211548 kb
Host smart-2798ca5d-84c8-46ae-91bb-c1c8a2bf410f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356891249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3356891249
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2646349427
Short name T826
Test name
Test status
Simulation time 109930320 ps
CPU time 7.46 seconds
Started Mar 24 12:47:50 PM PDT 24
Finished Mar 24 12:47:58 PM PDT 24
Peak memory 219564 kb
Host smart-b6f45404-41e9-437c-8f73-7a7d87f44b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646349427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2646349427
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2880107688
Short name T840
Test name
Test status
Simulation time 1834277302 ps
CPU time 13.69 seconds
Started Mar 24 12:48:14 PM PDT 24
Finished Mar 24 12:48:28 PM PDT 24
Peak memory 219564 kb
Host smart-19e36d31-2237-40fb-a721-ce67aade16b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880107688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2880107688
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2350818656
Short name T851
Test name
Test status
Simulation time 2274276472 ps
CPU time 79.21 seconds
Started Mar 24 12:47:54 PM PDT 24
Finished Mar 24 12:49:14 PM PDT 24
Peak memory 212052 kb
Host smart-230964e2-cadf-4064-9a4b-524b01d68ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350818656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2350818656
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2683341141
Short name T831
Test name
Test status
Simulation time 17904028839 ps
CPU time 76.02 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:49:31 PM PDT 24
Peak memory 211536 kb
Host smart-0640e3da-8848-444d-a096-84a6fb0cc6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683341141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2683341141
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3404542567
Short name T696
Test name
Test status
Simulation time 142904362 ps
CPU time 4.69 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:21 PM PDT 24
Peak memory 219492 kb
Host smart-d0c68ebe-87dd-4e04-a842-3b100cf2cf7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404542567 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3404542567
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4267923392
Short name T688
Test name
Test status
Simulation time 663241786 ps
CPU time 8.05 seconds
Started Mar 24 12:47:50 PM PDT 24
Finished Mar 24 12:47:58 PM PDT 24
Peak memory 219456 kb
Host smart-b5556964-d307-49a5-bcab-f68862762ede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267923392 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4267923392
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2903952363
Short name T921
Test name
Test status
Simulation time 8518274729 ps
CPU time 10.59 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:27 PM PDT 24
Peak memory 211400 kb
Host smart-733f51b4-d532-4e77-ae1b-5aa4ca590139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903952363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2903952363
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3094209076
Short name T79
Test name
Test status
Simulation time 175429346 ps
CPU time 4.07 seconds
Started Mar 24 12:47:48 PM PDT 24
Finished Mar 24 12:47:52 PM PDT 24
Peak memory 211332 kb
Host smart-f8684ae3-87a8-4028-90ad-a6d5bbec1061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094209076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3094209076
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3779103373
Short name T908
Test name
Test status
Simulation time 2255628060 ps
CPU time 27.94 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 211424 kb
Host smart-38ce6980-58b8-4271-a44e-3c563ac2aa88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779103373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3779103373
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.933500230
Short name T82
Test name
Test status
Simulation time 380661454 ps
CPU time 18.64 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:48:10 PM PDT 24
Peak memory 211344 kb
Host smart-68cb725b-7833-4026-b80b-15c565405c09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933500230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.933500230
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1914782274
Short name T811
Test name
Test status
Simulation time 637439449 ps
CPU time 4.3 seconds
Started Mar 24 12:47:50 PM PDT 24
Finished Mar 24 12:47:54 PM PDT 24
Peak memory 211340 kb
Host smart-7670c49d-fa58-4d0c-a5bc-9e6567d49bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914782274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1914782274
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2394885831
Short name T109
Test name
Test status
Simulation time 630630125 ps
CPU time 8.1 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 211296 kb
Host smart-2cf529bd-8a2b-48d2-bd1d-439009224464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394885831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2394885831
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1907612740
Short name T683
Test name
Test status
Simulation time 206641634 ps
CPU time 8.53 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:24 PM PDT 24
Peak memory 219480 kb
Host smart-07d837c4-402d-4b93-ae0b-b735ded1fb33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907612740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1907612740
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3139916524
Short name T689
Test name
Test status
Simulation time 416225478 ps
CPU time 10.92 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:48:02 PM PDT 24
Peak memory 219568 kb
Host smart-b3015d17-827a-4ecd-a8b8-7908306d8242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139916524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3139916524
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4234886023
Short name T126
Test name
Test status
Simulation time 1050872718 ps
CPU time 38.19 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:48:30 PM PDT 24
Peak memory 211320 kb
Host smart-819fdf72-f131-4375-b3a6-940a668cad27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234886023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4234886023
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.545533926
Short name T131
Test name
Test status
Simulation time 1752725568 ps
CPU time 76.55 seconds
Started Mar 24 12:48:16 PM PDT 24
Finished Mar 24 12:49:33 PM PDT 24
Peak memory 211320 kb
Host smart-c6c88d10-6c7c-440a-9728-29b04ee3e249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545533926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.545533926
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.157378800
Short name T684
Test name
Test status
Simulation time 567914859 ps
CPU time 7.9 seconds
Started Mar 24 12:47:48 PM PDT 24
Finished Mar 24 12:47:56 PM PDT 24
Peak memory 219424 kb
Host smart-0d54252e-9d2a-40f4-b3d4-4c77c8f4f42d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157378800 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.157378800
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1728737665
Short name T723
Test name
Test status
Simulation time 5089831013 ps
CPU time 8.05 seconds
Started Mar 24 12:48:14 PM PDT 24
Finished Mar 24 12:48:23 PM PDT 24
Peak memory 219628 kb
Host smart-08546bee-46af-473e-bfaa-38e9b3513c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728737665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1728737665
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1063577635
Short name T76
Test name
Test status
Simulation time 439153288 ps
CPU time 4.18 seconds
Started Mar 24 12:48:21 PM PDT 24
Finished Mar 24 12:48:25 PM PDT 24
Peak memory 211280 kb
Host smart-0b820dd2-5d95-42a5-bc5b-3c729a17365f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063577635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1063577635
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.108988008
Short name T795
Test name
Test status
Simulation time 508854782 ps
CPU time 7.3 seconds
Started Mar 24 12:47:50 PM PDT 24
Finished Mar 24 12:47:57 PM PDT 24
Peak memory 211292 kb
Host smart-fb46abb2-600d-40b8-ad82-dc228ee4c02f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108988008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.108988008
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2965797789
Short name T786
Test name
Test status
Simulation time 46255219488 ps
CPU time 92.62 seconds
Started Mar 24 12:47:52 PM PDT 24
Finished Mar 24 12:49:25 PM PDT 24
Peak memory 211420 kb
Host smart-85b59f38-4fc1-425b-8ce1-87c5515dd0e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965797789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2965797789
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3827565435
Short name T767
Test name
Test status
Simulation time 19166989179 ps
CPU time 47.73 seconds
Started Mar 24 12:48:17 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 211196 kb
Host smart-0bff2f5b-5c88-430a-970d-aa82367926b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827565435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3827565435
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3747428412
Short name T806
Test name
Test status
Simulation time 1744191945 ps
CPU time 14.3 seconds
Started Mar 24 12:47:54 PM PDT 24
Finished Mar 24 12:48:09 PM PDT 24
Peak memory 211312 kb
Host smart-3046f5b2-12ec-4e8b-8712-8548b5f555a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747428412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3747428412
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.448717974
Short name T112
Test name
Test status
Simulation time 89012083 ps
CPU time 4.34 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:20 PM PDT 24
Peak memory 211296 kb
Host smart-8d51bb00-1ac6-45a8-9cb4-76a886ef561a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448717974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.448717974
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.572153893
Short name T709
Test name
Test status
Simulation time 333066744 ps
CPU time 7.33 seconds
Started Mar 24 12:47:50 PM PDT 24
Finished Mar 24 12:47:58 PM PDT 24
Peak memory 219536 kb
Host smart-9b681a29-875b-4b4e-a6bd-2a37d4bf8ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572153893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.572153893
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.653717780
Short name T685
Test name
Test status
Simulation time 5119145374 ps
CPU time 13.88 seconds
Started Mar 24 12:48:15 PM PDT 24
Finished Mar 24 12:48:29 PM PDT 24
Peak memory 219540 kb
Host smart-7275b13f-d54e-463e-a3f7-29c0c89d49b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653717780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.653717780
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2242100926
Short name T845
Test name
Test status
Simulation time 34678994841 ps
CPU time 76.28 seconds
Started Mar 24 12:48:14 PM PDT 24
Finished Mar 24 12:49:31 PM PDT 24
Peak memory 212436 kb
Host smart-b63e2285-f859-445e-8478-b8485733c986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242100926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2242100926
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2585746753
Short name T916
Test name
Test status
Simulation time 361971597 ps
CPU time 71.31 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 219488 kb
Host smart-0ab7bf8f-e2a3-4bd1-a995-948a1a894b03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585746753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2585746753
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.110579614
Short name T725
Test name
Test status
Simulation time 1858926256 ps
CPU time 16.1 seconds
Started Mar 24 12:47:50 PM PDT 24
Finished Mar 24 12:48:06 PM PDT 24
Peak memory 219528 kb
Host smart-8163e642-ab0c-429e-a1cb-aabc0b8f18aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110579614 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.110579614
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.886610218
Short name T719
Test name
Test status
Simulation time 434436070 ps
CPU time 7.52 seconds
Started Mar 24 12:48:18 PM PDT 24
Finished Mar 24 12:48:26 PM PDT 24
Peak memory 215088 kb
Host smart-d6cd51f2-1d3f-4294-987f-6c4f4ec32992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886610218 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.886610218
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1508282172
Short name T84
Test name
Test status
Simulation time 649393915 ps
CPU time 8.22 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:47:59 PM PDT 24
Peak memory 211544 kb
Host smart-545f583f-9868-405e-b0f9-f79dc4f4311c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508282172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1508282172
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4056271215
Short name T116
Test name
Test status
Simulation time 1515732677 ps
CPU time 8.42 seconds
Started Mar 24 12:48:23 PM PDT 24
Finished Mar 24 12:48:31 PM PDT 24
Peak memory 211336 kb
Host smart-2253514c-7fa1-4fed-a906-e4c2d7ee503d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056271215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4056271215
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2537718023
Short name T863
Test name
Test status
Simulation time 7578101573 ps
CPU time 62.51 seconds
Started Mar 24 12:47:49 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 212388 kb
Host smart-00219f4b-adfc-40aa-be0c-6b0ebdc919ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537718023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2537718023
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.447399667
Short name T83
Test name
Test status
Simulation time 17533132431 ps
CPU time 65.32 seconds
Started Mar 24 12:48:17 PM PDT 24
Finished Mar 24 12:49:23 PM PDT 24
Peak memory 211384 kb
Host smart-f87ecef6-299a-4c2f-b120-043d79b6f182
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447399667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.447399667
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1472748083
Short name T744
Test name
Test status
Simulation time 8964480462 ps
CPU time 14.67 seconds
Started Mar 24 12:48:21 PM PDT 24
Finished Mar 24 12:48:37 PM PDT 24
Peak memory 211348 kb
Host smart-3cf5b58d-0036-4bb3-9781-13939cc9e66f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472748083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1472748083
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2512652632
Short name T113
Test name
Test status
Simulation time 2190935911 ps
CPU time 12.52 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:48:04 PM PDT 24
Peak memory 211344 kb
Host smart-fbf9da2e-64fd-402f-a6ad-4c044fca37c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512652632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2512652632
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2298120150
Short name T793
Test name
Test status
Simulation time 347543086 ps
CPU time 6.37 seconds
Started Mar 24 12:48:17 PM PDT 24
Finished Mar 24 12:48:24 PM PDT 24
Peak memory 219540 kb
Host smart-51b3cc7f-78d5-413e-998a-3a2a9c2b3274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298120150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2298120150
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3534886065
Short name T771
Test name
Test status
Simulation time 1203392872 ps
CPU time 11.06 seconds
Started Mar 24 12:47:51 PM PDT 24
Finished Mar 24 12:48:03 PM PDT 24
Peak memory 219548 kb
Host smart-d935e841-a40c-49b7-b87b-48daeae4afa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534886065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3534886065
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3225140918
Short name T693
Test name
Test status
Simulation time 4858570905 ps
CPU time 41.1 seconds
Started Mar 24 12:48:20 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 211536 kb
Host smart-23995232-9293-4a56-9576-bea3b524cab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225140918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3225140918
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3733158734
Short name T917
Test name
Test status
Simulation time 1947391749 ps
CPU time 45.72 seconds
Started Mar 24 12:47:49 PM PDT 24
Finished Mar 24 12:48:35 PM PDT 24
Peak memory 212104 kb
Host smart-3e08c98b-58f4-4e1e-8ed5-f36368f6e04a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733158734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3733158734
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3958298103
Short name T435
Test name
Test status
Simulation time 1762197065 ps
CPU time 14.02 seconds
Started Mar 24 12:56:53 PM PDT 24
Finished Mar 24 12:57:07 PM PDT 24
Peak memory 211156 kb
Host smart-f3c44c59-71cc-45ac-9b72-c7bd89d26938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958298103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3958298103
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.670042184
Short name T257
Test name
Test status
Simulation time 1526421635 ps
CPU time 13.21 seconds
Started Mar 24 01:07:55 PM PDT 24
Finished Mar 24 01:08:08 PM PDT 24
Peak memory 211156 kb
Host smart-97aa0944-2fc0-4e0f-8cfb-280d03746937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670042184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.670042184
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1214812667
Short name T508
Test name
Test status
Simulation time 221851176340 ps
CPU time 542.67 seconds
Started Mar 24 12:56:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 233812 kb
Host smart-211faaf7-cb3b-4eca-a6ea-2d7e44a22c72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214812667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1214812667
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2802653461
Short name T444
Test name
Test status
Simulation time 1060230084 ps
CPU time 68.39 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:09:00 PM PDT 24
Peak memory 212324 kb
Host smart-c665aca6-cfe7-480b-ba49-38ab878f8c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802653461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2802653461
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.277866857
Short name T672
Test name
Test status
Simulation time 665101372 ps
CPU time 9.23 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:08:03 PM PDT 24
Peak memory 211696 kb
Host smart-daeb444e-6682-4dda-a252-f79257cc3447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277866857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.277866857
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.534799724
Short name T543
Test name
Test status
Simulation time 1339949426 ps
CPU time 16.07 seconds
Started Mar 24 12:56:54 PM PDT 24
Finished Mar 24 12:57:11 PM PDT 24
Peak memory 211808 kb
Host smart-abbbc29d-f03e-4998-ab38-8caa11d848f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534799724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.534799724
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2059195021
Short name T527
Test name
Test status
Simulation time 1157284086 ps
CPU time 11.04 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:08:01 PM PDT 24
Peak memory 211036 kb
Host smart-21d8409e-5358-4d54-9c43-28810201a9e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059195021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2059195021
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2231132017
Short name T147
Test name
Test status
Simulation time 1524558162 ps
CPU time 14.07 seconds
Started Mar 24 12:56:54 PM PDT 24
Finished Mar 24 12:57:08 PM PDT 24
Peak memory 211068 kb
Host smart-630c1919-7b27-427b-83dd-c363c47c2e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231132017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2231132017
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2540735747
Short name T43
Test name
Test status
Simulation time 721261698 ps
CPU time 52.07 seconds
Started Mar 24 01:08:00 PM PDT 24
Finished Mar 24 01:08:52 PM PDT 24
Peak memory 232312 kb
Host smart-6871af93-12ae-4b62-84f9-7102c0a283f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540735747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2540735747
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.268837543
Short name T40
Test name
Test status
Simulation time 6912616059 ps
CPU time 105.97 seconds
Started Mar 24 12:56:54 PM PDT 24
Finished Mar 24 12:58:40 PM PDT 24
Peak memory 231576 kb
Host smart-76a45540-dabe-4a9c-a64c-5a8d18f7de44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268837543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.268837543
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.258566520
Short name T477
Test name
Test status
Simulation time 8328369925 ps
CPU time 18.47 seconds
Started Mar 24 01:07:50 PM PDT 24
Finished Mar 24 01:08:09 PM PDT 24
Peak memory 219408 kb
Host smart-0d4bcd48-e273-47fc-91ff-43ed2a4cbec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258566520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.258566520
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3290787183
Short name T568
Test name
Test status
Simulation time 8786561551 ps
CPU time 19.05 seconds
Started Mar 24 12:56:55 PM PDT 24
Finished Mar 24 12:57:14 PM PDT 24
Peak memory 214404 kb
Host smart-ee632a36-8e68-4701-9cce-f2099a271140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290787183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3290787183
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3218360129
Short name T245
Test name
Test status
Simulation time 4019473776 ps
CPU time 35.71 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 215092 kb
Host smart-91b626f8-55dc-4ac8-92bb-d5eded553ffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218360129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3218360129
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1820257749
Short name T450
Test name
Test status
Simulation time 121230380 ps
CPU time 4.26 seconds
Started Mar 24 12:57:00 PM PDT 24
Finished Mar 24 12:57:04 PM PDT 24
Peak memory 211112 kb
Host smart-16f889ea-56ef-43c9-b52a-6eed2daa8b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820257749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1820257749
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2901855973
Short name T229
Test name
Test status
Simulation time 1534192744 ps
CPU time 5.95 seconds
Started Mar 24 01:07:54 PM PDT 24
Finished Mar 24 01:08:00 PM PDT 24
Peak memory 211144 kb
Host smart-2a2ed316-2125-4e47-82bc-0afeda0f9d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901855973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2901855973
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1367114911
Short name T496
Test name
Test status
Simulation time 18163550638 ps
CPU time 191.15 seconds
Started Mar 24 12:56:55 PM PDT 24
Finished Mar 24 01:00:07 PM PDT 24
Peak memory 228864 kb
Host smart-738c3662-c339-4432-8f45-cc47ab555985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367114911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1367114911
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.275002901
Short name T363
Test name
Test status
Simulation time 177961988992 ps
CPU time 166.01 seconds
Started Mar 24 01:07:54 PM PDT 24
Finished Mar 24 01:10:41 PM PDT 24
Peak memory 241252 kb
Host smart-af7de397-3749-4f49-8404-0b7200939b7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275002901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.275002901
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.435498579
Short name T415
Test name
Test status
Simulation time 16511765555 ps
CPU time 33.62 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 212152 kb
Host smart-ea923990-886b-4e95-85ce-7b729e7155dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435498579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.435498579
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.797127693
Short name T262
Test name
Test status
Simulation time 754687950 ps
CPU time 14.69 seconds
Started Mar 24 12:56:56 PM PDT 24
Finished Mar 24 12:57:10 PM PDT 24
Peak memory 211848 kb
Host smart-be3f13c3-7582-4750-8a79-befb747f7948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797127693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.797127693
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1040511026
Short name T364
Test name
Test status
Simulation time 1091988612 ps
CPU time 7.33 seconds
Started Mar 24 01:07:56 PM PDT 24
Finished Mar 24 01:08:03 PM PDT 24
Peak memory 211108 kb
Host smart-b26fb12c-af29-4105-8a0b-f0b5897a230a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040511026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1040511026
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3091849168
Short name T217
Test name
Test status
Simulation time 2962708645 ps
CPU time 13.99 seconds
Started Mar 24 12:56:53 PM PDT 24
Finished Mar 24 12:57:07 PM PDT 24
Peak memory 211196 kb
Host smart-0ec2ce68-2bd1-48ef-9128-7e82dfd4711a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091849168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3091849168
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2174658357
Short name T41
Test name
Test status
Simulation time 804832207 ps
CPU time 65.34 seconds
Started Mar 24 12:56:54 PM PDT 24
Finished Mar 24 12:57:59 PM PDT 24
Peak memory 239336 kb
Host smart-5ff52fb0-2baa-4af7-9403-4824cf0f2180
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174658357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2174658357
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2499337250
Short name T35
Test name
Test status
Simulation time 6241790114 ps
CPU time 60.35 seconds
Started Mar 24 01:08:00 PM PDT 24
Finished Mar 24 01:09:00 PM PDT 24
Peak memory 236820 kb
Host smart-fac72dbf-3652-4550-b852-a4a2ca1af23c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499337250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2499337250
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1414271957
Short name T424
Test name
Test status
Simulation time 356156813 ps
CPU time 10.17 seconds
Started Mar 24 01:07:58 PM PDT 24
Finished Mar 24 01:08:08 PM PDT 24
Peak memory 219336 kb
Host smart-a17c1a70-0131-4e05-a397-b36918e6ce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414271957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1414271957
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3256487772
Short name T549
Test name
Test status
Simulation time 42118122874 ps
CPU time 39.93 seconds
Started Mar 24 12:56:54 PM PDT 24
Finished Mar 24 12:57:34 PM PDT 24
Peak memory 219420 kb
Host smart-735726bf-1590-499c-9fcf-712251396d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256487772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3256487772
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.360416692
Short name T679
Test name
Test status
Simulation time 4580094149 ps
CPU time 15.61 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:08:09 PM PDT 24
Peak memory 212500 kb
Host smart-20a4cfe3-136e-4e19-b1fe-309a970c270f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360416692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.360416692
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4171608906
Short name T397
Test name
Test status
Simulation time 23228082327 ps
CPU time 74.7 seconds
Started Mar 24 12:56:57 PM PDT 24
Finished Mar 24 12:58:11 PM PDT 24
Peak memory 219440 kb
Host smart-17ba237d-aac7-4101-a8c8-c9fa71cd25d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171608906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4171608906
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2704321792
Short name T470
Test name
Test status
Simulation time 991940452 ps
CPU time 6.17 seconds
Started Mar 24 01:08:10 PM PDT 24
Finished Mar 24 01:08:16 PM PDT 24
Peak memory 211156 kb
Host smart-44b2742a-94e1-402b-9f57-a029801424c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704321792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2704321792
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4015397823
Short name T455
Test name
Test status
Simulation time 3231798830 ps
CPU time 13.89 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:29 PM PDT 24
Peak memory 211288 kb
Host smart-36162370-69d9-4ae7-8259-d7335021f592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015397823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4015397823
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1802945055
Short name T540
Test name
Test status
Simulation time 23587800615 ps
CPU time 253.4 seconds
Started Mar 24 01:08:11 PM PDT 24
Finished Mar 24 01:12:25 PM PDT 24
Peak memory 211424 kb
Host smart-e4001317-19ed-4b1d-a52c-66eb481ece46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802945055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1802945055
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1997604555
Short name T243
Test name
Test status
Simulation time 8279686110 ps
CPU time 112 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 12:59:06 PM PDT 24
Peak memory 236804 kb
Host smart-1dde3ce4-cae4-4bc2-b287-d54f9a39758c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997604555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1997604555
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2428834153
Short name T447
Test name
Test status
Simulation time 9911567215 ps
CPU time 22.54 seconds
Started Mar 24 01:08:09 PM PDT 24
Finished Mar 24 01:08:32 PM PDT 24
Peak memory 212236 kb
Host smart-14d7ef7d-ee59-4e84-b553-1b17798bd7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428834153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2428834153
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3420806228
Short name T22
Test name
Test status
Simulation time 347532748 ps
CPU time 9.09 seconds
Started Mar 24 12:57:16 PM PDT 24
Finished Mar 24 12:57:25 PM PDT 24
Peak memory 211892 kb
Host smart-e76340fd-edda-410e-8c98-d1b9d249c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420806228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3420806228
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3010062579
Short name T646
Test name
Test status
Simulation time 197154326 ps
CPU time 5.66 seconds
Started Mar 24 01:08:10 PM PDT 24
Finished Mar 24 01:08:16 PM PDT 24
Peak memory 211100 kb
Host smart-c597a3f6-9398-404f-86fb-c56fb194e410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010062579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3010062579
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.533019353
Short name T250
Test name
Test status
Simulation time 387024660 ps
CPU time 5.68 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:20 PM PDT 24
Peak memory 210976 kb
Host smart-4ab27d50-85ee-4a9a-873e-35e78c4e5720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533019353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.533019353
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1759765079
Short name T100
Test name
Test status
Simulation time 557107774 ps
CPU time 13.92 seconds
Started Mar 24 12:57:16 PM PDT 24
Finished Mar 24 12:57:30 PM PDT 24
Peak memory 212916 kb
Host smart-81f1ccb2-a58f-4f54-974c-b6c8afbbdbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759765079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1759765079
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2662413509
Short name T565
Test name
Test status
Simulation time 2329946433 ps
CPU time 16.28 seconds
Started Mar 24 01:08:09 PM PDT 24
Finished Mar 24 01:08:25 PM PDT 24
Peak memory 213160 kb
Host smart-d08be840-4f08-4563-80ec-0f9cb76fc1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662413509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2662413509
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1768088538
Short name T671
Test name
Test status
Simulation time 7181754139 ps
CPU time 48.63 seconds
Started Mar 24 01:08:10 PM PDT 24
Finished Mar 24 01:08:59 PM PDT 24
Peak memory 219408 kb
Host smart-8e474692-ab31-4179-8f16-fc7bf9f68b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768088538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1768088538
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3562546057
Short name T570
Test name
Test status
Simulation time 92442427550 ps
CPU time 61.41 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 12:58:16 PM PDT 24
Peak memory 219408 kb
Host smart-ca35b1c8-fdba-41ee-9ca8-4db994dc7060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562546057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3562546057
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.117032070
Short name T120
Test name
Test status
Simulation time 53762146491 ps
CPU time 2068.91 seconds
Started Mar 24 12:57:23 PM PDT 24
Finished Mar 24 01:31:53 PM PDT 24
Peak memory 237184 kb
Host smart-af3817e4-4ba8-4ffe-adce-ec91db51bdc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117032070 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.117032070
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2289499269
Short name T564
Test name
Test status
Simulation time 378388291 ps
CPU time 4.4 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:18 PM PDT 24
Peak memory 211164 kb
Host smart-a3d34996-c262-4b82-9fe8-8d1affa1da84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289499269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2289499269
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2778086919
Short name T628
Test name
Test status
Simulation time 1737468260 ps
CPU time 14.43 seconds
Started Mar 24 12:57:17 PM PDT 24
Finished Mar 24 12:57:31 PM PDT 24
Peak memory 211120 kb
Host smart-7e269add-f051-4201-8649-5757b5b1de39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778086919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2778086919
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3159374811
Short name T342
Test name
Test status
Simulation time 15001897188 ps
CPU time 156.03 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:10:50 PM PDT 24
Peak memory 224752 kb
Host smart-b1e9753a-9549-4c25-b588-ed0097c5abda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159374811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3159374811
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3971114837
Short name T324
Test name
Test status
Simulation time 54895625265 ps
CPU time 302.17 seconds
Started Mar 24 12:57:16 PM PDT 24
Finished Mar 24 01:02:18 PM PDT 24
Peak memory 231032 kb
Host smart-8eb948a6-caff-497e-9444-313cea41ec43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971114837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3971114837
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.324651274
Short name T520
Test name
Test status
Simulation time 35492795024 ps
CPU time 34.74 seconds
Started Mar 24 12:57:19 PM PDT 24
Finished Mar 24 12:57:54 PM PDT 24
Peak memory 212084 kb
Host smart-ef801726-3f14-467d-b9b8-346cae3ca5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324651274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.324651274
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3366014840
Short name T330
Test name
Test status
Simulation time 8527169033 ps
CPU time 21.72 seconds
Started Mar 24 01:08:10 PM PDT 24
Finished Mar 24 01:08:32 PM PDT 24
Peak memory 211300 kb
Host smart-80fbd4d5-99df-49d1-a12c-ceb2311a778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366014840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3366014840
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2644480363
Short name T102
Test name
Test status
Simulation time 1203734721 ps
CPU time 12.43 seconds
Started Mar 24 01:08:11 PM PDT 24
Finished Mar 24 01:08:24 PM PDT 24
Peak memory 211056 kb
Host smart-28a8e69c-5fd1-4324-9643-72144a92b891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644480363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2644480363
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3743788247
Short name T428
Test name
Test status
Simulation time 7607351503 ps
CPU time 17.68 seconds
Started Mar 24 12:57:17 PM PDT 24
Finished Mar 24 12:57:35 PM PDT 24
Peak memory 211184 kb
Host smart-53af3fae-218d-45e0-8011-2b825f1b5a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743788247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3743788247
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.228124276
Short name T490
Test name
Test status
Simulation time 1548171758 ps
CPU time 21.83 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:37 PM PDT 24
Peak memory 219288 kb
Host smart-b63c1c2a-b57b-4da3-b02e-61cbc0632af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228124276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.228124276
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.901720965
Short name T191
Test name
Test status
Simulation time 7936076250 ps
CPU time 24.03 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:36 PM PDT 24
Peak memory 219412 kb
Host smart-c2c4eeda-da44-448c-bbd8-0d4d9059518c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901720965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.901720965
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2445091685
Short name T551
Test name
Test status
Simulation time 2469756060 ps
CPU time 25.83 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:41 PM PDT 24
Peak memory 213428 kb
Host smart-df330301-91ba-4700-af96-28114203405b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445091685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2445091685
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.293275073
Short name T665
Test name
Test status
Simulation time 913881200 ps
CPU time 27.69 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:42 PM PDT 24
Peak memory 219204 kb
Host smart-cb38eef7-ef1a-4611-b8fc-56316c778dcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293275073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.293275073
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1122523557
Short name T537
Test name
Test status
Simulation time 1331427226 ps
CPU time 12.39 seconds
Started Mar 24 01:08:10 PM PDT 24
Finished Mar 24 01:08:23 PM PDT 24
Peak memory 211204 kb
Host smart-589e245d-1f44-40e6-b1e6-54af34abecfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122523557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1122523557
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.307044565
Short name T325
Test name
Test status
Simulation time 88935560 ps
CPU time 4.19 seconds
Started Mar 24 12:57:18 PM PDT 24
Finished Mar 24 12:57:22 PM PDT 24
Peak memory 211084 kb
Host smart-e45273eb-bdb6-4ade-bc3b-e2eca50da4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307044565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.307044565
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2755444835
Short name T517
Test name
Test status
Simulation time 9723314610 ps
CPU time 103.35 seconds
Started Mar 24 01:08:11 PM PDT 24
Finished Mar 24 01:09:55 PM PDT 24
Peak memory 236560 kb
Host smart-6e1b4524-f6b7-458d-9633-a661238d7d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755444835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2755444835
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3950331029
Short name T24
Test name
Test status
Simulation time 43916817096 ps
CPU time 254.87 seconds
Started Mar 24 12:57:24 PM PDT 24
Finished Mar 24 01:01:40 PM PDT 24
Peak memory 229416 kb
Host smart-d121ed46-9425-4ff0-9d63-97a94d3a3431
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950331029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3950331029
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.984423906
Short name T616
Test name
Test status
Simulation time 2740613031 ps
CPU time 13.72 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:28 PM PDT 24
Peak memory 211852 kb
Host smart-c9b1aacc-c5f9-4ee1-b40e-b655e8d5304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984423906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.984423906
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1189855982
Short name T224
Test name
Test status
Simulation time 454477030 ps
CPU time 5.8 seconds
Started Mar 24 01:08:11 PM PDT 24
Finished Mar 24 01:08:16 PM PDT 24
Peak memory 211092 kb
Host smart-fadf5c1f-0454-4392-b782-28ee1fc7eefb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189855982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1189855982
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1515925934
Short name T590
Test name
Test status
Simulation time 191042112 ps
CPU time 5.35 seconds
Started Mar 24 12:57:23 PM PDT 24
Finished Mar 24 12:57:29 PM PDT 24
Peak memory 210976 kb
Host smart-686a7c32-750e-40d4-b448-3676fd9bfcd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515925934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1515925934
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.260853761
Short name T469
Test name
Test status
Simulation time 399472545 ps
CPU time 9.82 seconds
Started Mar 24 12:57:16 PM PDT 24
Finished Mar 24 12:57:26 PM PDT 24
Peak memory 219244 kb
Host smart-c5b91f38-c202-4615-a2f3-4daba2afde2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260853761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.260853761
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.534717043
Short name T329
Test name
Test status
Simulation time 2916172645 ps
CPU time 19.89 seconds
Started Mar 24 01:08:18 PM PDT 24
Finished Mar 24 01:08:38 PM PDT 24
Peak memory 214572 kb
Host smart-8a4209b9-8919-4c63-aee7-9106ecf1d21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534717043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.534717043
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3216278141
Short name T367
Test name
Test status
Simulation time 6317203590 ps
CPU time 52.42 seconds
Started Mar 24 01:08:11 PM PDT 24
Finished Mar 24 01:09:04 PM PDT 24
Peak memory 216180 kb
Host smart-cbcbe30e-8ae1-4f07-8e50-dc2e2e2f9746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216278141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3216278141
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.385569128
Short name T645
Test name
Test status
Simulation time 9011640738 ps
CPU time 38.06 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:53 PM PDT 24
Peak memory 219448 kb
Host smart-64076a08-9a23-4571-ba6b-2a0fe05c3d40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385569128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.385569128
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1147144233
Short name T280
Test name
Test status
Simulation time 1402107401 ps
CPU time 12.31 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 211192 kb
Host smart-7d54c102-2951-460e-969d-f53dba086265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147144233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1147144233
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2062129898
Short name T412
Test name
Test status
Simulation time 88963536 ps
CPU time 4.3 seconds
Started Mar 24 12:57:20 PM PDT 24
Finished Mar 24 12:57:25 PM PDT 24
Peak memory 211204 kb
Host smart-adb06182-19f2-44fb-bb1a-572531a160c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062129898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2062129898
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3176313782
Short name T55
Test name
Test status
Simulation time 31190405924 ps
CPU time 349.67 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:14:01 PM PDT 24
Peak memory 229808 kb
Host smart-c7370324-1b99-4f42-8b0a-df68d89b6b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176313782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3176313782
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3372130617
Short name T655
Test name
Test status
Simulation time 165818815872 ps
CPU time 402.05 seconds
Started Mar 24 12:57:23 PM PDT 24
Finished Mar 24 01:04:06 PM PDT 24
Peak memory 229376 kb
Host smart-12c1c525-9e0e-4c84-8fa2-1a29e63535de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372130617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3372130617
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.654366636
Short name T315
Test name
Test status
Simulation time 10175382073 ps
CPU time 25.32 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:37 PM PDT 24
Peak memory 212224 kb
Host smart-0b21c72b-98d5-42cb-8c4a-fdf2c57e0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654366636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.654366636
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.97084889
Short name T244
Test name
Test status
Simulation time 3777301003 ps
CPU time 15.45 seconds
Started Mar 24 12:57:21 PM PDT 24
Finished Mar 24 12:57:37 PM PDT 24
Peak memory 211848 kb
Host smart-487f66f4-92ac-41e2-9eb9-6c18eeb23f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97084889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.97084889
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.455987644
Short name T483
Test name
Test status
Simulation time 4922337883 ps
CPU time 12.84 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:25 PM PDT 24
Peak memory 211204 kb
Host smart-ab62b491-3280-47a4-bd6e-ea6a15a7a053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455987644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.455987644
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.936973943
Short name T406
Test name
Test status
Simulation time 2108026119 ps
CPU time 7.6 seconds
Started Mar 24 12:57:17 PM PDT 24
Finished Mar 24 12:57:25 PM PDT 24
Peak memory 211096 kb
Host smart-872618ce-9fc0-4565-97a0-7afcaf741663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936973943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.936973943
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1696096435
Short name T89
Test name
Test status
Simulation time 187326215 ps
CPU time 10.38 seconds
Started Mar 24 01:08:18 PM PDT 24
Finished Mar 24 01:08:28 PM PDT 24
Peak memory 213160 kb
Host smart-3a3f76e2-949b-4de0-8078-2e60aa56bcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696096435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1696096435
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.332583734
Short name T535
Test name
Test status
Simulation time 4449756364 ps
CPU time 49.38 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:58:04 PM PDT 24
Peak memory 213400 kb
Host smart-1ed78a73-b9fc-49ce-87ac-0b5316bb4844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332583734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.332583734
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3261818076
Short name T197
Test name
Test status
Simulation time 4760583422 ps
CPU time 33.22 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 216552 kb
Host smart-60301637-c8f8-4986-9f60-e0ec1efd2cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261818076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3261818076
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4044802705
Short name T649
Test name
Test status
Simulation time 76197902943 ps
CPU time 67.2 seconds
Started Mar 24 12:57:18 PM PDT 24
Finished Mar 24 12:58:25 PM PDT 24
Peak memory 217432 kb
Host smart-d77b4cd7-1c61-44ee-a61e-e23e57a5b01e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044802705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4044802705
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4231529523
Short name T292
Test name
Test status
Simulation time 2686748323 ps
CPU time 15.82 seconds
Started Mar 24 12:57:19 PM PDT 24
Finished Mar 24 12:57:35 PM PDT 24
Peak memory 211288 kb
Host smart-c13b8bc3-fa7d-4e00-a044-b4ceb4c8f75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231529523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4231529523
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.889549712
Short name T226
Test name
Test status
Simulation time 93941400 ps
CPU time 4.3 seconds
Started Mar 24 01:08:11 PM PDT 24
Finished Mar 24 01:08:15 PM PDT 24
Peak memory 211204 kb
Host smart-bab422f0-1c31-4981-bc1d-4688698ef308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889549712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.889549712
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1470457026
Short name T585
Test name
Test status
Simulation time 4004298397 ps
CPU time 132.47 seconds
Started Mar 24 12:57:26 PM PDT 24
Finished Mar 24 12:59:39 PM PDT 24
Peak memory 228724 kb
Host smart-7da822ea-3a96-4a11-89d9-1851bb3c4922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470457026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1470457026
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3905920402
Short name T617
Test name
Test status
Simulation time 1570282690 ps
CPU time 52.36 seconds
Started Mar 24 01:08:15 PM PDT 24
Finished Mar 24 01:09:07 PM PDT 24
Peak memory 237156 kb
Host smart-472c19d9-5a17-447d-95a6-b1e7c5ccbe88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905920402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3905920402
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.216514916
Short name T609
Test name
Test status
Simulation time 4807585622 ps
CPU time 23.56 seconds
Started Mar 24 12:57:19 PM PDT 24
Finished Mar 24 12:57:43 PM PDT 24
Peak memory 212268 kb
Host smart-83b8b1df-f3c9-49aa-8e98-f567edf4d6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216514916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.216514916
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1715421890
Short name T502
Test name
Test status
Simulation time 228813149 ps
CPU time 5.3 seconds
Started Mar 24 12:57:20 PM PDT 24
Finished Mar 24 12:57:26 PM PDT 24
Peak memory 211072 kb
Host smart-625bba70-480b-4ea9-a69d-6248760a77c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715421890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1715421890
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.492125245
Short name T60
Test name
Test status
Simulation time 1163035364 ps
CPU time 11.75 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:24 PM PDT 24
Peak memory 211088 kb
Host smart-e8363b86-98c8-470c-b475-96c398f8e015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492125245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.492125245
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.283894277
Short name T487
Test name
Test status
Simulation time 10958396785 ps
CPU time 32.4 seconds
Started Mar 24 01:08:18 PM PDT 24
Finished Mar 24 01:08:50 PM PDT 24
Peak memory 213960 kb
Host smart-bec10d7f-4cda-4eeb-a93e-2f6acd650299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283894277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.283894277
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3736321502
Short name T373
Test name
Test status
Simulation time 3735105020 ps
CPU time 26.33 seconds
Started Mar 24 12:57:26 PM PDT 24
Finished Mar 24 12:57:52 PM PDT 24
Peak memory 212984 kb
Host smart-50255cbb-a54b-4c28-a394-8954e9617f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736321502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3736321502
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1080950196
Short name T165
Test name
Test status
Simulation time 1638283844 ps
CPU time 20.25 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:34 PM PDT 24
Peak memory 219200 kb
Host smart-6309dccb-26c2-4846-9b5b-6c95e68d4678
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080950196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1080950196
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.584950616
Short name T506
Test name
Test status
Simulation time 2762968895 ps
CPU time 16.92 seconds
Started Mar 24 12:57:26 PM PDT 24
Finished Mar 24 12:57:43 PM PDT 24
Peak memory 211168 kb
Host smart-d0578470-e398-4293-aca8-3e29cbd98322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584950616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.584950616
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.299228358
Short name T121
Test name
Test status
Simulation time 45040905755 ps
CPU time 1704.73 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:36:39 PM PDT 24
Peak memory 235844 kb
Host smart-35555178-8b2e-48a7-84e8-67accba0f3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299228358 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.299228358
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2622825837
Short name T272
Test name
Test status
Simulation time 2196028269 ps
CPU time 8.79 seconds
Started Mar 24 12:57:22 PM PDT 24
Finished Mar 24 12:57:31 PM PDT 24
Peak memory 211312 kb
Host smart-069ed814-df2f-429d-8286-f164a952f03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622825837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2622825837
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3043570412
Short name T77
Test name
Test status
Simulation time 347769626 ps
CPU time 4.21 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:18 PM PDT 24
Peak memory 211172 kb
Host smart-df1c6ed5-4234-46ab-9fe9-ac9c86bf0244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043570412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3043570412
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3415179917
Short name T271
Test name
Test status
Simulation time 29418713807 ps
CPU time 222 seconds
Started Mar 24 12:57:22 PM PDT 24
Finished Mar 24 01:01:05 PM PDT 24
Peak memory 213476 kb
Host smart-44a74180-9a33-461f-b15d-2ddefd40e82d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415179917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3415179917
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.644410253
Short name T107
Test name
Test status
Simulation time 95904279958 ps
CPU time 151.45 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:10:44 PM PDT 24
Peak memory 219564 kb
Host smart-11901d94-e53b-46aa-b765-e558b413f5e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644410253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.644410253
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.156990856
Short name T599
Test name
Test status
Simulation time 2072060841 ps
CPU time 9.36 seconds
Started Mar 24 01:08:15 PM PDT 24
Finished Mar 24 01:08:25 PM PDT 24
Peak memory 211888 kb
Host smart-83d61177-a241-41ba-a7b2-b703240c0429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156990856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.156990856
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.286598347
Short name T205
Test name
Test status
Simulation time 497333565 ps
CPU time 12.9 seconds
Started Mar 24 12:57:21 PM PDT 24
Finished Mar 24 12:57:35 PM PDT 24
Peak memory 212000 kb
Host smart-cc8d018d-bfee-43a9-bfd8-30ce12422953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286598347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.286598347
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1844745698
Short name T372
Test name
Test status
Simulation time 1388357345 ps
CPU time 13.25 seconds
Started Mar 24 12:57:20 PM PDT 24
Finished Mar 24 12:57:34 PM PDT 24
Peak memory 211096 kb
Host smart-68410742-b026-43a4-9cf8-7bca6716cd5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844745698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1844745698
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3977023384
Short name T495
Test name
Test status
Simulation time 1495133526 ps
CPU time 14.95 seconds
Started Mar 24 01:08:15 PM PDT 24
Finished Mar 24 01:08:30 PM PDT 24
Peak memory 211080 kb
Host smart-6d283424-443b-4dba-95af-e46d4d533382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977023384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3977023384
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.315722609
Short name T47
Test name
Test status
Simulation time 7546704468 ps
CPU time 23.52 seconds
Started Mar 24 01:08:15 PM PDT 24
Finished Mar 24 01:08:39 PM PDT 24
Peak memory 219444 kb
Host smart-49dcf99b-17ea-4fbc-86f5-ae33eed43e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315722609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.315722609
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.885812206
Short name T53
Test name
Test status
Simulation time 2993563702 ps
CPU time 25.98 seconds
Started Mar 24 12:57:21 PM PDT 24
Finished Mar 24 12:57:48 PM PDT 24
Peak memory 219444 kb
Host smart-8349c181-70bc-434a-80fd-ac0be631ba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885812206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.885812206
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.160193674
Short name T473
Test name
Test status
Simulation time 2172866642 ps
CPU time 8.96 seconds
Started Mar 24 12:57:22 PM PDT 24
Finished Mar 24 12:57:31 PM PDT 24
Peak memory 211300 kb
Host smart-8e771125-df17-4d60-9140-7f679681b06a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160193674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.160193674
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2291915379
Short name T407
Test name
Test status
Simulation time 6727256030 ps
CPU time 27.45 seconds
Started Mar 24 01:08:10 PM PDT 24
Finished Mar 24 01:08:37 PM PDT 24
Peak memory 217088 kb
Host smart-558a35a2-7835-4312-b356-fc15658d9096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291915379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2291915379
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1729076754
Short name T344
Test name
Test status
Simulation time 2251858734 ps
CPU time 11.13 seconds
Started Mar 24 01:08:16 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 211240 kb
Host smart-93f58fe1-f457-400c-9a90-b1c98f10432e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729076754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1729076754
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1942675741
Short name T392
Test name
Test status
Simulation time 3922232931 ps
CPU time 15.58 seconds
Started Mar 24 12:57:24 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 211284 kb
Host smart-9adc603c-d2f0-4615-b986-f3f4abd46f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942675741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1942675741
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1558928165
Short name T346
Test name
Test status
Simulation time 2179914471 ps
CPU time 61.82 seconds
Started Mar 24 01:08:19 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 219560 kb
Host smart-dfb68e11-302a-4afb-9644-474ed266256d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558928165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1558928165
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2402891816
Short name T657
Test name
Test status
Simulation time 9270147728 ps
CPU time 223.14 seconds
Started Mar 24 12:57:23 PM PDT 24
Finished Mar 24 01:01:07 PM PDT 24
Peak memory 212472 kb
Host smart-09a7288d-d8a9-4e62-a9fe-555db5545765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402891816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2402891816
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1329573040
Short name T479
Test name
Test status
Simulation time 3948647690 ps
CPU time 32.28 seconds
Started Mar 24 12:57:27 PM PDT 24
Finished Mar 24 12:57:59 PM PDT 24
Peak memory 211788 kb
Host smart-62ae49c4-a375-4698-828b-dc99b26d16f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329573040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1329573040
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.941577694
Short name T144
Test name
Test status
Simulation time 4452367435 ps
CPU time 16.81 seconds
Started Mar 24 01:08:16 PM PDT 24
Finished Mar 24 01:08:33 PM PDT 24
Peak memory 212308 kb
Host smart-5515fb41-1a16-4d5a-8bdc-ccba80b5d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941577694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.941577694
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1701089613
Short name T571
Test name
Test status
Simulation time 1074616043 ps
CPU time 11.39 seconds
Started Mar 24 01:08:15 PM PDT 24
Finished Mar 24 01:08:26 PM PDT 24
Peak memory 211048 kb
Host smart-a3d12081-7cdd-44ae-b78c-d3e0d495639c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701089613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1701089613
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.255300137
Short name T253
Test name
Test status
Simulation time 378274320 ps
CPU time 5.24 seconds
Started Mar 24 12:57:20 PM PDT 24
Finished Mar 24 12:57:26 PM PDT 24
Peak memory 211108 kb
Host smart-6d5a5ed2-fb70-4a6e-8014-7f418cb4a80d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255300137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.255300137
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3681760017
Short name T631
Test name
Test status
Simulation time 12430403879 ps
CPU time 39.45 seconds
Started Mar 24 12:57:19 PM PDT 24
Finished Mar 24 12:57:59 PM PDT 24
Peak memory 219436 kb
Host smart-96b2297e-a7d7-468d-86bf-3188e9f8decf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681760017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3681760017
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3913746429
Short name T214
Test name
Test status
Simulation time 720077425 ps
CPU time 10.44 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:24 PM PDT 24
Peak memory 213012 kb
Host smart-f447ab95-53ef-4e17-8d88-db4776236f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913746429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3913746429
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3772927260
Short name T246
Test name
Test status
Simulation time 480902399 ps
CPU time 9.23 seconds
Started Mar 24 01:08:18 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 211144 kb
Host smart-f2e72b7c-aa46-454c-b479-5e5a7e082c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772927260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3772927260
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.483008169
Short name T151
Test name
Test status
Simulation time 13235139698 ps
CPU time 28.09 seconds
Started Mar 24 12:57:22 PM PDT 24
Finished Mar 24 12:57:50 PM PDT 24
Peak memory 214472 kb
Host smart-8a041de4-43f8-44b4-9b19-f2fa57ad7af6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483008169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.483008169
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1575112652
Short name T305
Test name
Test status
Simulation time 347935127 ps
CPU time 4.21 seconds
Started Mar 24 01:08:15 PM PDT 24
Finished Mar 24 01:08:20 PM PDT 24
Peak memory 211084 kb
Host smart-e8c7a2c2-3de1-4233-8b5d-0fe89229cca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575112652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1575112652
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2359906321
Short name T176
Test name
Test status
Simulation time 4417011159 ps
CPU time 10.5 seconds
Started Mar 24 12:57:24 PM PDT 24
Finished Mar 24 12:57:35 PM PDT 24
Peak memory 211348 kb
Host smart-b4af57f3-1443-4fd7-8dd7-51b173d897a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359906321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2359906321
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2918791488
Short name T557
Test name
Test status
Simulation time 57388105114 ps
CPU time 192.93 seconds
Started Mar 24 01:08:19 PM PDT 24
Finished Mar 24 01:11:32 PM PDT 24
Peak memory 213564 kb
Host smart-bdde07f1-f4b6-4851-adf2-5b8e8f40d8d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918791488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2918791488
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2953718565
Short name T519
Test name
Test status
Simulation time 3881564321 ps
CPU time 74.72 seconds
Started Mar 24 12:57:25 PM PDT 24
Finished Mar 24 12:58:40 PM PDT 24
Peak memory 236856 kb
Host smart-20fc32a3-ba99-4a3d-b38a-09cfb32d4b51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953718565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2953718565
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2903241790
Short name T194
Test name
Test status
Simulation time 193481582 ps
CPU time 9.04 seconds
Started Mar 24 01:08:16 PM PDT 24
Finished Mar 24 01:08:26 PM PDT 24
Peak memory 211840 kb
Host smart-412e86b1-69e5-4b9c-aab4-966c5956113e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903241790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2903241790
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3398101107
Short name T600
Test name
Test status
Simulation time 1040887257 ps
CPU time 12.62 seconds
Started Mar 24 12:57:25 PM PDT 24
Finished Mar 24 12:57:38 PM PDT 24
Peak memory 211196 kb
Host smart-8ba12cb2-faa1-4b4b-be8e-f63f7d48b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398101107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3398101107
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3866739407
Short name T336
Test name
Test status
Simulation time 1769245603 ps
CPU time 15.74 seconds
Started Mar 24 01:08:19 PM PDT 24
Finished Mar 24 01:08:35 PM PDT 24
Peak memory 211060 kb
Host smart-990af412-67b8-44e0-bd29-5231caa29c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866739407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3866739407
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.452987926
Short name T103
Test name
Test status
Simulation time 185272235 ps
CPU time 5.69 seconds
Started Mar 24 12:57:25 PM PDT 24
Finished Mar 24 12:57:31 PM PDT 24
Peak memory 211300 kb
Host smart-dd015cc8-c24a-4ef6-b9e5-b335b8970e2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452987926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.452987926
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2089432148
Short name T267
Test name
Test status
Simulation time 1866016965 ps
CPU time 17.8 seconds
Started Mar 24 01:08:16 PM PDT 24
Finished Mar 24 01:08:34 PM PDT 24
Peak memory 219344 kb
Host smart-ebec7525-8f0b-49af-a4b5-c6137a7966ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089432148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2089432148
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3452249251
Short name T70
Test name
Test status
Simulation time 3171255339 ps
CPU time 22.05 seconds
Started Mar 24 12:57:26 PM PDT 24
Finished Mar 24 12:57:48 PM PDT 24
Peak memory 213716 kb
Host smart-1dd5db72-2f7f-42ae-ba5b-a0d267facf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452249251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3452249251
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1205242819
Short name T658
Test name
Test status
Simulation time 11870442620 ps
CPU time 44.5 seconds
Started Mar 24 01:08:17 PM PDT 24
Finished Mar 24 01:09:02 PM PDT 24
Peak memory 219456 kb
Host smart-de3c7753-8e06-4fb9-85ee-09fb3fcefcbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205242819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1205242819
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3303858724
Short name T288
Test name
Test status
Simulation time 456106547 ps
CPU time 7.83 seconds
Started Mar 24 12:57:26 PM PDT 24
Finished Mar 24 12:57:34 PM PDT 24
Peak memory 211120 kb
Host smart-fe8e3abe-67ee-457c-b1b2-b7b1822c7cea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303858724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3303858724
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1227726281
Short name T283
Test name
Test status
Simulation time 5431146454 ps
CPU time 105.09 seconds
Started Mar 24 01:08:16 PM PDT 24
Finished Mar 24 01:10:02 PM PDT 24
Peak memory 221236 kb
Host smart-fc90bafb-d155-49ca-8294-4eac3e15a483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227726281 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1227726281
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1594138516
Short name T172
Test name
Test status
Simulation time 1454237435 ps
CPU time 12.92 seconds
Started Mar 24 12:57:26 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 211180 kb
Host smart-61cd52d7-7ab6-4972-a465-c845e68e82fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594138516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1594138516
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2241552615
Short name T210
Test name
Test status
Simulation time 346233882 ps
CPU time 6.53 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:08:26 PM PDT 24
Peak memory 211168 kb
Host smart-f869b708-d071-4c04-9d5b-c9659bbdcdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241552615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2241552615
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3502827882
Short name T252
Test name
Test status
Simulation time 56159495499 ps
CPU time 206.57 seconds
Started Mar 24 12:57:24 PM PDT 24
Finished Mar 24 01:00:51 PM PDT 24
Peak memory 234776 kb
Host smart-e74ee8ec-4cad-4dca-9eb3-ffa11568e279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502827882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3502827882
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1982052768
Short name T158
Test name
Test status
Simulation time 3537659163 ps
CPU time 29.37 seconds
Started Mar 24 12:57:25 PM PDT 24
Finished Mar 24 12:57:55 PM PDT 24
Peak memory 212120 kb
Host smart-e7878137-9a23-4e5b-8afe-7545b81afd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982052768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1982052768
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3715709602
Short name T472
Test name
Test status
Simulation time 2058592111 ps
CPU time 12.96 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 211744 kb
Host smart-51a44338-5b0f-4365-bdfb-16c32ae63b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715709602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3715709602
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2570010904
Short name T167
Test name
Test status
Simulation time 4631362623 ps
CPU time 12.15 seconds
Started Mar 24 01:08:16 PM PDT 24
Finished Mar 24 01:08:29 PM PDT 24
Peak memory 211096 kb
Host smart-35a334ee-a7ed-487e-a14f-5b36c8e68a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570010904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2570010904
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.592163476
Short name T380
Test name
Test status
Simulation time 607737985 ps
CPU time 6.11 seconds
Started Mar 24 12:57:23 PM PDT 24
Finished Mar 24 12:57:30 PM PDT 24
Peak memory 211028 kb
Host smart-8b255be6-8714-4d4d-aafc-cbf91a06001f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=592163476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.592163476
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1715649008
Short name T636
Test name
Test status
Simulation time 1878571590 ps
CPU time 14.76 seconds
Started Mar 24 12:57:27 PM PDT 24
Finished Mar 24 12:57:42 PM PDT 24
Peak memory 213168 kb
Host smart-3d18e267-3c1b-476a-9acc-61c3dbe6c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715649008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1715649008
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.809373916
Short name T497
Test name
Test status
Simulation time 755549209 ps
CPU time 10.62 seconds
Started Mar 24 01:08:17 PM PDT 24
Finished Mar 24 01:08:28 PM PDT 24
Peak memory 219320 kb
Host smart-8901dd7d-d7a3-401c-b8ce-f5b0c1fa1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809373916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.809373916
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1754336923
Short name T140
Test name
Test status
Simulation time 20042108990 ps
CPU time 45.03 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:59 PM PDT 24
Peak memory 219388 kb
Host smart-79ee4a53-fc98-405e-96a5-b5122d94cd15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754336923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1754336923
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3675627015
Short name T574
Test name
Test status
Simulation time 1065105095 ps
CPU time 14.45 seconds
Started Mar 24 12:57:25 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 219288 kb
Host smart-9cc68a5f-43f7-428c-931a-ed7ee0c82d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675627015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3675627015
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2742577695
Short name T162
Test name
Test status
Simulation time 2342767706 ps
CPU time 15.28 seconds
Started Mar 24 12:57:30 PM PDT 24
Finished Mar 24 12:57:46 PM PDT 24
Peak memory 211292 kb
Host smart-b265e03b-0366-4d06-924a-350a7f815b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742577695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2742577695
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.321731138
Short name T159
Test name
Test status
Simulation time 171860751 ps
CPU time 4.26 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:08:25 PM PDT 24
Peak memory 211196 kb
Host smart-e1a98bff-84b5-4963-98a1-8cf5fdaa67e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321731138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.321731138
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1123439041
Short name T31
Test name
Test status
Simulation time 1868967571 ps
CPU time 98.68 seconds
Started Mar 24 12:57:33 PM PDT 24
Finished Mar 24 12:59:12 PM PDT 24
Peak memory 237776 kb
Host smart-beda48be-b89c-4f05-8869-dd3868bf5488
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123439041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1123439041
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2788150310
Short name T378
Test name
Test status
Simulation time 28840717513 ps
CPU time 287.38 seconds
Started Mar 24 01:08:23 PM PDT 24
Finished Mar 24 01:13:10 PM PDT 24
Peak memory 228936 kb
Host smart-ce1ecb0d-c7ff-4a68-875c-5ab8cc2ee743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788150310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2788150310
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3108885067
Short name T573
Test name
Test status
Simulation time 2629546295 ps
CPU time 17.88 seconds
Started Mar 24 12:57:30 PM PDT 24
Finished Mar 24 12:57:48 PM PDT 24
Peak memory 211932 kb
Host smart-b99474d9-26a6-4363-9372-0610acbc5d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108885067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3108885067
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3586324907
Short name T6
Test name
Test status
Simulation time 12973047872 ps
CPU time 33.04 seconds
Started Mar 24 01:08:25 PM PDT 24
Finished Mar 24 01:08:58 PM PDT 24
Peak memory 212044 kb
Host smart-c3fbf3ba-e469-43e5-a01e-738131948f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586324907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3586324907
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3242977693
Short name T591
Test name
Test status
Simulation time 1978806453 ps
CPU time 11.27 seconds
Started Mar 24 01:08:22 PM PDT 24
Finished Mar 24 01:08:34 PM PDT 24
Peak memory 211084 kb
Host smart-b8ee72c6-d960-4815-8d76-039515a1fdc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242977693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3242977693
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.769002549
Short name T587
Test name
Test status
Simulation time 9521809529 ps
CPU time 16.83 seconds
Started Mar 24 12:57:31 PM PDT 24
Finished Mar 24 12:57:48 PM PDT 24
Peak memory 211220 kb
Host smart-a4acde47-dc2d-45f0-989f-4d5cceaf423a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769002549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.769002549
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1276486006
Short name T427
Test name
Test status
Simulation time 429347460 ps
CPU time 12.4 seconds
Started Mar 24 12:57:24 PM PDT 24
Finished Mar 24 12:57:37 PM PDT 24
Peak memory 219324 kb
Host smart-8d56069b-cb1f-4374-ad7d-10f44d87a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276486006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1276486006
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2953681313
Short name T489
Test name
Test status
Simulation time 759761985 ps
CPU time 16.16 seconds
Started Mar 24 01:08:34 PM PDT 24
Finished Mar 24 01:08:50 PM PDT 24
Peak memory 213212 kb
Host smart-0c4cc557-5227-4338-b364-6ac862fe9481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953681313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2953681313
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2816578412
Short name T417
Test name
Test status
Simulation time 2967841375 ps
CPU time 16.59 seconds
Started Mar 24 12:57:25 PM PDT 24
Finished Mar 24 12:57:42 PM PDT 24
Peak memory 211148 kb
Host smart-13f51ccf-22cb-4b9b-9cee-d0623eeb2aeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816578412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2816578412
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2880784722
Short name T88
Test name
Test status
Simulation time 213415744 ps
CPU time 13.72 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:08:34 PM PDT 24
Peak memory 213080 kb
Host smart-8dbbcea4-71d6-4302-b070-49308af676e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880784722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2880784722
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2876619508
Short name T366
Test name
Test status
Simulation time 1283732890 ps
CPU time 12.05 seconds
Started Mar 24 12:57:00 PM PDT 24
Finished Mar 24 12:57:12 PM PDT 24
Peak memory 211196 kb
Host smart-dd282c6b-7ecc-4c29-a6d5-e03bc25b9764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876619508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2876619508
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.606725189
Short name T395
Test name
Test status
Simulation time 7940160303 ps
CPU time 15.49 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:08:08 PM PDT 24
Peak memory 211304 kb
Host smart-b8798a21-df30-4cfe-ab5a-aa5a23f34760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606725189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.606725189
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1726180026
Short name T335
Test name
Test status
Simulation time 58734341383 ps
CPU time 158.3 seconds
Started Mar 24 12:57:02 PM PDT 24
Finished Mar 24 12:59:41 PM PDT 24
Peak memory 234184 kb
Host smart-4a357f58-9fa7-4214-a3aa-6b38bc431762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726180026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1726180026
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1010407993
Short name T354
Test name
Test status
Simulation time 2617899367 ps
CPU time 13.93 seconds
Started Mar 24 01:07:54 PM PDT 24
Finished Mar 24 01:08:08 PM PDT 24
Peak memory 211276 kb
Host smart-4fcaa4ba-87d7-4fe0-bbe5-434f42cdc2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010407993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1010407993
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.584968457
Short name T602
Test name
Test status
Simulation time 19925185182 ps
CPU time 25.54 seconds
Started Mar 24 12:57:04 PM PDT 24
Finished Mar 24 12:57:30 PM PDT 24
Peak memory 212392 kb
Host smart-fb0dc17f-1887-4d64-9011-aaa44e0517fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584968457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.584968457
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1270696272
Short name T499
Test name
Test status
Simulation time 897821400 ps
CPU time 7.05 seconds
Started Mar 24 01:07:55 PM PDT 24
Finished Mar 24 01:08:02 PM PDT 24
Peak memory 211064 kb
Host smart-f87579af-37b8-4ff2-a646-23b160520fa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270696272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1270696272
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2440109681
Short name T643
Test name
Test status
Simulation time 1901821695 ps
CPU time 15.9 seconds
Started Mar 24 12:57:02 PM PDT 24
Finished Mar 24 12:57:18 PM PDT 24
Peak memory 211100 kb
Host smart-f8eda411-0bf4-4084-8b3d-27dd0623db9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440109681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2440109681
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2252233464
Short name T44
Test name
Test status
Simulation time 4306139200 ps
CPU time 53.36 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:08:47 PM PDT 24
Peak memory 230504 kb
Host smart-53174844-f61c-48a4-abd4-50edd4da5c57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252233464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2252233464
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3405597849
Short name T36
Test name
Test status
Simulation time 506440580 ps
CPU time 104.98 seconds
Started Mar 24 12:57:04 PM PDT 24
Finished Mar 24 12:58:50 PM PDT 24
Peak memory 236740 kb
Host smart-af830157-5bb3-4b53-a32b-af02168ec60e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405597849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3405597849
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2719078528
Short name T405
Test name
Test status
Simulation time 10272161570 ps
CPU time 25.87 seconds
Started Mar 24 01:07:55 PM PDT 24
Finished Mar 24 01:08:21 PM PDT 24
Peak memory 219668 kb
Host smart-679933b7-0f4b-4455-aa9e-95174d52a407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719078528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2719078528
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3464784709
Short name T419
Test name
Test status
Simulation time 189904647 ps
CPU time 9.97 seconds
Started Mar 24 12:57:00 PM PDT 24
Finished Mar 24 12:57:10 PM PDT 24
Peak memory 213676 kb
Host smart-4e746114-4170-4f2d-b685-70605c5eb98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464784709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3464784709
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2254845477
Short name T209
Test name
Test status
Simulation time 2133728807 ps
CPU time 10.62 seconds
Started Mar 24 12:56:59 PM PDT 24
Finished Mar 24 12:57:10 PM PDT 24
Peak memory 212048 kb
Host smart-394c4038-dcde-45c2-9fbb-381d43b64ac9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254845477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2254845477
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3340986309
Short name T375
Test name
Test status
Simulation time 403421781 ps
CPU time 23.64 seconds
Started Mar 24 01:07:57 PM PDT 24
Finished Mar 24 01:08:21 PM PDT 24
Peak memory 219344 kb
Host smart-d5f42a8b-16cd-4e57-80b8-85ccba4e63d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340986309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3340986309
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1944126397
Short name T575
Test name
Test status
Simulation time 21508706432 ps
CPU time 814.38 seconds
Started Mar 24 01:08:00 PM PDT 24
Finished Mar 24 01:21:34 PM PDT 24
Peak memory 226800 kb
Host smart-6baa67a0-02c5-4140-9d48-90d0274582d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944126397 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1944126397
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2000767281
Short name T460
Test name
Test status
Simulation time 540580020 ps
CPU time 7.77 seconds
Started Mar 24 12:57:29 PM PDT 24
Finished Mar 24 12:57:37 PM PDT 24
Peak memory 211156 kb
Host smart-f6445be6-dec6-4a80-bf0b-4e63e50715a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000767281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2000767281
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.207394249
Short name T480
Test name
Test status
Simulation time 167941825 ps
CPU time 4.26 seconds
Started Mar 24 01:08:23 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 211160 kb
Host smart-dfb94d17-eadd-43bf-9315-92713a087eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207394249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.207394249
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1059195038
Short name T523
Test name
Test status
Simulation time 6514125007 ps
CPU time 92.17 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:10:02 PM PDT 24
Peak memory 229776 kb
Host smart-98eb255c-7cad-459b-a6c1-bf90566bbcde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059195038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1059195038
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3085251639
Short name T567
Test name
Test status
Simulation time 58901746525 ps
CPU time 208.29 seconds
Started Mar 24 12:57:28 PM PDT 24
Finished Mar 24 01:00:56 PM PDT 24
Peak memory 240012 kb
Host smart-e9488538-ef32-47bd-bcce-25adf5e3a53e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085251639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3085251639
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.387544270
Short name T156
Test name
Test status
Simulation time 343794721 ps
CPU time 11.64 seconds
Started Mar 24 12:57:29 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 211664 kb
Host smart-453d086e-4664-4e64-84bd-e8eccb5399c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387544270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.387544270
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3937647877
Short name T661
Test name
Test status
Simulation time 7035608414 ps
CPU time 31.19 seconds
Started Mar 24 01:08:22 PM PDT 24
Finished Mar 24 01:08:54 PM PDT 24
Peak memory 212392 kb
Host smart-c6414f18-0470-418c-b6a9-aff3922a5b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937647877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3937647877
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1799322229
Short name T482
Test name
Test status
Simulation time 4499289423 ps
CPU time 17.71 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:08:49 PM PDT 24
Peak memory 211232 kb
Host smart-ee1f680b-c88d-4f24-bc2c-63a90ab8a996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799322229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1799322229
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.890626373
Short name T188
Test name
Test status
Simulation time 596349933 ps
CPU time 8.27 seconds
Started Mar 24 12:57:31 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 211068 kb
Host smart-c352bb4a-5af7-487a-a0c8-7b9b67ada0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890626373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.890626373
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2126182732
Short name T157
Test name
Test status
Simulation time 15734345114 ps
CPU time 32.02 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:08:52 PM PDT 24
Peak memory 214164 kb
Host smart-95742220-d554-4352-8c45-661bb8ae9c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126182732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2126182732
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.605380887
Short name T410
Test name
Test status
Simulation time 4508144343 ps
CPU time 37.69 seconds
Started Mar 24 12:57:31 PM PDT 24
Finished Mar 24 12:58:09 PM PDT 24
Peak memory 219440 kb
Host smart-f729dbea-c2a7-4118-90aa-e86f3d48c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605380887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.605380887
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1709420463
Short name T388
Test name
Test status
Simulation time 2229051432 ps
CPU time 19.91 seconds
Started Mar 24 12:57:31 PM PDT 24
Finished Mar 24 12:57:51 PM PDT 24
Peak memory 216272 kb
Host smart-399bf4df-8e61-45a7-a4bd-68848791752a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709420463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1709420463
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4201697284
Short name T181
Test name
Test status
Simulation time 2355743368 ps
CPU time 25.54 seconds
Started Mar 24 01:08:25 PM PDT 24
Finished Mar 24 01:08:50 PM PDT 24
Peak memory 219348 kb
Host smart-a0eb6980-82c5-4e6d-985c-4f8a7a3c4b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201697284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4201697284
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1092413077
Short name T420
Test name
Test status
Simulation time 71393845996 ps
CPU time 1497.75 seconds
Started Mar 24 01:08:25 PM PDT 24
Finished Mar 24 01:33:23 PM PDT 24
Peak memory 236516 kb
Host smart-e63378bc-7e64-4fbe-9cb3-e0ce40195e08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092413077 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1092413077
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2016441779
Short name T66
Test name
Test status
Simulation time 61121789174 ps
CPU time 6038.69 seconds
Started Mar 24 12:57:31 PM PDT 24
Finished Mar 24 02:38:10 PM PDT 24
Peak memory 235780 kb
Host smart-1e67404e-a550-4d37-aabc-3e7aa08aacf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016441779 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2016441779
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3661877565
Short name T266
Test name
Test status
Simulation time 5987992709 ps
CPU time 11.2 seconds
Started Mar 24 01:08:18 PM PDT 24
Finished Mar 24 01:08:30 PM PDT 24
Peak memory 211292 kb
Host smart-5c60c2f8-6c1f-4d10-baca-59549eac0811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661877565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3661877565
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.755732409
Short name T306
Test name
Test status
Simulation time 3188357912 ps
CPU time 13.6 seconds
Started Mar 24 12:57:34 PM PDT 24
Finished Mar 24 12:57:48 PM PDT 24
Peak memory 211340 kb
Host smart-e47142f2-5e05-4b50-9237-db88c8024fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755732409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.755732409
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1131093305
Short name T56
Test name
Test status
Simulation time 22497903809 ps
CPU time 288.53 seconds
Started Mar 24 12:57:35 PM PDT 24
Finished Mar 24 01:02:24 PM PDT 24
Peak memory 233812 kb
Host smart-e3895a60-0d16-4c4b-a45f-5b800640566f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131093305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1131093305
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.24320400
Short name T313
Test name
Test status
Simulation time 9086229621 ps
CPU time 84.05 seconds
Started Mar 24 01:08:34 PM PDT 24
Finished Mar 24 01:09:59 PM PDT 24
Peak memory 230708 kb
Host smart-41cc3b0a-11be-414f-ad73-d115485c714b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_co
rrupt_sig_fatal_chk.24320400
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1101441628
Short name T8
Test name
Test status
Simulation time 6528958166 ps
CPU time 27.96 seconds
Started Mar 24 12:57:34 PM PDT 24
Finished Mar 24 12:58:03 PM PDT 24
Peak memory 212324 kb
Host smart-f04edea5-5d43-45e6-bc1c-216cbed74e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101441628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1101441628
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3899851315
Short name T630
Test name
Test status
Simulation time 692655585 ps
CPU time 9.21 seconds
Started Mar 24 01:08:22 PM PDT 24
Finished Mar 24 01:08:31 PM PDT 24
Peak memory 211940 kb
Host smart-74e8f10e-6812-4287-866c-f73cf4711106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899851315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3899851315
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1038078613
Short name T270
Test name
Test status
Simulation time 3282755703 ps
CPU time 9.82 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 211152 kb
Host smart-9db4efef-7ede-4730-aede-062100903b70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038078613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1038078613
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3247355226
Short name T187
Test name
Test status
Simulation time 194763551 ps
CPU time 5.37 seconds
Started Mar 24 12:57:34 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 211056 kb
Host smart-a207b525-6137-4a84-8daa-efefad93bed8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247355226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3247355226
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1146533778
Short name T218
Test name
Test status
Simulation time 1247391064 ps
CPU time 19.09 seconds
Started Mar 24 12:57:30 PM PDT 24
Finished Mar 24 12:57:49 PM PDT 24
Peak memory 219280 kb
Host smart-ff8865ae-d101-4eea-8d81-3e1345933738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146533778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1146533778
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3895395374
Short name T263
Test name
Test status
Simulation time 10845614304 ps
CPU time 27.29 seconds
Started Mar 24 01:08:21 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 213876 kb
Host smart-4feb9c84-b9b8-40dd-bfda-7ecca6e3f0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895395374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3895395374
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3453069146
Short name T189
Test name
Test status
Simulation time 714190194 ps
CPU time 9.48 seconds
Started Mar 24 12:57:28 PM PDT 24
Finished Mar 24 12:57:38 PM PDT 24
Peak memory 211136 kb
Host smart-e834f51f-526a-43d1-b23e-9cbb989439b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453069146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3453069146
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3882115622
Short name T180
Test name
Test status
Simulation time 1961244968 ps
CPU time 32.91 seconds
Started Mar 24 01:08:25 PM PDT 24
Finished Mar 24 01:08:58 PM PDT 24
Peak memory 211912 kb
Host smart-72da66d9-e431-4184-8b7c-be09e5bae76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882115622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3882115622
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.124052651
Short name T675
Test name
Test status
Simulation time 1251809505 ps
CPU time 10.87 seconds
Started Mar 24 12:57:43 PM PDT 24
Finished Mar 24 12:57:54 PM PDT 24
Peak memory 211168 kb
Host smart-85a5b4aa-d89b-4152-82ad-54fe6a7a1df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124052651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.124052651
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3817863012
Short name T293
Test name
Test status
Simulation time 987430643 ps
CPU time 6.07 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:08:37 PM PDT 24
Peak memory 211204 kb
Host smart-beddaa3b-5548-4862-8620-9ed9b0110308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817863012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3817863012
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3426946024
Short name T323
Test name
Test status
Simulation time 53498517268 ps
CPU time 334.69 seconds
Started Mar 24 12:57:41 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 224748 kb
Host smart-36501566-5f4a-4a39-9be9-8b8b627b933a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426946024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3426946024
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.724102534
Short name T101
Test name
Test status
Simulation time 129468071041 ps
CPU time 397.73 seconds
Started Mar 24 01:08:21 PM PDT 24
Finished Mar 24 01:14:59 PM PDT 24
Peak memory 230472 kb
Host smart-0dc8a9d0-36d1-459d-8268-f65d67875070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724102534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.724102534
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1533420411
Short name T623
Test name
Test status
Simulation time 11773697847 ps
CPU time 28.16 seconds
Started Mar 24 12:57:40 PM PDT 24
Finished Mar 24 12:58:09 PM PDT 24
Peak memory 212156 kb
Host smart-46f1233f-2629-4bf6-be6a-846a41a502cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533420411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1533420411
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.23713846
Short name T249
Test name
Test status
Simulation time 2856559144 ps
CPU time 26.12 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:08:57 PM PDT 24
Peak memory 211808 kb
Host smart-35760d40-9970-4f7a-9940-10127b07f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23713846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.23713846
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2517959698
Short name T2
Test name
Test status
Simulation time 2403948429 ps
CPU time 8.83 seconds
Started Mar 24 01:08:34 PM PDT 24
Finished Mar 24 01:08:43 PM PDT 24
Peak memory 211232 kb
Host smart-0e2923be-2bc0-41c6-8d3e-ce47db668ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517959698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2517959698
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3502740033
Short name T279
Test name
Test status
Simulation time 5289895182 ps
CPU time 13.13 seconds
Started Mar 24 12:57:40 PM PDT 24
Finished Mar 24 12:57:54 PM PDT 24
Peak memory 211200 kb
Host smart-4d5e12c2-7d1e-4dbe-ae7d-52c586a0a976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502740033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3502740033
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2348745510
Short name T452
Test name
Test status
Simulation time 2251131850 ps
CPU time 10.31 seconds
Started Mar 24 12:57:43 PM PDT 24
Finished Mar 24 12:57:54 PM PDT 24
Peak memory 219416 kb
Host smart-ce94f05f-ab06-4697-9d70-bfb16a864a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348745510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2348745510
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1023249310
Short name T160
Test name
Test status
Simulation time 333630450 ps
CPU time 4.96 seconds
Started Mar 24 12:57:40 PM PDT 24
Finished Mar 24 12:57:46 PM PDT 24
Peak memory 210996 kb
Host smart-d1195b10-bdd4-43e0-ae34-d942083396a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023249310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1023249310
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1182924176
Short name T274
Test name
Test status
Simulation time 3444727212 ps
CPU time 35.06 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:09:06 PM PDT 24
Peak memory 219448 kb
Host smart-303b655f-c74e-4f12-944a-55173382072d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182924176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1182924176
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.382950340
Short name T67
Test name
Test status
Simulation time 47945889223 ps
CPU time 3243.3 seconds
Started Mar 24 12:57:41 PM PDT 24
Finished Mar 24 01:51:45 PM PDT 24
Peak memory 235840 kb
Host smart-ddd51f27-766b-4514-b9e2-992f28a53ee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382950340 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.382950340
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1699273480
Short name T627
Test name
Test status
Simulation time 3771602731 ps
CPU time 10.06 seconds
Started Mar 24 01:08:22 PM PDT 24
Finished Mar 24 01:08:33 PM PDT 24
Peak memory 211236 kb
Host smart-6ff87188-110e-49a9-956a-07c7b1299e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699273480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1699273480
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1976986513
Short name T352
Test name
Test status
Simulation time 333440421 ps
CPU time 4.3 seconds
Started Mar 24 12:57:46 PM PDT 24
Finished Mar 24 12:57:50 PM PDT 24
Peak memory 211220 kb
Host smart-1bb7995c-b05c-4ee0-b008-f1d576927fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976986513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1976986513
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.241262219
Short name T215
Test name
Test status
Simulation time 24452259673 ps
CPU time 220.27 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:12:12 PM PDT 24
Peak memory 232816 kb
Host smart-a3c294ea-0b2c-443b-b3fa-3a67319642e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241262219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.241262219
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4178332080
Short name T678
Test name
Test status
Simulation time 43590789019 ps
CPU time 235.05 seconds
Started Mar 24 12:57:40 PM PDT 24
Finished Mar 24 01:01:36 PM PDT 24
Peak memory 236196 kb
Host smart-3c53fac5-a31d-47ad-86f1-316b5aaf38f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178332080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4178332080
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3190333120
Short name T386
Test name
Test status
Simulation time 17024485179 ps
CPU time 33.3 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:09:05 PM PDT 24
Peak memory 212232 kb
Host smart-2c2a9110-70e0-4aeb-896e-0b6783bd4673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190333120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3190333120
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.35891158
Short name T303
Test name
Test status
Simulation time 2365260439 ps
CPU time 23.45 seconds
Started Mar 24 12:57:45 PM PDT 24
Finished Mar 24 12:58:09 PM PDT 24
Peak memory 211824 kb
Host smart-6e6cbe9e-a075-49ee-a411-1339a6b26033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35891158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.35891158
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1604264175
Short name T343
Test name
Test status
Simulation time 2117902066 ps
CPU time 11.74 seconds
Started Mar 24 12:57:39 PM PDT 24
Finished Mar 24 12:57:51 PM PDT 24
Peak memory 210964 kb
Host smart-56425a2d-6d94-4882-b7dd-fae29a13bb89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604264175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1604264175
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1946727834
Short name T259
Test name
Test status
Simulation time 781166071 ps
CPU time 10.16 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 211028 kb
Host smart-05c9e9d7-582b-4635-b320-06b75e2e3401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946727834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1946727834
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2078703355
Short name T629
Test name
Test status
Simulation time 190965055 ps
CPU time 10.06 seconds
Started Mar 24 12:57:42 PM PDT 24
Finished Mar 24 12:57:53 PM PDT 24
Peak memory 219320 kb
Host smart-57c96243-cdb6-4c69-b43a-2c1c60818046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078703355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2078703355
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2965470855
Short name T174
Test name
Test status
Simulation time 13060278877 ps
CPU time 30.87 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:08:51 PM PDT 24
Peak memory 219416 kb
Host smart-8b21b988-6fbb-4744-9537-8629c5429a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965470855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2965470855
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2174813057
Short name T413
Test name
Test status
Simulation time 8213776150 ps
CPU time 84.33 seconds
Started Mar 24 12:57:41 PM PDT 24
Finished Mar 24 12:59:06 PM PDT 24
Peak memory 219404 kb
Host smart-4b5dac6a-10c6-4d71-bc0a-15bb921c277e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174813057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2174813057
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3931079596
Short name T612
Test name
Test status
Simulation time 18820629527 ps
CPU time 97.73 seconds
Started Mar 24 01:08:25 PM PDT 24
Finished Mar 24 01:10:03 PM PDT 24
Peak memory 217572 kb
Host smart-a48af7b0-780c-48c4-8a0f-af5e0b2829ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931079596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3931079596
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1101002125
Short name T348
Test name
Test status
Simulation time 3582526087 ps
CPU time 15.19 seconds
Started Mar 24 12:57:47 PM PDT 24
Finished Mar 24 12:58:02 PM PDT 24
Peak memory 211324 kb
Host smart-c39af35a-3883-4bbd-abb7-26b4dc73c83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101002125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1101002125
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3659415343
Short name T143
Test name
Test status
Simulation time 3510209093 ps
CPU time 7.78 seconds
Started Mar 24 01:08:33 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 211328 kb
Host smart-aa44a026-9f55-4a0a-a0fa-a1091f1e2f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659415343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3659415343
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1961305499
Short name T298
Test name
Test status
Simulation time 224161051534 ps
CPU time 511.36 seconds
Started Mar 24 12:57:47 PM PDT 24
Finished Mar 24 01:06:19 PM PDT 24
Peak memory 234544 kb
Host smart-a5839f9d-eac5-4f96-aaf8-3da7258b9c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961305499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1961305499
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2426382905
Short name T501
Test name
Test status
Simulation time 21896293179 ps
CPU time 115.54 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:10:16 PM PDT 24
Peak memory 225576 kb
Host smart-e3da9388-9611-4fac-b4a0-967cd22aea36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426382905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2426382905
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3077270061
Short name T142
Test name
Test status
Simulation time 4242020994 ps
CPU time 33.88 seconds
Started Mar 24 12:57:44 PM PDT 24
Finished Mar 24 12:58:18 PM PDT 24
Peak memory 211952 kb
Host smart-b4b4f607-c37c-43d1-9e41-a01d84c632bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077270061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3077270061
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.51972355
Short name T524
Test name
Test status
Simulation time 8074861581 ps
CPU time 33.49 seconds
Started Mar 24 01:08:34 PM PDT 24
Finished Mar 24 01:09:07 PM PDT 24
Peak memory 212128 kb
Host smart-c73f3f1e-cbd0-49a2-b7f1-502099f22600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51972355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.51972355
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2673970443
Short name T421
Test name
Test status
Simulation time 95221552 ps
CPU time 5.61 seconds
Started Mar 24 12:57:45 PM PDT 24
Finished Mar 24 12:57:51 PM PDT 24
Peak memory 211068 kb
Host smart-cd156cb6-bc52-40d7-ad8f-0683568000e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673970443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2673970443
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3999921455
Short name T377
Test name
Test status
Simulation time 97330620 ps
CPU time 5.65 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:08:26 PM PDT 24
Peak memory 211064 kb
Host smart-4c69a340-9f42-46cb-b57e-0a422c017c61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999921455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3999921455
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.230276097
Short name T281
Test name
Test status
Simulation time 2065123448 ps
CPU time 18.98 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:08:47 PM PDT 24
Peak memory 212940 kb
Host smart-87d71f4c-1ee2-4fad-afcd-706744d61eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230276097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.230276097
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3716300065
Short name T265
Test name
Test status
Simulation time 3063088300 ps
CPU time 28.36 seconds
Started Mar 24 12:57:44 PM PDT 24
Finished Mar 24 12:58:12 PM PDT 24
Peak memory 219360 kb
Host smart-43defc21-1e8b-47dd-966d-a5d23191c93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716300065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3716300065
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1900466034
Short name T538
Test name
Test status
Simulation time 3509787776 ps
CPU time 37.65 seconds
Started Mar 24 12:57:43 PM PDT 24
Finished Mar 24 12:58:21 PM PDT 24
Peak memory 213616 kb
Host smart-0e8b7669-abce-4ffe-83d8-6e40dbc38abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900466034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1900466034
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3642430711
Short name T371
Test name
Test status
Simulation time 1538120725 ps
CPU time 24.66 seconds
Started Mar 24 01:08:23 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 216548 kb
Host smart-a8fe43ea-2079-45b5-b72d-56719b2dd2d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642430711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3642430711
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2191677698
Short name T620
Test name
Test status
Simulation time 614102115 ps
CPU time 6.29 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:08:37 PM PDT 24
Peak memory 211140 kb
Host smart-2771b350-4cbb-4474-a908-4cb5f0d4b2a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191677698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2191677698
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2194017146
Short name T478
Test name
Test status
Simulation time 7148140097 ps
CPU time 15.03 seconds
Started Mar 24 12:57:49 PM PDT 24
Finished Mar 24 12:58:05 PM PDT 24
Peak memory 211312 kb
Host smart-bad8585c-cbb5-43f3-b3d0-671a0e38a96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194017146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2194017146
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1086874161
Short name T425
Test name
Test status
Simulation time 108613558135 ps
CPU time 168.21 seconds
Started Mar 24 12:57:53 PM PDT 24
Finished Mar 24 01:00:42 PM PDT 24
Peak memory 211444 kb
Host smart-2415631b-3dc3-4360-a513-889898b5cfac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086874161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1086874161
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1450256265
Short name T297
Test name
Test status
Simulation time 23678036562 ps
CPU time 222.73 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:12:14 PM PDT 24
Peak memory 228384 kb
Host smart-bdd33317-ec07-4dc9-8437-f5a2a65b81ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450256265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1450256265
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.373308561
Short name T409
Test name
Test status
Simulation time 407467626 ps
CPU time 9.39 seconds
Started Mar 24 12:57:53 PM PDT 24
Finished Mar 24 12:58:02 PM PDT 24
Peak memory 211756 kb
Host smart-9cf2bda3-9791-4bc1-8fa3-60f508bdbb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373308561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.373308561
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.521818824
Short name T651
Test name
Test status
Simulation time 5127821316 ps
CPU time 17.43 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 212384 kb
Host smart-7212e5fc-1019-4d82-b3e5-1826b26e975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521818824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.521818824
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2919708353
Short name T221
Test name
Test status
Simulation time 3030061057 ps
CPU time 13.43 seconds
Started Mar 24 12:57:46 PM PDT 24
Finished Mar 24 12:58:00 PM PDT 24
Peak memory 211220 kb
Host smart-c25ee35e-3afc-4f53-964a-4bd6b249f58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919708353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2919708353
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.473498272
Short name T300
Test name
Test status
Simulation time 1893096687 ps
CPU time 15.37 seconds
Started Mar 24 01:08:24 PM PDT 24
Finished Mar 24 01:08:40 PM PDT 24
Peak memory 211104 kb
Host smart-1be258d1-5da6-4163-897c-ffe947293e20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473498272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.473498272
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.300133620
Short name T528
Test name
Test status
Simulation time 491078409 ps
CPU time 9.88 seconds
Started Mar 24 01:08:20 PM PDT 24
Finished Mar 24 01:08:30 PM PDT 24
Peak memory 219320 kb
Host smart-4465ba73-d6cb-42dd-a168-ffe1f78baebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300133620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.300133620
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3670406711
Short name T625
Test name
Test status
Simulation time 381398850 ps
CPU time 9.87 seconds
Started Mar 24 12:57:47 PM PDT 24
Finished Mar 24 12:57:57 PM PDT 24
Peak memory 213248 kb
Host smart-8cadb306-c77a-4462-863d-0cc54d218244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670406711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3670406711
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1993887009
Short name T105
Test name
Test status
Simulation time 2721890861 ps
CPU time 21.52 seconds
Started Mar 24 12:57:45 PM PDT 24
Finished Mar 24 12:58:06 PM PDT 24
Peak memory 216524 kb
Host smart-db04fd5a-642a-44f1-97f8-84249d7d6cfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993887009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1993887009
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4174435474
Short name T310
Test name
Test status
Simulation time 7570068672 ps
CPU time 72.62 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:09:44 PM PDT 24
Peak memory 219384 kb
Host smart-d886f45c-cb0f-48bf-9e4e-de708c176b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174435474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4174435474
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1144188815
Short name T445
Test name
Test status
Simulation time 259977483 ps
CPU time 5.14 seconds
Started Mar 24 12:57:53 PM PDT 24
Finished Mar 24 12:57:59 PM PDT 24
Peak memory 211224 kb
Host smart-6560ba79-5181-4a9d-bc36-e131a4eb16a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144188815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1144188815
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4039314502
Short name T177
Test name
Test status
Simulation time 102484967 ps
CPU time 4.67 seconds
Started Mar 24 01:08:27 PM PDT 24
Finished Mar 24 01:08:32 PM PDT 24
Peak memory 211424 kb
Host smart-9ebc1675-9979-4c27-98ff-873a1d5a630d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039314502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4039314502
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1864206131
Short name T186
Test name
Test status
Simulation time 16773953190 ps
CPU time 222.28 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:12:14 PM PDT 24
Peak memory 229364 kb
Host smart-c1d40d3f-9161-42aa-8495-995cd15c884c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864206131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1864206131
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2165388535
Short name T525
Test name
Test status
Simulation time 47231602952 ps
CPU time 240.26 seconds
Started Mar 24 12:57:54 PM PDT 24
Finished Mar 24 01:01:55 PM PDT 24
Peak memory 225092 kb
Host smart-0fdc66d1-5bae-4672-9361-4284ba0a5175
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165388535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2165388535
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1502687051
Short name T46
Test name
Test status
Simulation time 5783593477 ps
CPU time 25.6 seconds
Started Mar 24 12:57:52 PM PDT 24
Finished Mar 24 12:58:17 PM PDT 24
Peak memory 213248 kb
Host smart-c6647049-ca48-412d-90a9-259d8ba0e551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502687051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1502687051
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1641220181
Short name T390
Test name
Test status
Simulation time 32745753667 ps
CPU time 20.49 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 212124 kb
Host smart-954ef4ee-9ad6-4622-b5b3-d2adc4b886d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641220181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1641220181
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3349419038
Short name T234
Test name
Test status
Simulation time 1931688777 ps
CPU time 8.36 seconds
Started Mar 24 01:08:25 PM PDT 24
Finished Mar 24 01:08:33 PM PDT 24
Peak memory 211000 kb
Host smart-1aa0b7cc-0717-47ed-a050-c9d0f15a350d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349419038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3349419038
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.753131888
Short name T304
Test name
Test status
Simulation time 2011895891 ps
CPU time 17.55 seconds
Started Mar 24 12:57:50 PM PDT 24
Finished Mar 24 12:58:08 PM PDT 24
Peak memory 211064 kb
Host smart-959c460b-87f0-4dae-8ab0-83cdce9a59aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753131888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.753131888
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2670736001
Short name T374
Test name
Test status
Simulation time 1164254876 ps
CPU time 17.36 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:08:49 PM PDT 24
Peak memory 212772 kb
Host smart-2574b79f-d8fa-48f9-b2c7-3a14bf8d1a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670736001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2670736001
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.317306919
Short name T448
Test name
Test status
Simulation time 3714703821 ps
CPU time 30.67 seconds
Started Mar 24 12:57:52 PM PDT 24
Finished Mar 24 12:58:24 PM PDT 24
Peak memory 219436 kb
Host smart-9d30df87-516e-451c-8044-00ea6c0e9b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317306919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.317306919
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1439172656
Short name T108
Test name
Test status
Simulation time 17804194065 ps
CPU time 41.68 seconds
Started Mar 24 12:57:50 PM PDT 24
Finished Mar 24 12:58:32 PM PDT 24
Peak memory 213932 kb
Host smart-8274f7bf-f780-413b-aa4c-3d33efdad8a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439172656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1439172656
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.424538620
Short name T595
Test name
Test status
Simulation time 15656755169 ps
CPU time 39.26 seconds
Started Mar 24 01:08:21 PM PDT 24
Finished Mar 24 01:09:00 PM PDT 24
Peak memory 219416 kb
Host smart-c31c75a4-ac70-4aa7-be1c-12fe76f0f662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424538620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.424538620
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3930292283
Short name T268
Test name
Test status
Simulation time 75452345214 ps
CPU time 9565.07 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 03:48:01 PM PDT 24
Peak memory 238332 kb
Host smart-3fc63fc1-5937-492c-8c1b-937ac24b8661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930292283 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3930292283
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1887164681
Short name T514
Test name
Test status
Simulation time 6058050148 ps
CPU time 13.12 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 211344 kb
Host smart-65619c30-033d-4122-a2bb-11f005e51182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887164681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1887164681
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2083980240
Short name T593
Test name
Test status
Simulation time 173233848 ps
CPU time 5.37 seconds
Started Mar 24 12:57:56 PM PDT 24
Finished Mar 24 12:58:02 PM PDT 24
Peak memory 211072 kb
Host smart-f6bfc44d-a589-4246-8128-a28c517376a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083980240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2083980240
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3973660887
Short name T429
Test name
Test status
Simulation time 41214188017 ps
CPU time 197.78 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 01:01:18 PM PDT 24
Peak memory 237212 kb
Host smart-988ae52f-9508-4250-aab7-a33facf8903a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973660887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3973660887
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.540454856
Short name T170
Test name
Test status
Simulation time 31124833388 ps
CPU time 301.54 seconds
Started Mar 24 01:08:29 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 225148 kb
Host smart-4517374c-8021-42c7-8002-ce636ece12e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540454856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.540454856
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3296486531
Short name T27
Test name
Test status
Simulation time 2071337003 ps
CPU time 21.48 seconds
Started Mar 24 01:08:26 PM PDT 24
Finished Mar 24 01:08:47 PM PDT 24
Peak memory 212296 kb
Host smart-524fad5c-1a0c-4217-b888-d80c5d6bbfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296486531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3296486531
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3383113347
Short name T227
Test name
Test status
Simulation time 341142333 ps
CPU time 9.04 seconds
Started Mar 24 12:57:53 PM PDT 24
Finished Mar 24 12:58:03 PM PDT 24
Peak memory 211796 kb
Host smart-bfa9dd73-3159-468f-b36e-6359de6a7cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383113347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3383113347
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1256079979
Short name T69
Test name
Test status
Simulation time 2212753454 ps
CPU time 11.68 seconds
Started Mar 24 01:08:29 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 211196 kb
Host smart-960053a3-b342-4d57-911c-be61047bc97b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256079979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1256079979
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3885511130
Short name T184
Test name
Test status
Simulation time 223269052 ps
CPU time 6.77 seconds
Started Mar 24 12:57:56 PM PDT 24
Finished Mar 24 12:58:03 PM PDT 24
Peak memory 211068 kb
Host smart-84b3de8b-9aa1-4661-8319-feb3aab0e5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885511130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3885511130
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3943697691
Short name T312
Test name
Test status
Simulation time 194720623 ps
CPU time 10.27 seconds
Started Mar 24 01:08:38 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 213720 kb
Host smart-5cce56fc-b73b-4d5c-9e3a-ea787c870ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943697691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3943697691
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.927939615
Short name T212
Test name
Test status
Simulation time 901275694 ps
CPU time 10.42 seconds
Started Mar 24 12:57:52 PM PDT 24
Finished Mar 24 12:58:03 PM PDT 24
Peak memory 213244 kb
Host smart-a7b97ddf-d20c-49b8-92fd-f46fa268582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927939615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.927939615
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4221069809
Short name T458
Test name
Test status
Simulation time 2816931201 ps
CPU time 49.16 seconds
Started Mar 24 01:08:27 PM PDT 24
Finished Mar 24 01:09:16 PM PDT 24
Peak memory 216708 kb
Host smart-7a96b067-20c2-491f-a9da-07d94312e321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221069809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4221069809
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.570373548
Short name T552
Test name
Test status
Simulation time 2948233711 ps
CPU time 23.9 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 12:58:24 PM PDT 24
Peak memory 219412 kb
Host smart-0fb8a4d3-b21c-4e22-bbbb-df72fda9400d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570373548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.570373548
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1564328773
Short name T17
Test name
Test status
Simulation time 105021023428 ps
CPU time 8823.67 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 03:25:04 PM PDT 24
Peak memory 232728 kb
Host smart-1472a155-d1bc-4730-b700-f40e522f4420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564328773 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1564328773
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1376186624
Short name T334
Test name
Test status
Simulation time 2117649262 ps
CPU time 16.18 seconds
Started Mar 24 01:08:26 PM PDT 24
Finished Mar 24 01:08:43 PM PDT 24
Peak memory 211160 kb
Host smart-1bf7225b-36bc-4f8f-ae6c-936e6bc1edcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376186624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1376186624
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2120758681
Short name T601
Test name
Test status
Simulation time 167464796 ps
CPU time 5.59 seconds
Started Mar 24 12:58:01 PM PDT 24
Finished Mar 24 12:58:07 PM PDT 24
Peak memory 211212 kb
Host smart-a9db584d-3ad7-4245-9a66-17af2a156db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120758681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2120758681
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1614612131
Short name T626
Test name
Test status
Simulation time 27383932170 ps
CPU time 260.34 seconds
Started Mar 24 12:57:55 PM PDT 24
Finished Mar 24 01:02:17 PM PDT 24
Peak memory 228908 kb
Host smart-7ff66c35-2614-47e7-b104-9a5918381724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614612131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1614612131
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.316246604
Short name T531
Test name
Test status
Simulation time 24349319307 ps
CPU time 142.95 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:10:53 PM PDT 24
Peak memory 228872 kb
Host smart-e092a068-8c04-4a4e-93bd-6a39d2aa2f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316246604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.316246604
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1466551987
Short name T637
Test name
Test status
Simulation time 1276907963 ps
CPU time 17.8 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 211772 kb
Host smart-fe5ad1fc-1d26-4676-9370-4cd366e5ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466551987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1466551987
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.632904713
Short name T668
Test name
Test status
Simulation time 1381317394 ps
CPU time 11.88 seconds
Started Mar 24 12:57:57 PM PDT 24
Finished Mar 24 12:58:09 PM PDT 24
Peak memory 211796 kb
Host smart-a2e72631-ab92-40b2-9d9c-d50ba672081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632904713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.632904713
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1440861441
Short name T544
Test name
Test status
Simulation time 856106338 ps
CPU time 10.51 seconds
Started Mar 24 12:57:57 PM PDT 24
Finished Mar 24 12:58:08 PM PDT 24
Peak memory 211008 kb
Host smart-ceeee12b-5e53-4a1e-ac1a-e371498f89ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1440861441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1440861441
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3076283310
Short name T542
Test name
Test status
Simulation time 345339523 ps
CPU time 8.09 seconds
Started Mar 24 01:08:26 PM PDT 24
Finished Mar 24 01:08:34 PM PDT 24
Peak memory 211100 kb
Host smart-2c16c2d0-1d7f-4c17-8cd5-67e6b08867aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076283310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3076283310
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3761772421
Short name T345
Test name
Test status
Simulation time 730941097 ps
CPU time 10.33 seconds
Started Mar 24 12:57:55 PM PDT 24
Finished Mar 24 12:58:05 PM PDT 24
Peak memory 219208 kb
Host smart-896ac9a6-84d2-47af-9b45-ded9fa6a2713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761772421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3761772421
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.958070013
Short name T216
Test name
Test status
Simulation time 2925887223 ps
CPU time 18.01 seconds
Started Mar 24 01:08:27 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 213340 kb
Host smart-c2b4e121-a0e5-4b74-bd40-0a6facf08171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958070013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.958070013
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3395052817
Short name T588
Test name
Test status
Simulation time 38986573652 ps
CPU time 42.83 seconds
Started Mar 24 12:57:55 PM PDT 24
Finished Mar 24 12:58:39 PM PDT 24
Peak memory 214356 kb
Host smart-92dae342-ae64-49b5-bbd9-863008b8de98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395052817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3395052817
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3438051106
Short name T52
Test name
Test status
Simulation time 2372888714 ps
CPU time 11.68 seconds
Started Mar 24 01:08:26 PM PDT 24
Finished Mar 24 01:08:39 PM PDT 24
Peak memory 211296 kb
Host smart-4efc3eb5-6766-4ecb-b25a-8cc002f644b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438051106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3438051106
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2295030832
Short name T18
Test name
Test status
Simulation time 81983761333 ps
CPU time 1994.99 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 01:31:15 PM PDT 24
Peak memory 228580 kb
Host smart-205a7217-c4df-42be-a502-fe5f2d51c24f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295030832 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2295030832
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3042139675
Short name T299
Test name
Test status
Simulation time 4116158937 ps
CPU time 16.49 seconds
Started Mar 24 12:58:02 PM PDT 24
Finished Mar 24 12:58:19 PM PDT 24
Peak memory 211292 kb
Host smart-04644fb9-dd04-4482-bede-bcad6d430341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042139675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3042139675
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.65622796
Short name T581
Test name
Test status
Simulation time 3973714144 ps
CPU time 13.57 seconds
Started Mar 24 01:08:27 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 211320 kb
Host smart-dcef5150-1db1-444c-adda-c3770b5dd3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65622796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.65622796
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3722161790
Short name T545
Test name
Test status
Simulation time 201512494945 ps
CPU time 472.02 seconds
Started Mar 24 12:57:59 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 236880 kb
Host smart-7694169e-91c2-489e-8f44-bf47865fbf35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722161790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3722161790
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4038086447
Short name T168
Test name
Test status
Simulation time 106264339895 ps
CPU time 274.07 seconds
Started Mar 24 01:08:26 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 225500 kb
Host smart-c7e0f9d5-4c0a-46bf-b187-4ad356efda33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038086447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4038086447
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3759527499
Short name T361
Test name
Test status
Simulation time 4506327370 ps
CPU time 15.08 seconds
Started Mar 24 12:58:01 PM PDT 24
Finished Mar 24 12:58:16 PM PDT 24
Peak memory 212248 kb
Host smart-af2778b9-dc43-4b6c-903f-ce2b7f57087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759527499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3759527499
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2391904327
Short name T222
Test name
Test status
Simulation time 3643240873 ps
CPU time 15.54 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 12:58:15 PM PDT 24
Peak memory 211216 kb
Host smart-94f6311c-7aee-4bbc-b100-be1a554c1ed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391904327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2391904327
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.476867764
Short name T432
Test name
Test status
Simulation time 10499383501 ps
CPU time 15.57 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:08:44 PM PDT 24
Peak memory 211224 kb
Host smart-a208afde-3bfb-462b-ad3a-35139e288671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476867764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.476867764
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1993704542
Short name T539
Test name
Test status
Simulation time 7859228606 ps
CPU time 28.99 seconds
Started Mar 24 12:58:02 PM PDT 24
Finished Mar 24 12:58:31 PM PDT 24
Peak memory 214548 kb
Host smart-01e405b6-a2e9-4b26-be5d-b0792576b365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993704542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1993704542
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2984236853
Short name T562
Test name
Test status
Simulation time 4820057451 ps
CPU time 23.66 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:08:58 PM PDT 24
Peak memory 213736 kb
Host smart-3640719a-3cf2-40d3-96f1-a5aec0b1bc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984236853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2984236853
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1351338885
Short name T439
Test name
Test status
Simulation time 1189895304 ps
CPU time 14.89 seconds
Started Mar 24 01:08:29 PM PDT 24
Finished Mar 24 01:08:44 PM PDT 24
Peak memory 211832 kb
Host smart-6fb607c1-81c6-4bcd-935e-4d3aa6fd424b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351338885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1351338885
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2344224695
Short name T358
Test name
Test status
Simulation time 29159924388 ps
CPU time 75.97 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 12:59:16 PM PDT 24
Peak memory 216840 kb
Host smart-17ddabd8-a3bd-411e-a1ee-64351d71a165
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344224695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2344224695
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1217487616
Short name T254
Test name
Test status
Simulation time 85646940 ps
CPU time 4.34 seconds
Started Mar 24 01:07:54 PM PDT 24
Finished Mar 24 01:07:58 PM PDT 24
Peak memory 211204 kb
Host smart-bf98049a-2240-4245-87e7-55c121db70e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217487616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1217487616
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1774281795
Short name T476
Test name
Test status
Simulation time 7766989615 ps
CPU time 8.72 seconds
Started Mar 24 12:57:06 PM PDT 24
Finished Mar 24 12:57:15 PM PDT 24
Peak memory 211332 kb
Host smart-fd021428-cf70-42a5-af63-52647547f9c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774281795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1774281795
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.213789690
Short name T433
Test name
Test status
Simulation time 20007902524 ps
CPU time 230.01 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:11:44 PM PDT 24
Peak memory 212460 kb
Host smart-f57d818a-d002-481e-8e10-a078c25317ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213789690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.213789690
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.880723580
Short name T54
Test name
Test status
Simulation time 20908836087 ps
CPU time 206.06 seconds
Started Mar 24 12:57:04 PM PDT 24
Finished Mar 24 01:00:31 PM PDT 24
Peak memory 218588 kb
Host smart-71bc1646-9a89-4762-97f7-65d518074d44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880723580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.880723580
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2964485327
Short name T608
Test name
Test status
Simulation time 6784868003 ps
CPU time 30.22 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:08:24 PM PDT 24
Peak memory 219500 kb
Host smart-f6113336-eec1-4702-8d1f-8c54501783ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964485327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2964485327
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3026051233
Short name T596
Test name
Test status
Simulation time 8864857916 ps
CPU time 22.18 seconds
Started Mar 24 12:56:59 PM PDT 24
Finished Mar 24 12:57:21 PM PDT 24
Peak memory 212528 kb
Host smart-b576aacc-cb0d-4f04-bef4-f2e0be9d24a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026051233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3026051233
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2285276920
Short name T241
Test name
Test status
Simulation time 7445545341 ps
CPU time 16.63 seconds
Started Mar 24 12:57:01 PM PDT 24
Finished Mar 24 12:57:18 PM PDT 24
Peak memory 211224 kb
Host smart-cda0e149-7d05-457d-9b84-287eb478dae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285276920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2285276920
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2507917386
Short name T610
Test name
Test status
Simulation time 863267302 ps
CPU time 10.66 seconds
Started Mar 24 01:07:55 PM PDT 24
Finished Mar 24 01:08:06 PM PDT 24
Peak memory 211092 kb
Host smart-7f7f4c89-2344-46bd-bfbf-a090588478c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507917386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2507917386
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3301496042
Short name T39
Test name
Test status
Simulation time 2198783217 ps
CPU time 65.38 seconds
Started Mar 24 12:56:59 PM PDT 24
Finished Mar 24 12:58:05 PM PDT 24
Peak memory 233604 kb
Host smart-4a7339f4-d666-401c-98ff-ba36d27d17aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301496042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3301496042
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1243716951
Short name T148
Test name
Test status
Simulation time 12893152717 ps
CPU time 29.32 seconds
Started Mar 24 12:56:58 PM PDT 24
Finished Mar 24 12:57:27 PM PDT 24
Peak memory 213680 kb
Host smart-ed6be4ec-7639-4bf7-ad7d-1aa2c3b81a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243716951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1243716951
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2319527266
Short name T333
Test name
Test status
Simulation time 3097964229 ps
CPU time 20.44 seconds
Started Mar 24 01:07:58 PM PDT 24
Finished Mar 24 01:08:18 PM PDT 24
Peak memory 213296 kb
Host smart-eafcaa7f-0329-4ca6-a5a4-123c261a35ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319527266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2319527266
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2496703902
Short name T204
Test name
Test status
Simulation time 7042575854 ps
CPU time 26.56 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:08:20 PM PDT 24
Peak memory 214740 kb
Host smart-01b9f3e3-4e79-4155-9756-022f62e3d449
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496703902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2496703902
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.986464824
Short name T500
Test name
Test status
Simulation time 3706063242 ps
CPU time 12.44 seconds
Started Mar 24 12:57:02 PM PDT 24
Finished Mar 24 12:57:14 PM PDT 24
Peak memory 211028 kb
Host smart-b0c50e44-7994-43c1-9a26-f4d59555875a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986464824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.986464824
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1030683499
Short name T586
Test name
Test status
Simulation time 2197478327 ps
CPU time 16.21 seconds
Started Mar 24 12:58:06 PM PDT 24
Finished Mar 24 12:58:23 PM PDT 24
Peak memory 211252 kb
Host smart-d1e1478f-61af-4351-9594-2a75a9528821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030683499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1030683499
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2435477742
Short name T163
Test name
Test status
Simulation time 3686176078 ps
CPU time 15.89 seconds
Started Mar 24 01:08:29 PM PDT 24
Finished Mar 24 01:08:45 PM PDT 24
Peak memory 211244 kb
Host smart-4037d924-0d04-4de9-a909-7c3209f69e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435477742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2435477742
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1643836033
Short name T401
Test name
Test status
Simulation time 82890022854 ps
CPU time 188.62 seconds
Started Mar 24 01:08:29 PM PDT 24
Finished Mar 24 01:11:38 PM PDT 24
Peak memory 229588 kb
Host smart-2e59d280-1e15-4a19-928e-078e6bfa31ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643836033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1643836033
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1732837422
Short name T242
Test name
Test status
Simulation time 15655654429 ps
CPU time 108.38 seconds
Started Mar 24 12:58:03 PM PDT 24
Finished Mar 24 12:59:51 PM PDT 24
Peak memory 219504 kb
Host smart-5e8e6869-4bc9-4e14-8595-0b3f6432412a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732837422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1732837422
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3226489191
Short name T149
Test name
Test status
Simulation time 8667892121 ps
CPU time 36.06 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:09:04 PM PDT 24
Peak memory 212240 kb
Host smart-2707a223-4118-41b9-ad5f-9acbcf40bace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226489191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3226489191
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3631974215
Short name T59
Test name
Test status
Simulation time 6820730072 ps
CPU time 20 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 12:58:20 PM PDT 24
Peak memory 212536 kb
Host smart-c87044a6-9811-4e83-bdd0-772854ec2a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631974215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3631974215
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2492993147
Short name T276
Test name
Test status
Simulation time 2212861601 ps
CPU time 17.11 seconds
Started Mar 24 01:08:37 PM PDT 24
Finished Mar 24 01:08:55 PM PDT 24
Peak memory 211212 kb
Host smart-7fdfab96-2ccc-46a9-ac7a-7b5760ec5a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492993147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2492993147
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3211049766
Short name T589
Test name
Test status
Simulation time 7779258423 ps
CPU time 16.84 seconds
Started Mar 24 12:58:01 PM PDT 24
Finished Mar 24 12:58:18 PM PDT 24
Peak memory 211424 kb
Host smart-9f9c8340-5263-4a47-bb90-ae09b0158dbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211049766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3211049766
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2257487461
Short name T510
Test name
Test status
Simulation time 10065056686 ps
CPU time 24.14 seconds
Started Mar 24 12:58:00 PM PDT 24
Finished Mar 24 12:58:24 PM PDT 24
Peak memory 214144 kb
Host smart-a03b8014-0b91-4397-bf78-a387c8bba8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257487461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2257487461
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3425501044
Short name T569
Test name
Test status
Simulation time 2529764866 ps
CPU time 10.4 seconds
Started Mar 24 01:08:38 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 213820 kb
Host smart-c9bd55ae-1aa4-438c-b4b3-a4db8c452f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425501044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3425501044
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1321482700
Short name T558
Test name
Test status
Simulation time 6707873559 ps
CPU time 42.98 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:09:18 PM PDT 24
Peak memory 214092 kb
Host smart-d83f3c58-6428-49b4-af0a-d53966bb168b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321482700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1321482700
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1524243407
Short name T411
Test name
Test status
Simulation time 1192405605 ps
CPU time 16.48 seconds
Started Mar 24 12:58:01 PM PDT 24
Finished Mar 24 12:58:18 PM PDT 24
Peak memory 214608 kb
Host smart-872756ba-0a61-4bbc-a5c9-3cc98a305c2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524243407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1524243407
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1402878736
Short name T199
Test name
Test status
Simulation time 1942951996 ps
CPU time 16.42 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:08:44 PM PDT 24
Peak memory 211200 kb
Host smart-0710f1ed-8e8e-4185-9934-12cdf814f27c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402878736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1402878736
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.754065964
Short name T579
Test name
Test status
Simulation time 1126748012 ps
CPU time 11.66 seconds
Started Mar 24 12:58:08 PM PDT 24
Finished Mar 24 12:58:20 PM PDT 24
Peak memory 211196 kb
Host smart-aeabb8e1-ba1a-4b0c-b970-f43f267269b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754065964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.754065964
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1955736317
Short name T104
Test name
Test status
Simulation time 175050232921 ps
CPU time 382.18 seconds
Started Mar 24 12:58:05 PM PDT 24
Finished Mar 24 01:04:27 PM PDT 24
Peak memory 224740 kb
Host smart-321d6b01-680a-4cc0-a4e5-5b5cf3b94257
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955736317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1955736317
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2131779866
Short name T232
Test name
Test status
Simulation time 18941299460 ps
CPU time 173.99 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:11:22 PM PDT 24
Peak memory 218576 kb
Host smart-43eda37e-763b-4c73-9953-92da81bc2c3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131779866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2131779866
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.125013475
Short name T606
Test name
Test status
Simulation time 2968683671 ps
CPU time 27.47 seconds
Started Mar 24 12:58:10 PM PDT 24
Finished Mar 24 12:58:37 PM PDT 24
Peak memory 211956 kb
Host smart-ef9ccb1d-514a-4581-a4e1-a1d1374c10cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125013475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.125013475
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3038229358
Short name T29
Test name
Test status
Simulation time 608901355 ps
CPU time 13.71 seconds
Started Mar 24 01:08:29 PM PDT 24
Finished Mar 24 01:08:43 PM PDT 24
Peak memory 211876 kb
Host smart-d77c3acb-194f-4154-912a-62512e9a9d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038229358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3038229358
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2112745040
Short name T248
Test name
Test status
Simulation time 697579272 ps
CPU time 6.42 seconds
Started Mar 24 12:58:11 PM PDT 24
Finished Mar 24 12:58:17 PM PDT 24
Peak memory 211008 kb
Host smart-1d8922ee-7f10-4c53-a00e-68fef30a7e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112745040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2112745040
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3110041519
Short name T14
Test name
Test status
Simulation time 349768569 ps
CPU time 7.91 seconds
Started Mar 24 01:08:38 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 211088 kb
Host smart-843a0e8f-d828-4a02-9ad1-74a0ed55ffd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110041519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3110041519
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2654643660
Short name T529
Test name
Test status
Simulation time 13201392114 ps
CPU time 27.68 seconds
Started Mar 24 12:58:06 PM PDT 24
Finished Mar 24 12:58:34 PM PDT 24
Peak memory 219412 kb
Host smart-1e161360-e66d-497e-8804-b591d3b92ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654643660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2654643660
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3698055363
Short name T592
Test name
Test status
Simulation time 19296227429 ps
CPU time 41.48 seconds
Started Mar 24 01:08:28 PM PDT 24
Finished Mar 24 01:09:09 PM PDT 24
Peak memory 214264 kb
Host smart-fc4c7300-0203-4f5c-a675-bbed97ae8ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698055363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3698055363
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2395178960
Short name T516
Test name
Test status
Simulation time 11927403344 ps
CPU time 33.92 seconds
Started Mar 24 01:08:38 PM PDT 24
Finished Mar 24 01:09:12 PM PDT 24
Peak memory 219444 kb
Host smart-fc3e16a5-748e-4992-8c34-078b97c960eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395178960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2395178960
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.290478231
Short name T453
Test name
Test status
Simulation time 2945157863 ps
CPU time 38.32 seconds
Started Mar 24 12:58:08 PM PDT 24
Finished Mar 24 12:58:47 PM PDT 24
Peak memory 215412 kb
Host smart-b8d8a4db-5c95-4800-9b5f-87b88dc81cea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290478231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.290478231
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1783738619
Short name T68
Test name
Test status
Simulation time 227440772427 ps
CPU time 1044 seconds
Started Mar 24 12:58:03 PM PDT 24
Finished Mar 24 01:15:27 PM PDT 24
Peak memory 230004 kb
Host smart-8a3037a0-1d9b-4b74-8571-7b98d31c4111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783738619 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1783738619
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2645264239
Short name T337
Test name
Test status
Simulation time 175136871 ps
CPU time 4.3 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:08:40 PM PDT 24
Peak memory 211112 kb
Host smart-b55d6d41-43d7-4457-ac2f-a6aba7fe11f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645264239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2645264239
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.670178048
Short name T230
Test name
Test status
Simulation time 5002175243 ps
CPU time 11.43 seconds
Started Mar 24 12:58:06 PM PDT 24
Finished Mar 24 12:58:18 PM PDT 24
Peak memory 211336 kb
Host smart-5d762513-5d84-444b-9e9a-b212f5e7209f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670178048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.670178048
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3490289429
Short name T634
Test name
Test status
Simulation time 2178986754 ps
CPU time 108.71 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:10:20 PM PDT 24
Peak memory 211440 kb
Host smart-c0272eae-416f-49ea-91f5-e5a9ed079cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490289429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3490289429
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.529764392
Short name T423
Test name
Test status
Simulation time 280073114289 ps
CPU time 362.89 seconds
Started Mar 24 12:58:04 PM PDT 24
Finished Mar 24 01:04:07 PM PDT 24
Peak memory 234916 kb
Host smart-c84c7be7-a7ce-48bc-828d-a5422c604f6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529764392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.529764392
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4065850994
Short name T619
Test name
Test status
Simulation time 175354879 ps
CPU time 9.59 seconds
Started Mar 24 01:08:36 PM PDT 24
Finished Mar 24 01:08:45 PM PDT 24
Peak memory 211180 kb
Host smart-0cc9cf81-073c-4799-83d9-5fe371a19e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065850994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4065850994
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4269137062
Short name T287
Test name
Test status
Simulation time 20863504117 ps
CPU time 25.93 seconds
Started Mar 24 12:58:05 PM PDT 24
Finished Mar 24 12:58:31 PM PDT 24
Peak memory 212212 kb
Host smart-e7538594-9f5a-4906-bb80-e47baa5bdf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269137062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4269137062
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2607145
Short name T664
Test name
Test status
Simulation time 1865981195 ps
CPU time 16.47 seconds
Started Mar 24 01:08:32 PM PDT 24
Finished Mar 24 01:08:50 PM PDT 24
Peak memory 211000 kb
Host smart-85150bb2-8748-4d8e-a69f-5cbab57e290f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2607145
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.663886602
Short name T656
Test name
Test status
Simulation time 469281667 ps
CPU time 6.94 seconds
Started Mar 24 12:58:06 PM PDT 24
Finished Mar 24 12:58:13 PM PDT 24
Peak memory 211092 kb
Host smart-f3a31a04-9f42-423d-ae0a-67abcd04e904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663886602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.663886602
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2255428223
Short name T440
Test name
Test status
Simulation time 369307646 ps
CPU time 9.76 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:08:45 PM PDT 24
Peak memory 219340 kb
Host smart-325a9aab-e25b-4540-90a9-9d037f19b078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255428223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2255428223
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.739434180
Short name T459
Test name
Test status
Simulation time 4191354805 ps
CPU time 38.83 seconds
Started Mar 24 12:58:04 PM PDT 24
Finished Mar 24 12:58:43 PM PDT 24
Peak memory 212944 kb
Host smart-10c31e5b-ef24-4b63-8c09-e4503f7ae432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739434180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.739434180
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1637301960
Short name T50
Test name
Test status
Simulation time 1180589991 ps
CPU time 22.57 seconds
Started Mar 24 01:08:34 PM PDT 24
Finished Mar 24 01:08:57 PM PDT 24
Peak memory 213340 kb
Host smart-9b541089-f193-4d2c-8741-bc5ebc7ae287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637301960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1637301960
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.685285470
Short name T526
Test name
Test status
Simulation time 10121809497 ps
CPU time 63.82 seconds
Started Mar 24 12:58:08 PM PDT 24
Finished Mar 24 12:59:12 PM PDT 24
Peak memory 218612 kb
Host smart-90e630b7-d3d5-4e42-a5e7-5af15c287db9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685285470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.685285470
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2852557081
Short name T64
Test name
Test status
Simulation time 625604673711 ps
CPU time 3278.46 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 02:03:15 PM PDT 24
Peak memory 244428 kb
Host smart-b54e9c69-1ade-424c-92be-ad3ad6eaca84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852557081 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2852557081
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.544039926
Short name T381
Test name
Test status
Simulation time 413813194 ps
CPU time 7.1 seconds
Started Mar 24 12:58:06 PM PDT 24
Finished Mar 24 12:58:14 PM PDT 24
Peak memory 211220 kb
Host smart-127ad324-c9fd-4a3a-b1fc-e72e9ec1fc8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544039926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.544039926
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.990974066
Short name T451
Test name
Test status
Simulation time 168204413 ps
CPU time 5.41 seconds
Started Mar 24 01:08:34 PM PDT 24
Finished Mar 24 01:08:39 PM PDT 24
Peak memory 211172 kb
Host smart-7b0437b8-3b96-49b5-94b1-a9a647da52f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990974066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.990974066
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1683067334
Short name T384
Test name
Test status
Simulation time 32357111775 ps
CPU time 190.76 seconds
Started Mar 24 12:58:04 PM PDT 24
Finished Mar 24 01:01:15 PM PDT 24
Peak memory 238044 kb
Host smart-d9827c6b-8d12-46ec-a850-d772a3e9523e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683067334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1683067334
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4257004863
Short name T193
Test name
Test status
Simulation time 12760611190 ps
CPU time 109.18 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:10:19 PM PDT 24
Peak memory 220608 kb
Host smart-a0d7aa9f-e07e-458a-8498-7d17da37d16e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257004863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4257004863
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1105239992
Short name T426
Test name
Test status
Simulation time 434456020 ps
CPU time 12.31 seconds
Started Mar 24 12:58:11 PM PDT 24
Finished Mar 24 12:58:23 PM PDT 24
Peak memory 211668 kb
Host smart-fdd60938-76f6-4886-99e6-3ba2f06de821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105239992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1105239992
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.37155365
Short name T561
Test name
Test status
Simulation time 2928494235 ps
CPU time 26.81 seconds
Started Mar 24 01:08:32 PM PDT 24
Finished Mar 24 01:09:00 PM PDT 24
Peak memory 211868 kb
Host smart-ac081d95-23e5-478d-98b5-c293319799fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37155365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.37155365
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1620456180
Short name T340
Test name
Test status
Simulation time 2742717238 ps
CPU time 13.35 seconds
Started Mar 24 12:58:08 PM PDT 24
Finished Mar 24 12:58:21 PM PDT 24
Peak memory 211420 kb
Host smart-e8d38128-ec65-491a-9369-b190a09e2d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620456180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1620456180
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.625851842
Short name T443
Test name
Test status
Simulation time 2601876112 ps
CPU time 10.23 seconds
Started Mar 24 01:08:32 PM PDT 24
Finished Mar 24 01:08:42 PM PDT 24
Peak memory 211204 kb
Host smart-c26d73b6-0334-46ca-845b-f34105d4f8b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625851842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.625851842
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2664459040
Short name T338
Test name
Test status
Simulation time 5919579914 ps
CPU time 34.26 seconds
Started Mar 24 01:08:32 PM PDT 24
Finished Mar 24 01:09:06 PM PDT 24
Peak memory 214632 kb
Host smart-3472b5b3-0b01-4cb3-8487-2055cbfe3232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664459040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2664459040
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.668510909
Short name T438
Test name
Test status
Simulation time 1648900080 ps
CPU time 9.82 seconds
Started Mar 24 12:58:07 PM PDT 24
Finished Mar 24 12:58:17 PM PDT 24
Peak memory 219316 kb
Host smart-d0578105-dd15-4bc7-9a0d-4ecb1f2a3aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668510909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.668510909
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2019373124
Short name T164
Test name
Test status
Simulation time 2445845502 ps
CPU time 16.56 seconds
Started Mar 24 12:58:04 PM PDT 24
Finished Mar 24 12:58:21 PM PDT 24
Peak memory 212284 kb
Host smart-62d65ea3-171d-4e34-b569-ddddc96395bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019373124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2019373124
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3978584663
Short name T282
Test name
Test status
Simulation time 3232687164 ps
CPU time 14.62 seconds
Started Mar 24 01:08:32 PM PDT 24
Finished Mar 24 01:08:47 PM PDT 24
Peak memory 211140 kb
Host smart-7bd2bb83-ae49-49f1-8134-072df340d299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978584663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3978584663
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2992946992
Short name T328
Test name
Test status
Simulation time 20332791246 ps
CPU time 784.56 seconds
Started Mar 24 12:58:06 PM PDT 24
Finished Mar 24 01:11:11 PM PDT 24
Peak memory 225288 kb
Host smart-09a8fa69-8c46-4d44-b0d9-d0bcbd3e33ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992946992 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2992946992
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.855105472
Short name T541
Test name
Test status
Simulation time 4913918359 ps
CPU time 11.92 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 211284 kb
Host smart-a8e4bac0-7e7e-4e3b-a9af-11a0e1765d23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855105472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.855105472
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.994988019
Short name T225
Test name
Test status
Simulation time 7765967950 ps
CPU time 12.46 seconds
Started Mar 24 12:58:11 PM PDT 24
Finished Mar 24 12:58:23 PM PDT 24
Peak memory 211308 kb
Host smart-a56bf704-3cb5-4601-baca-b8726252cf0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994988019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.994988019
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1159266326
Short name T468
Test name
Test status
Simulation time 154328529101 ps
CPU time 248.23 seconds
Started Mar 24 01:08:33 PM PDT 24
Finished Mar 24 01:12:42 PM PDT 24
Peak memory 229800 kb
Host smart-3406d8b7-2f92-4d38-b294-968d54a806c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159266326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1159266326
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2238303600
Short name T57
Test name
Test status
Simulation time 94405540729 ps
CPU time 269.28 seconds
Started Mar 24 12:58:12 PM PDT 24
Finished Mar 24 01:02:41 PM PDT 24
Peak memory 228584 kb
Host smart-e149ec17-20cd-4e6b-8f99-b41e04cc7092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238303600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2238303600
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2636190030
Short name T404
Test name
Test status
Simulation time 1859482981 ps
CPU time 20.22 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:08:56 PM PDT 24
Peak memory 211104 kb
Host smart-08558ea9-fac2-46a2-b514-ee126b33ea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636190030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2636190030
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2981745392
Short name T493
Test name
Test status
Simulation time 175738098 ps
CPU time 9.4 seconds
Started Mar 24 12:58:12 PM PDT 24
Finished Mar 24 12:58:22 PM PDT 24
Peak memory 211764 kb
Host smart-8d1d4f72-46d8-4512-ae40-5db239731d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981745392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2981745392
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.212913485
Short name T202
Test name
Test status
Simulation time 4146684697 ps
CPU time 13.06 seconds
Started Mar 24 01:08:33 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 210756 kb
Host smart-7c9dc0d3-b4dc-44e9-aa4f-5e921909fa89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212913485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.212913485
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.464174797
Short name T491
Test name
Test status
Simulation time 23331435897 ps
CPU time 15.33 seconds
Started Mar 24 12:58:06 PM PDT 24
Finished Mar 24 12:58:21 PM PDT 24
Peak memory 211220 kb
Host smart-05920e20-c3a0-4757-8339-a3947e1f6ecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464174797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.464174797
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1042334847
Short name T350
Test name
Test status
Simulation time 4484888111 ps
CPU time 21.81 seconds
Started Mar 24 12:58:04 PM PDT 24
Finished Mar 24 12:58:26 PM PDT 24
Peak memory 219412 kb
Host smart-34ba20df-61d9-4f66-b3ce-33717b88c71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042334847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1042334847
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3866026888
Short name T512
Test name
Test status
Simulation time 187542773 ps
CPU time 10.15 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 212884 kb
Host smart-06ba1c5e-ba29-4121-a4d3-d8c0a83d2803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866026888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3866026888
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2078103697
Short name T139
Test name
Test status
Simulation time 12813263440 ps
CPU time 37.99 seconds
Started Mar 24 12:58:05 PM PDT 24
Finished Mar 24 12:58:43 PM PDT 24
Peak memory 217288 kb
Host smart-3ebffe44-6cb9-4bb0-a7b2-786905d838a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078103697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2078103697
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.877525223
Short name T331
Test name
Test status
Simulation time 1130140399 ps
CPU time 17.83 seconds
Started Mar 24 01:08:32 PM PDT 24
Finished Mar 24 01:08:50 PM PDT 24
Peak memory 213848 kb
Host smart-6f66207b-1821-4f2b-a35c-5d06a349d0ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877525223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.877525223
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3371226862
Short name T511
Test name
Test status
Simulation time 1059541570 ps
CPU time 9.74 seconds
Started Mar 24 12:58:10 PM PDT 24
Finished Mar 24 12:58:20 PM PDT 24
Peak memory 211220 kb
Host smart-c591b7a0-07f5-416a-b684-2d0aca21003c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371226862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3371226862
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.521105143
Short name T37
Test name
Test status
Simulation time 2124561490 ps
CPU time 17.03 seconds
Started Mar 24 01:08:37 PM PDT 24
Finished Mar 24 01:08:54 PM PDT 24
Peak memory 211180 kb
Host smart-075f0532-9640-4d31-8bb4-167d913ea970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521105143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.521105143
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1232864812
Short name T536
Test name
Test status
Simulation time 36685993735 ps
CPU time 371.87 seconds
Started Mar 24 01:08:30 PM PDT 24
Finished Mar 24 01:14:42 PM PDT 24
Peak memory 220244 kb
Host smart-b443340a-ac5c-421b-9809-ef439d35e914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232864812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1232864812
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2832839815
Short name T239
Test name
Test status
Simulation time 2185747979 ps
CPU time 59.3 seconds
Started Mar 24 12:58:11 PM PDT 24
Finished Mar 24 12:59:10 PM PDT 24
Peak memory 236872 kb
Host smart-3bd2bb5e-e373-4aa0-ab68-98526281615d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832839815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2832839815
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1670395481
Short name T577
Test name
Test status
Simulation time 693982657 ps
CPU time 9.66 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 211716 kb
Host smart-991113a1-d911-48c6-afa3-14f2d1301b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670395481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1670395481
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2199729233
Short name T309
Test name
Test status
Simulation time 173740381 ps
CPU time 9.41 seconds
Started Mar 24 12:58:10 PM PDT 24
Finished Mar 24 12:58:20 PM PDT 24
Peak memory 211940 kb
Host smart-b0e9ad77-7cab-4599-ac68-db49004b0265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199729233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2199729233
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3492904515
Short name T339
Test name
Test status
Simulation time 1752585149 ps
CPU time 12.84 seconds
Started Mar 24 12:58:12 PM PDT 24
Finished Mar 24 12:58:25 PM PDT 24
Peak memory 211056 kb
Host smart-de9f9279-2578-4881-80dc-ef71930ece47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492904515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3492904515
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.987525873
Short name T650
Test name
Test status
Simulation time 5669124596 ps
CPU time 13.97 seconds
Started Mar 24 01:08:32 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 211224 kb
Host smart-44bab9fb-628f-4577-89bd-97de35bc78a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987525873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.987525873
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.223551590
Short name T642
Test name
Test status
Simulation time 19259745739 ps
CPU time 34.15 seconds
Started Mar 24 01:08:31 PM PDT 24
Finished Mar 24 01:09:06 PM PDT 24
Peak memory 219408 kb
Host smart-a7330c5f-218f-41bc-a5b9-d11c30c5ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223551590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.223551590
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4056984100
Short name T394
Test name
Test status
Simulation time 22390907454 ps
CPU time 33.56 seconds
Started Mar 24 12:58:16 PM PDT 24
Finished Mar 24 12:58:49 PM PDT 24
Peak memory 214608 kb
Host smart-298fc54f-6114-425d-8e6c-a79dea4ee467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056984100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4056984100
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3070261685
Short name T1
Test name
Test status
Simulation time 2217996463 ps
CPU time 21.08 seconds
Started Mar 24 01:08:33 PM PDT 24
Finished Mar 24 01:08:54 PM PDT 24
Peak memory 214684 kb
Host smart-01c634a2-0423-4fcb-9c2a-3a938f90ab80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070261685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3070261685
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3533835091
Short name T553
Test name
Test status
Simulation time 6082452691 ps
CPU time 16.31 seconds
Started Mar 24 12:58:10 PM PDT 24
Finished Mar 24 12:58:27 PM PDT 24
Peak memory 218372 kb
Host smart-093a8bab-4129-43bf-9f1e-304bc0bef1f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533835091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3533835091
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1844931777
Short name T462
Test name
Test status
Simulation time 7143240049 ps
CPU time 913.42 seconds
Started Mar 24 12:58:11 PM PDT 24
Finished Mar 24 01:13:25 PM PDT 24
Peak memory 229324 kb
Host smart-0869c197-d06e-4c51-96b7-9915736df3cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844931777 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1844931777
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2354919320
Short name T640
Test name
Test status
Simulation time 1613059956 ps
CPU time 7.33 seconds
Started Mar 24 01:08:38 PM PDT 24
Finished Mar 24 01:08:45 PM PDT 24
Peak memory 211172 kb
Host smart-d8bdb69e-f34e-4903-958b-823edf91d845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354919320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2354919320
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3807192760
Short name T597
Test name
Test status
Simulation time 3162031818 ps
CPU time 10.56 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:26 PM PDT 24
Peak memory 211336 kb
Host smart-78ec419c-496a-4a56-b1db-545e0df9edf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807192760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3807192760
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2645629183
Short name T296
Test name
Test status
Simulation time 6550332115 ps
CPU time 105.33 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 01:00:01 PM PDT 24
Peak memory 228844 kb
Host smart-5e216e08-0c3f-491b-b41e-6109e7932a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645629183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2645629183
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4032875962
Short name T465
Test name
Test status
Simulation time 8994389463 ps
CPU time 153.7 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:11:09 PM PDT 24
Peak memory 233164 kb
Host smart-78681647-1333-44d6-b854-2da13d5eeb67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032875962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4032875962
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1573884346
Short name T505
Test name
Test status
Simulation time 242860790 ps
CPU time 9.43 seconds
Started Mar 24 01:08:38 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 211832 kb
Host smart-2e67c34c-0a6f-4240-b0e3-f122e966a50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573884346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1573884346
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4164258886
Short name T584
Test name
Test status
Simulation time 11243166291 ps
CPU time 25.24 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:41 PM PDT 24
Peak memory 212752 kb
Host smart-7141b1ad-4d0a-4466-ae90-f7ce9ced6cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164258886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4164258886
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1289428285
Short name T154
Test name
Test status
Simulation time 3920945403 ps
CPU time 11.11 seconds
Started Mar 24 12:58:10 PM PDT 24
Finished Mar 24 12:58:21 PM PDT 24
Peak memory 211196 kb
Host smart-a7bfc49f-764a-484d-972a-fb8602a10705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289428285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1289428285
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3365591921
Short name T351
Test name
Test status
Simulation time 4904692764 ps
CPU time 15.13 seconds
Started Mar 24 01:08:38 PM PDT 24
Finished Mar 24 01:08:54 PM PDT 24
Peak memory 211132 kb
Host smart-73b588fa-78d6-4255-8c11-b55cd4f93b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365591921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3365591921
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1481140949
Short name T171
Test name
Test status
Simulation time 2182633061 ps
CPU time 26.89 seconds
Started Mar 24 12:58:12 PM PDT 24
Finished Mar 24 12:58:39 PM PDT 24
Peak memory 213604 kb
Host smart-cfa53e31-6985-4f2a-a971-8c75b70af32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481140949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1481140949
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.363915727
Short name T611
Test name
Test status
Simulation time 7979876828 ps
CPU time 27.8 seconds
Started Mar 24 01:08:39 PM PDT 24
Finished Mar 24 01:09:07 PM PDT 24
Peak memory 214044 kb
Host smart-072664c5-2315-40a8-8c6f-e99bd099170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363915727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.363915727
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2459567806
Short name T507
Test name
Test status
Simulation time 25246482387 ps
CPU time 68.68 seconds
Started Mar 24 12:58:10 PM PDT 24
Finished Mar 24 12:59:19 PM PDT 24
Peak memory 219472 kb
Host smart-7aedd35a-045d-4207-8aae-bf0be7690a6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459567806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2459567806
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.330646226
Short name T615
Test name
Test status
Simulation time 3146139083 ps
CPU time 33.67 seconds
Started Mar 24 01:08:35 PM PDT 24
Finished Mar 24 01:09:09 PM PDT 24
Peak memory 219408 kb
Host smart-0d37a3d5-a161-4c60-b2af-d2fed96a0a8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330646226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.330646226
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.533635668
Short name T233
Test name
Test status
Simulation time 2018237514 ps
CPU time 16.17 seconds
Started Mar 24 01:08:42 PM PDT 24
Finished Mar 24 01:08:58 PM PDT 24
Peak memory 211192 kb
Host smart-01d735c0-886f-45fc-a061-314d5748d5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533635668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.533635668
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.999092824
Short name T598
Test name
Test status
Simulation time 643405482 ps
CPU time 8.61 seconds
Started Mar 24 12:58:14 PM PDT 24
Finished Mar 24 12:58:22 PM PDT 24
Peak memory 211188 kb
Host smart-7310f499-f374-415d-9dc8-0254535abecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999092824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.999092824
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2938766337
Short name T48
Test name
Test status
Simulation time 32306658950 ps
CPU time 345.78 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 01:04:01 PM PDT 24
Peak memory 221236 kb
Host smart-50b043bd-a954-4502-b7f0-d5819c64e200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938766337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2938766337
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4032653506
Short name T387
Test name
Test status
Simulation time 2292375401 ps
CPU time 145.19 seconds
Started Mar 24 01:08:43 PM PDT 24
Finished Mar 24 01:11:08 PM PDT 24
Peak memory 228760 kb
Host smart-23378d10-ec37-46f7-adc3-805fcd38bc29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032653506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4032653506
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1274682838
Short name T471
Test name
Test status
Simulation time 665167439 ps
CPU time 9.31 seconds
Started Mar 24 12:58:16 PM PDT 24
Finished Mar 24 12:58:25 PM PDT 24
Peak memory 211784 kb
Host smart-45f9a181-b763-4a39-88f3-ad70bbfc0abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274682838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1274682838
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1383523548
Short name T23
Test name
Test status
Simulation time 168656530 ps
CPU time 9.55 seconds
Started Mar 24 01:08:42 PM PDT 24
Finished Mar 24 01:08:51 PM PDT 24
Peak memory 211728 kb
Host smart-bb82ecfb-99c1-4ab8-8d75-ea49c9982502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383523548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1383523548
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.263393889
Short name T153
Test name
Test status
Simulation time 99510323 ps
CPU time 5.69 seconds
Started Mar 24 01:08:40 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 211064 kb
Host smart-d0f9047c-f41d-42d3-b1da-ae7893d4b5d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263393889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.263393889
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3116725832
Short name T555
Test name
Test status
Simulation time 4043669320 ps
CPU time 16.37 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:31 PM PDT 24
Peak memory 211172 kb
Host smart-032eecc9-eb73-49e1-bc8f-20a704ce057d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116725832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3116725832
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1122213858
Short name T141
Test name
Test status
Simulation time 1085949484 ps
CPU time 11.65 seconds
Started Mar 24 01:08:46 PM PDT 24
Finished Mar 24 01:08:57 PM PDT 24
Peak memory 213228 kb
Host smart-dd60798b-82e3-461e-a277-1239973aa154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122213858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1122213858
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2549960365
Short name T503
Test name
Test status
Simulation time 16412976807 ps
CPU time 37.74 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:53 PM PDT 24
Peak memory 219452 kb
Host smart-00a3fbb6-7056-4a56-8a54-b0763595fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549960365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2549960365
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2048446972
Short name T264
Test name
Test status
Simulation time 2322034962 ps
CPU time 18.5 seconds
Started Mar 24 01:08:43 PM PDT 24
Finished Mar 24 01:09:01 PM PDT 24
Peak memory 211192 kb
Host smart-19eecf80-a883-486a-a538-0c2d65268378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048446972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2048446972
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3415562877
Short name T190
Test name
Test status
Simulation time 4780505525 ps
CPU time 55.71 seconds
Started Mar 24 12:58:16 PM PDT 24
Finished Mar 24 12:59:11 PM PDT 24
Peak memory 219360 kb
Host smart-c8d36c09-96fd-48eb-b5be-6fe93e882d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415562877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3415562877
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1389299415
Short name T20
Test name
Test status
Simulation time 46228936931 ps
CPU time 3518.08 seconds
Started Mar 24 01:08:43 PM PDT 24
Finished Mar 24 02:07:21 PM PDT 24
Peak memory 232080 kb
Host smart-8f5e2d26-68b4-4241-9d70-e3a071e17bcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389299415 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1389299415
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1232372359
Short name T166
Test name
Test status
Simulation time 2171568738 ps
CPU time 16.71 seconds
Started Mar 24 01:08:49 PM PDT 24
Finished Mar 24 01:09:06 PM PDT 24
Peak memory 211240 kb
Host smart-c862d05a-f1e3-4134-afb8-ac47d45fb187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232372359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1232372359
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1976023993
Short name T572
Test name
Test status
Simulation time 8402709524 ps
CPU time 14.78 seconds
Started Mar 24 12:58:16 PM PDT 24
Finished Mar 24 12:58:31 PM PDT 24
Peak memory 211328 kb
Host smart-093a5563-dab0-4102-a796-b2e717d0c652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976023993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1976023993
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2851540001
Short name T618
Test name
Test status
Simulation time 157312098035 ps
CPU time 262.65 seconds
Started Mar 24 12:58:16 PM PDT 24
Finished Mar 24 01:02:39 PM PDT 24
Peak memory 218784 kb
Host smart-f1d2bffe-8b24-40bd-9ee3-2d5f7c4bf065
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851540001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2851540001
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4085025972
Short name T431
Test name
Test status
Simulation time 378909080666 ps
CPU time 376.07 seconds
Started Mar 24 01:08:46 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 234128 kb
Host smart-9828567a-88af-48d7-bc3b-f1fdc0cce217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085025972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4085025972
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2520781822
Short name T236
Test name
Test status
Simulation time 12062316711 ps
CPU time 21.43 seconds
Started Mar 24 01:08:45 PM PDT 24
Finished Mar 24 01:09:07 PM PDT 24
Peak memory 211332 kb
Host smart-90c85dc5-126c-4738-a2e1-1b1262c183d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520781822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2520781822
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3114058730
Short name T594
Test name
Test status
Simulation time 20862082279 ps
CPU time 33.69 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:49 PM PDT 24
Peak memory 212100 kb
Host smart-84122a9e-3d0c-4303-8241-37c4a44dbf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114058730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3114058730
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3518547113
Short name T613
Test name
Test status
Simulation time 99702066 ps
CPU time 5.58 seconds
Started Mar 24 01:08:42 PM PDT 24
Finished Mar 24 01:08:48 PM PDT 24
Peak memory 211052 kb
Host smart-34cb2df7-cf3a-4097-a128-2e472e2b86ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518547113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3518547113
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4002037366
Short name T365
Test name
Test status
Simulation time 1500453583 ps
CPU time 13.52 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:29 PM PDT 24
Peak memory 211048 kb
Host smart-9406e26d-c014-4d60-ba44-72e39870e678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002037366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4002037366
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1132981434
Short name T316
Test name
Test status
Simulation time 3390901860 ps
CPU time 33.59 seconds
Started Mar 24 01:08:43 PM PDT 24
Finished Mar 24 01:09:17 PM PDT 24
Peak memory 219332 kb
Host smart-b87d4482-395f-4fb0-b6dd-88ba26d00ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132981434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1132981434
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3777014277
Short name T446
Test name
Test status
Simulation time 1134229176 ps
CPU time 17.24 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:32 PM PDT 24
Peak memory 213196 kb
Host smart-3eca6ca7-70ed-4775-b8da-24e842d7c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777014277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3777014277
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3247703094
Short name T219
Test name
Test status
Simulation time 9153697215 ps
CPU time 26.25 seconds
Started Mar 24 12:58:15 PM PDT 24
Finished Mar 24 12:58:42 PM PDT 24
Peak memory 214736 kb
Host smart-8dbfc738-0a92-4b78-bae6-4631d2e2a666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247703094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3247703094
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.727609804
Short name T559
Test name
Test status
Simulation time 5237650361 ps
CPU time 40.79 seconds
Started Mar 24 01:08:42 PM PDT 24
Finished Mar 24 01:09:23 PM PDT 24
Peak memory 213812 kb
Host smart-f29c2023-317e-46a1-ab34-52f97bfb4652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727609804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.727609804
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4069970582
Short name T670
Test name
Test status
Simulation time 95683303949 ps
CPU time 3572.12 seconds
Started Mar 24 01:08:46 PM PDT 24
Finished Mar 24 02:08:18 PM PDT 24
Peak memory 245568 kb
Host smart-7472aec0-b70d-448f-ad4b-56d2acd55327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069970582 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4069970582
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2770729294
Short name T457
Test name
Test status
Simulation time 7284895368 ps
CPU time 16.09 seconds
Started Mar 24 01:08:53 PM PDT 24
Finished Mar 24 01:09:09 PM PDT 24
Peak memory 211292 kb
Host smart-026b0267-bf7f-4c5f-ab2a-2ee60763d14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770729294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2770729294
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2435875238
Short name T408
Test name
Test status
Simulation time 45859845787 ps
CPU time 134.38 seconds
Started Mar 24 01:08:54 PM PDT 24
Finished Mar 24 01:11:08 PM PDT 24
Peak memory 228680 kb
Host smart-c99f84f4-691a-422d-8a0d-4f802aecda59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435875238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2435875238
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.674409994
Short name T677
Test name
Test status
Simulation time 83448649249 ps
CPU time 239.47 seconds
Started Mar 24 12:58:21 PM PDT 24
Finished Mar 24 01:02:20 PM PDT 24
Peak memory 225052 kb
Host smart-90103923-3960-49b8-809f-f2d1e724f2e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674409994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.674409994
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3774324110
Short name T461
Test name
Test status
Simulation time 1378781493 ps
CPU time 11.6 seconds
Started Mar 24 12:58:21 PM PDT 24
Finished Mar 24 12:58:33 PM PDT 24
Peak memory 211820 kb
Host smart-eae3079b-92a0-4085-8655-57f751dc3da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774324110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3774324110
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.89626655
Short name T652
Test name
Test status
Simulation time 19703914027 ps
CPU time 33.01 seconds
Started Mar 24 01:08:53 PM PDT 24
Finished Mar 24 01:09:26 PM PDT 24
Peak memory 211260 kb
Host smart-8f10d3a6-a4eb-404c-a1f8-d9afd19c17b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89626655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.89626655
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4290194448
Short name T437
Test name
Test status
Simulation time 8981487262 ps
CPU time 14.39 seconds
Started Mar 24 01:08:51 PM PDT 24
Finished Mar 24 01:09:06 PM PDT 24
Peak memory 211196 kb
Host smart-0fe6b102-75f9-4711-a2ee-70ebc407f472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290194448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4290194448
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.94687774
Short name T403
Test name
Test status
Simulation time 186995806 ps
CPU time 5.38 seconds
Started Mar 24 12:58:24 PM PDT 24
Finished Mar 24 12:58:29 PM PDT 24
Peak memory 211052 kb
Host smart-e5a135c6-67f9-421e-b96e-1fcdba5b8398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94687774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.94687774
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1074759266
Short name T258
Test name
Test status
Simulation time 5714504950 ps
CPU time 16.07 seconds
Started Mar 24 12:58:14 PM PDT 24
Finished Mar 24 12:58:30 PM PDT 24
Peak memory 214052 kb
Host smart-4db35a26-5dad-42d6-83d0-8deec297c1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074759266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1074759266
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3520870444
Short name T169
Test name
Test status
Simulation time 7935736940 ps
CPU time 22.08 seconds
Started Mar 24 01:08:47 PM PDT 24
Finished Mar 24 01:09:09 PM PDT 24
Peak memory 214212 kb
Host smart-16139667-3fab-4957-b998-719c9ed83c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520870444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3520870444
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2531949565
Short name T332
Test name
Test status
Simulation time 781371132 ps
CPU time 21.35 seconds
Started Mar 24 12:58:20 PM PDT 24
Finished Mar 24 12:58:42 PM PDT 24
Peak memory 214520 kb
Host smart-a8fb8eb7-81d6-40cf-8215-677abc845580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531949565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2531949565
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3028541037
Short name T238
Test name
Test status
Simulation time 4022078915 ps
CPU time 12.26 seconds
Started Mar 24 01:08:49 PM PDT 24
Finished Mar 24 01:09:02 PM PDT 24
Peak memory 212024 kb
Host smart-1de4c493-7ffe-4026-80e8-202edb5c2efd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028541037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3028541037
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2184326466
Short name T65
Test name
Test status
Simulation time 102291045515 ps
CPU time 4289.84 seconds
Started Mar 24 12:58:21 PM PDT 24
Finished Mar 24 02:09:51 PM PDT 24
Peak memory 253328 kb
Host smart-62741523-7d3a-4f87-b15c-2ffd8fed361f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184326466 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2184326466
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1442554716
Short name T449
Test name
Test status
Simulation time 693270672 ps
CPU time 4.27 seconds
Started Mar 24 12:57:06 PM PDT 24
Finished Mar 24 12:57:10 PM PDT 24
Peak memory 211212 kb
Host smart-8cc19758-dc7d-42ed-a038-35cbdf16573d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442554716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1442554716
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1911437468
Short name T294
Test name
Test status
Simulation time 673114470 ps
CPU time 8.2 seconds
Started Mar 24 01:08:01 PM PDT 24
Finished Mar 24 01:08:09 PM PDT 24
Peak memory 211180 kb
Host smart-ec6aa959-50b0-460a-a471-45cc5377404a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911437468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1911437468
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2550802111
Short name T522
Test name
Test status
Simulation time 25504409373 ps
CPU time 72.11 seconds
Started Mar 24 01:08:00 PM PDT 24
Finished Mar 24 01:09:12 PM PDT 24
Peak memory 219548 kb
Host smart-60aae77b-4986-43dc-8276-1761289a53a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550802111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2550802111
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3892659375
Short name T532
Test name
Test status
Simulation time 28558575286 ps
CPU time 290.33 seconds
Started Mar 24 12:57:06 PM PDT 24
Finished Mar 24 01:01:57 PM PDT 24
Peak memory 240908 kb
Host smart-b0db0469-44f9-4005-904d-a8185e56dfa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892659375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3892659375
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.566017356
Short name T550
Test name
Test status
Simulation time 6146325175 ps
CPU time 18.88 seconds
Started Mar 24 01:07:59 PM PDT 24
Finished Mar 24 01:08:19 PM PDT 24
Peak memory 212616 kb
Host smart-0b6b635e-9a95-4d41-b7bc-ced1c90efbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566017356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.566017356
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.895006139
Short name T228
Test name
Test status
Simulation time 34976643358 ps
CPU time 30.35 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 12:57:45 PM PDT 24
Peak memory 212308 kb
Host smart-f1d3117a-aebf-4829-b684-3c3af63653b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895006139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.895006139
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2423525002
Short name T603
Test name
Test status
Simulation time 117093095 ps
CPU time 5.42 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 12:57:19 PM PDT 24
Peak memory 211092 kb
Host smart-08284dcf-d74d-4119-93f4-baa200db1465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423525002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2423525002
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3961827400
Short name T61
Test name
Test status
Simulation time 10321814097 ps
CPU time 13.33 seconds
Started Mar 24 01:08:01 PM PDT 24
Finished Mar 24 01:08:14 PM PDT 24
Peak memory 211236 kb
Host smart-2bbfdaf7-c509-401f-8028-5c9380113573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961827400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3961827400
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3438794444
Short name T42
Test name
Test status
Simulation time 4989892209 ps
CPU time 108.96 seconds
Started Mar 24 01:08:01 PM PDT 24
Finished Mar 24 01:09:50 PM PDT 24
Peak memory 230856 kb
Host smart-a7f2a18c-d52a-4465-bea8-1f7d911cabb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438794444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3438794444
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.967808453
Short name T45
Test name
Test status
Simulation time 669611797 ps
CPU time 55.15 seconds
Started Mar 24 12:57:05 PM PDT 24
Finished Mar 24 12:58:01 PM PDT 24
Peak memory 236704 kb
Host smart-a265c9d3-64c9-4ec6-9adf-7c101f80eb2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967808453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.967808453
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1341014142
Short name T622
Test name
Test status
Simulation time 10318920939 ps
CPU time 27.86 seconds
Started Mar 24 01:08:01 PM PDT 24
Finished Mar 24 01:08:29 PM PDT 24
Peak memory 219460 kb
Host smart-b20ebd95-a98d-4d54-81fc-33d42b3810f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341014142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1341014142
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3421383859
Short name T359
Test name
Test status
Simulation time 367677580 ps
CPU time 10.02 seconds
Started Mar 24 12:57:09 PM PDT 24
Finished Mar 24 12:57:19 PM PDT 24
Peak memory 219280 kb
Host smart-404442c4-4755-46af-8777-0f1e6450f5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421383859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3421383859
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2366310889
Short name T71
Test name
Test status
Simulation time 16083084145 ps
CPU time 104.33 seconds
Started Mar 24 12:57:06 PM PDT 24
Finished Mar 24 12:58:50 PM PDT 24
Peak memory 219440 kb
Host smart-ebb6c0bf-fc7a-4f1f-873e-6be9102fc7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366310889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2366310889
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4069584079
Short name T521
Test name
Test status
Simulation time 14942001264 ps
CPU time 121.42 seconds
Started Mar 24 01:08:01 PM PDT 24
Finished Mar 24 01:10:02 PM PDT 24
Peak memory 219452 kb
Host smart-46c80981-b6e7-4d7a-a21e-bfb6e49795c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069584079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4069584079
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1402583883
Short name T290
Test name
Test status
Simulation time 1960217449 ps
CPU time 15.24 seconds
Started Mar 24 12:58:24 PM PDT 24
Finished Mar 24 12:58:40 PM PDT 24
Peak memory 211140 kb
Host smart-190b872d-0b5a-480f-9c5f-682e048a8afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402583883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1402583883
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4037305827
Short name T614
Test name
Test status
Simulation time 574556513 ps
CPU time 6.37 seconds
Started Mar 24 01:08:54 PM PDT 24
Finished Mar 24 01:09:00 PM PDT 24
Peak memory 211212 kb
Host smart-b7d165d8-c3fb-4ccc-a7bb-37452eacc003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037305827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4037305827
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3958406869
Short name T195
Test name
Test status
Simulation time 64634062693 ps
CPU time 149.5 seconds
Started Mar 24 12:58:22 PM PDT 24
Finished Mar 24 01:00:51 PM PDT 24
Peak memory 212388 kb
Host smart-1bbfc659-1b67-4ade-af4f-82a8d78e6359
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958406869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3958406869
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.662085010
Short name T201
Test name
Test status
Simulation time 131857591388 ps
CPU time 288.67 seconds
Started Mar 24 01:08:54 PM PDT 24
Finished Mar 24 01:13:43 PM PDT 24
Peak memory 228700 kb
Host smart-32f37c9e-2864-4388-b930-3d87871258f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662085010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.662085010
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1245715331
Short name T464
Test name
Test status
Simulation time 1976842863 ps
CPU time 20.78 seconds
Started Mar 24 01:08:55 PM PDT 24
Finished Mar 24 01:09:15 PM PDT 24
Peak memory 211848 kb
Host smart-4862538b-8148-4283-b67d-ea2a7254bbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245715331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1245715331
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.610376
Short name T322
Test name
Test status
Simulation time 4517857950 ps
CPU time 22.79 seconds
Started Mar 24 12:58:21 PM PDT 24
Finished Mar 24 12:58:44 PM PDT 24
Peak memory 212200 kb
Host smart-f3c0dfa4-3c5c-4ec5-a792-54bef15de10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.610376
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2908251329
Short name T155
Test name
Test status
Simulation time 811117027 ps
CPU time 10.27 seconds
Started Mar 24 01:08:53 PM PDT 24
Finished Mar 24 01:09:03 PM PDT 24
Peak memory 211064 kb
Host smart-4225f328-b24b-4cde-8ad3-0ce635037100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908251329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2908251329
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3629442480
Short name T639
Test name
Test status
Simulation time 1547942013 ps
CPU time 13.58 seconds
Started Mar 24 12:58:24 PM PDT 24
Finished Mar 24 12:58:38 PM PDT 24
Peak memory 211028 kb
Host smart-6f22e6e2-3a8d-43fc-bdc9-9a633420ddb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629442480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3629442480
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1946627937
Short name T145
Test name
Test status
Simulation time 2058329522 ps
CPU time 22.29 seconds
Started Mar 24 01:08:55 PM PDT 24
Finished Mar 24 01:09:17 PM PDT 24
Peak memory 212900 kb
Host smart-cc35c567-08ea-4c14-aad0-3ebf4766da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946627937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1946627937
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3047241195
Short name T638
Test name
Test status
Simulation time 14527129065 ps
CPU time 32.07 seconds
Started Mar 24 12:58:22 PM PDT 24
Finished Mar 24 12:58:54 PM PDT 24
Peak memory 213832 kb
Host smart-8924b984-f073-4173-b9ed-0014f3720996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047241195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3047241195
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1436106037
Short name T11
Test name
Test status
Simulation time 1059711434 ps
CPU time 13.6 seconds
Started Mar 24 12:58:24 PM PDT 24
Finished Mar 24 12:58:38 PM PDT 24
Peak memory 211680 kb
Host smart-e43419e2-7e99-4fdb-814d-38ec93208d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436106037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1436106037
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1853840750
Short name T357
Test name
Test status
Simulation time 166409204 ps
CPU time 8.1 seconds
Started Mar 24 01:08:56 PM PDT 24
Finished Mar 24 01:09:04 PM PDT 24
Peak memory 211372 kb
Host smart-35069d75-e2eb-41de-bc67-c1ccecf82de4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853840750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1853840750
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1881063675
Short name T314
Test name
Test status
Simulation time 10149437856 ps
CPU time 13.55 seconds
Started Mar 24 01:09:02 PM PDT 24
Finished Mar 24 01:09:16 PM PDT 24
Peak memory 211240 kb
Host smart-aece61a2-4c87-47cb-9b0e-6af1f2667465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881063675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1881063675
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.400021145
Short name T513
Test name
Test status
Simulation time 333708910 ps
CPU time 4.39 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:30 PM PDT 24
Peak memory 211424 kb
Host smart-dc733888-e8a1-4dda-9b9e-3f87d29141ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400021145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.400021145
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.19872915
Short name T255
Test name
Test status
Simulation time 5867923362 ps
CPU time 94.43 seconds
Started Mar 24 01:08:53 PM PDT 24
Finished Mar 24 01:10:28 PM PDT 24
Peak memory 229920 kb
Host smart-53eb4824-2b51-4269-a39d-ab64dc06c0d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19872915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_co
rrupt_sig_fatal_chk.19872915
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4159386546
Short name T136
Test name
Test status
Simulation time 9002371610 ps
CPU time 107.62 seconds
Started Mar 24 12:58:21 PM PDT 24
Finished Mar 24 01:00:09 PM PDT 24
Peak memory 237812 kb
Host smart-537426c8-b3f8-4c82-9458-db84adf2b9de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159386546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4159386546
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2042809198
Short name T666
Test name
Test status
Simulation time 2544182226 ps
CPU time 25.11 seconds
Started Mar 24 01:08:59 PM PDT 24
Finished Mar 24 01:09:25 PM PDT 24
Peak memory 212044 kb
Host smart-b746a2b1-03f1-4dff-8ef2-07e8c10ca636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042809198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2042809198
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2273631064
Short name T504
Test name
Test status
Simulation time 641277952 ps
CPU time 9.37 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:35 PM PDT 24
Peak memory 212312 kb
Host smart-c9213f9a-0da9-4447-bbf7-b4b0eec16842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273631064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2273631064
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1308162088
Short name T546
Test name
Test status
Simulation time 1265370129 ps
CPU time 12.36 seconds
Started Mar 24 12:58:24 PM PDT 24
Finished Mar 24 12:58:37 PM PDT 24
Peak memory 211028 kb
Host smart-528d8f50-be28-4833-a314-625aae275cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308162088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1308162088
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3804658732
Short name T456
Test name
Test status
Simulation time 1840036088 ps
CPU time 16.7 seconds
Started Mar 24 01:08:52 PM PDT 24
Finished Mar 24 01:09:09 PM PDT 24
Peak memory 211096 kb
Host smart-5beb77ea-285e-4f02-a90c-b1b81dd1b062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804658732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3804658732
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.127265560
Short name T251
Test name
Test status
Simulation time 188944569 ps
CPU time 10.43 seconds
Started Mar 24 12:58:22 PM PDT 24
Finished Mar 24 12:58:32 PM PDT 24
Peak memory 213336 kb
Host smart-3dde7d45-b213-4ded-a105-eb5cee1a70a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127265560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.127265560
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1361076180
Short name T647
Test name
Test status
Simulation time 2834901734 ps
CPU time 25.35 seconds
Started Mar 24 01:08:55 PM PDT 24
Finished Mar 24 01:09:20 PM PDT 24
Peak memory 213200 kb
Host smart-e545b51e-4513-4e8a-8eee-4d4abe8338ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361076180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1361076180
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1030125462
Short name T418
Test name
Test status
Simulation time 8465324679 ps
CPU time 85 seconds
Started Mar 24 12:58:22 PM PDT 24
Finished Mar 24 12:59:47 PM PDT 24
Peak memory 216368 kb
Host smart-9e7869b4-e8d6-422d-a5e9-aaa3e60d1e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030125462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1030125462
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.233724179
Short name T605
Test name
Test status
Simulation time 41100936352 ps
CPU time 81.95 seconds
Started Mar 24 01:08:54 PM PDT 24
Finished Mar 24 01:10:16 PM PDT 24
Peak memory 219412 kb
Host smart-cbf130f9-ef42-4260-aee9-339f06ec50d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233724179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.233724179
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1930776389
Short name T376
Test name
Test status
Simulation time 2226687114 ps
CPU time 7.73 seconds
Started Mar 24 01:09:00 PM PDT 24
Finished Mar 24 01:09:07 PM PDT 24
Peak memory 211320 kb
Host smart-5496b3bc-a401-48f5-93a7-dc6d4c64f9d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930776389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1930776389
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4086472745
Short name T416
Test name
Test status
Simulation time 21240696252 ps
CPU time 11.12 seconds
Started Mar 24 12:58:25 PM PDT 24
Finished Mar 24 12:58:36 PM PDT 24
Peak memory 211312 kb
Host smart-c9c7625f-a76f-4a1c-8fa0-7927bc56905a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086472745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4086472745
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2152839477
Short name T137
Test name
Test status
Simulation time 58628660776 ps
CPU time 141.96 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 01:00:48 PM PDT 24
Peak memory 220512 kb
Host smart-1e93e2d8-d986-47b0-8721-44b8a7475816
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152839477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2152839477
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.271121457
Short name T273
Test name
Test status
Simulation time 28459244432 ps
CPU time 139.72 seconds
Started Mar 24 01:08:59 PM PDT 24
Finished Mar 24 01:11:19 PM PDT 24
Peak memory 230088 kb
Host smart-ce6fad60-b934-4e7e-9a7d-5a352381f248
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271121457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.271121457
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1452196257
Short name T583
Test name
Test status
Simulation time 845343476 ps
CPU time 12.21 seconds
Started Mar 24 01:09:03 PM PDT 24
Finished Mar 24 01:09:15 PM PDT 24
Peak memory 211864 kb
Host smart-08dc892e-f1de-4d8a-9b34-4ab0cfc7ffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452196257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1452196257
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1867836446
Short name T321
Test name
Test status
Simulation time 2229772989 ps
CPU time 22.57 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:49 PM PDT 24
Peak memory 211836 kb
Host smart-716aea3f-0990-4ee1-9e58-0a1cebbe2d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867836446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1867836446
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3258744097
Short name T207
Test name
Test status
Simulation time 939240025 ps
CPU time 10.61 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:36 PM PDT 24
Peak memory 211088 kb
Host smart-b609cef8-2b99-4a95-a932-745c951ac6e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258744097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3258744097
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3666285577
Short name T237
Test name
Test status
Simulation time 1571874707 ps
CPU time 5.87 seconds
Started Mar 24 01:09:00 PM PDT 24
Finished Mar 24 01:09:06 PM PDT 24
Peak memory 211044 kb
Host smart-e24aea84-3157-4f26-a3e1-87b75c2eca74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666285577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3666285577
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3699090925
Short name T261
Test name
Test status
Simulation time 9749283736 ps
CPU time 30.09 seconds
Started Mar 24 01:08:58 PM PDT 24
Finished Mar 24 01:09:28 PM PDT 24
Peak memory 219432 kb
Host smart-00500606-df8b-4e8f-a419-ff00882715b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699090925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3699090925
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.573184836
Short name T256
Test name
Test status
Simulation time 3982847937 ps
CPU time 39.48 seconds
Started Mar 24 12:58:28 PM PDT 24
Finished Mar 24 12:59:08 PM PDT 24
Peak memory 212892 kb
Host smart-f8ec3c82-ddf6-4255-9ae4-93d88029db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573184836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.573184836
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2735407047
Short name T560
Test name
Test status
Simulation time 6958394676 ps
CPU time 79.02 seconds
Started Mar 24 12:58:27 PM PDT 24
Finished Mar 24 12:59:46 PM PDT 24
Peak memory 217180 kb
Host smart-eafd67ac-d6ff-4109-afe7-ad952674d268
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735407047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2735407047
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.987161345
Short name T454
Test name
Test status
Simulation time 10268345315 ps
CPU time 32.75 seconds
Started Mar 24 01:09:00 PM PDT 24
Finished Mar 24 01:09:33 PM PDT 24
Peak memory 219400 kb
Host smart-5dfc4dc6-3d20-4ada-b45f-1c9a5a358ade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987161345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.987161345
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1675059159
Short name T179
Test name
Test status
Simulation time 21086715083 ps
CPU time 12.24 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:38 PM PDT 24
Peak memory 211324 kb
Host smart-b4b44005-0f16-458d-a679-78b64bea0176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675059159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1675059159
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.70592004
Short name T178
Test name
Test status
Simulation time 168621205 ps
CPU time 4.35 seconds
Started Mar 24 01:08:58 PM PDT 24
Finished Mar 24 01:09:03 PM PDT 24
Peak memory 211144 kb
Host smart-f7f691c1-982c-4f5a-857a-216c75b85aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70592004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.70592004
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1463887041
Short name T673
Test name
Test status
Simulation time 39923112455 ps
CPU time 409.02 seconds
Started Mar 24 12:58:29 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 229064 kb
Host smart-62c63de0-7b2d-496b-8ad8-cba1015f35f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463887041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1463887041
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.754434601
Short name T32
Test name
Test status
Simulation time 270799730358 ps
CPU time 513.29 seconds
Started Mar 24 01:08:58 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 212948 kb
Host smart-b365d4a9-853a-4be6-9dae-fe987331061a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754434601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.754434601
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.296883324
Short name T391
Test name
Test status
Simulation time 13103556135 ps
CPU time 30.24 seconds
Started Mar 24 01:08:58 PM PDT 24
Finished Mar 24 01:09:29 PM PDT 24
Peak memory 211316 kb
Host smart-0f035928-d33b-4ddd-aa0b-fbb6c0db6961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296883324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.296883324
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3382605070
Short name T393
Test name
Test status
Simulation time 2203925633 ps
CPU time 22.66 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:49 PM PDT 24
Peak memory 211844 kb
Host smart-2105fba2-1a75-49ad-bf02-47a2c879359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382605070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3382605070
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3347358473
Short name T106
Test name
Test status
Simulation time 1226373010 ps
CPU time 8.25 seconds
Started Mar 24 01:09:00 PM PDT 24
Finished Mar 24 01:09:08 PM PDT 24
Peak memory 211112 kb
Host smart-37cbe1e4-4a57-480e-9120-1279b8050481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347358473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3347358473
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4056275216
Short name T152
Test name
Test status
Simulation time 6144664201 ps
CPU time 14.04 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:41 PM PDT 24
Peak memory 211176 kb
Host smart-23175ae3-cace-40ed-be5f-8fddf2b6aa8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056275216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4056275216
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3395096454
Short name T9
Test name
Test status
Simulation time 3227118724 ps
CPU time 20.06 seconds
Started Mar 24 12:58:28 PM PDT 24
Finished Mar 24 12:58:48 PM PDT 24
Peak memory 213796 kb
Host smart-b0745216-5b3b-4163-9c6b-7d283580922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395096454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3395096454
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4185990967
Short name T653
Test name
Test status
Simulation time 4016627723 ps
CPU time 18.84 seconds
Started Mar 24 01:09:00 PM PDT 24
Finished Mar 24 01:09:19 PM PDT 24
Peak memory 219396 kb
Host smart-10ac0ede-fe69-4589-ab30-7820e43fd325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185990967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4185990967
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1729264296
Short name T534
Test name
Test status
Simulation time 2200460466 ps
CPU time 27.04 seconds
Started Mar 24 12:58:28 PM PDT 24
Finished Mar 24 12:58:55 PM PDT 24
Peak memory 219436 kb
Host smart-8f50a05e-85a1-4be4-aae8-36daf3ad3a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729264296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1729264296
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.457785311
Short name T463
Test name
Test status
Simulation time 3747490269 ps
CPU time 32.28 seconds
Started Mar 24 01:09:01 PM PDT 24
Finished Mar 24 01:09:34 PM PDT 24
Peak memory 219408 kb
Host smart-28e20935-01a1-4932-86af-5b7027290aab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457785311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.457785311
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1274382666
Short name T530
Test name
Test status
Simulation time 2052983084 ps
CPU time 16.26 seconds
Started Mar 24 01:09:01 PM PDT 24
Finished Mar 24 01:09:17 PM PDT 24
Peak memory 211220 kb
Host smart-d391c59f-a9ce-4dbd-9998-baf5a035dce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274382666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1274382666
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4245537730
Short name T196
Test name
Test status
Simulation time 1395256144 ps
CPU time 12.03 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:38 PM PDT 24
Peak memory 211220 kb
Host smart-490519e9-70ab-49ab-9eeb-bdb4f1752aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245537730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4245537730
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2701996110
Short name T341
Test name
Test status
Simulation time 33149519716 ps
CPU time 324.49 seconds
Started Mar 24 01:09:01 PM PDT 24
Finished Mar 24 01:14:26 PM PDT 24
Peak memory 223512 kb
Host smart-f1b580dc-d565-430a-9800-aeeded35c7b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701996110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2701996110
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3028049565
Short name T173
Test name
Test status
Simulation time 11955653763 ps
CPU time 149.04 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 01:00:55 PM PDT 24
Peak memory 213592 kb
Host smart-6661ca59-f21c-4387-85a1-3bccd335e72b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028049565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3028049565
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.245790241
Short name T662
Test name
Test status
Simulation time 2849311460 ps
CPU time 24.01 seconds
Started Mar 24 12:58:27 PM PDT 24
Finished Mar 24 12:58:51 PM PDT 24
Peak memory 212060 kb
Host smart-03903953-68fc-46da-8dff-f25abce296cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245790241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.245790241
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3970431216
Short name T235
Test name
Test status
Simulation time 496241731 ps
CPU time 13.12 seconds
Started Mar 24 01:09:01 PM PDT 24
Finished Mar 24 01:09:14 PM PDT 24
Peak memory 211868 kb
Host smart-2015e6a3-e914-408f-a144-30e77715632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970431216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3970431216
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1922001380
Short name T362
Test name
Test status
Simulation time 361968209 ps
CPU time 5.58 seconds
Started Mar 24 12:58:27 PM PDT 24
Finished Mar 24 12:58:33 PM PDT 24
Peak memory 211296 kb
Host smart-0b5fa127-5a3b-4795-b136-c68f6dbf5487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922001380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1922001380
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3566335601
Short name T442
Test name
Test status
Simulation time 3529105687 ps
CPU time 15.32 seconds
Started Mar 24 01:09:00 PM PDT 24
Finished Mar 24 01:09:16 PM PDT 24
Peak memory 211160 kb
Host smart-379ec7b4-6691-48c7-981f-f319280dc4fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566335601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3566335601
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1447589520
Short name T5
Test name
Test status
Simulation time 2998345117 ps
CPU time 26.4 seconds
Started Mar 24 12:58:25 PM PDT 24
Finished Mar 24 12:58:52 PM PDT 24
Peak memory 213220 kb
Host smart-e630c448-cbbf-4f0c-a505-381af685e06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447589520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1447589520
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2373369825
Short name T659
Test name
Test status
Simulation time 354555385 ps
CPU time 9.87 seconds
Started Mar 24 01:09:00 PM PDT 24
Finished Mar 24 01:09:10 PM PDT 24
Peak memory 213140 kb
Host smart-551a9691-750b-4ddf-b1a2-d3bba3beb59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373369825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2373369825
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2052652470
Short name T302
Test name
Test status
Simulation time 10097409075 ps
CPU time 44.7 seconds
Started Mar 24 01:08:58 PM PDT 24
Finished Mar 24 01:09:43 PM PDT 24
Peak memory 216328 kb
Host smart-d6afea22-7482-4783-8181-a8cf0fd2d6e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052652470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2052652470
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2580302545
Short name T51
Test name
Test status
Simulation time 403232062 ps
CPU time 11.85 seconds
Started Mar 24 12:58:25 PM PDT 24
Finished Mar 24 12:58:37 PM PDT 24
Peak memory 213828 kb
Host smart-d0407fe7-2d2e-4635-a76a-05201a8eec36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580302545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2580302545
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.340570864
Short name T644
Test name
Test status
Simulation time 1822465058 ps
CPU time 14.49 seconds
Started Mar 24 12:58:35 PM PDT 24
Finished Mar 24 12:58:50 PM PDT 24
Peak memory 211164 kb
Host smart-dd1bcc1f-0272-4d9b-81ca-d093791b69b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340570864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.340570864
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.819700324
Short name T604
Test name
Test status
Simulation time 493351311 ps
CPU time 7.09 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:09:18 PM PDT 24
Peak memory 211424 kb
Host smart-aaaae73b-0271-40c9-a0aa-293e38433aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819700324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.819700324
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.214473254
Short name T578
Test name
Test status
Simulation time 27772325574 ps
CPU time 111.49 seconds
Started Mar 24 12:58:31 PM PDT 24
Finished Mar 24 01:00:23 PM PDT 24
Peak memory 236888 kb
Host smart-b3a8c390-c546-4c9d-a84b-89b408c798b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214473254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.214473254
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3415515504
Short name T494
Test name
Test status
Simulation time 9301112095 ps
CPU time 99.81 seconds
Started Mar 24 01:09:06 PM PDT 24
Finished Mar 24 01:10:46 PM PDT 24
Peak memory 237924 kb
Host smart-c1b51e0b-c469-47d7-b064-0980437f4a48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415515504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3415515504
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.568661700
Short name T582
Test name
Test status
Simulation time 15708434311 ps
CPU time 33.42 seconds
Started Mar 24 12:58:32 PM PDT 24
Finished Mar 24 12:59:06 PM PDT 24
Peak memory 211976 kb
Host smart-13e9e058-8b1d-4889-9370-f45ae01e6563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568661700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.568661700
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.792667946
Short name T379
Test name
Test status
Simulation time 3291151122 ps
CPU time 20.09 seconds
Started Mar 24 01:09:09 PM PDT 24
Finished Mar 24 01:09:29 PM PDT 24
Peak memory 211888 kb
Host smart-3869f6a9-74a0-46a3-b6a1-4f620a8cd9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792667946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.792667946
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3319879634
Short name T240
Test name
Test status
Simulation time 2198460121 ps
CPU time 17.37 seconds
Started Mar 24 12:58:33 PM PDT 24
Finished Mar 24 12:58:50 PM PDT 24
Peak memory 211096 kb
Host smart-11e39593-d3fd-45f3-bdae-800ff294d09d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319879634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3319879634
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.671365513
Short name T327
Test name
Test status
Simulation time 1250742687 ps
CPU time 13.04 seconds
Started Mar 24 01:09:06 PM PDT 24
Finished Mar 24 01:09:19 PM PDT 24
Peak memory 211100 kb
Host smart-627674d4-0b3d-494e-add0-8f9917895e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671365513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.671365513
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1818781226
Short name T548
Test name
Test status
Simulation time 3439696711 ps
CPU time 22.25 seconds
Started Mar 24 01:08:59 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 213120 kb
Host smart-065d5dfa-bad2-46e9-9ed1-3c9a37975668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818781226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1818781226
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.665716138
Short name T474
Test name
Test status
Simulation time 7767599799 ps
CPU time 19.67 seconds
Started Mar 24 12:58:26 PM PDT 24
Finished Mar 24 12:58:46 PM PDT 24
Peak memory 214784 kb
Host smart-45497f4f-1de0-4ecb-9c1d-108b5307ff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665716138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.665716138
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3634137210
Short name T317
Test name
Test status
Simulation time 6585908818 ps
CPU time 23.52 seconds
Started Mar 24 12:58:28 PM PDT 24
Finished Mar 24 12:58:52 PM PDT 24
Peak memory 215020 kb
Host smart-1e1220cf-cb54-43ef-abd7-481558cffb53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634137210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3634137210
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.880233164
Short name T208
Test name
Test status
Simulation time 3779102186 ps
CPU time 41.13 seconds
Started Mar 24 01:08:58 PM PDT 24
Finished Mar 24 01:09:39 PM PDT 24
Peak memory 215952 kb
Host smart-cefb758a-c311-4f28-9141-d0623f249e3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880233164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.880233164
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1176939046
Short name T198
Test name
Test status
Simulation time 1717548499 ps
CPU time 9.71 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:09:22 PM PDT 24
Peak memory 211100 kb
Host smart-59c6b61c-1464-45b6-99fa-530513857c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176939046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1176939046
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2382627022
Short name T311
Test name
Test status
Simulation time 754546120 ps
CPU time 7.05 seconds
Started Mar 24 12:58:38 PM PDT 24
Finished Mar 24 12:58:45 PM PDT 24
Peak memory 211204 kb
Host smart-5ba13a50-e217-4fff-9353-e73d73b7d37c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382627022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2382627022
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.116705234
Short name T669
Test name
Test status
Simulation time 23779976129 ps
CPU time 116.21 seconds
Started Mar 24 12:58:35 PM PDT 24
Finished Mar 24 01:00:31 PM PDT 24
Peak memory 228928 kb
Host smart-dd729263-257e-4b89-a7fb-aaed9af7c545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116705234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.116705234
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.11974136
Short name T183
Test name
Test status
Simulation time 4315236570 ps
CPU time 87.62 seconds
Started Mar 24 01:09:06 PM PDT 24
Finished Mar 24 01:10:33 PM PDT 24
Peak memory 237216 kb
Host smart-a05789d5-4cda-4067-a8ae-9127bf0bd60d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11974136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_co
rrupt_sig_fatal_chk.11974136
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2366247703
Short name T667
Test name
Test status
Simulation time 1859287652 ps
CPU time 21.25 seconds
Started Mar 24 01:09:05 PM PDT 24
Finished Mar 24 01:09:27 PM PDT 24
Peak memory 211952 kb
Host smart-7887ba32-018c-4d2a-aae1-8040b1046a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366247703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2366247703
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3368397303
Short name T320
Test name
Test status
Simulation time 11375343978 ps
CPU time 25.93 seconds
Started Mar 24 12:58:33 PM PDT 24
Finished Mar 24 12:59:00 PM PDT 24
Peak memory 212224 kb
Host smart-2ce85d23-d2e1-4bae-9419-7ddc0e2d066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368397303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3368397303
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1562147332
Short name T660
Test name
Test status
Simulation time 1138897528 ps
CPU time 12.27 seconds
Started Mar 24 01:09:09 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 211056 kb
Host smart-cfebb565-9175-4674-87a1-802f2415cbfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562147332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1562147332
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.371745077
Short name T399
Test name
Test status
Simulation time 7776244698 ps
CPU time 15.25 seconds
Started Mar 24 12:58:32 PM PDT 24
Finished Mar 24 12:58:48 PM PDT 24
Peak memory 211172 kb
Host smart-dc54a4cf-43e1-49c6-9ce2-56f7a8e1599a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371745077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.371745077
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2873432750
Short name T385
Test name
Test status
Simulation time 10092133892 ps
CPU time 31.52 seconds
Started Mar 24 01:09:08 PM PDT 24
Finished Mar 24 01:09:40 PM PDT 24
Peak memory 213604 kb
Host smart-474c7223-aa22-4705-8a50-e314b3c2afa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873432750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2873432750
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3420037307
Short name T12
Test name
Test status
Simulation time 4015242150 ps
CPU time 27.89 seconds
Started Mar 24 12:58:33 PM PDT 24
Finished Mar 24 12:59:01 PM PDT 24
Peak memory 217048 kb
Host smart-77952f98-33bd-4b0a-9936-bc6a90f72c5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420037307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3420037307
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3528749007
Short name T319
Test name
Test status
Simulation time 10147842608 ps
CPU time 60.4 seconds
Started Mar 24 01:09:07 PM PDT 24
Finished Mar 24 01:10:08 PM PDT 24
Peak memory 219456 kb
Host smart-9aab7b5c-3616-406c-82f5-7192d22e0829
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528749007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3528749007
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2213705479
Short name T119
Test name
Test status
Simulation time 88861518866 ps
CPU time 1546.66 seconds
Started Mar 24 12:58:38 PM PDT 24
Finished Mar 24 01:24:25 PM PDT 24
Peak memory 233828 kb
Host smart-cbd2e283-7a3f-4d97-96b3-9a651c167562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213705479 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2213705479
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1167324512
Short name T488
Test name
Test status
Simulation time 3797884968 ps
CPU time 15.46 seconds
Started Mar 24 01:09:07 PM PDT 24
Finished Mar 24 01:09:23 PM PDT 24
Peak memory 211328 kb
Host smart-d03ca47e-96ad-407e-bf2c-c306dffed0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167324512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1167324512
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.48791944
Short name T422
Test name
Test status
Simulation time 518948632 ps
CPU time 5.21 seconds
Started Mar 24 12:58:38 PM PDT 24
Finished Mar 24 12:58:44 PM PDT 24
Peak memory 211180 kb
Host smart-480a866f-454e-42af-9577-677551c7d3ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48791944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.48791944
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.271248366
Short name T566
Test name
Test status
Simulation time 5802427905 ps
CPU time 79.06 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:10:31 PM PDT 24
Peak memory 212660 kb
Host smart-b1fac0ec-38be-4d2f-8e30-f15c765fb2d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271248366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.271248366
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3843063984
Short name T436
Test name
Test status
Simulation time 24473848255 ps
CPU time 199.88 seconds
Started Mar 24 12:58:40 PM PDT 24
Finished Mar 24 01:02:00 PM PDT 24
Peak memory 237832 kb
Host smart-71d8a968-26ca-4a94-9129-00d18c306eb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843063984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3843063984
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.938335540
Short name T607
Test name
Test status
Simulation time 6058405247 ps
CPU time 27.96 seconds
Started Mar 24 01:09:05 PM PDT 24
Finished Mar 24 01:09:33 PM PDT 24
Peak memory 212312 kb
Host smart-b780c2b4-d275-4087-9f3b-71766ac31df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938335540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.938335540
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2873397086
Short name T161
Test name
Test status
Simulation time 1348467132 ps
CPU time 13.27 seconds
Started Mar 24 12:58:39 PM PDT 24
Finished Mar 24 12:58:53 PM PDT 24
Peak memory 210964 kb
Host smart-5bbe5884-f6c4-4aa9-8d6e-b6e190e9dd46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873397086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2873397086
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3670916902
Short name T663
Test name
Test status
Simulation time 2826996301 ps
CPU time 13.59 seconds
Started Mar 24 01:09:09 PM PDT 24
Finished Mar 24 01:09:23 PM PDT 24
Peak memory 211188 kb
Host smart-a8e764eb-7d68-43fa-9d0e-5dad13f170ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670916902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3670916902
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3566714437
Short name T360
Test name
Test status
Simulation time 3359727708 ps
CPU time 22.57 seconds
Started Mar 24 12:58:38 PM PDT 24
Finished Mar 24 12:59:01 PM PDT 24
Peak memory 213372 kb
Host smart-54e2aafd-9f70-467c-ab35-005a6cd1a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566714437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3566714437
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4152704348
Short name T355
Test name
Test status
Simulation time 10605125309 ps
CPU time 28.62 seconds
Started Mar 24 01:09:07 PM PDT 24
Finished Mar 24 01:09:36 PM PDT 24
Peak memory 219420 kb
Host smart-ea6d409c-60d5-46c1-956f-7f4004b19cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152704348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4152704348
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2823694420
Short name T295
Test name
Test status
Simulation time 2595574599 ps
CPU time 20.76 seconds
Started Mar 24 12:58:37 PM PDT 24
Finished Mar 24 12:58:58 PM PDT 24
Peak memory 215060 kb
Host smart-b7f2a257-7a30-4ab5-8ab8-71f755bcfe35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823694420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2823694420
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4237636924
Short name T641
Test name
Test status
Simulation time 12661399849 ps
CPU time 31.32 seconds
Started Mar 24 01:09:08 PM PDT 24
Finished Mar 24 01:09:39 PM PDT 24
Peak memory 214996 kb
Host smart-fd232910-d40b-45ad-89ac-64e8c1d3027e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237636924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4237636924
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2275264484
Short name T498
Test name
Test status
Simulation time 2156971815 ps
CPU time 16.18 seconds
Started Mar 24 12:58:39 PM PDT 24
Finished Mar 24 12:58:55 PM PDT 24
Peak memory 211288 kb
Host smart-c065f32a-8f7b-4594-98c4-c5741c84a572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275264484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2275264484
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3563655391
Short name T356
Test name
Test status
Simulation time 2109409943 ps
CPU time 16.2 seconds
Started Mar 24 01:09:05 PM PDT 24
Finished Mar 24 01:09:22 PM PDT 24
Peak memory 211212 kb
Host smart-be44f04e-2282-4776-9197-8ee5bbbc327c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563655391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3563655391
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1038418155
Short name T284
Test name
Test status
Simulation time 2576936440 ps
CPU time 75.53 seconds
Started Mar 24 01:09:06 PM PDT 24
Finished Mar 24 01:10:22 PM PDT 24
Peak memory 229476 kb
Host smart-9688ff2a-9704-4629-a599-909ab5e248c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038418155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1038418155
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2251208469
Short name T648
Test name
Test status
Simulation time 18811962079 ps
CPU time 127.21 seconds
Started Mar 24 12:58:40 PM PDT 24
Finished Mar 24 01:00:47 PM PDT 24
Peak memory 230692 kb
Host smart-db604c33-350c-4360-93a3-840b0ea37e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251208469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2251208469
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1412565980
Short name T220
Test name
Test status
Simulation time 2638541102 ps
CPU time 14.01 seconds
Started Mar 24 01:09:08 PM PDT 24
Finished Mar 24 01:09:22 PM PDT 24
Peak memory 212092 kb
Host smart-642995d5-47e5-49ba-be30-d413dfc1ad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412565980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1412565980
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1828508549
Short name T200
Test name
Test status
Simulation time 1539851641 ps
CPU time 19.11 seconds
Started Mar 24 12:58:43 PM PDT 24
Finished Mar 24 12:59:03 PM PDT 24
Peak memory 211216 kb
Host smart-c37f24eb-a0e7-4b04-a8fc-4654f2f410bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828508549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1828508549
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1079422780
Short name T554
Test name
Test status
Simulation time 5182155685 ps
CPU time 13.18 seconds
Started Mar 24 01:09:07 PM PDT 24
Finished Mar 24 01:09:20 PM PDT 24
Peak memory 211220 kb
Host smart-26fcc4b8-7a47-44ae-8923-6787a680c463
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079422780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1079422780
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.835937282
Short name T383
Test name
Test status
Simulation time 319185529 ps
CPU time 7.47 seconds
Started Mar 24 12:58:43 PM PDT 24
Finished Mar 24 12:58:50 PM PDT 24
Peak memory 211100 kb
Host smart-ea023c49-ccfd-476f-ae9c-09627c34f977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=835937282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.835937282
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1343164015
Short name T289
Test name
Test status
Simulation time 13613364177 ps
CPU time 35.17 seconds
Started Mar 24 12:58:39 PM PDT 24
Finished Mar 24 12:59:14 PM PDT 24
Peak memory 219436 kb
Host smart-74b41269-c48e-4e15-842f-1b41070353e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343164015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1343164015
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1550503412
Short name T347
Test name
Test status
Simulation time 6540351626 ps
CPU time 34.43 seconds
Started Mar 24 01:09:08 PM PDT 24
Finished Mar 24 01:09:42 PM PDT 24
Peak memory 219456 kb
Host smart-9cf5ed5f-ea86-4031-8264-a867bf9168ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550503412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1550503412
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1647678834
Short name T533
Test name
Test status
Simulation time 825913454 ps
CPU time 15.01 seconds
Started Mar 24 01:09:06 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 219312 kb
Host smart-d11b1426-c57f-46fc-91c2-b471560a1fbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647678834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1647678834
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3792326592
Short name T223
Test name
Test status
Simulation time 69946481825 ps
CPU time 76.99 seconds
Started Mar 24 12:58:41 PM PDT 24
Finished Mar 24 12:59:59 PM PDT 24
Peak memory 219428 kb
Host smart-61368b2b-bda9-47e9-93bd-d870bd8c14ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792326592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3792326592
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.512463592
Short name T307
Test name
Test status
Simulation time 58666198945 ps
CPU time 1674.39 seconds
Started Mar 24 12:58:41 PM PDT 24
Finished Mar 24 01:26:36 PM PDT 24
Peak memory 235784 kb
Host smart-032378a6-8b4b-4c48-ad74-cbc3387e4f96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512463592 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.512463592
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3842068629
Short name T192
Test name
Test status
Simulation time 177933004 ps
CPU time 5.45 seconds
Started Mar 24 12:58:38 PM PDT 24
Finished Mar 24 12:58:44 PM PDT 24
Peak memory 211212 kb
Host smart-0bc624e3-72ad-42f9-a821-33f0d01a5365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842068629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3842068629
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.983521555
Short name T654
Test name
Test status
Simulation time 3379867704 ps
CPU time 10.31 seconds
Started Mar 24 01:09:15 PM PDT 24
Finished Mar 24 01:09:25 PM PDT 24
Peak memory 211308 kb
Host smart-76dc1c03-01b0-45e6-a498-f39e535cec85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983521555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.983521555
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1076419638
Short name T484
Test name
Test status
Simulation time 10551492328 ps
CPU time 291.74 seconds
Started Mar 24 12:58:41 PM PDT 24
Finished Mar 24 01:03:32 PM PDT 24
Peak memory 237004 kb
Host smart-ba5295ef-374d-4827-9019-8d1ae62bd813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076419638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1076419638
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.398966744
Short name T481
Test name
Test status
Simulation time 41007558107 ps
CPU time 257.14 seconds
Started Mar 24 01:09:13 PM PDT 24
Finished Mar 24 01:13:30 PM PDT 24
Peak memory 225744 kb
Host smart-1374980f-9c51-4131-9d20-e66bd09bacc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398966744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.398966744
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.166255370
Short name T492
Test name
Test status
Simulation time 1654576724 ps
CPU time 12.39 seconds
Started Mar 24 01:09:18 PM PDT 24
Finished Mar 24 01:09:30 PM PDT 24
Peak memory 211176 kb
Host smart-7037e8dc-a9da-44b2-b897-9defaac6aaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166255370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.166255370
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2038511031
Short name T382
Test name
Test status
Simulation time 664204398 ps
CPU time 9.34 seconds
Started Mar 24 12:58:40 PM PDT 24
Finished Mar 24 12:58:50 PM PDT 24
Peak memory 211820 kb
Host smart-1ab0da3a-0e5d-4d7e-9ae0-0c3c3da290b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038511031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2038511031
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1382048855
Short name T624
Test name
Test status
Simulation time 2113582638 ps
CPU time 17.02 seconds
Started Mar 24 01:09:07 PM PDT 24
Finished Mar 24 01:09:24 PM PDT 24
Peak memory 211088 kb
Host smart-b4d7aa59-9272-4d5b-b729-b333876ab954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382048855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1382048855
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2801264313
Short name T291
Test name
Test status
Simulation time 2267704399 ps
CPU time 11.79 seconds
Started Mar 24 12:58:38 PM PDT 24
Finished Mar 24 12:58:50 PM PDT 24
Peak memory 211220 kb
Host smart-249e8d45-be0b-412e-840d-2cbdd5b3bf27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801264313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2801264313
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2209264189
Short name T475
Test name
Test status
Simulation time 1722258154 ps
CPU time 22.1 seconds
Started Mar 24 12:58:39 PM PDT 24
Finished Mar 24 12:59:02 PM PDT 24
Peak memory 219288 kb
Host smart-eb33eb1f-778b-47ef-8d68-55a6a80fd85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209264189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2209264189
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2931191774
Short name T353
Test name
Test status
Simulation time 5315354572 ps
CPU time 25.15 seconds
Started Mar 24 01:09:09 PM PDT 24
Finished Mar 24 01:09:35 PM PDT 24
Peak memory 213524 kb
Host smart-577c49d2-e35a-44c7-b3b7-0fa9259a7994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931191774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2931191774
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1481549722
Short name T203
Test name
Test status
Simulation time 33482656265 ps
CPU time 52.88 seconds
Started Mar 24 01:09:06 PM PDT 24
Finished Mar 24 01:10:00 PM PDT 24
Peak memory 219404 kb
Host smart-87dfd052-a73c-4d30-9a1e-043069841a65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481549722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1481549722
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2255763977
Short name T633
Test name
Test status
Simulation time 50576717377 ps
CPU time 59.55 seconds
Started Mar 24 12:58:40 PM PDT 24
Finished Mar 24 12:59:40 PM PDT 24
Peak memory 219316 kb
Host smart-cbf9e552-2aeb-4b18-8c93-05f0d3d6a5cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255763977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2255763977
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3269575957
Short name T211
Test name
Test status
Simulation time 2247830473 ps
CPU time 16.79 seconds
Started Mar 24 12:57:06 PM PDT 24
Finished Mar 24 12:57:23 PM PDT 24
Peak memory 211332 kb
Host smart-0c4fb410-07dd-45cf-8ac2-8e79749f6639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269575957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3269575957
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4179666196
Short name T635
Test name
Test status
Simulation time 321345218 ps
CPU time 4.49 seconds
Started Mar 24 01:08:01 PM PDT 24
Finished Mar 24 01:08:05 PM PDT 24
Peak memory 211220 kb
Host smart-004f4498-6672-4bf2-8df1-346b5e4e7f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179666196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4179666196
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1084797458
Short name T269
Test name
Test status
Simulation time 24375719633 ps
CPU time 200.68 seconds
Started Mar 24 01:07:57 PM PDT 24
Finished Mar 24 01:11:18 PM PDT 24
Peak memory 219604 kb
Host smart-f1d34f30-4ff5-4299-bcd6-0756720d4a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084797458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1084797458
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.683160617
Short name T260
Test name
Test status
Simulation time 39988701012 ps
CPU time 229.65 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 01:01:04 PM PDT 24
Peak memory 227844 kb
Host smart-62266356-3f55-40a2-abce-fb26a1885a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683160617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.683160617
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.19105596
Short name T308
Test name
Test status
Simulation time 3369129592 ps
CPU time 29.46 seconds
Started Mar 24 12:57:04 PM PDT 24
Finished Mar 24 12:57:34 PM PDT 24
Peak memory 211900 kb
Host smart-aa5ffca3-145a-4dfa-8edd-4082bb17f8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19105596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.19105596
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2488856779
Short name T466
Test name
Test status
Simulation time 4588838527 ps
CPU time 17.07 seconds
Started Mar 24 01:08:01 PM PDT 24
Finished Mar 24 01:08:19 PM PDT 24
Peak memory 212272 kb
Host smart-a46d2aea-3820-4461-b261-bcea6b7e2281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488856779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2488856779
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1932550605
Short name T515
Test name
Test status
Simulation time 317355665 ps
CPU time 7.84 seconds
Started Mar 24 01:07:59 PM PDT 24
Finished Mar 24 01:08:06 PM PDT 24
Peak memory 211088 kb
Host smart-3b56ed2d-0f12-476d-b99e-a1ce4450afdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932550605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1932550605
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2573537756
Short name T621
Test name
Test status
Simulation time 1140627237 ps
CPU time 11.87 seconds
Started Mar 24 12:57:09 PM PDT 24
Finished Mar 24 12:57:21 PM PDT 24
Peak memory 211056 kb
Host smart-62253e69-f598-4888-961b-432c5f5cf8b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573537756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2573537756
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.71872240
Short name T674
Test name
Test status
Simulation time 11724974257 ps
CPU time 27.49 seconds
Started Mar 24 12:57:07 PM PDT 24
Finished Mar 24 12:57:35 PM PDT 24
Peak memory 214100 kb
Host smart-7fb61036-2b07-44e0-a9ab-4684115a2fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71872240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.71872240
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.987785442
Short name T301
Test name
Test status
Simulation time 8265450920 ps
CPU time 43.23 seconds
Started Mar 24 01:07:59 PM PDT 24
Finished Mar 24 01:08:43 PM PDT 24
Peak memory 214364 kb
Host smart-91d69768-e10c-486f-8b67-4081d20e28cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987785442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.987785442
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3353550023
Short name T518
Test name
Test status
Simulation time 1911047710 ps
CPU time 25.91 seconds
Started Mar 24 01:08:00 PM PDT 24
Finished Mar 24 01:08:26 PM PDT 24
Peak memory 215364 kb
Host smart-29a7af5d-5175-4dda-a379-064ec9d32089
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353550023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3353550023
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4089295202
Short name T206
Test name
Test status
Simulation time 93379753 ps
CPU time 6.63 seconds
Started Mar 24 12:57:06 PM PDT 24
Finished Mar 24 12:57:13 PM PDT 24
Peak memory 211004 kb
Host smart-c7c3db4b-f78e-49c7-a9a8-8417b829eb3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089295202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4089295202
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4153367401
Short name T49
Test name
Test status
Simulation time 2112673016 ps
CPU time 16.37 seconds
Started Mar 24 01:08:05 PM PDT 24
Finished Mar 24 01:08:21 PM PDT 24
Peak memory 211508 kb
Host smart-13168e13-ab22-41f1-b480-9f25e93ddfb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153367401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4153367401
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.977002298
Short name T485
Test name
Test status
Simulation time 86684459 ps
CPU time 4.2 seconds
Started Mar 24 12:57:11 PM PDT 24
Finished Mar 24 12:57:15 PM PDT 24
Peak memory 211192 kb
Host smart-7d3dd427-72fd-4fe2-b02e-7b5df4bb6854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977002298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.977002298
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1786621048
Short name T231
Test name
Test status
Simulation time 64685883686 ps
CPU time 140.03 seconds
Started Mar 24 12:57:11 PM PDT 24
Finished Mar 24 12:59:31 PM PDT 24
Peak memory 220120 kb
Host smart-61324e16-7c3d-4b19-9f25-82e131566f8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786621048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1786621048
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2143512765
Short name T175
Test name
Test status
Simulation time 37743900582 ps
CPU time 172.9 seconds
Started Mar 24 01:08:10 PM PDT 24
Finished Mar 24 01:11:03 PM PDT 24
Peak memory 228536 kb
Host smart-a9274cc7-d8ca-49cd-8b16-86971b20d6af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143512765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2143512765
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1626932094
Short name T326
Test name
Test status
Simulation time 8194684138 ps
CPU time 18.91 seconds
Started Mar 24 01:08:04 PM PDT 24
Finished Mar 24 01:08:23 PM PDT 24
Peak memory 212364 kb
Host smart-07514447-656a-4e29-abfb-e86aa509f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626932094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1626932094
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2092916761
Short name T278
Test name
Test status
Simulation time 14187449874 ps
CPU time 27.81 seconds
Started Mar 24 12:57:11 PM PDT 24
Finished Mar 24 12:57:39 PM PDT 24
Peak memory 212308 kb
Host smart-f422c72a-82fc-49ba-b0a8-6003f7cd4706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092916761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2092916761
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1918515862
Short name T486
Test name
Test status
Simulation time 2759157720 ps
CPU time 13.9 seconds
Started Mar 24 12:57:11 PM PDT 24
Finished Mar 24 12:57:25 PM PDT 24
Peak memory 211216 kb
Host smart-8c37af15-74bb-4e46-b028-679a489db1c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918515862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1918515862
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3126523347
Short name T138
Test name
Test status
Simulation time 7280366988 ps
CPU time 14.93 seconds
Started Mar 24 01:08:05 PM PDT 24
Finished Mar 24 01:08:20 PM PDT 24
Peak memory 211520 kb
Host smart-60509778-d09e-4e71-8965-fd4bac6ab5b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126523347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3126523347
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2342401355
Short name T389
Test name
Test status
Simulation time 2472560236 ps
CPU time 27.02 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 12:57:41 PM PDT 24
Peak memory 219432 kb
Host smart-74ce54a8-c709-452c-b669-8d5ebfe4cd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342401355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2342401355
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3537938456
Short name T275
Test name
Test status
Simulation time 2536736928 ps
CPU time 23.66 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:35 PM PDT 24
Peak memory 219668 kb
Host smart-57f2e1bd-d71e-4c69-b3c0-05562ddc5a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537938456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3537938456
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1238185181
Short name T414
Test name
Test status
Simulation time 7864680136 ps
CPU time 91.11 seconds
Started Mar 24 01:08:07 PM PDT 24
Finished Mar 24 01:09:38 PM PDT 24
Peak memory 219436 kb
Host smart-dc6218e3-8ec6-4394-b0e1-ed5bb80753da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238185181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1238185181
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3340563050
Short name T13
Test name
Test status
Simulation time 1088609765 ps
CPU time 15.59 seconds
Started Mar 24 12:57:11 PM PDT 24
Finished Mar 24 12:57:27 PM PDT 24
Peak memory 212576 kb
Host smart-84d0c9f7-902e-423d-986e-998e7ccd968a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340563050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3340563050
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3392438626
Short name T286
Test name
Test status
Simulation time 1112220907 ps
CPU time 11.02 seconds
Started Mar 24 12:57:12 PM PDT 24
Finished Mar 24 12:57:23 PM PDT 24
Peak memory 211196 kb
Host smart-f7b90196-f737-456f-9e41-4092b3c63bfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392438626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3392438626
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.440455129
Short name T38
Test name
Test status
Simulation time 6205864710 ps
CPU time 13.7 seconds
Started Mar 24 01:08:04 PM PDT 24
Finished Mar 24 01:08:18 PM PDT 24
Peak memory 211304 kb
Host smart-fde47cc9-7563-4901-9e42-2fa7dab8f068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440455129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.440455129
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3089936984
Short name T402
Test name
Test status
Simulation time 42981750505 ps
CPU time 235.9 seconds
Started Mar 24 12:57:10 PM PDT 24
Finished Mar 24 01:01:06 PM PDT 24
Peak memory 237868 kb
Host smart-f707e975-f2fb-4af7-85b1-f2bb580a5b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089936984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3089936984
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.669939774
Short name T33
Test name
Test status
Simulation time 58740055213 ps
CPU time 293.42 seconds
Started Mar 24 01:08:06 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 231216 kb
Host smart-6a52c677-6630-40b2-a463-87e9ebcd02b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669939774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.669939774
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2691322455
Short name T509
Test name
Test status
Simulation time 168447606 ps
CPU time 9.49 seconds
Started Mar 24 01:08:05 PM PDT 24
Finished Mar 24 01:08:15 PM PDT 24
Peak memory 211788 kb
Host smart-99639aa6-b971-4886-82af-fc44754a6e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691322455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2691322455
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3563372227
Short name T398
Test name
Test status
Simulation time 168855676 ps
CPU time 9.66 seconds
Started Mar 24 12:57:12 PM PDT 24
Finished Mar 24 12:57:22 PM PDT 24
Peak memory 211736 kb
Host smart-da9401c0-71d3-403f-8a90-b068e240dbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563372227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3563372227
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2021335324
Short name T318
Test name
Test status
Simulation time 17031401143 ps
CPU time 14.16 seconds
Started Mar 24 12:57:11 PM PDT 24
Finished Mar 24 12:57:26 PM PDT 24
Peak memory 211128 kb
Host smart-2245b451-51d5-4a2e-bfe4-b5d10681d428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021335324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2021335324
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4032183504
Short name T580
Test name
Test status
Simulation time 3963187745 ps
CPU time 16.54 seconds
Started Mar 24 01:08:06 PM PDT 24
Finished Mar 24 01:08:23 PM PDT 24
Peak memory 211232 kb
Host smart-92ed19a8-b3c2-45ce-af05-ee02fa16c107
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032183504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4032183504
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1390212148
Short name T547
Test name
Test status
Simulation time 2513800699 ps
CPU time 19.23 seconds
Started Mar 24 12:57:12 PM PDT 24
Finished Mar 24 12:57:31 PM PDT 24
Peak memory 213476 kb
Host smart-fdd7341f-5e2d-4701-9bee-86ce4a5dd589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390212148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1390212148
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2868224498
Short name T441
Test name
Test status
Simulation time 753890628 ps
CPU time 10.18 seconds
Started Mar 24 01:08:03 PM PDT 24
Finished Mar 24 01:08:14 PM PDT 24
Peak memory 219256 kb
Host smart-d1d9e969-d784-4f8b-9fa2-fa9d75d254b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868224498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2868224498
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2374384672
Short name T556
Test name
Test status
Simulation time 586490046 ps
CPU time 32.14 seconds
Started Mar 24 01:08:05 PM PDT 24
Finished Mar 24 01:08:37 PM PDT 24
Peak memory 215400 kb
Host smart-5cb87a56-8ddc-4a0f-9047-a98338679bf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374384672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2374384672
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3540675666
Short name T370
Test name
Test status
Simulation time 98884240157 ps
CPU time 124.72 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:59:19 PM PDT 24
Peak memory 219456 kb
Host smart-b8175ebb-d712-42d3-9afa-874e9ec0a85e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540675666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3540675666
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3955061850
Short name T368
Test name
Test status
Simulation time 953342875 ps
CPU time 7.09 seconds
Started Mar 24 12:57:18 PM PDT 24
Finished Mar 24 12:57:25 PM PDT 24
Peak memory 211084 kb
Host smart-82fdff4d-3483-4323-ae42-f66b838b686c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955061850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3955061850
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3982022183
Short name T396
Test name
Test status
Simulation time 842288561 ps
CPU time 9.45 seconds
Started Mar 24 01:08:07 PM PDT 24
Finished Mar 24 01:08:16 PM PDT 24
Peak memory 211060 kb
Host smart-d3f52870-e804-494e-9b83-8527cdf813f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982022183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3982022183
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1853857607
Short name T349
Test name
Test status
Simulation time 12713034865 ps
CPU time 96.12 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:09:48 PM PDT 24
Peak memory 237936 kb
Host smart-5dbdc996-700b-450b-99a5-1877092bb597
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853857607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1853857607
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.218968715
Short name T15
Test name
Test status
Simulation time 2588974890 ps
CPU time 76.07 seconds
Started Mar 24 12:57:12 PM PDT 24
Finished Mar 24 12:58:28 PM PDT 24
Peak memory 239088 kb
Host smart-44e61db9-fde4-461e-be58-71bef8d1f821
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218968715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.218968715
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2197127102
Short name T576
Test name
Test status
Simulation time 57116529059 ps
CPU time 32.51 seconds
Started Mar 24 12:57:12 PM PDT 24
Finished Mar 24 12:57:44 PM PDT 24
Peak memory 212320 kb
Host smart-48a441d2-8e22-4783-8bea-1ba900dd492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197127102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2197127102
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.837660219
Short name T369
Test name
Test status
Simulation time 4039007892 ps
CPU time 33.69 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:46 PM PDT 24
Peak memory 212100 kb
Host smart-71efcd4b-2a46-489e-9ce1-ee2fe3d9d05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837660219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.837660219
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1677413951
Short name T146
Test name
Test status
Simulation time 177687367 ps
CPU time 6.74 seconds
Started Mar 24 01:08:06 PM PDT 24
Finished Mar 24 01:08:12 PM PDT 24
Peak memory 211064 kb
Host smart-af866e12-f90a-443a-bba0-17441e5da985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677413951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1677413951
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.533437919
Short name T563
Test name
Test status
Simulation time 383786670 ps
CPU time 5.65 seconds
Started Mar 24 12:57:10 PM PDT 24
Finished Mar 24 12:57:15 PM PDT 24
Peak memory 211084 kb
Host smart-2c39365f-32d5-4bb8-ab0c-2d53a60098ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533437919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.533437919
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2419471374
Short name T277
Test name
Test status
Simulation time 25720029352 ps
CPU time 35.86 seconds
Started Mar 24 01:08:06 PM PDT 24
Finished Mar 24 01:08:42 PM PDT 24
Peak memory 213708 kb
Host smart-fc563591-72db-423b-b1ee-a4b3424679ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419471374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2419471374
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2818266774
Short name T185
Test name
Test status
Simulation time 13705089064 ps
CPU time 36.55 seconds
Started Mar 24 12:57:11 PM PDT 24
Finished Mar 24 12:57:47 PM PDT 24
Peak memory 219408 kb
Host smart-9bf6fe5d-f6a7-4756-8915-3cd5c19fac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818266774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2818266774
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3466743363
Short name T26
Test name
Test status
Simulation time 7175001893 ps
CPU time 84.05 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:09:36 PM PDT 24
Peak memory 219648 kb
Host smart-8918636e-3e3d-44f3-8bd7-91eeb5a471a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466743363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3466743363
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.598641848
Short name T676
Test name
Test status
Simulation time 1472299317 ps
CPU time 24.2 seconds
Started Mar 24 12:57:09 PM PDT 24
Finished Mar 24 12:57:34 PM PDT 24
Peak memory 219340 kb
Host smart-d8206a72-91be-4c89-97c2-67223e15c9db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598641848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.598641848
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2949556396
Short name T182
Test name
Test status
Simulation time 1179958480 ps
CPU time 11.11 seconds
Started Mar 24 01:08:07 PM PDT 24
Finished Mar 24 01:08:18 PM PDT 24
Peak memory 211144 kb
Host smart-13767c6f-32b9-4a8c-855c-44dbe8427bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949556396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2949556396
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2965166636
Short name T78
Test name
Test status
Simulation time 8009774690 ps
CPU time 16.15 seconds
Started Mar 24 12:57:17 PM PDT 24
Finished Mar 24 12:57:33 PM PDT 24
Peak memory 211308 kb
Host smart-e069d17b-f526-43f4-8a17-a9ca27bdad1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965166636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2965166636
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2136037319
Short name T434
Test name
Test status
Simulation time 140907523918 ps
CPU time 343.38 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 01:02:58 PM PDT 24
Peak memory 228108 kb
Host smart-6fbf83fd-5b92-402e-bfaa-186fe6f6914a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136037319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2136037319
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4187070090
Short name T632
Test name
Test status
Simulation time 6344027478 ps
CPU time 134.1 seconds
Started Mar 24 01:08:05 PM PDT 24
Finished Mar 24 01:10:19 PM PDT 24
Peak memory 237128 kb
Host smart-c1b8610c-8352-4c67-8150-7a8ae61330cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187070090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4187070090
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3757961958
Short name T213
Test name
Test status
Simulation time 507125832 ps
CPU time 9.36 seconds
Started Mar 24 01:08:14 PM PDT 24
Finished Mar 24 01:08:24 PM PDT 24
Peak memory 213288 kb
Host smart-c39e4128-f39e-465f-b0d6-c09c85ce58be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757961958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3757961958
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.398924440
Short name T150
Test name
Test status
Simulation time 13105170100 ps
CPU time 29.32 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:45 PM PDT 24
Peak memory 212116 kb
Host smart-c002f513-f743-4186-bf9c-446d8f86a7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398924440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.398924440
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2302701318
Short name T4
Test name
Test status
Simulation time 1575084072 ps
CPU time 10.53 seconds
Started Mar 24 12:57:15 PM PDT 24
Finished Mar 24 12:57:26 PM PDT 24
Peak memory 211016 kb
Host smart-8bae16ac-a982-47fe-b1be-9f1c4c4ca388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302701318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2302701318
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3366921181
Short name T247
Test name
Test status
Simulation time 6840417851 ps
CPU time 15.25 seconds
Started Mar 24 01:08:04 PM PDT 24
Finished Mar 24 01:08:20 PM PDT 24
Peak memory 211220 kb
Host smart-d15d6304-24c0-424c-b2e5-f35c05e62bbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366921181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3366921181
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1517739985
Short name T285
Test name
Test status
Simulation time 8681086858 ps
CPU time 34.52 seconds
Started Mar 24 12:57:14 PM PDT 24
Finished Mar 24 12:57:49 PM PDT 24
Peak memory 219412 kb
Host smart-b7aac765-be91-4610-a008-80f2a6b2e715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517739985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1517739985
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3434413921
Short name T467
Test name
Test status
Simulation time 7587699116 ps
CPU time 38.56 seconds
Started Mar 24 01:08:12 PM PDT 24
Finished Mar 24 01:08:51 PM PDT 24
Peak memory 219668 kb
Host smart-66910f39-bf87-467b-92bd-53ca94727549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434413921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3434413921
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3670634584
Short name T430
Test name
Test status
Simulation time 5363310688 ps
CPU time 48.83 seconds
Started Mar 24 12:57:17 PM PDT 24
Finished Mar 24 12:58:06 PM PDT 24
Peak memory 219424 kb
Host smart-df798ac6-54f8-4c2f-9eea-642380c6b84e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670634584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3670634584
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.438931257
Short name T400
Test name
Test status
Simulation time 3838632260 ps
CPU time 35.57 seconds
Started Mar 24 01:08:05 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 216088 kb
Host smart-5d18418e-4365-4bd0-b182-91f77f7a4237
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438931257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.438931257
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.919538419
Short name T19
Test name
Test status
Simulation time 288954640050 ps
CPU time 1580.74 seconds
Started Mar 24 01:08:09 PM PDT 24
Finished Mar 24 01:34:30 PM PDT 24
Peak memory 235868 kb
Host smart-3c4e8053-589d-469a-9c0e-9cf5dbfe3fb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919538419 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.919538419
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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